Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T541 /workspace/coverage/default/9.rstmgr_por_stretcher.403664161 Aug 04 05:35:29 PM PDT 24 Aug 04 05:35:30 PM PDT 24 158111295 ps
T542 /workspace/coverage/default/32.rstmgr_por_stretcher.2630657466 Aug 04 05:36:15 PM PDT 24 Aug 04 05:36:17 PM PDT 24 166123701 ps
T543 /workspace/coverage/default/4.rstmgr_smoke.3322073007 Aug 04 05:35:16 PM PDT 24 Aug 04 05:35:18 PM PDT 24 115239409 ps
T544 /workspace/coverage/default/5.rstmgr_smoke.2170598453 Aug 04 05:35:22 PM PDT 24 Aug 04 05:35:24 PM PDT 24 198707322 ps
T545 /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3612080796 Aug 04 05:36:00 PM PDT 24 Aug 04 05:36:01 PM PDT 24 245993278 ps
T69 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1623834890 Aug 04 05:28:13 PM PDT 24 Aug 04 05:28:15 PM PDT 24 255070920 ps
T63 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3428804313 Aug 04 05:27:54 PM PDT 24 Aug 04 05:28:03 PM PDT 24 1990842262 ps
T64 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3441690878 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:58 PM PDT 24 68362258 ps
T65 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1561278653 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:58 PM PDT 24 222656023 ps
T67 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1408392420 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:58 PM PDT 24 77647284 ps
T66 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1438828019 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:58 PM PDT 24 502078493 ps
T70 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1254471033 Aug 04 05:28:07 PM PDT 24 Aug 04 05:28:08 PM PDT 24 209736341 ps
T93 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.621806596 Aug 04 05:27:54 PM PDT 24 Aug 04 05:27:56 PM PDT 24 63529902 ps
T94 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.360589159 Aug 04 05:28:09 PM PDT 24 Aug 04 05:28:10 PM PDT 24 81159499 ps
T72 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4031707147 Aug 04 05:27:52 PM PDT 24 Aug 04 05:27:54 PM PDT 24 443525865 ps
T95 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.606900667 Aug 04 05:27:58 PM PDT 24 Aug 04 05:27:59 PM PDT 24 222443979 ps
T71 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.259937360 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:02 PM PDT 24 199124830 ps
T101 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3219708565 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:59 PM PDT 24 462364474 ps
T81 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2103197034 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:58 PM PDT 24 199400903 ps
T82 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.523494245 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:01 PM PDT 24 166830769 ps
T96 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3739013271 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:01 PM PDT 24 102664995 ps
T83 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1077331671 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:06 PM PDT 24 160491259 ps
T97 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.664602846 Aug 04 05:28:02 PM PDT 24 Aug 04 05:28:03 PM PDT 24 152613425 ps
T84 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4058626674 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:01 PM PDT 24 111067587 ps
T98 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2247892810 Aug 04 05:28:07 PM PDT 24 Aug 04 05:28:08 PM PDT 24 78499669 ps
T85 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3833850616 Aug 04 05:28:01 PM PDT 24 Aug 04 05:28:02 PM PDT 24 113531554 ps
T113 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1849459539 Aug 04 05:27:58 PM PDT 24 Aug 04 05:28:00 PM PDT 24 406827944 ps
T99 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1860253434 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:58 PM PDT 24 86565038 ps
T100 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4239136185 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:00 PM PDT 24 85403804 ps
T102 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1614015290 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:08 PM PDT 24 875284999 ps
T546 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3639576344 Aug 04 05:27:47 PM PDT 24 Aug 04 05:27:50 PM PDT 24 463620599 ps
T86 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.401042017 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:04 PM PDT 24 951212298 ps
T105 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4200010203 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:02 PM PDT 24 230081512 ps
T109 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3577314670 Aug 04 05:27:58 PM PDT 24 Aug 04 05:28:01 PM PDT 24 905505383 ps
T103 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4008887128 Aug 04 05:27:50 PM PDT 24 Aug 04 05:27:54 PM PDT 24 932338859 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3195346603 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:58 PM PDT 24 69314161 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3373756574 Aug 04 05:28:03 PM PDT 24 Aug 04 05:28:05 PM PDT 24 498157215 ps
T548 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3211171135 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:59 PM PDT 24 253064505 ps
T106 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3934573465 Aug 04 05:27:55 PM PDT 24 Aug 04 05:27:57 PM PDT 24 210070817 ps
T89 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.257562578 Aug 04 05:28:06 PM PDT 24 Aug 04 05:28:07 PM PDT 24 92081629 ps
T549 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4153822195 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:59 PM PDT 24 277404397 ps
T104 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2692430772 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:59 PM PDT 24 192833587 ps
T550 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.319137485 Aug 04 05:28:07 PM PDT 24 Aug 04 05:28:08 PM PDT 24 176452254 ps
T551 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.187455473 Aug 04 05:28:02 PM PDT 24 Aug 04 05:28:05 PM PDT 24 957701805 ps
T552 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3330887367 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:56 PM PDT 24 67070096 ps
T120 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3809902868 Aug 04 05:28:14 PM PDT 24 Aug 04 05:28:16 PM PDT 24 488067413 ps
T553 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3821848814 Aug 04 05:28:05 PM PDT 24 Aug 04 05:28:06 PM PDT 24 77189440 ps
T554 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2860543462 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:01 PM PDT 24 94772314 ps
T555 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1283270393 Aug 04 05:28:03 PM PDT 24 Aug 04 05:28:04 PM PDT 24 144287348 ps
T556 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.492827547 Aug 04 05:28:15 PM PDT 24 Aug 04 05:28:16 PM PDT 24 79232122 ps
T112 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2372485510 Aug 04 05:28:01 PM PDT 24 Aug 04 05:28:05 PM PDT 24 446487653 ps
T557 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.171347977 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:06 PM PDT 24 158655616 ps
T558 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2358918015 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:01 PM PDT 24 246363861 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2660615825 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:59 PM PDT 24 145940588 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2392960624 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:57 PM PDT 24 91117343 ps
T561 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3521217681 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:03 PM PDT 24 427649783 ps
T110 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1695338261 Aug 04 05:28:14 PM PDT 24 Aug 04 05:28:22 PM PDT 24 813490305 ps
T562 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.10279356 Aug 04 05:28:05 PM PDT 24 Aug 04 05:28:07 PM PDT 24 252625057 ps
T563 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3092340080 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:57 PM PDT 24 94231281 ps
T564 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.893681516 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:05 PM PDT 24 559236108 ps
T565 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2925794854 Aug 04 05:27:45 PM PDT 24 Aug 04 05:27:49 PM PDT 24 268940845 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.299770100 Aug 04 05:27:55 PM PDT 24 Aug 04 05:27:57 PM PDT 24 225909702 ps
T567 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1198189416 Aug 04 05:27:55 PM PDT 24 Aug 04 05:27:59 PM PDT 24 878085282 ps
T568 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1356555627 Aug 04 05:27:55 PM PDT 24 Aug 04 05:27:58 PM PDT 24 397035331 ps
T569 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1140274746 Aug 04 05:28:09 PM PDT 24 Aug 04 05:28:10 PM PDT 24 62690579 ps
T570 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2188292772 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:05 PM PDT 24 132275755 ps
T571 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1478090669 Aug 04 05:28:07 PM PDT 24 Aug 04 05:28:09 PM PDT 24 145076937 ps
T572 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.596528545 Aug 04 05:28:03 PM PDT 24 Aug 04 05:28:05 PM PDT 24 96862927 ps
T573 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.385384227 Aug 04 05:27:55 PM PDT 24 Aug 04 05:27:56 PM PDT 24 134113519 ps
T121 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1832094192 Aug 04 05:28:08 PM PDT 24 Aug 04 05:28:10 PM PDT 24 431707697 ps
T574 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3974830963 Aug 04 05:27:58 PM PDT 24 Aug 04 05:28:00 PM PDT 24 412574678 ps
T575 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1022946677 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:00 PM PDT 24 55330894 ps
T576 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3217978831 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:02 PM PDT 24 303790849 ps
T577 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2485233158 Aug 04 05:28:08 PM PDT 24 Aug 04 05:28:09 PM PDT 24 154287699 ps
T578 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3020195163 Aug 04 05:27:55 PM PDT 24 Aug 04 05:27:57 PM PDT 24 475325781 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3979872237 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:00 PM PDT 24 224706413 ps
T580 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.761132132 Aug 04 05:28:01 PM PDT 24 Aug 04 05:28:05 PM PDT 24 908363066 ps
T581 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.287165510 Aug 04 05:28:05 PM PDT 24 Aug 04 05:28:06 PM PDT 24 148569041 ps
T582 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1266852838 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:00 PM PDT 24 110813982 ps
T583 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2430954358 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:59 PM PDT 24 176107881 ps
T584 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2314033325 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:06 PM PDT 24 125860522 ps
T585 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.785279996 Aug 04 05:28:02 PM PDT 24 Aug 04 05:28:03 PM PDT 24 77115797 ps
T586 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.287114481 Aug 04 05:27:58 PM PDT 24 Aug 04 05:27:59 PM PDT 24 86330136 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3229404584 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:02 PM PDT 24 113779078 ps
T588 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2805081548 Aug 04 05:27:55 PM PDT 24 Aug 04 05:27:56 PM PDT 24 75404386 ps
T589 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2063624024 Aug 04 05:28:09 PM PDT 24 Aug 04 05:28:10 PM PDT 24 121818037 ps
T122 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.650958103 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:03 PM PDT 24 817499860 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.899595045 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:59 PM PDT 24 356231982 ps
T591 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2642645796 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:06 PM PDT 24 160650789 ps
T592 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3824619566 Aug 04 05:27:51 PM PDT 24 Aug 04 05:27:52 PM PDT 24 111326112 ps
T107 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3477876708 Aug 04 05:27:57 PM PDT 24 Aug 04 05:28:00 PM PDT 24 888745970 ps
T593 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1367420358 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:00 PM PDT 24 154445974 ps
T594 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1563281218 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:02 PM PDT 24 110202397 ps
T595 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2854551145 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:00 PM PDT 24 59277819 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1912787094 Aug 04 05:28:01 PM PDT 24 Aug 04 05:28:02 PM PDT 24 108234180 ps
T597 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1577536449 Aug 04 05:28:13 PM PDT 24 Aug 04 05:28:15 PM PDT 24 248079983 ps
T598 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.169629976 Aug 04 05:27:57 PM PDT 24 Aug 04 05:28:00 PM PDT 24 347367839 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1682408314 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:58 PM PDT 24 74491161 ps
T600 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1214114240 Aug 04 05:28:10 PM PDT 24 Aug 04 05:28:15 PM PDT 24 588282303 ps
T601 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2656690012 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:01 PM PDT 24 75566658 ps
T108 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.170264675 Aug 04 05:27:58 PM PDT 24 Aug 04 05:28:00 PM PDT 24 433875200 ps
T602 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1891523987 Aug 04 05:27:57 PM PDT 24 Aug 04 05:27:59 PM PDT 24 127605160 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4005579614 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:01 PM PDT 24 121580800 ps
T604 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1674362195 Aug 04 05:27:58 PM PDT 24 Aug 04 05:27:59 PM PDT 24 73496409 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3798278937 Aug 04 05:27:56 PM PDT 24 Aug 04 05:28:00 PM PDT 24 794995277 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.904328102 Aug 04 05:28:03 PM PDT 24 Aug 04 05:28:05 PM PDT 24 277362852 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2570997327 Aug 04 05:28:00 PM PDT 24 Aug 04 05:28:01 PM PDT 24 134945955 ps
T608 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3042290823 Aug 04 05:28:04 PM PDT 24 Aug 04 05:28:05 PM PDT 24 71828790 ps
T609 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2716144007 Aug 04 05:28:09 PM PDT 24 Aug 04 05:28:11 PM PDT 24 177903409 ps
T610 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3948784240 Aug 04 05:28:01 PM PDT 24 Aug 04 05:28:02 PM PDT 24 112912037 ps
T611 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2512812908 Aug 04 05:27:56 PM PDT 24 Aug 04 05:27:57 PM PDT 24 77243459 ps
T612 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2676792712 Aug 04 05:27:58 PM PDT 24 Aug 04 05:28:00 PM PDT 24 181164536 ps
T613 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2437009670 Aug 04 05:28:02 PM PDT 24 Aug 04 05:28:05 PM PDT 24 865243225 ps
T614 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2593895831 Aug 04 05:27:59 PM PDT 24 Aug 04 05:28:00 PM PDT 24 150356237 ps
T615 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3445427071 Aug 04 05:28:10 PM PDT 24 Aug 04 05:28:12 PM PDT 24 89240742 ps
T616 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.171184764 Aug 04 05:28:01 PM PDT 24 Aug 04 05:28:04 PM PDT 24 277622608 ps
T617 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1787961678 Aug 04 05:27:51 PM PDT 24 Aug 04 05:27:52 PM PDT 24 142248144 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1212384940 Aug 04 05:27:51 PM PDT 24 Aug 04 05:27:53 PM PDT 24 234292308 ps
T619 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1195046378 Aug 04 05:27:50 PM PDT 24 Aug 04 05:27:51 PM PDT 24 66082081 ps
T620 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1026764889 Aug 04 05:28:14 PM PDT 24 Aug 04 05:28:15 PM PDT 24 114791681 ps

Test location /workspace/coverage/default/3.rstmgr_stress_all.648258048
Short name T10
Test name
Test status
Simulation time 4354949518 ps
CPU time 20.57 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 200496 kb
Host smart-0659c489-5ddb-4c63-8fff-d9e0c3f14f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648258048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.648258048
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.520684437
Short name T62
Test name
Test status
Simulation time 446789668 ps
CPU time 2.78 seconds
Started Aug 04 05:35:55 PM PDT 24
Finished Aug 04 05:35:58 PM PDT 24
Peak memory 200268 kb
Host smart-359f3e04-220d-493e-b578-fb7fb409dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520684437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.520684437
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1254471033
Short name T70
Test name
Test status
Simulation time 209736341 ps
CPU time 1.5 seconds
Started Aug 04 05:28:07 PM PDT 24
Finished Aug 04 05:28:08 PM PDT 24
Peak memory 208380 kb
Host smart-07d2c67c-2b4d-4ba2-b4ff-8dc28707ed21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254471033 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1254471033
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2077773470
Short name T3
Test name
Test status
Simulation time 8981057741 ps
CPU time 14.05 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:33 PM PDT 24
Peak memory 217508 kb
Host smart-fa6d8be7-a533-4b23-82cf-0c7acbaac633
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077773470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2077773470
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.167117826
Short name T40
Test name
Test status
Simulation time 1225795248 ps
CPU time 5.7 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 217660 kb
Host smart-38ab0ac2-0ae2-49b9-8711-fe54e58479ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167117826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.167117826
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3577314670
Short name T109
Test name
Test status
Simulation time 905505383 ps
CPU time 3.06 seconds
Started Aug 04 05:27:58 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 200272 kb
Host smart-7414e937-99fc-476c-b4ae-49c0d77f2606
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577314670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3577314670
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.309626262
Short name T87
Test name
Test status
Simulation time 10694499210 ps
CPU time 37.89 seconds
Started Aug 04 05:35:58 PM PDT 24
Finished Aug 04 05:36:36 PM PDT 24
Peak memory 208728 kb
Host smart-1b011f81-dd2f-4f0a-b725-a2a286b6d8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309626262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.309626262
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.259937360
Short name T71
Test name
Test status
Simulation time 199124830 ps
CPU time 2.91 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 208396 kb
Host smart-e6ad1c53-367c-4825-9655-64846b60d3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259937360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.259937360
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1689750872
Short name T6
Test name
Test status
Simulation time 80199883 ps
CPU time 0.86 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 200176 kb
Host smart-9b04b4a1-ae3c-4aea-a394-f41ed0908610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689750872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1689750872
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1744168625
Short name T39
Test name
Test status
Simulation time 173497538 ps
CPU time 1.17 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:31 PM PDT 24
Peak memory 200552 kb
Host smart-926186ae-5614-484d-b4d4-52094f9ba7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744168625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1744168625
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3459247323
Short name T35
Test name
Test status
Simulation time 2345005064 ps
CPU time 8.03 seconds
Started Aug 04 05:36:01 PM PDT 24
Finished Aug 04 05:36:09 PM PDT 24
Peak memory 217232 kb
Host smart-f8414a3f-803b-48de-9b26-bdc31ac99549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459247323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3459247323
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.650958103
Short name T122
Test name
Test status
Simulation time 817499860 ps
CPU time 3.07 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 200248 kb
Host smart-f45e3cc4-32c5-424f-b824-6d4e36097b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650958103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
650958103
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1182151071
Short name T114
Test name
Test status
Simulation time 2012665303 ps
CPU time 7.35 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 200592 kb
Host smart-98ac3e94-9b0f-4aac-8135-54a5bdba98ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182151071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1182151071
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.327057756
Short name T2
Test name
Test status
Simulation time 98707661 ps
CPU time 1 seconds
Started Aug 04 05:35:35 PM PDT 24
Finished Aug 04 05:35:36 PM PDT 24
Peak memory 200252 kb
Host smart-50509e06-abd4-4f6a-84e7-94f1e34921b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327057756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.327057756
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.254433554
Short name T26
Test name
Test status
Simulation time 1230907368 ps
CPU time 5.47 seconds
Started Aug 04 05:35:41 PM PDT 24
Finished Aug 04 05:35:46 PM PDT 24
Peak memory 217892 kb
Host smart-0731b278-1c4d-4c5a-840b-653d175dc119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254433554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.254433554
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3934573465
Short name T106
Test name
Test status
Simulation time 210070817 ps
CPU time 1.51 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 200204 kb
Host smart-e4516c46-d933-4843-a5cc-f8b43f29a54d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934573465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3934573465
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.621806596
Short name T93
Test name
Test status
Simulation time 63529902 ps
CPU time 0.82 seconds
Started Aug 04 05:27:54 PM PDT 24
Finished Aug 04 05:27:56 PM PDT 24
Peak memory 200048 kb
Host smart-59d3dc37-c845-4714-8c89-bd7fb8aa6c05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621806596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.621806596
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2405789159
Short name T15
Test name
Test status
Simulation time 232783333 ps
CPU time 0.95 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:28 PM PDT 24
Peak memory 200140 kb
Host smart-7a25910b-3b31-4875-b528-7aa66c7575aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405789159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2405789159
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3477876708
Short name T107
Test name
Test status
Simulation time 888745970 ps
CPU time 2.95 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200204 kb
Host smart-2bad14a4-919f-417e-ab5c-7e685048ebcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477876708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3477876708
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3639576344
Short name T546
Test name
Test status
Simulation time 463620599 ps
CPU time 2.67 seconds
Started Aug 04 05:27:47 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 208328 kb
Host smart-8972e1e4-ab5f-4653-9da2-4dffd2d9a553
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639576344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
639576344
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2925794854
Short name T565
Test name
Test status
Simulation time 268940845 ps
CPU time 3.34 seconds
Started Aug 04 05:27:45 PM PDT 24
Finished Aug 04 05:27:49 PM PDT 24
Peak memory 200076 kb
Host smart-ff4a0082-370f-4ed4-b822-069a7b1eab80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925794854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
925794854
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3824619566
Short name T592
Test name
Test status
Simulation time 111326112 ps
CPU time 0.86 seconds
Started Aug 04 05:27:51 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 199976 kb
Host smart-a7682d46-c6cd-423b-8124-69b146676fa0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824619566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
824619566
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2642645796
Short name T591
Test name
Test status
Simulation time 160650789 ps
CPU time 1.41 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:06 PM PDT 24
Peak memory 208132 kb
Host smart-956feba2-e129-431e-b435-669badf8e8da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642645796 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2642645796
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3195346603
Short name T547
Test name
Test status
Simulation time 69314161 ps
CPU time 0.81 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 200024 kb
Host smart-dec4f01b-4dff-4cda-b8c1-605e79e03488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195346603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3195346603
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2860543462
Short name T554
Test name
Test status
Simulation time 94772314 ps
CPU time 1.17 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 200396 kb
Host smart-141d40fd-6b7f-4d56-910c-75db7fd9d5f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860543462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2860543462
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1212384940
Short name T618
Test name
Test status
Simulation time 234292308 ps
CPU time 1.89 seconds
Started Aug 04 05:27:51 PM PDT 24
Finished Aug 04 05:27:53 PM PDT 24
Peak memory 208356 kb
Host smart-31a9d253-fd81-4adf-9ebf-f3d27dfee0e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212384940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1212384940
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4008887128
Short name T103
Test name
Test status
Simulation time 932338859 ps
CPU time 3.21 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 200184 kb
Host smart-a8618e34-e238-43c5-9d56-34a0394d9c11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008887128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4008887128
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2660615825
Short name T559
Test name
Test status
Simulation time 145940588 ps
CPU time 2 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200156 kb
Host smart-ab68e44f-ff36-4452-8881-e16049a44459
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660615825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
660615825
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3798278937
Short name T605
Test name
Test status
Simulation time 794995277 ps
CPU time 4.6 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200012 kb
Host smart-06a1766a-f79f-4863-9637-46318f64e861
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798278937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
798278937
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1787961678
Short name T617
Test name
Test status
Simulation time 142248144 ps
CPU time 0.92 seconds
Started Aug 04 05:27:51 PM PDT 24
Finished Aug 04 05:27:52 PM PDT 24
Peak memory 199996 kb
Host smart-8ed81fa8-7d89-4313-bf84-36c4bef7953b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787961678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
787961678
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3833850616
Short name T85
Test name
Test status
Simulation time 113531554 ps
CPU time 0.92 seconds
Started Aug 04 05:28:01 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 200108 kb
Host smart-fea0ec5e-5669-43bd-9a14-60e0b22fa9ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833850616 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3833850616
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2854551145
Short name T595
Test name
Test status
Simulation time 59277819 ps
CPU time 0.84 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200008 kb
Host smart-7792f342-63a9-49ca-baa4-fc23016e3303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854551145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2854551145
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.385384227
Short name T573
Test name
Test status
Simulation time 134113519 ps
CPU time 1.3 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:27:56 PM PDT 24
Peak memory 200188 kb
Host smart-8fd3fdee-76af-492b-9614-8bad0c835a3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385384227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.385384227
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4031707147
Short name T72
Test name
Test status
Simulation time 443525865 ps
CPU time 1.9 seconds
Started Aug 04 05:27:52 PM PDT 24
Finished Aug 04 05:27:54 PM PDT 24
Peak memory 200248 kb
Host smart-8a601e0c-7ea1-4fc6-885a-d2cd6b49c5d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031707147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.4031707147
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2593895831
Short name T614
Test name
Test status
Simulation time 150356237 ps
CPU time 1.22 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 208360 kb
Host smart-a455827e-0f82-4278-97f2-683c61c024c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593895831 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2593895831
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1367420358
Short name T593
Test name
Test status
Simulation time 154445974 ps
CPU time 1.17 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200032 kb
Host smart-9ba3a554-5ffc-4bb8-af13-f868b46f0a09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367420358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1367420358
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.169629976
Short name T598
Test name
Test status
Simulation time 347367839 ps
CPU time 2.61 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 208384 kb
Host smart-e7a6a8e7-7906-4bfd-bd9e-a89c82ea5d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169629976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.169629976
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.287165510
Short name T581
Test name
Test status
Simulation time 148569041 ps
CPU time 1.09 seconds
Started Aug 04 05:28:05 PM PDT 24
Finished Aug 04 05:28:06 PM PDT 24
Peak memory 208268 kb
Host smart-4882facf-eb12-4bde-8599-e87ff6a810ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287165510 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.287165510
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1022946677
Short name T575
Test name
Test status
Simulation time 55330894 ps
CPU time 0.75 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 199896 kb
Host smart-f793394b-e43e-4bbf-b45d-7d856aee9756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022946677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1022946677
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.606900667
Short name T95
Test name
Test status
Simulation time 222443979 ps
CPU time 1.43 seconds
Started Aug 04 05:27:58 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200132 kb
Host smart-1c9f4f5a-66da-4e11-8c32-904080feddee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606900667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.606900667
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.10279356
Short name T562
Test name
Test status
Simulation time 252625057 ps
CPU time 1.88 seconds
Started Aug 04 05:28:05 PM PDT 24
Finished Aug 04 05:28:07 PM PDT 24
Peak memory 200076 kb
Host smart-0389de6e-efc8-4585-8fad-a214809ada79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10279356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.10279356
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.761132132
Short name T580
Test name
Test status
Simulation time 908363066 ps
CPU time 3.44 seconds
Started Aug 04 05:28:01 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 200208 kb
Host smart-dc906575-a210-4810-b209-f94b999d41f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761132132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.761132132
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1140274746
Short name T569
Test name
Test status
Simulation time 62690579 ps
CPU time 0.83 seconds
Started Aug 04 05:28:09 PM PDT 24
Finished Aug 04 05:28:10 PM PDT 24
Peak memory 200032 kb
Host smart-db58dbe4-9a21-419b-9c18-9d4de1ba998b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140274746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1140274746
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.664602846
Short name T97
Test name
Test status
Simulation time 152613425 ps
CPU time 1.09 seconds
Started Aug 04 05:28:02 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 200156 kb
Host smart-85a77664-ec39-4033-8b4e-0f6167d4f690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664602846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_sa
me_csr_outstanding.664602846
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.893681516
Short name T564
Test name
Test status
Simulation time 559236108 ps
CPU time 4.14 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 208352 kb
Host smart-c412ca57-d17d-4db0-8ca9-d068ddd0af4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893681516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.893681516
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3219708565
Short name T101
Test name
Test status
Simulation time 462364474 ps
CPU time 1.96 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200176 kb
Host smart-4e296eda-586d-462d-8a7d-61f44e0d3bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219708565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3219708565
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2314033325
Short name T584
Test name
Test status
Simulation time 125860522 ps
CPU time 1.44 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:06 PM PDT 24
Peak memory 208348 kb
Host smart-78ff3329-cb90-405b-b47d-840dd1af76b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314033325 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2314033325
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1674362195
Short name T604
Test name
Test status
Simulation time 73496409 ps
CPU time 0.86 seconds
Started Aug 04 05:27:58 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200032 kb
Host smart-e91578d1-7b6a-4d3f-ad9c-d9615ff085e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674362195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1674362195
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4239136185
Short name T100
Test name
Test status
Simulation time 85403804 ps
CPU time 1.02 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200108 kb
Host smart-c1e4ed2b-8061-4fd1-af7b-29870707500e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239136185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.4239136185
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1577536449
Short name T597
Test name
Test status
Simulation time 248079983 ps
CPU time 1.79 seconds
Started Aug 04 05:28:13 PM PDT 24
Finished Aug 04 05:28:15 PM PDT 24
Peak memory 208380 kb
Host smart-386fbb8c-9065-41e6-9e87-9bbd357285e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577536449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1577536449
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1614015290
Short name T102
Test name
Test status
Simulation time 875284999 ps
CPU time 3.21 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:08 PM PDT 24
Peak memory 200152 kb
Host smart-90349ac3-8bf4-452a-a22d-2b88d3908324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614015290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1614015290
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1077331671
Short name T83
Test name
Test status
Simulation time 160491259 ps
CPU time 1.41 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:06 PM PDT 24
Peak memory 208452 kb
Host smart-b628dd28-6974-49b4-90ce-71dc96f76923
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077331671 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1077331671
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.785279996
Short name T585
Test name
Test status
Simulation time 77115797 ps
CPU time 0.85 seconds
Started Aug 04 05:28:02 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 200032 kb
Host smart-1be11aea-fa72-4666-9f30-b037d492a710
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785279996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.785279996
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1283270393
Short name T555
Test name
Test status
Simulation time 144287348 ps
CPU time 1.15 seconds
Started Aug 04 05:28:03 PM PDT 24
Finished Aug 04 05:28:04 PM PDT 24
Peak memory 200088 kb
Host smart-944475aa-bfd8-4d8c-84f2-53e4f226942a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283270393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1283270393
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4200010203
Short name T105
Test name
Test status
Simulation time 230081512 ps
CPU time 1.88 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 208296 kb
Host smart-52bbb073-dacf-47cd-87ea-fc0a8cae25e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200010203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4200010203
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.187455473
Short name T551
Test name
Test status
Simulation time 957701805 ps
CPU time 3.23 seconds
Started Aug 04 05:28:02 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 200184 kb
Host smart-64dec7ab-7ba6-4ca0-bda9-e3fe12b4ebcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187455473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.187455473
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2063624024
Short name T589
Test name
Test status
Simulation time 121818037 ps
CPU time 0.94 seconds
Started Aug 04 05:28:09 PM PDT 24
Finished Aug 04 05:28:10 PM PDT 24
Peak memory 200072 kb
Host smart-c040e795-5894-4beb-a177-36bc1cb16b37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063624024 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2063624024
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2656690012
Short name T601
Test name
Test status
Simulation time 75566658 ps
CPU time 0.78 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 200012 kb
Host smart-4565752e-7a29-411f-8c5b-e30508e35046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656690012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2656690012
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3445427071
Short name T615
Test name
Test status
Simulation time 89240742 ps
CPU time 1.06 seconds
Started Aug 04 05:28:10 PM PDT 24
Finished Aug 04 05:28:12 PM PDT 24
Peak memory 200064 kb
Host smart-6ef9549b-a8fc-4fa8-a8f3-033fbaaae03e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445427071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3445427071
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1623834890
Short name T69
Test name
Test status
Simulation time 255070920 ps
CPU time 1.87 seconds
Started Aug 04 05:28:13 PM PDT 24
Finished Aug 04 05:28:15 PM PDT 24
Peak memory 208324 kb
Host smart-5df9768b-6e97-4cb2-b822-a59a09078a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623834890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1623834890
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3809902868
Short name T120
Test name
Test status
Simulation time 488067413 ps
CPU time 1.89 seconds
Started Aug 04 05:28:14 PM PDT 24
Finished Aug 04 05:28:16 PM PDT 24
Peak memory 200200 kb
Host smart-feba6316-25e2-48dd-9904-0b8e31c69e81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809902868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3809902868
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4005579614
Short name T603
Test name
Test status
Simulation time 121580800 ps
CPU time 1.19 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 208292 kb
Host smart-800537e0-2f1d-4277-b07b-a7b610e586f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005579614 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.4005579614
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3821848814
Short name T553
Test name
Test status
Simulation time 77189440 ps
CPU time 0.79 seconds
Started Aug 04 05:28:05 PM PDT 24
Finished Aug 04 05:28:06 PM PDT 24
Peak memory 199924 kb
Host smart-9ea96540-ee67-4cc5-b90c-0153d9d2ca83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821848814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3821848814
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.360589159
Short name T94
Test name
Test status
Simulation time 81159499 ps
CPU time 0.96 seconds
Started Aug 04 05:28:09 PM PDT 24
Finished Aug 04 05:28:10 PM PDT 24
Peak memory 200064 kb
Host smart-335676cb-e37d-4cb1-9a76-ff54739ae77c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360589159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.360589159
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1214114240
Short name T600
Test name
Test status
Simulation time 588282303 ps
CPU time 4.04 seconds
Started Aug 04 05:28:10 PM PDT 24
Finished Aug 04 05:28:15 PM PDT 24
Peak memory 208216 kb
Host smart-002e9c1d-8735-47fc-944b-759d9d006575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214114240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1214114240
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3373756574
Short name T111
Test name
Test status
Simulation time 498157215 ps
CPU time 2.12 seconds
Started Aug 04 05:28:03 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 200168 kb
Host smart-00630306-6fe5-4568-83cd-b9f3fea10826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373756574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3373756574
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1026764889
Short name T620
Test name
Test status
Simulation time 114791681 ps
CPU time 0.93 seconds
Started Aug 04 05:28:14 PM PDT 24
Finished Aug 04 05:28:15 PM PDT 24
Peak memory 200136 kb
Host smart-c387b88d-30b7-4e6e-8114-93aebe8487ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026764889 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1026764889
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.257562578
Short name T89
Test name
Test status
Simulation time 92081629 ps
CPU time 0.96 seconds
Started Aug 04 05:28:06 PM PDT 24
Finished Aug 04 05:28:07 PM PDT 24
Peak memory 199996 kb
Host smart-7df04a78-4bac-46a9-bf3d-d33002bce655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257562578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.257562578
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.171347977
Short name T557
Test name
Test status
Simulation time 158655616 ps
CPU time 1.19 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:06 PM PDT 24
Peak memory 199944 kb
Host smart-cb0f782a-a4b7-4339-b21e-f41d516f0b46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171347977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.171347977
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.596528545
Short name T572
Test name
Test status
Simulation time 96862927 ps
CPU time 1.23 seconds
Started Aug 04 05:28:03 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 208220 kb
Host smart-eeb56381-574d-4f8c-b692-bf45596c06bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596528545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.596528545
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2437009670
Short name T613
Test name
Test status
Simulation time 865243225 ps
CPU time 3.06 seconds
Started Aug 04 05:28:02 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 200212 kb
Host smart-469d1404-7765-4e8e-a361-178b5e2a21f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437009670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2437009670
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2485233158
Short name T577
Test name
Test status
Simulation time 154287699 ps
CPU time 1.34 seconds
Started Aug 04 05:28:08 PM PDT 24
Finished Aug 04 05:28:09 PM PDT 24
Peak memory 208424 kb
Host smart-9bb50a4a-d670-4296-81ca-3b101c64b5e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485233158 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2485233158
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2247892810
Short name T98
Test name
Test status
Simulation time 78499669 ps
CPU time 0.83 seconds
Started Aug 04 05:28:07 PM PDT 24
Finished Aug 04 05:28:08 PM PDT 24
Peak memory 200016 kb
Host smart-e30782a6-0a6d-424b-9c1b-61037abd52e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247892810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2247892810
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2188292772
Short name T570
Test name
Test status
Simulation time 132275755 ps
CPU time 1.26 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 200244 kb
Host smart-f6cb0a44-77f1-4dc2-b332-3fb61f44664f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188292772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2188292772
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.904328102
Short name T606
Test name
Test status
Simulation time 277362852 ps
CPU time 1.91 seconds
Started Aug 04 05:28:03 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 200108 kb
Host smart-c55985c6-f56f-42bf-b683-56b10c20d0e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904328102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.904328102
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1832094192
Short name T121
Test name
Test status
Simulation time 431707697 ps
CPU time 1.73 seconds
Started Aug 04 05:28:08 PM PDT 24
Finished Aug 04 05:28:10 PM PDT 24
Peak memory 200172 kb
Host smart-77562a0c-ed63-4a83-aa5b-159ff55f6e73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832094192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1832094192
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.319137485
Short name T550
Test name
Test status
Simulation time 176452254 ps
CPU time 1.2 seconds
Started Aug 04 05:28:07 PM PDT 24
Finished Aug 04 05:28:08 PM PDT 24
Peak memory 208372 kb
Host smart-d458d9bb-b3ac-44ae-9a34-9bf8ef4364e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319137485 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.319137485
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.492827547
Short name T556
Test name
Test status
Simulation time 79232122 ps
CPU time 0.84 seconds
Started Aug 04 05:28:15 PM PDT 24
Finished Aug 04 05:28:16 PM PDT 24
Peak memory 200032 kb
Host smart-535d281b-359e-43d3-a8fe-af2b1f8dc5e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492827547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.492827547
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3948784240
Short name T610
Test name
Test status
Simulation time 112912037 ps
CPU time 1.01 seconds
Started Aug 04 05:28:01 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 200084 kb
Host smart-f1ba2631-da4b-45b5-8c39-1fa2b1d55ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948784240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3948784240
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2716144007
Short name T609
Test name
Test status
Simulation time 177903409 ps
CPU time 2.58 seconds
Started Aug 04 05:28:09 PM PDT 24
Finished Aug 04 05:28:11 PM PDT 24
Peak memory 211012 kb
Host smart-9185513f-b480-4969-85e2-30363f0f3117
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716144007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2716144007
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1695338261
Short name T110
Test name
Test status
Simulation time 813490305 ps
CPU time 2.77 seconds
Started Aug 04 05:28:14 PM PDT 24
Finished Aug 04 05:28:22 PM PDT 24
Peak memory 200188 kb
Host smart-8cc61679-2d00-478c-95bd-97771a984d00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695338261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1695338261
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3974830963
Short name T574
Test name
Test status
Simulation time 412574678 ps
CPU time 2.44 seconds
Started Aug 04 05:27:58 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 208320 kb
Host smart-01d73203-479d-4edd-ac19-45d4e127d97d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974830963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
974830963
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.171184764
Short name T616
Test name
Test status
Simulation time 277622608 ps
CPU time 3.27 seconds
Started Aug 04 05:28:01 PM PDT 24
Finished Aug 04 05:28:04 PM PDT 24
Peak memory 200320 kb
Host smart-0b7eb874-d753-4a8f-a378-e84e3c788439
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171184764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.171184764
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1912787094
Short name T596
Test name
Test status
Simulation time 108234180 ps
CPU time 0.87 seconds
Started Aug 04 05:28:01 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 200160 kb
Host smart-3968a8d5-9185-4266-bbe7-07ab67de561e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912787094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
912787094
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2103197034
Short name T81
Test name
Test status
Simulation time 199400903 ps
CPU time 1.35 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 208292 kb
Host smart-bc166651-d029-41d5-b495-56f42f2487a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103197034 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2103197034
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1682408314
Short name T599
Test name
Test status
Simulation time 74491161 ps
CPU time 0.78 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 200004 kb
Host smart-6e30aab2-0e2a-46ba-9c42-75ba6be65388
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682408314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1682408314
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1561278653
Short name T65
Test name
Test status
Simulation time 222656023 ps
CPU time 1.55 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 200224 kb
Host smart-cc50fb10-67e6-4cff-a9a5-54a9e834c859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561278653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1561278653
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2430954358
Short name T583
Test name
Test status
Simulation time 176107881 ps
CPU time 2.45 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200156 kb
Host smart-17b0f183-4675-4674-b126-fd74d92d334f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430954358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2430954358
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1849459539
Short name T113
Test name
Test status
Simulation time 406827944 ps
CPU time 1.81 seconds
Started Aug 04 05:27:58 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200256 kb
Host smart-bc90076a-14cc-443b-850f-ac962af69c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849459539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1849459539
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.899595045
Short name T590
Test name
Test status
Simulation time 356231982 ps
CPU time 2.45 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 208340 kb
Host smart-c1911847-3413-4477-b76f-9f19a42af4e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899595045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.899595045
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3428804313
Short name T63
Test name
Test status
Simulation time 1990842262 ps
CPU time 9.51 seconds
Started Aug 04 05:27:54 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 200112 kb
Host smart-a5d7f8c1-e10c-4f98-981a-b96f650a7c94
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428804313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
428804313
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1891523987
Short name T602
Test name
Test status
Simulation time 127605160 ps
CPU time 0.89 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200036 kb
Host smart-8c8a4f0b-0b47-488b-977f-838a412f4589
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891523987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
891523987
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4058626674
Short name T84
Test name
Test status
Simulation time 111067587 ps
CPU time 0.99 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 200136 kb
Host smart-072909da-7844-485f-93b0-efcc09018fdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058626674 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.4058626674
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1195046378
Short name T619
Test name
Test status
Simulation time 66082081 ps
CPU time 0.85 seconds
Started Aug 04 05:27:50 PM PDT 24
Finished Aug 04 05:27:51 PM PDT 24
Peak memory 200012 kb
Host smart-b6b75828-fc49-4d87-9cfc-2414d5c7c4bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195046378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1195046378
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1408392420
Short name T67
Test name
Test status
Simulation time 77647284 ps
CPU time 0.98 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 200028 kb
Host smart-618348cf-2e77-4e7d-978d-ecc82fb0d79a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408392420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1408392420
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1563281218
Short name T594
Test name
Test status
Simulation time 110202397 ps
CPU time 1.58 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 216460 kb
Host smart-5c8bd4b1-8654-415e-b2ca-f6c79ce99330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563281218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1563281218
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1438828019
Short name T66
Test name
Test status
Simulation time 502078493 ps
CPU time 1.87 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 200248 kb
Host smart-4f1ecd4e-ab6f-4078-af5b-c01ba68868d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438828019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1438828019
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3211171135
Short name T548
Test name
Test status
Simulation time 253064505 ps
CPU time 1.72 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 199976 kb
Host smart-9597db3b-9782-46b3-ab09-9a79910d4eb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211171135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
211171135
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4153822195
Short name T549
Test name
Test status
Simulation time 277404397 ps
CPU time 3.18 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200084 kb
Host smart-79fc7ebd-c7a5-47c8-97da-031218b97a7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153822195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
153822195
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2392960624
Short name T560
Test name
Test status
Simulation time 91117343 ps
CPU time 0.82 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 200036 kb
Host smart-f1e47cb4-9364-427b-8d2e-b2a62db4ede8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392960624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
392960624
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3229404584
Short name T587
Test name
Test status
Simulation time 113779078 ps
CPU time 1.08 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 208328 kb
Host smart-2d699e82-2ee1-44f0-bdee-11e675cfc4eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229404584 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3229404584
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3441690878
Short name T64
Test name
Test status
Simulation time 68362258 ps
CPU time 0.75 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 200004 kb
Host smart-c3616c52-ecfc-4e7e-b6b4-67c2f7a5ccec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441690878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3441690878
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3979872237
Short name T579
Test name
Test status
Simulation time 224706413 ps
CPU time 1.48 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200208 kb
Host smart-ea22a5ff-db3f-4d20-808c-56c066e64fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979872237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3979872237
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3217978831
Short name T576
Test name
Test status
Simulation time 303790849 ps
CPU time 2.06 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:02 PM PDT 24
Peak memory 208344 kb
Host smart-0ba08cf9-324d-491b-af67-c1839cc9b381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217978831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3217978831
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2676792712
Short name T612
Test name
Test status
Simulation time 181164536 ps
CPU time 1.72 seconds
Started Aug 04 05:27:58 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 208520 kb
Host smart-ea2e5334-f36e-4fd9-9f3e-8f8a657652da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676792712 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2676792712
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3042290823
Short name T608
Test name
Test status
Simulation time 71828790 ps
CPU time 0.86 seconds
Started Aug 04 05:28:04 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 199960 kb
Host smart-87ee6aea-53e8-436d-ae01-e39dc93ccaf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042290823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3042290823
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3092340080
Short name T563
Test name
Test status
Simulation time 94231281 ps
CPU time 1.19 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 200100 kb
Host smart-fa3091c6-364b-48d0-9b5b-c5e31cd85233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092340080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3092340080
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1198189416
Short name T567
Test name
Test status
Simulation time 878085282 ps
CPU time 3.1 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200156 kb
Host smart-28b3f668-0dde-4149-b995-dbc5725fb97f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198189416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1198189416
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1266852838
Short name T582
Test name
Test status
Simulation time 110813982 ps
CPU time 0.93 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200124 kb
Host smart-8cda2330-6ba5-4736-8466-6a031fd63e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266852838 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1266852838
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.287114481
Short name T586
Test name
Test status
Simulation time 86330136 ps
CPU time 0.9 seconds
Started Aug 04 05:27:58 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 200068 kb
Host smart-a226753e-aeff-48c7-8e6a-8560eb75d763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287114481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.287114481
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2805081548
Short name T588
Test name
Test status
Simulation time 75404386 ps
CPU time 0.96 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:27:56 PM PDT 24
Peak memory 200116 kb
Host smart-5987384e-b216-44e5-8e92-eec7ba3fe09f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805081548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2805081548
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3521217681
Short name T561
Test name
Test status
Simulation time 427649783 ps
CPU time 3.17 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:03 PM PDT 24
Peak memory 212212 kb
Host smart-7a6c9fc6-f2cd-49e2-85b0-e389056a0c87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521217681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3521217681
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1478090669
Short name T571
Test name
Test status
Simulation time 145076937 ps
CPU time 1.18 seconds
Started Aug 04 05:28:07 PM PDT 24
Finished Aug 04 05:28:09 PM PDT 24
Peak memory 208380 kb
Host smart-dab19e57-6fbf-4362-8c04-d024e14a34a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478090669 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1478090669
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2512812908
Short name T611
Test name
Test status
Simulation time 77243459 ps
CPU time 0.9 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 199944 kb
Host smart-87d90a48-6228-4a99-8e67-94388fd546e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512812908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2512812908
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2570997327
Short name T607
Test name
Test status
Simulation time 134945955 ps
CPU time 1.1 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 200028 kb
Host smart-6d4bc71e-6aaf-4a35-862a-7f2b688d1518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570997327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2570997327
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1356555627
Short name T568
Test name
Test status
Simulation time 397035331 ps
CPU time 3.12 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 208372 kb
Host smart-0454dff1-c846-42d0-a80c-2020426467bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356555627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1356555627
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.170264675
Short name T108
Test name
Test status
Simulation time 433875200 ps
CPU time 1.76 seconds
Started Aug 04 05:27:58 PM PDT 24
Finished Aug 04 05:28:00 PM PDT 24
Peak memory 200296 kb
Host smart-f52a6b84-c4e7-4f93-a4bb-44bf99efbb0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170264675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
170264675
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2692430772
Short name T104
Test name
Test status
Simulation time 192833587 ps
CPU time 2.06 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:59 PM PDT 24
Peak memory 214084 kb
Host smart-772e6523-3837-4aae-a561-528dd5795a03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692430772 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2692430772
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1860253434
Short name T99
Test name
Test status
Simulation time 86565038 ps
CPU time 0.82 seconds
Started Aug 04 05:27:57 PM PDT 24
Finished Aug 04 05:27:58 PM PDT 24
Peak memory 200072 kb
Host smart-e2c7c307-ec03-469a-999d-9a5fcd0a8516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860253434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1860253434
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.299770100
Short name T566
Test name
Test status
Simulation time 225909702 ps
CPU time 1.52 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 200180 kb
Host smart-519d7abd-ee0d-4d16-bd22-8c585d284647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299770100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.299770100
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2358918015
Short name T558
Test name
Test status
Simulation time 246363861 ps
CPU time 1.85 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 208376 kb
Host smart-93dbcd7a-6daf-426c-b89c-5ee540d16c36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358918015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2358918015
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.401042017
Short name T86
Test name
Test status
Simulation time 951212298 ps
CPU time 3.06 seconds
Started Aug 04 05:28:00 PM PDT 24
Finished Aug 04 05:28:04 PM PDT 24
Peak memory 200232 kb
Host smart-aca77a2e-e59b-423e-8c8f-067cb75e0365
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401042017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
401042017
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.523494245
Short name T82
Test name
Test status
Simulation time 166830769 ps
CPU time 1.55 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 208436 kb
Host smart-37ba1809-89d8-4457-aa80-053bdc36c2f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523494245 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.523494245
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3330887367
Short name T552
Test name
Test status
Simulation time 67070096 ps
CPU time 0.8 seconds
Started Aug 04 05:27:56 PM PDT 24
Finished Aug 04 05:27:56 PM PDT 24
Peak memory 200016 kb
Host smart-00b74b01-e016-4dad-bb03-3025930c6a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330887367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3330887367
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3739013271
Short name T96
Test name
Test status
Simulation time 102664995 ps
CPU time 1.28 seconds
Started Aug 04 05:27:59 PM PDT 24
Finished Aug 04 05:28:01 PM PDT 24
Peak memory 200228 kb
Host smart-b255effa-60b5-4142-8bc3-1f94f912fb50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739013271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3739013271
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2372485510
Short name T112
Test name
Test status
Simulation time 446487653 ps
CPU time 3.24 seconds
Started Aug 04 05:28:01 PM PDT 24
Finished Aug 04 05:28:05 PM PDT 24
Peak memory 208520 kb
Host smart-2ef98086-da2a-4e34-92fa-cc2aa7bad1f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372485510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2372485510
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3020195163
Short name T578
Test name
Test status
Simulation time 475325781 ps
CPU time 1.9 seconds
Started Aug 04 05:27:55 PM PDT 24
Finished Aug 04 05:27:57 PM PDT 24
Peak memory 200240 kb
Host smart-978d53f4-59c1-44ea-ba92-a9ed6560e341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020195163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3020195163
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3038938444
Short name T438
Test name
Test status
Simulation time 56785128 ps
CPU time 0.72 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 200016 kb
Host smart-53aeb542-ae1d-470e-ac62-19e2d89f7960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038938444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3038938444
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1058113901
Short name T34
Test name
Test status
Simulation time 2371628247 ps
CPU time 8.18 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 217832 kb
Host smart-58950270-b5f4-4b06-8216-e194546dd1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058113901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1058113901
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1673865589
Short name T396
Test name
Test status
Simulation time 244529748 ps
CPU time 1.03 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 217500 kb
Host smart-55c3d9de-5b23-4a22-a220-dfdaba2a3aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673865589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1673865589
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3925852761
Short name T363
Test name
Test status
Simulation time 247249112 ps
CPU time 0.93 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 200140 kb
Host smart-2a51fe6a-4d4c-4f18-99b5-a3ef4c3b866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925852761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3925852761
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2228549903
Short name T399
Test name
Test status
Simulation time 966827874 ps
CPU time 4.61 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 200588 kb
Host smart-a6a35e03-c09a-44cb-a69d-7d7221cda46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228549903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2228549903
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3142144255
Short name T372
Test name
Test status
Simulation time 144575277 ps
CPU time 1.11 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 200352 kb
Host smart-33bb46b0-10ce-4114-b5ed-f571381815a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142144255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3142144255
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2070163305
Short name T139
Test name
Test status
Simulation time 244115194 ps
CPU time 1.6 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 200524 kb
Host smart-0f087197-578c-429a-9dc1-ca3ed5cf3c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070163305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2070163305
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3232960294
Short name T456
Test name
Test status
Simulation time 4908819014 ps
CPU time 22.75 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 208712 kb
Host smart-49954686-028a-486d-a5a6-3412d237de86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232960294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3232960294
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.2184108451
Short name T275
Test name
Test status
Simulation time 114612798 ps
CPU time 1.46 seconds
Started Aug 04 05:35:15 PM PDT 24
Finished Aug 04 05:35:17 PM PDT 24
Peak memory 200508 kb
Host smart-ff0c3655-b43c-46f0-9a04-d7405e7719f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184108451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2184108451
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.4126708619
Short name T283
Test name
Test status
Simulation time 62074288 ps
CPU time 0.74 seconds
Started Aug 04 05:35:23 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 200368 kb
Host smart-6b1c1d02-7890-45b3-a249-4145a201f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126708619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.4126708619
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.886210993
Short name T517
Test name
Test status
Simulation time 66816138 ps
CPU time 0.78 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:28 PM PDT 24
Peak memory 200040 kb
Host smart-bd46c28d-a3c2-44df-9944-c56d26747142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886210993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.886210993
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.977840084
Short name T59
Test name
Test status
Simulation time 1217744751 ps
CPU time 5.34 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 216772 kb
Host smart-6318bf1e-f96d-420e-9c1c-66d3c9208d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977840084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.977840084
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.288199325
Short name T263
Test name
Test status
Simulation time 244118572 ps
CPU time 1.05 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 217508 kb
Host smart-9d14cdde-acd2-452a-b58d-8735887e9a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288199325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.288199325
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3749681480
Short name T322
Test name
Test status
Simulation time 102664923 ps
CPU time 0.82 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 200160 kb
Host smart-7e9d8baa-5737-4d33-9495-1bc92529eee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749681480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3749681480
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2120740866
Short name T77
Test name
Test status
Simulation time 16523654010 ps
CPU time 28.97 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 217424 kb
Host smart-8ac2ce8d-7067-43f5-95b1-a05a2e0f5a34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120740866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2120740866
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2200615483
Short name T285
Test name
Test status
Simulation time 168289172 ps
CPU time 1.12 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200336 kb
Host smart-5e5cdff7-c0bc-4e58-beef-be76939e3bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200615483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2200615483
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.252789567
Short name T451
Test name
Test status
Simulation time 117115005 ps
CPU time 1.17 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 200508 kb
Host smart-34dd240a-99a7-4ec4-9c15-6d79d6eb45e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252789567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.252789567
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2558131310
Short name T459
Test name
Test status
Simulation time 6656168528 ps
CPU time 29.91 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:54 PM PDT 24
Peak memory 208772 kb
Host smart-14781349-051d-42ee-98fe-be8a3cf40fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558131310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2558131310
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.142650126
Short name T442
Test name
Test status
Simulation time 141249704 ps
CPU time 1.65 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:21 PM PDT 24
Peak memory 200152 kb
Host smart-fc7424bc-3e3e-469a-89ea-7dca9bdf7de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142650126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.142650126
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3985510557
Short name T188
Test name
Test status
Simulation time 185575237 ps
CPU time 1.38 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 200312 kb
Host smart-29036477-ac1d-4dee-8fbe-5b9b564e646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985510557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3985510557
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.4290053395
Short name T262
Test name
Test status
Simulation time 74830738 ps
CPU time 0.8 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 200176 kb
Host smart-8efd44af-ac20-4ecc-bca7-8901bef3219e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290053395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4290053395
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.865220724
Short name T449
Test name
Test status
Simulation time 1219919998 ps
CPU time 5.58 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 217380 kb
Host smart-7677d0ae-064c-40a2-b7a8-7362427fab9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865220724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.865220724
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1676940231
Short name T269
Test name
Test status
Simulation time 243784796 ps
CPU time 1.17 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 217396 kb
Host smart-4c02c45d-8e3e-4296-aa24-abff11365139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676940231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1676940231
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3787771271
Short name T140
Test name
Test status
Simulation time 1498410142 ps
CPU time 5.84 seconds
Started Aug 04 05:35:29 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200528 kb
Host smart-51f3ab10-eec9-4f30-bf5d-016e66e80cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787771271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3787771271
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1865519365
Short name T149
Test name
Test status
Simulation time 220244618 ps
CPU time 1.41 seconds
Started Aug 04 05:35:29 PM PDT 24
Finished Aug 04 05:35:30 PM PDT 24
Peak memory 200512 kb
Host smart-16f61131-374f-4642-bee8-b548c148b604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865519365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1865519365
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.227805922
Short name T538
Test name
Test status
Simulation time 6943620334 ps
CPU time 27.04 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:36:00 PM PDT 24
Peak memory 200628 kb
Host smart-7c6b11d2-c55d-48f8-8ef1-0bb68690033e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227805922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.227805922
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.260187459
Short name T240
Test name
Test status
Simulation time 328196983 ps
CPU time 2.27 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 200200 kb
Host smart-93049a8e-500c-429b-8125-72e5d4669577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260187459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.260187459
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1300041161
Short name T76
Test name
Test status
Simulation time 72415180 ps
CPU time 0.84 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:28 PM PDT 24
Peak memory 200168 kb
Host smart-68337db3-943f-49c7-916e-180fac23406f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300041161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1300041161
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4586121
Short name T482
Test name
Test status
Simulation time 2191378224 ps
CPU time 7.52 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 217924 kb
Host smart-d12d6815-fc29-4c04-bc53-ae9b45fa4e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4586121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4586121
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.616421742
Short name T73
Test name
Test status
Simulation time 245080448 ps
CPU time 1.06 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 217536 kb
Host smart-3ba9d7cf-7a09-4237-a303-ced0a337c80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616421742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.616421742
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2930509108
Short name T235
Test name
Test status
Simulation time 219409847 ps
CPU time 0.88 seconds
Started Aug 04 05:35:35 PM PDT 24
Finished Aug 04 05:35:36 PM PDT 24
Peak memory 200168 kb
Host smart-53c3634d-65ad-4b4f-a540-3db1531c6446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930509108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2930509108
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.3886526540
Short name T209
Test name
Test status
Simulation time 1027167311 ps
CPU time 4.7 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:33 PM PDT 24
Peak memory 200564 kb
Host smart-6d529458-0f31-49f2-b9b6-24e9615c1c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886526540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3886526540
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.4102557963
Short name T361
Test name
Test status
Simulation time 176279574 ps
CPU time 1.2 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200344 kb
Host smart-b88a2a46-2f14-4e02-ab94-1a50ee849641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102557963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.4102557963
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1129645768
Short name T257
Test name
Test status
Simulation time 116230092 ps
CPU time 1.09 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 200460 kb
Host smart-6e520117-9749-4e8d-b808-4a2f6349023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129645768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1129645768
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.602971171
Short name T293
Test name
Test status
Simulation time 1008085887 ps
CPU time 5.2 seconds
Started Aug 04 05:35:29 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200536 kb
Host smart-748658c3-4825-40d5-b771-ec6bca1abf90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602971171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.602971171
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1970585350
Short name T331
Test name
Test status
Simulation time 522986911 ps
CPU time 3.02 seconds
Started Aug 04 05:35:29 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 200296 kb
Host smart-4ab1ee23-8b80-4e16-ab08-a35c0a37b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970585350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1970585350
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3471740797
Short name T347
Test name
Test status
Simulation time 145166131 ps
CPU time 1.02 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 200356 kb
Host smart-ba63a8cf-c1b3-4de8-a1ab-5c31e37b5a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471740797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3471740797
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3836504267
Short name T236
Test name
Test status
Simulation time 72325645 ps
CPU time 0.83 seconds
Started Aug 04 05:35:34 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200164 kb
Host smart-c9627387-0564-429e-aeec-8ae6681a1f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836504267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3836504267
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3472979652
Short name T375
Test name
Test status
Simulation time 244078728 ps
CPU time 1.15 seconds
Started Aug 04 05:35:31 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 217528 kb
Host smart-1f27eaae-3912-4f43-99f6-e8a2228e2b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472979652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3472979652
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2061355922
Short name T463
Test name
Test status
Simulation time 91743611 ps
CPU time 0.8 seconds
Started Aug 04 05:35:31 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 200148 kb
Host smart-fb72aeb9-881e-45fb-8efe-e1e7507efea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061355922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2061355922
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.965401871
Short name T181
Test name
Test status
Simulation time 1359376382 ps
CPU time 5.54 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:36 PM PDT 24
Peak memory 200576 kb
Host smart-4e1c6e33-c264-48ab-a2d6-886fa97ebd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965401871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.965401871
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3995272089
Short name T340
Test name
Test status
Simulation time 181698192 ps
CPU time 1.19 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:31 PM PDT 24
Peak memory 200300 kb
Host smart-c13cce39-c32c-40b8-9a1b-87d6f29297d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995272089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3995272089
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3996274984
Short name T466
Test name
Test status
Simulation time 246317120 ps
CPU time 1.54 seconds
Started Aug 04 05:35:35 PM PDT 24
Finished Aug 04 05:35:37 PM PDT 24
Peak memory 200456 kb
Host smart-3fa7edb3-4fdc-4333-bb0b-3d7e537a6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996274984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3996274984
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.1173923702
Short name T135
Test name
Test status
Simulation time 306404255 ps
CPU time 1.67 seconds
Started Aug 04 05:35:31 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 200076 kb
Host smart-f81f03ea-bca9-4f88-8f24-b420fcd30b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173923702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1173923702
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3743001105
Short name T500
Test name
Test status
Simulation time 268364580 ps
CPU time 1.89 seconds
Started Aug 04 05:35:35 PM PDT 24
Finished Aug 04 05:35:37 PM PDT 24
Peak memory 200216 kb
Host smart-12484402-43c7-415a-a631-aa3008dca41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743001105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3743001105
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3729264900
Short name T487
Test name
Test status
Simulation time 97830620 ps
CPU time 0.82 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 200332 kb
Host smart-f1c32677-4826-4b7b-8c93-9ff3b5990a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729264900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3729264900
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.18708630
Short name T391
Test name
Test status
Simulation time 69486256 ps
CPU time 0.74 seconds
Started Aug 04 05:35:31 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 199948 kb
Host smart-a745accb-be53-4f08-934f-c32b8c593bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18708630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.18708630
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.4243021741
Short name T57
Test name
Test status
Simulation time 1884547030 ps
CPU time 7.24 seconds
Started Aug 04 05:35:34 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 216756 kb
Host smart-d8527e96-a5e2-4522-926e-0d3e3815c895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243021741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4243021741
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1074995423
Short name T227
Test name
Test status
Simulation time 244867934 ps
CPU time 1.06 seconds
Started Aug 04 05:35:31 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 217532 kb
Host smart-3339d7e8-2dd8-428f-9dee-bd8b9519d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074995423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1074995423
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2553598350
Short name T432
Test name
Test status
Simulation time 126871864 ps
CPU time 0.79 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 200132 kb
Host smart-e8f5cfb9-4d3e-4daf-8391-f622a093fcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553598350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2553598350
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3762850788
Short name T220
Test name
Test status
Simulation time 1327158087 ps
CPU time 5.1 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 200448 kb
Host smart-adde9bcb-8fc7-4b54-8457-7ddd685cc084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762850788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3762850788
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1294221
Short name T478
Test name
Test status
Simulation time 145539279 ps
CPU time 1.1 seconds
Started Aug 04 05:35:35 PM PDT 24
Finished Aug 04 05:35:36 PM PDT 24
Peak memory 200364 kb
Host smart-b5cfffb2-6dca-4539-ab52-2c15282edf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1294221
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1841090080
Short name T177
Test name
Test status
Simulation time 123611431 ps
CPU time 1.2 seconds
Started Aug 04 05:35:36 PM PDT 24
Finished Aug 04 05:35:37 PM PDT 24
Peak memory 200512 kb
Host smart-16a247f0-e49e-4158-a6cf-f03b8fc723a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841090080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1841090080
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1999358930
Short name T53
Test name
Test status
Simulation time 8517594599 ps
CPU time 36.26 seconds
Started Aug 04 05:35:32 PM PDT 24
Finished Aug 04 05:36:08 PM PDT 24
Peak memory 208820 kb
Host smart-0371cf62-31e7-42dc-8d1a-3ed9626c4b41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999358930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1999358930
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1260067562
Short name T406
Test name
Test status
Simulation time 387663582 ps
CPU time 2.3 seconds
Started Aug 04 05:35:31 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 200300 kb
Host smart-c3f94f33-f77e-4648-b5f8-b764d3ea804c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260067562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1260067562
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3129203
Short name T124
Test name
Test status
Simulation time 171624705 ps
CPU time 1.16 seconds
Started Aug 04 05:35:32 PM PDT 24
Finished Aug 04 05:35:33 PM PDT 24
Peak memory 200348 kb
Host smart-9efc7211-8bab-4ae4-89e5-51cff6174a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3129203
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.4020347038
Short name T284
Test name
Test status
Simulation time 65731260 ps
CPU time 0.78 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 200168 kb
Host smart-2495ca39-d931-4e5a-8c04-f5885a2f440b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020347038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4020347038
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2449241882
Short name T339
Test name
Test status
Simulation time 1226960460 ps
CPU time 6 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:47 PM PDT 24
Peak memory 221628 kb
Host smart-938bbb3b-3e1d-47bc-8ee1-e1e778c01383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449241882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2449241882
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1839854972
Short name T367
Test name
Test status
Simulation time 245231206 ps
CPU time 1.04 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:31 PM PDT 24
Peak memory 217532 kb
Host smart-15bae2f3-688f-48b4-9c7a-aa7f9c21894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839854972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1839854972
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1644106612
Short name T21
Test name
Test status
Simulation time 164865283 ps
CPU time 0.91 seconds
Started Aug 04 05:35:34 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200168 kb
Host smart-1fe16ef0-06b3-4d31-9158-fb66650a188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644106612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1644106612
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1079825336
Short name T394
Test name
Test status
Simulation time 1955171549 ps
CPU time 7.5 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 200536 kb
Host smart-f8edd28b-60d1-47f1-b300-87f04d75344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079825336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1079825336
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3468244129
Short name T142
Test name
Test status
Simulation time 111410946 ps
CPU time 1.04 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:31 PM PDT 24
Peak memory 200332 kb
Host smart-7cc81346-6123-4a97-83fa-da34006981fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468244129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3468244129
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3838728968
Short name T343
Test name
Test status
Simulation time 195992256 ps
CPU time 1.35 seconds
Started Aug 04 05:35:29 PM PDT 24
Finished Aug 04 05:35:30 PM PDT 24
Peak memory 200576 kb
Host smart-e7430a13-06e8-4273-ad2e-12547b25b568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838728968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3838728968
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2889441938
Short name T50
Test name
Test status
Simulation time 3045838691 ps
CPU time 15.08 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 200568 kb
Host smart-5af6443f-f4bb-4e27-a42f-16e6b043fd32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889441938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2889441938
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2317854608
Short name T481
Test name
Test status
Simulation time 472775332 ps
CPU time 2.62 seconds
Started Aug 04 05:35:36 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 200312 kb
Host smart-75209dd7-740f-470a-9166-3689b7b9acc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317854608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2317854608
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2454979659
Short name T241
Test name
Test status
Simulation time 146568518 ps
CPU time 1.16 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:31 PM PDT 24
Peak memory 200300 kb
Host smart-b25ba7dd-1528-405a-a2fc-4104e589bf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454979659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2454979659
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2331533199
Short name T352
Test name
Test status
Simulation time 76069107 ps
CPU time 0.75 seconds
Started Aug 04 05:35:32 PM PDT 24
Finished Aug 04 05:35:33 PM PDT 24
Peak memory 200144 kb
Host smart-d57f77b6-e132-4a05-add8-122499f83188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331533199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2331533199
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2813174125
Short name T29
Test name
Test status
Simulation time 1220711078 ps
CPU time 5.59 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 221672 kb
Host smart-40507ced-7b94-433c-8b7d-768044071d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813174125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2813174125
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3090017233
Short name T531
Test name
Test status
Simulation time 244456543 ps
CPU time 1.11 seconds
Started Aug 04 05:35:38 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 217484 kb
Host smart-6ba2c9dd-a2e0-41b7-a307-e15c826f568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090017233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3090017233
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.163375203
Short name T17
Test name
Test status
Simulation time 124610672 ps
CPU time 0.81 seconds
Started Aug 04 05:35:32 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 200156 kb
Host smart-6bb44856-3896-4344-9135-ac579254368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163375203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.163375203
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3401100538
Short name T470
Test name
Test status
Simulation time 1672960311 ps
CPU time 5.97 seconds
Started Aug 04 05:35:37 PM PDT 24
Finished Aug 04 05:35:43 PM PDT 24
Peak memory 200620 kb
Host smart-9c3e532c-360e-4833-be9d-d224a8e25388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401100538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3401100538
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2976407108
Short name T441
Test name
Test status
Simulation time 96036225 ps
CPU time 0.97 seconds
Started Aug 04 05:35:38 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 200360 kb
Host smart-08030c0d-8cfa-4b93-aee9-e06147c151a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976407108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2976407108
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.541389748
Short name T193
Test name
Test status
Simulation time 245331486 ps
CPU time 1.44 seconds
Started Aug 04 05:35:32 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 200464 kb
Host smart-e6bb78a9-7e0d-45f2-a2ee-3ac638c46d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541389748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.541389748
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3074652822
Short name T373
Test name
Test status
Simulation time 5986379788 ps
CPU time 21.28 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:36:05 PM PDT 24
Peak memory 208820 kb
Host smart-ea57deb6-d364-4234-b374-77998fdffeb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074652822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3074652822
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2474178364
Short name T382
Test name
Test status
Simulation time 466458867 ps
CPU time 2.41 seconds
Started Aug 04 05:35:35 PM PDT 24
Finished Aug 04 05:35:37 PM PDT 24
Peak memory 200304 kb
Host smart-05f881b3-916b-47bb-9e4f-3660d50526a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474178364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2474178364
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2756283956
Short name T160
Test name
Test status
Simulation time 133899354 ps
CPU time 1.11 seconds
Started Aug 04 05:35:37 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 200356 kb
Host smart-e9f4eb64-bcf7-4509-9eec-d01c302bc7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756283956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2756283956
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3608307248
Short name T231
Test name
Test status
Simulation time 57362739 ps
CPU time 0.75 seconds
Started Aug 04 05:35:38 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 200164 kb
Host smart-aadb5162-4384-48c2-8e1c-1f9b638d5e7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608307248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3608307248
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4231335998
Short name T433
Test name
Test status
Simulation time 1895670116 ps
CPU time 7.02 seconds
Started Aug 04 05:35:36 PM PDT 24
Finished Aug 04 05:35:44 PM PDT 24
Peak memory 216856 kb
Host smart-38ac567f-b1a6-496b-afab-9c42eb6328b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231335998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4231335998
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1620460614
Short name T471
Test name
Test status
Simulation time 243953910 ps
CPU time 1.17 seconds
Started Aug 04 05:35:34 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 217488 kb
Host smart-f9f6fa18-b5b6-43b6-9bfe-c2648c5c7539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620460614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1620460614
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3378080628
Short name T20
Test name
Test status
Simulation time 128528424 ps
CPU time 0.83 seconds
Started Aug 04 05:35:36 PM PDT 24
Finished Aug 04 05:35:37 PM PDT 24
Peak memory 200128 kb
Host smart-fb74c695-6873-4e3a-9332-da8b5c8e4590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378080628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3378080628
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2048562010
Short name T290
Test name
Test status
Simulation time 1317129043 ps
CPU time 5.82 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:46 PM PDT 24
Peak memory 200548 kb
Host smart-37aafcef-6718-449b-aec7-e98896938cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048562010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2048562010
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1225092217
Short name T180
Test name
Test status
Simulation time 153247214 ps
CPU time 1.12 seconds
Started Aug 04 05:35:37 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 200368 kb
Host smart-e9b724ec-5413-48b0-9958-e6ff3691cc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225092217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1225092217
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2875755547
Short name T392
Test name
Test status
Simulation time 190569485 ps
CPU time 1.48 seconds
Started Aug 04 05:35:36 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 200484 kb
Host smart-e92a2f6f-93de-45c4-be07-3ce189c4a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875755547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2875755547
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3544654656
Short name T280
Test name
Test status
Simulation time 11039955855 ps
CPU time 43.7 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 200616 kb
Host smart-53fd7ba9-f1a2-40c1-841c-3fc63884afdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544654656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3544654656
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1013013838
Short name T371
Test name
Test status
Simulation time 398540557 ps
CPU time 2.29 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200300 kb
Host smart-243e1dd0-fada-491e-bbbc-de277da26ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013013838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1013013838
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1828024849
Short name T393
Test name
Test status
Simulation time 124748707 ps
CPU time 1.05 seconds
Started Aug 04 05:35:37 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 200300 kb
Host smart-1787e0dc-f38c-4f33-9c5c-2f2bdd978753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828024849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1828024849
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1716234425
Short name T321
Test name
Test status
Simulation time 67567787 ps
CPU time 0.81 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 200124 kb
Host smart-98a9263b-10d2-4181-aae2-d05129d3bad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716234425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1716234425
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2571089142
Short name T247
Test name
Test status
Simulation time 244865336 ps
CPU time 1.07 seconds
Started Aug 04 05:35:39 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 217448 kb
Host smart-189cbed1-3d5a-4a9c-a56f-446acfe64f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571089142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2571089142
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.888633014
Short name T473
Test name
Test status
Simulation time 121786331 ps
CPU time 0.76 seconds
Started Aug 04 05:35:39 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 200168 kb
Host smart-cd7036ff-cf00-4bc6-ae9b-d80ae1b29ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888633014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.888633014
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2461501259
Short name T489
Test name
Test status
Simulation time 1785179633 ps
CPU time 6.74 seconds
Started Aug 04 05:35:36 PM PDT 24
Finished Aug 04 05:35:43 PM PDT 24
Peak memory 200608 kb
Host smart-ebac8e40-d855-4c81-9a9d-5e548304acf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461501259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2461501259
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3119717997
Short name T243
Test name
Test status
Simulation time 187662985 ps
CPU time 1.29 seconds
Started Aug 04 05:35:34 PM PDT 24
Finished Aug 04 05:35:36 PM PDT 24
Peak memory 200344 kb
Host smart-9bfa0e29-8635-4163-b773-70a04cc9ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119717997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3119717997
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3924093946
Short name T532
Test name
Test status
Simulation time 191444316 ps
CPU time 1.4 seconds
Started Aug 04 05:35:38 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 200436 kb
Host smart-592c0801-5546-4b91-b743-b6b6898e3492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924093946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3924093946
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.4235708954
Short name T332
Test name
Test status
Simulation time 7071841486 ps
CPU time 30.95 seconds
Started Aug 04 05:35:39 PM PDT 24
Finished Aug 04 05:36:10 PM PDT 24
Peak memory 208772 kb
Host smart-8fd9bc51-1ffe-468b-9fe8-044eb758c4e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235708954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.4235708954
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.583550776
Short name T295
Test name
Test status
Simulation time 490164609 ps
CPU time 2.51 seconds
Started Aug 04 05:35:34 PM PDT 24
Finished Aug 04 05:35:37 PM PDT 24
Peak memory 200292 kb
Host smart-fe25c2e5-506b-47ec-bbad-a0953ed7f31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583550776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.583550776
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2296451735
Short name T287
Test name
Test status
Simulation time 132321043 ps
CPU time 1.05 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 200236 kb
Host smart-2fa7680e-35a4-471d-a3be-0eb718dd4278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296451735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2296451735
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1807780567
Short name T223
Test name
Test status
Simulation time 90415201 ps
CPU time 0.81 seconds
Started Aug 04 05:35:39 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 200160 kb
Host smart-fa272c6d-80b2-4ad0-af65-a03fa3fbd3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807780567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1807780567
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2328404057
Short name T503
Test name
Test status
Simulation time 1223631646 ps
CPU time 5.59 seconds
Started Aug 04 05:35:39 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 221692 kb
Host smart-3a4d287d-45c4-4c79-bcc8-85c6a676a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328404057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2328404057
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3147426068
Short name T395
Test name
Test status
Simulation time 244151926 ps
CPU time 1.05 seconds
Started Aug 04 05:35:39 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 217508 kb
Host smart-90e0a9db-00e3-4718-9ade-d1e262f98c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147426068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3147426068
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.767412520
Short name T388
Test name
Test status
Simulation time 84816508 ps
CPU time 0.76 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 200144 kb
Host smart-422edef1-387b-4d8c-93b5-a8bb6a0889b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767412520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.767412520
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1725491603
Short name T326
Test name
Test status
Simulation time 1970299013 ps
CPU time 7.93 seconds
Started Aug 04 05:35:38 PM PDT 24
Finished Aug 04 05:35:46 PM PDT 24
Peak memory 200500 kb
Host smart-ccf4e4d9-94e0-48eb-9a05-bae554605fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725491603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1725491603
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3094562431
Short name T474
Test name
Test status
Simulation time 102657975 ps
CPU time 1.06 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 200192 kb
Host smart-6b184162-41ad-4100-ae1b-0ca24a1edfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094562431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3094562431
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.737765594
Short name T528
Test name
Test status
Simulation time 226534142 ps
CPU time 1.44 seconds
Started Aug 04 05:35:36 PM PDT 24
Finished Aug 04 05:35:37 PM PDT 24
Peak memory 200376 kb
Host smart-01895002-4fac-42c7-8441-215f28981d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737765594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.737765594
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3093199853
Short name T175
Test name
Test status
Simulation time 3914678063 ps
CPU time 17.52 seconds
Started Aug 04 05:35:42 PM PDT 24
Finished Aug 04 05:36:00 PM PDT 24
Peak memory 200588 kb
Host smart-89cd5693-6d29-450d-9251-51909fdeb330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093199853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3093199853
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.239718420
Short name T408
Test name
Test status
Simulation time 392204795 ps
CPU time 2.3 seconds
Started Aug 04 05:35:38 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 200308 kb
Host smart-bbc1ffd6-f414-4fb6-b821-5c613721f330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239718420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.239718420
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3769715557
Short name T419
Test name
Test status
Simulation time 76955539 ps
CPU time 0.83 seconds
Started Aug 04 05:35:37 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 200296 kb
Host smart-e88f6e75-ec60-4337-ad99-f8e9aca0663f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769715557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3769715557
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1047134074
Short name T221
Test name
Test status
Simulation time 56438536 ps
CPU time 0.76 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:35:49 PM PDT 24
Peak memory 200340 kb
Host smart-ae2de9ef-26c4-4dc0-a245-505e2342c5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047134074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1047134074
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3848457819
Short name T501
Test name
Test status
Simulation time 1883120641 ps
CPU time 7.91 seconds
Started Aug 04 05:35:39 PM PDT 24
Finished Aug 04 05:35:47 PM PDT 24
Peak memory 221736 kb
Host smart-be7bca44-1ff1-4e54-8dd4-8db6ca5bdf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848457819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3848457819
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2046891075
Short name T485
Test name
Test status
Simulation time 244404416 ps
CPU time 1.14 seconds
Started Aug 04 05:35:41 PM PDT 24
Finished Aug 04 05:35:42 PM PDT 24
Peak memory 217548 kb
Host smart-4f558834-3493-4cb6-a684-c01dd3e3b8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046891075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2046891075
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.184655777
Short name T458
Test name
Test status
Simulation time 153324013 ps
CPU time 0.94 seconds
Started Aug 04 05:35:38 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 200156 kb
Host smart-bded4521-a1d9-4aef-8527-3abeef709495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184655777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.184655777
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.141369149
Short name T281
Test name
Test status
Simulation time 1543927311 ps
CPU time 5.91 seconds
Started Aug 04 05:35:41 PM PDT 24
Finished Aug 04 05:35:47 PM PDT 24
Peak memory 200552 kb
Host smart-c83d5a75-34dd-486a-b170-5671d138e800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141369149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.141369149
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3851824678
Short name T152
Test name
Test status
Simulation time 98871633 ps
CPU time 0.95 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:35:44 PM PDT 24
Peak memory 200368 kb
Host smart-deaafe10-92c5-444f-be75-9bf7880c2fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851824678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3851824678
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1184066542
Short name T242
Test name
Test status
Simulation time 249988641 ps
CPU time 1.45 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:42 PM PDT 24
Peak memory 200524 kb
Host smart-a6f28f5f-0f4c-4ab0-8dca-7bd9d1865470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184066542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1184066542
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2567420198
Short name T91
Test name
Test status
Simulation time 2540211762 ps
CPU time 8.83 seconds
Started Aug 04 05:35:42 PM PDT 24
Finished Aug 04 05:35:50 PM PDT 24
Peak memory 200844 kb
Host smart-03278865-3517-42bc-8aba-8907e4848f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567420198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2567420198
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1700427301
Short name T137
Test name
Test status
Simulation time 356624502 ps
CPU time 2.48 seconds
Started Aug 04 05:35:41 PM PDT 24
Finished Aug 04 05:35:44 PM PDT 24
Peak memory 200472 kb
Host smart-71bee815-3369-4e58-acc5-8fb522fcf25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700427301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1700427301
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4145620254
Short name T468
Test name
Test status
Simulation time 109163826 ps
CPU time 0.98 seconds
Started Aug 04 05:35:39 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 200352 kb
Host smart-ba28ab34-1a66-40e1-a378-07955a48ef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145620254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4145620254
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1341652553
Short name T496
Test name
Test status
Simulation time 58410791 ps
CPU time 0.69 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 200188 kb
Host smart-c3c816d6-cc09-4601-89fc-f82d24541e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341652553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1341652553
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.688954127
Short name T488
Test name
Test status
Simulation time 1222408296 ps
CPU time 5.81 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 217536 kb
Host smart-3462e827-e603-4db2-8209-ec5684e85660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688954127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.688954127
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3023602428
Short name T172
Test name
Test status
Simulation time 244070936 ps
CPU time 1.01 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:21 PM PDT 24
Peak memory 216860 kb
Host smart-99c348ee-ee08-4202-93c2-0643dc7bf867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023602428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3023602428
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2934934502
Short name T267
Test name
Test status
Simulation time 143497193 ps
CPU time 0.79 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 200144 kb
Host smart-516be945-9dd2-4f1a-b08f-1023344871a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934934502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2934934502
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.929570198
Short name T368
Test name
Test status
Simulation time 1356702340 ps
CPU time 5.8 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200028 kb
Host smart-74abc65e-c5e0-46a9-8791-04ab212321a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929570198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.929570198
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1954206085
Short name T75
Test name
Test status
Simulation time 16718918628 ps
CPU time 24.56 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:44 PM PDT 24
Peak memory 217032 kb
Host smart-83df8ca5-2875-4eaf-8b80-b1c54a442055
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954206085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1954206085
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1685931117
Short name T219
Test name
Test status
Simulation time 187906054 ps
CPU time 1.21 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 200196 kb
Host smart-57c43746-1bba-4922-b4e0-fc4123d29769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685931117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1685931117
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.671881763
Short name T42
Test name
Test status
Simulation time 115621704 ps
CPU time 1.17 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 200480 kb
Host smart-1fe6a3fc-dbdd-4190-9f29-ab4a2cd46ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671881763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.671881763
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.457260285
Short name T54
Test name
Test status
Simulation time 12618256547 ps
CPU time 46.79 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:36:05 PM PDT 24
Peak memory 208716 kb
Host smart-8cfcffe3-3702-43d4-b9a1-f769c90a26f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457260285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.457260285
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.957585363
Short name T49
Test name
Test status
Simulation time 553292390 ps
CPU time 3 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 200260 kb
Host smart-4065aad3-9202-4c76-94b6-fd18cc2ec5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957585363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.957585363
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4118937270
Short name T325
Test name
Test status
Simulation time 113818118 ps
CPU time 1.04 seconds
Started Aug 04 05:35:23 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 200248 kb
Host smart-75be1904-2a5f-482f-b59e-67dbf42a6d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118937270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4118937270
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3309788795
Short name T502
Test name
Test status
Simulation time 57950440 ps
CPU time 0.76 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:35:44 PM PDT 24
Peak memory 200160 kb
Host smart-ba72f7c3-bbb0-4451-860a-0282c080de88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309788795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3309788795
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3549165140
Short name T55
Test name
Test status
Simulation time 1228049334 ps
CPU time 5.54 seconds
Started Aug 04 05:35:42 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 217300 kb
Host smart-c176c4e8-cfdf-44ac-a3d3-72d103e25b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549165140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3549165140
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1553884393
Short name T316
Test name
Test status
Simulation time 244704753 ps
CPU time 1.09 seconds
Started Aug 04 05:35:48 PM PDT 24
Finished Aug 04 05:35:49 PM PDT 24
Peak memory 217572 kb
Host smart-42dd5ac6-fb4b-46e9-bf2b-0c09646a79fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553884393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1553884393
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3656397531
Short name T5
Test name
Test status
Simulation time 212856789 ps
CPU time 0.93 seconds
Started Aug 04 05:35:42 PM PDT 24
Finished Aug 04 05:35:43 PM PDT 24
Peak memory 200328 kb
Host smart-13b06531-3d03-44d6-8254-bacb5ce4173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656397531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3656397531
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3927999088
Short name T183
Test name
Test status
Simulation time 1039163221 ps
CPU time 4.97 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 200532 kb
Host smart-6762fad6-13e6-4915-a91c-626038fb6b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927999088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3927999088
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.803780738
Short name T176
Test name
Test status
Simulation time 181241757 ps
CPU time 1.2 seconds
Started Aug 04 05:35:38 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 200348 kb
Host smart-c8669f14-b304-4335-bd1c-5a687f4cf972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803780738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.803780738
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1602552135
Short name T222
Test name
Test status
Simulation time 118453136 ps
CPU time 1.25 seconds
Started Aug 04 05:35:52 PM PDT 24
Finished Aug 04 05:35:53 PM PDT 24
Peak memory 200488 kb
Host smart-f0801d43-13d2-4c33-afcf-37a5eb76efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602552135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1602552135
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3332612371
Short name T259
Test name
Test status
Simulation time 136658024 ps
CPU time 1.05 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:35:44 PM PDT 24
Peak memory 200164 kb
Host smart-719e21a4-8cb2-4bc7-9e00-288cb0333e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332612371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3332612371
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.143208948
Short name T204
Test name
Test status
Simulation time 370733762 ps
CPU time 2.12 seconds
Started Aug 04 05:35:45 PM PDT 24
Finished Aug 04 05:35:47 PM PDT 24
Peak memory 208496 kb
Host smart-d9f24855-8e56-45b0-b3d7-79ea6a3706e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143208948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.143208948
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.4084250967
Short name T409
Test name
Test status
Simulation time 110399221 ps
CPU time 0.93 seconds
Started Aug 04 05:35:44 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 200320 kb
Host smart-82e4a79c-aa3f-4b31-a1aa-2c6ab373a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084250967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4084250967
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3112310642
Short name T238
Test name
Test status
Simulation time 85416453 ps
CPU time 0.87 seconds
Started Aug 04 05:36:08 PM PDT 24
Finished Aug 04 05:36:09 PM PDT 24
Peak memory 200124 kb
Host smart-c99000b4-69ba-4c12-80b8-bbdc4c364e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112310642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3112310642
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3941997335
Short name T58
Test name
Test status
Simulation time 1897836675 ps
CPU time 7.68 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:35:51 PM PDT 24
Peak memory 220976 kb
Host smart-5b20e15f-7b19-4cbf-8a79-778646a667af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941997335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3941997335
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.138704567
Short name T200
Test name
Test status
Simulation time 244246172 ps
CPU time 1.06 seconds
Started Aug 04 05:35:48 PM PDT 24
Finished Aug 04 05:35:49 PM PDT 24
Peak memory 217480 kb
Host smart-3c94aade-fad8-4eb4-886b-705247e19c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138704567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.138704567
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.169510255
Short name T248
Test name
Test status
Simulation time 100985352 ps
CPU time 0.8 seconds
Started Aug 04 05:35:40 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 200144 kb
Host smart-3d57f465-26d1-4228-b042-8698991b8239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169510255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.169510255
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.519226368
Short name T299
Test name
Test status
Simulation time 1514084175 ps
CPU time 5.9 seconds
Started Aug 04 05:35:51 PM PDT 24
Finished Aug 04 05:35:57 PM PDT 24
Peak memory 200500 kb
Host smart-7c44aa7b-5966-4940-a7f7-348ea63b18f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519226368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.519226368
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3687578264
Short name T130
Test name
Test status
Simulation time 144784081 ps
CPU time 1.09 seconds
Started Aug 04 05:35:45 PM PDT 24
Finished Aug 04 05:35:47 PM PDT 24
Peak memory 200324 kb
Host smart-2a2db2b9-034d-4384-835c-326ea0b63ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687578264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3687578264
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1321068755
Short name T415
Test name
Test status
Simulation time 117525107 ps
CPU time 1.14 seconds
Started Aug 04 05:35:44 PM PDT 24
Finished Aug 04 05:35:46 PM PDT 24
Peak memory 200660 kb
Host smart-ec127812-90ba-4f5a-a188-dbce319c7a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321068755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1321068755
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1826554674
Short name T376
Test name
Test status
Simulation time 3821178151 ps
CPU time 17.85 seconds
Started Aug 04 05:35:46 PM PDT 24
Finished Aug 04 05:36:04 PM PDT 24
Peak memory 200868 kb
Host smart-dc618956-a205-4049-9cb3-6ae6e0653f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826554674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1826554674
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.842893895
Short name T349
Test name
Test status
Simulation time 406407031 ps
CPU time 2.3 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:35:46 PM PDT 24
Peak memory 200300 kb
Host smart-b8aab35c-1c5c-4329-9304-52b8b96811a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842893895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.842893895
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.4252413393
Short name T334
Test name
Test status
Simulation time 74746093 ps
CPU time 0.84 seconds
Started Aug 04 05:35:47 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 200544 kb
Host smart-96d40c33-8a72-42fb-b532-9d6accfe2fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252413393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.4252413393
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.921595657
Short name T533
Test name
Test status
Simulation time 86441143 ps
CPU time 0.81 seconds
Started Aug 04 05:35:47 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 200020 kb
Host smart-05e460b0-98e6-474d-9496-a4afaee01c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921595657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.921595657
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1735876517
Short name T258
Test name
Test status
Simulation time 1231864711 ps
CPU time 5.53 seconds
Started Aug 04 05:35:49 PM PDT 24
Finished Aug 04 05:35:54 PM PDT 24
Peak memory 217736 kb
Host smart-e2b5c9ff-5b82-4e2f-92ed-1640bf8f76ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735876517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1735876517
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3612080796
Short name T545
Test name
Test status
Simulation time 245993278 ps
CPU time 1.02 seconds
Started Aug 04 05:36:00 PM PDT 24
Finished Aug 04 05:36:01 PM PDT 24
Peak memory 217516 kb
Host smart-a8d4857f-654f-4ca1-ae6c-bebd6bd10fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612080796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3612080796
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4080120378
Short name T365
Test name
Test status
Simulation time 82363253 ps
CPU time 0.74 seconds
Started Aug 04 05:35:45 PM PDT 24
Finished Aug 04 05:35:46 PM PDT 24
Peak memory 200128 kb
Host smart-f4910051-2757-4852-85e3-b6005cea7af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080120378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4080120378
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2052674796
Short name T51
Test name
Test status
Simulation time 888668248 ps
CPU time 4.41 seconds
Started Aug 04 05:35:46 PM PDT 24
Finished Aug 04 05:35:50 PM PDT 24
Peak memory 200568 kb
Host smart-5897ba8a-b85c-4af5-a948-b2e92c2d5032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052674796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2052674796
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.704940636
Short name T440
Test name
Test status
Simulation time 110999242 ps
CPU time 1.02 seconds
Started Aug 04 05:35:52 PM PDT 24
Finished Aug 04 05:35:53 PM PDT 24
Peak memory 200376 kb
Host smart-d30eff27-942c-4037-b503-3db595bc387c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704940636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.704940636
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.4021047934
Short name T324
Test name
Test status
Simulation time 191397377 ps
CPU time 1.37 seconds
Started Aug 04 05:35:47 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 200468 kb
Host smart-5066a41b-681a-4991-b6c9-38793cfe73a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021047934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4021047934
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.553004220
Short name T469
Test name
Test status
Simulation time 5201115199 ps
CPU time 18.55 seconds
Started Aug 04 05:35:58 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 208816 kb
Host smart-32726168-0541-45aa-8e3c-854a280eaec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553004220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.553004220
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1420125073
Short name T217
Test name
Test status
Simulation time 340326530 ps
CPU time 2.54 seconds
Started Aug 04 05:35:51 PM PDT 24
Finished Aug 04 05:35:53 PM PDT 24
Peak memory 200296 kb
Host smart-a457fd7a-812c-4385-b3ed-04abd4b8acd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420125073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1420125073
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.861286958
Short name T212
Test name
Test status
Simulation time 69191201 ps
CPU time 0.79 seconds
Started Aug 04 05:35:47 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 200328 kb
Host smart-58b89525-1563-4734-9f5d-64ab92f04ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861286958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.861286958
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1002409286
Short name T229
Test name
Test status
Simulation time 66369826 ps
CPU time 0.72 seconds
Started Aug 04 05:35:58 PM PDT 24
Finished Aug 04 05:35:59 PM PDT 24
Peak memory 200124 kb
Host smart-e1991f54-d18e-4c16-98a0-7f8c36df2ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002409286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1002409286
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2335909432
Short name T28
Test name
Test status
Simulation time 1887180884 ps
CPU time 7.13 seconds
Started Aug 04 05:35:47 PM PDT 24
Finished Aug 04 05:35:54 PM PDT 24
Peak memory 217444 kb
Host smart-ff0de778-d451-402f-a277-a6d5daa8d0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335909432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2335909432
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3098396011
Short name T168
Test name
Test status
Simulation time 244234503 ps
CPU time 1.11 seconds
Started Aug 04 05:35:48 PM PDT 24
Finished Aug 04 05:35:54 PM PDT 24
Peak memory 217480 kb
Host smart-7175676b-4c97-4b72-b7b6-5fc86277ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098396011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3098396011
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.640738591
Short name T417
Test name
Test status
Simulation time 151531378 ps
CPU time 0.84 seconds
Started Aug 04 05:35:48 PM PDT 24
Finished Aug 04 05:35:49 PM PDT 24
Peak memory 200120 kb
Host smart-4aedc272-24d6-4665-b374-85b9a0e7b95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640738591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.640738591
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2593700553
Short name T486
Test name
Test status
Simulation time 1555589496 ps
CPU time 5.95 seconds
Started Aug 04 05:35:46 PM PDT 24
Finished Aug 04 05:35:53 PM PDT 24
Peak memory 200760 kb
Host smart-7c28af42-ff8f-4796-8131-0fbcfb0f0a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593700553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2593700553
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.349244035
Short name T490
Test name
Test status
Simulation time 161867988 ps
CPU time 1.25 seconds
Started Aug 04 05:35:51 PM PDT 24
Finished Aug 04 05:35:52 PM PDT 24
Peak memory 200288 kb
Host smart-4f2a16c0-fcb0-4005-a93f-53fbdbfe3048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349244035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.349244035
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1684707077
Short name T133
Test name
Test status
Simulation time 196331828 ps
CPU time 1.45 seconds
Started Aug 04 05:35:48 PM PDT 24
Finished Aug 04 05:35:50 PM PDT 24
Peak memory 200500 kb
Host smart-56ae734f-b63e-49e5-9902-e162dbb5309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684707077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1684707077
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.141155202
Short name T540
Test name
Test status
Simulation time 2136541980 ps
CPU time 8.06 seconds
Started Aug 04 05:35:51 PM PDT 24
Finished Aug 04 05:35:59 PM PDT 24
Peak memory 208764 kb
Host smart-bafb1e2d-d349-49c9-8439-4de138575ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141155202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.141155202
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3652466909
Short name T164
Test name
Test status
Simulation time 266027073 ps
CPU time 1.82 seconds
Started Aug 04 05:35:43 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 200288 kb
Host smart-b2fa8a79-4733-4997-8240-2c5243601b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652466909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3652466909
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2546795841
Short name T492
Test name
Test status
Simulation time 112531854 ps
CPU time 0.98 seconds
Started Aug 04 05:35:47 PM PDT 24
Finished Aug 04 05:35:48 PM PDT 24
Peak memory 200368 kb
Host smart-0fbadbbf-0259-4180-ab19-a49a78c55032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546795841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2546795841
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3444893441
Short name T282
Test name
Test status
Simulation time 58773476 ps
CPU time 0.72 seconds
Started Aug 04 05:35:58 PM PDT 24
Finished Aug 04 05:35:59 PM PDT 24
Peak memory 200180 kb
Host smart-e79df59b-57c0-42ec-9a7a-8f03081b94e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444893441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3444893441
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.31337039
Short name T536
Test name
Test status
Simulation time 1222839500 ps
CPU time 5.65 seconds
Started Aug 04 05:35:56 PM PDT 24
Finished Aug 04 05:36:02 PM PDT 24
Peak memory 221700 kb
Host smart-d4b55a68-764a-4afc-884c-a9bf53e7aa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31337039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.31337039
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.186296897
Short name T497
Test name
Test status
Simulation time 244990353 ps
CPU time 1.07 seconds
Started Aug 04 05:35:48 PM PDT 24
Finished Aug 04 05:35:49 PM PDT 24
Peak memory 217428 kb
Host smart-8a7e7061-4c65-4ca2-8f3b-2afc3e0f7240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186296897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.186296897
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3193159587
Short name T233
Test name
Test status
Simulation time 190273893 ps
CPU time 0.86 seconds
Started Aug 04 05:35:49 PM PDT 24
Finished Aug 04 05:35:50 PM PDT 24
Peak memory 200152 kb
Host smart-6e3ec8d3-b4b9-4310-a279-41c6a5d18edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193159587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3193159587
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1799172740
Short name T92
Test name
Test status
Simulation time 1294953509 ps
CPU time 5.06 seconds
Started Aug 04 05:35:51 PM PDT 24
Finished Aug 04 05:35:56 PM PDT 24
Peak memory 200556 kb
Host smart-388ca495-88a6-4714-869f-57cd505af139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799172740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1799172740
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.4067362830
Short name T404
Test name
Test status
Simulation time 172857260 ps
CPU time 1.1 seconds
Started Aug 04 05:35:57 PM PDT 24
Finished Aug 04 05:35:58 PM PDT 24
Peak memory 200312 kb
Host smart-f9c11944-19b5-4d76-bf39-714e8c8328e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067362830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.4067362830
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.837662064
Short name T143
Test name
Test status
Simulation time 253738674 ps
CPU time 1.45 seconds
Started Aug 04 05:35:56 PM PDT 24
Finished Aug 04 05:35:58 PM PDT 24
Peak memory 200492 kb
Host smart-28a1920c-c5d7-49e4-a566-82eb3529cffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837662064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.837662064
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3512187570
Short name T384
Test name
Test status
Simulation time 9395650387 ps
CPU time 36.18 seconds
Started Aug 04 05:36:04 PM PDT 24
Finished Aug 04 05:36:40 PM PDT 24
Peak memory 200636 kb
Host smart-c33c5c9e-02c0-4feb-b82b-74824475dfa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512187570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3512187570
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2592188975
Short name T345
Test name
Test status
Simulation time 447615378 ps
CPU time 2.28 seconds
Started Aug 04 05:35:53 PM PDT 24
Finished Aug 04 05:35:55 PM PDT 24
Peak memory 200300 kb
Host smart-3ad8451a-884d-4b20-a962-5599a2523228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592188975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2592188975
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.241693546
Short name T291
Test name
Test status
Simulation time 164706410 ps
CPU time 1.31 seconds
Started Aug 04 05:35:58 PM PDT 24
Finished Aug 04 05:35:59 PM PDT 24
Peak memory 200456 kb
Host smart-26ca21ad-342e-403e-a37f-58819b224564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241693546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.241693546
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3202979877
Short name T277
Test name
Test status
Simulation time 69107983 ps
CPU time 0.82 seconds
Started Aug 04 05:36:03 PM PDT 24
Finished Aug 04 05:36:04 PM PDT 24
Peak memory 200132 kb
Host smart-04e03a66-7a28-473e-97b1-7a3248660f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202979877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3202979877
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1191154145
Short name T333
Test name
Test status
Simulation time 2369803867 ps
CPU time 8.49 seconds
Started Aug 04 05:35:54 PM PDT 24
Finished Aug 04 05:36:03 PM PDT 24
Peak memory 217960 kb
Host smart-7d92d210-787f-4853-93bc-78e29c76b9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191154145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1191154145
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1126677316
Short name T306
Test name
Test status
Simulation time 244915286 ps
CPU time 1.06 seconds
Started Aug 04 05:36:06 PM PDT 24
Finished Aug 04 05:36:07 PM PDT 24
Peak memory 217468 kb
Host smart-6e411042-a1db-404a-8b86-d324ddf33dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126677316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1126677316
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1788275813
Short name T201
Test name
Test status
Simulation time 233908451 ps
CPU time 0.91 seconds
Started Aug 04 05:35:49 PM PDT 24
Finished Aug 04 05:35:50 PM PDT 24
Peak memory 200144 kb
Host smart-1ae2724b-b524-4565-b8e0-568346ec6c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788275813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1788275813
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1312815111
Short name T309
Test name
Test status
Simulation time 2093589226 ps
CPU time 7.25 seconds
Started Aug 04 05:35:48 PM PDT 24
Finished Aug 04 05:35:55 PM PDT 24
Peak memory 200560 kb
Host smart-e0fa378e-1e81-4113-8eae-73e51272f7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312815111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1312815111
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3759052027
Short name T79
Test name
Test status
Simulation time 147735227 ps
CPU time 1.11 seconds
Started Aug 04 05:35:55 PM PDT 24
Finished Aug 04 05:35:56 PM PDT 24
Peak memory 200312 kb
Host smart-e7f17f29-4732-4223-b12b-e4af52d7de48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759052027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3759052027
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4192441567
Short name T465
Test name
Test status
Simulation time 119564921 ps
CPU time 1.16 seconds
Started Aug 04 05:36:00 PM PDT 24
Finished Aug 04 05:36:01 PM PDT 24
Peak memory 200452 kb
Host smart-427dcc44-07a1-45f1-b474-c58a585185f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192441567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4192441567
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1871723510
Short name T246
Test name
Test status
Simulation time 132195809 ps
CPU time 1.25 seconds
Started Aug 04 05:35:57 PM PDT 24
Finished Aug 04 05:35:59 PM PDT 24
Peak memory 200116 kb
Host smart-d966a540-09bf-4b24-ba35-4ed933b4d758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871723510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1871723510
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2080786236
Short name T226
Test name
Test status
Simulation time 350982085 ps
CPU time 2.37 seconds
Started Aug 04 05:35:50 PM PDT 24
Finished Aug 04 05:35:52 PM PDT 24
Peak memory 200336 kb
Host smart-2aee9263-767a-4e2d-bd00-d3b9e0ec5fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080786236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2080786236
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3748807901
Short name T260
Test name
Test status
Simulation time 138364170 ps
CPU time 1.03 seconds
Started Aug 04 05:35:51 PM PDT 24
Finished Aug 04 05:35:52 PM PDT 24
Peak memory 200332 kb
Host smart-1fcefa64-d44c-4685-84af-e1aab291522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748807901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3748807901
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.530554423
Short name T185
Test name
Test status
Simulation time 68159702 ps
CPU time 0.78 seconds
Started Aug 04 05:35:53 PM PDT 24
Finished Aug 04 05:35:53 PM PDT 24
Peak memory 200124 kb
Host smart-96d74f8c-bf05-4a7f-9531-226f629aef8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530554423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.530554423
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3479478784
Short name T455
Test name
Test status
Simulation time 1889956449 ps
CPU time 6.85 seconds
Started Aug 04 05:36:04 PM PDT 24
Finished Aug 04 05:36:11 PM PDT 24
Peak memory 216808 kb
Host smart-41ead9a4-cfce-406f-93f8-7da04f8acfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479478784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3479478784
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2123673157
Short name T308
Test name
Test status
Simulation time 245653384 ps
CPU time 1.05 seconds
Started Aug 04 05:35:55 PM PDT 24
Finished Aug 04 05:35:56 PM PDT 24
Peak memory 217480 kb
Host smart-74aa4127-2c02-4e47-9e13-a6304f919df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123673157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2123673157
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3893834803
Short name T16
Test name
Test status
Simulation time 119321192 ps
CPU time 0.84 seconds
Started Aug 04 05:35:56 PM PDT 24
Finished Aug 04 05:35:57 PM PDT 24
Peak memory 200144 kb
Host smart-335fa20e-9a63-4540-8468-77823717e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893834803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3893834803
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3697031653
Short name T157
Test name
Test status
Simulation time 1040795380 ps
CPU time 4.98 seconds
Started Aug 04 05:35:52 PM PDT 24
Finished Aug 04 05:35:57 PM PDT 24
Peak memory 200592 kb
Host smart-f3c0c581-6a2d-4155-b998-c85f66d610d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697031653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3697031653
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.987473300
Short name T356
Test name
Test status
Simulation time 112121749 ps
CPU time 1.03 seconds
Started Aug 04 05:35:53 PM PDT 24
Finished Aug 04 05:35:59 PM PDT 24
Peak memory 200348 kb
Host smart-a68ade21-165c-4e90-ae37-e90792d13775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987473300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.987473300
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3712264974
Short name T68
Test name
Test status
Simulation time 249701183 ps
CPU time 1.46 seconds
Started Aug 04 05:36:01 PM PDT 24
Finished Aug 04 05:36:03 PM PDT 24
Peak memory 200496 kb
Host smart-13b4a0bc-e040-444a-bffa-b904e672503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712264974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3712264974
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3719244846
Short name T296
Test name
Test status
Simulation time 392705573 ps
CPU time 2.17 seconds
Started Aug 04 05:36:07 PM PDT 24
Finished Aug 04 05:36:09 PM PDT 24
Peak memory 200252 kb
Host smart-d87c1580-2a54-40f1-930a-31b6529ced81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719244846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3719244846
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.1818581580
Short name T161
Test name
Test status
Simulation time 122533130 ps
CPU time 1.04 seconds
Started Aug 04 05:35:57 PM PDT 24
Finished Aug 04 05:35:58 PM PDT 24
Peak memory 200316 kb
Host smart-8ea52c42-6046-4563-a691-049ae048dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818581580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1818581580
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3602380057
Short name T9
Test name
Test status
Simulation time 77358890 ps
CPU time 0.82 seconds
Started Aug 04 05:35:53 PM PDT 24
Finished Aug 04 05:35:54 PM PDT 24
Peak memory 200136 kb
Host smart-c3e2d169-41d1-4317-9dd4-82525131d123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602380057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3602380057
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.283783528
Short name T32
Test name
Test status
Simulation time 1230160016 ps
CPU time 5.45 seconds
Started Aug 04 05:35:52 PM PDT 24
Finished Aug 04 05:35:58 PM PDT 24
Peak memory 217788 kb
Host smart-011f6558-b203-4996-b7fb-e6a9d036d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283783528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.283783528
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2322830208
Short name T472
Test name
Test status
Simulation time 243736550 ps
CPU time 1.09 seconds
Started Aug 04 05:36:05 PM PDT 24
Finished Aug 04 05:36:07 PM PDT 24
Peak memory 217460 kb
Host smart-80dc3bc1-986c-4c51-9b15-f8138e0148c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322830208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2322830208
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.94037506
Short name T304
Test name
Test status
Simulation time 109359027 ps
CPU time 0.76 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:13 PM PDT 24
Peak memory 200100 kb
Host smart-e01f0e91-290f-4f7b-8787-656b85f53c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94037506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.94037506
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.509260475
Short name T405
Test name
Test status
Simulation time 813291572 ps
CPU time 3.8 seconds
Started Aug 04 05:35:54 PM PDT 24
Finished Aug 04 05:35:58 PM PDT 24
Peak memory 200628 kb
Host smart-f457dcd4-8e1e-4134-80be-7a0c07890a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509260475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.509260475
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2468386659
Short name T208
Test name
Test status
Simulation time 180653837 ps
CPU time 1.23 seconds
Started Aug 04 05:36:01 PM PDT 24
Finished Aug 04 05:36:03 PM PDT 24
Peak memory 200376 kb
Host smart-d28b44aa-f6ce-4c7b-bb0a-7f4b60b6c89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468386659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2468386659
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2121376982
Short name T191
Test name
Test status
Simulation time 117249894 ps
CPU time 1.17 seconds
Started Aug 04 05:35:57 PM PDT 24
Finished Aug 04 05:35:58 PM PDT 24
Peak memory 200448 kb
Host smart-834ff2f6-5b0b-42ac-9d12-28257902df71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121376982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2121376982
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1760337402
Short name T52
Test name
Test status
Simulation time 5343789479 ps
CPU time 17.36 seconds
Started Aug 04 05:36:02 PM PDT 24
Finished Aug 04 05:36:19 PM PDT 24
Peak memory 200608 kb
Host smart-31243909-7de0-45d5-9da8-1743c4e8fc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760337402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1760337402
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.322379771
Short name T145
Test name
Test status
Simulation time 255537253 ps
CPU time 1.88 seconds
Started Aug 04 05:36:02 PM PDT 24
Finished Aug 04 05:36:04 PM PDT 24
Peak memory 200308 kb
Host smart-72cd2ab0-7b4e-4f83-acba-398e2a045ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322379771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.322379771
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3549933618
Short name T174
Test name
Test status
Simulation time 225082247 ps
CPU time 1.43 seconds
Started Aug 04 05:36:01 PM PDT 24
Finished Aug 04 05:36:03 PM PDT 24
Peak memory 200460 kb
Host smart-cf04e966-7e12-42d4-82a1-240724cdde3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549933618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3549933618
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1143973337
Short name T320
Test name
Test status
Simulation time 90356540 ps
CPU time 0.83 seconds
Started Aug 04 05:36:03 PM PDT 24
Finished Aug 04 05:36:09 PM PDT 24
Peak memory 200136 kb
Host smart-8935fc9c-7ef9-4d1e-aa23-b6417cbaf10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143973337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1143973337
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1356324366
Short name T1
Test name
Test status
Simulation time 1228246699 ps
CPU time 5.66 seconds
Started Aug 04 05:36:18 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 217460 kb
Host smart-5cc16340-0352-46e5-9fd2-74563ec5f302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356324366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1356324366
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.438056020
Short name T529
Test name
Test status
Simulation time 243523123 ps
CPU time 1.07 seconds
Started Aug 04 05:36:01 PM PDT 24
Finished Aug 04 05:36:02 PM PDT 24
Peak memory 217560 kb
Host smart-60ee972c-7ae7-4664-9df4-f83412ac0930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438056020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.438056020
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1622081720
Short name T508
Test name
Test status
Simulation time 115162735 ps
CPU time 0.83 seconds
Started Aug 04 05:36:14 PM PDT 24
Finished Aug 04 05:36:14 PM PDT 24
Peak memory 200108 kb
Host smart-91bea7d4-2eee-40bc-b98c-d19171f1737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622081720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1622081720
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1023966664
Short name T522
Test name
Test status
Simulation time 900796134 ps
CPU time 4.19 seconds
Started Aug 04 05:35:51 PM PDT 24
Finished Aug 04 05:36:00 PM PDT 24
Peak memory 200560 kb
Host smart-7457a2ec-e18c-48a5-8f6e-d97db90cebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023966664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1023966664
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.25616476
Short name T218
Test name
Test status
Simulation time 144286750 ps
CPU time 1.14 seconds
Started Aug 04 05:35:59 PM PDT 24
Finished Aug 04 05:36:01 PM PDT 24
Peak memory 200324 kb
Host smart-4dde8d35-70ae-42a6-8fd3-ab1eef433c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25616476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.25616476
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1524585493
Short name T125
Test name
Test status
Simulation time 112748737 ps
CPU time 1.19 seconds
Started Aug 04 05:36:02 PM PDT 24
Finished Aug 04 05:36:03 PM PDT 24
Peak memory 200464 kb
Host smart-e80dafd6-6e4c-4a80-86a0-e579b5ee142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524585493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1524585493
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2702587439
Short name T460
Test name
Test status
Simulation time 7748294167 ps
CPU time 27.81 seconds
Started Aug 04 05:36:06 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 210188 kb
Host smart-ad287f3a-02d6-4c17-8568-8185d0b62db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702587439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2702587439
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3365353539
Short name T273
Test name
Test status
Simulation time 227621240 ps
CPU time 1.32 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:13 PM PDT 24
Peak memory 200472 kb
Host smart-aa86ef03-a958-4eda-9eaa-497308d7bf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365353539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3365353539
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1286421117
Short name T431
Test name
Test status
Simulation time 61161525 ps
CPU time 0.74 seconds
Started Aug 04 05:35:55 PM PDT 24
Finished Aug 04 05:35:56 PM PDT 24
Peak memory 200136 kb
Host smart-5802028a-6741-4917-ab50-dcc1a96566f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286421117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1286421117
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1240019171
Short name T329
Test name
Test status
Simulation time 2350373310 ps
CPU time 8.34 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 221708 kb
Host smart-fd8df32b-5973-48ad-870b-119c384cab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240019171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1240019171
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3708793287
Short name T150
Test name
Test status
Simulation time 244481883 ps
CPU time 1.12 seconds
Started Aug 04 05:36:02 PM PDT 24
Finished Aug 04 05:36:04 PM PDT 24
Peak memory 217508 kb
Host smart-2afba34e-8a28-40ba-b0ac-9724ae3a4632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708793287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3708793287
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1376053369
Short name T184
Test name
Test status
Simulation time 89075864 ps
CPU time 0.76 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:13 PM PDT 24
Peak memory 200124 kb
Host smart-6a959137-4c1b-4248-8aa4-9d6949e92e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376053369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1376053369
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3537572782
Short name T167
Test name
Test status
Simulation time 1032368092 ps
CPU time 4.93 seconds
Started Aug 04 05:36:13 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 200572 kb
Host smart-b26daa31-3dbb-4c2b-87b9-fc19ab950ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537572782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3537572782
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1163622520
Short name T41
Test name
Test status
Simulation time 140150898 ps
CPU time 1.1 seconds
Started Aug 04 05:36:01 PM PDT 24
Finished Aug 04 05:36:03 PM PDT 24
Peak memory 200296 kb
Host smart-ff5f87af-e74f-445f-b464-d66d69f178e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163622520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1163622520
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.930494986
Short name T286
Test name
Test status
Simulation time 250820450 ps
CPU time 1.61 seconds
Started Aug 04 05:35:52 PM PDT 24
Finished Aug 04 05:35:53 PM PDT 24
Peak memory 200508 kb
Host smart-60daa339-5993-4525-9391-3b9f038b9de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930494986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.930494986
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3821092510
Short name T303
Test name
Test status
Simulation time 4987561781 ps
CPU time 21.04 seconds
Started Aug 04 05:35:59 PM PDT 24
Finished Aug 04 05:36:21 PM PDT 24
Peak memory 209784 kb
Host smart-be28168e-4a74-4bec-bf82-e1b97665bbf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821092510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3821092510
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3453474969
Short name T173
Test name
Test status
Simulation time 505872764 ps
CPU time 2.79 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:14 PM PDT 24
Peak memory 200312 kb
Host smart-e06eb265-11e7-4202-b971-ad27b4cf6f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453474969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3453474969
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3687314861
Short name T513
Test name
Test status
Simulation time 273279240 ps
CPU time 1.53 seconds
Started Aug 04 05:36:28 PM PDT 24
Finished Aug 04 05:36:30 PM PDT 24
Peak memory 200296 kb
Host smart-2d971a93-971d-48a7-a84b-0d624d812aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687314861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3687314861
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.442707096
Short name T386
Test name
Test status
Simulation time 58498190 ps
CPU time 0.73 seconds
Started Aug 04 05:35:17 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 200176 kb
Host smart-fd2e39c4-bbd4-4c84-91e0-502efd3552e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442707096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.442707096
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3654050096
Short name T302
Test name
Test status
Simulation time 1226410845 ps
CPU time 5.69 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 217596 kb
Host smart-b22346ca-c36f-4b90-bd54-320234edea2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654050096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3654050096
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3481289212
Short name T156
Test name
Test status
Simulation time 244732073 ps
CPU time 1.02 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 217480 kb
Host smart-f11b959f-3dff-4029-8332-3c32080671f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481289212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3481289212
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.445262861
Short name T437
Test name
Test status
Simulation time 111333067 ps
CPU time 0.8 seconds
Started Aug 04 05:35:44 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 200172 kb
Host smart-ba3040bb-0c95-4909-80ca-f113a83ff055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445262861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.445262861
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4196716638
Short name T521
Test name
Test status
Simulation time 2026253216 ps
CPU time 8.25 seconds
Started Aug 04 05:35:20 PM PDT 24
Finished Aug 04 05:35:28 PM PDT 24
Peak memory 200584 kb
Host smart-51c163f6-5d59-4ea6-b6d5-4013d0493e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196716638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4196716638
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.74901603
Short name T78
Test name
Test status
Simulation time 16517001590 ps
CPU time 31.49 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:51 PM PDT 24
Peak memory 218260 kb
Host smart-83eb1167-52ef-43f3-bb07-a5a41cf34065
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74901603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.74901603
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1646464358
Short name T507
Test name
Test status
Simulation time 182079021 ps
CPU time 1.27 seconds
Started Aug 04 05:35:21 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 200356 kb
Host smart-e47f7edf-c64f-4f16-854a-17e01608e907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646464358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1646464358
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4288467597
Short name T254
Test name
Test status
Simulation time 113118567 ps
CPU time 1.15 seconds
Started Aug 04 05:35:21 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 200396 kb
Host smart-d4b612d5-9df5-461e-97a8-d669a6cc8733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288467597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4288467597
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2853907039
Short name T265
Test name
Test status
Simulation time 330617246 ps
CPU time 2.16 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 200192 kb
Host smart-c8922d2d-e44c-4588-8755-3f0530b529aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853907039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2853907039
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.4119767093
Short name T509
Test name
Test status
Simulation time 174606254 ps
CPU time 1.25 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:20 PM PDT 24
Peak memory 200496 kb
Host smart-1f00b0b6-3878-4fab-8262-a94e379e31c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119767093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.4119767093
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2413881209
Short name T410
Test name
Test status
Simulation time 64771828 ps
CPU time 0.75 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 200136 kb
Host smart-42dc4b90-5aca-420d-80bb-8a3aba309fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413881209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2413881209
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.582470752
Short name T141
Test name
Test status
Simulation time 244734156 ps
CPU time 1.04 seconds
Started Aug 04 05:36:00 PM PDT 24
Finished Aug 04 05:36:01 PM PDT 24
Peak memory 217496 kb
Host smart-9101cb28-1863-4db6-a92a-bae77befc4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582470752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.582470752
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1312931100
Short name T447
Test name
Test status
Simulation time 160361096 ps
CPU time 0.88 seconds
Started Aug 04 05:35:56 PM PDT 24
Finished Aug 04 05:35:57 PM PDT 24
Peak memory 200100 kb
Host smart-c52c31db-7b3b-4163-82da-69465576d900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312931100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1312931100
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3931710457
Short name T323
Test name
Test status
Simulation time 2077707865 ps
CPU time 7.29 seconds
Started Aug 04 05:36:04 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 200528 kb
Host smart-75e4c1aa-6384-40f7-9592-fd6e1aaa34a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931710457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3931710457
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.507660588
Short name T514
Test name
Test status
Simulation time 146574177 ps
CPU time 1.09 seconds
Started Aug 04 05:35:54 PM PDT 24
Finished Aug 04 05:35:55 PM PDT 24
Peak memory 200336 kb
Host smart-d5efd256-883a-44f7-824e-82e6cdfe7202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507660588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.507660588
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1784189428
Short name T118
Test name
Test status
Simulation time 261286524 ps
CPU time 1.51 seconds
Started Aug 04 05:36:20 PM PDT 24
Finished Aug 04 05:36:21 PM PDT 24
Peak memory 200436 kb
Host smart-c88b85eb-819a-4f91-bc4c-c97be86e64e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784189428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1784189428
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2060243133
Short name T245
Test name
Test status
Simulation time 2453930427 ps
CPU time 10.72 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 208808 kb
Host smart-92467cfe-d7f4-4817-8681-8f8bdbbfc2cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060243133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2060243133
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.834411570
Short name T448
Test name
Test status
Simulation time 262609371 ps
CPU time 1.85 seconds
Started Aug 04 05:36:10 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 200504 kb
Host smart-fc904ef3-a802-41ca-97af-77c541b6cd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834411570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.834411570
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2425036852
Short name T252
Test name
Test status
Simulation time 222485844 ps
CPU time 1.26 seconds
Started Aug 04 05:35:54 PM PDT 24
Finished Aug 04 05:35:55 PM PDT 24
Peak memory 200352 kb
Host smart-94318714-fdd9-4c4a-8733-8465093232f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425036852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2425036852
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.921388644
Short name T389
Test name
Test status
Simulation time 59776944 ps
CPU time 0.75 seconds
Started Aug 04 05:36:07 PM PDT 24
Finished Aug 04 05:36:08 PM PDT 24
Peak memory 200144 kb
Host smart-29fb8f2e-8a39-4e90-8770-d5a6fa7d1fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921388644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.921388644
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2732126598
Short name T33
Test name
Test status
Simulation time 1882303306 ps
CPU time 7.02 seconds
Started Aug 04 05:36:17 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 217488 kb
Host smart-193a3475-d58f-4412-8307-adeb2d750bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732126598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2732126598
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.797755679
Short name T366
Test name
Test status
Simulation time 244788204 ps
CPU time 1.08 seconds
Started Aug 04 05:36:16 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 217512 kb
Host smart-6011889e-018c-409e-8566-b9ddb296461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797755679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.797755679
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1768769158
Short name T12
Test name
Test status
Simulation time 154112357 ps
CPU time 0.87 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 200056 kb
Host smart-22249e52-2165-4725-9684-30c20ab23836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768769158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1768769158
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3375964597
Short name T251
Test name
Test status
Simulation time 1404829804 ps
CPU time 5.76 seconds
Started Aug 04 05:36:13 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 200604 kb
Host smart-e8605693-e19a-4dba-807c-ca4185aef93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375964597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3375964597
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1424831089
Short name T147
Test name
Test status
Simulation time 104898652 ps
CPU time 0.97 seconds
Started Aug 04 05:36:05 PM PDT 24
Finished Aug 04 05:36:06 PM PDT 24
Peak memory 200340 kb
Host smart-bbdcde90-56be-4f0b-b266-d047129f778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424831089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1424831089
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3687334194
Short name T407
Test name
Test status
Simulation time 188038950 ps
CPU time 1.27 seconds
Started Aug 04 05:36:21 PM PDT 24
Finished Aug 04 05:36:22 PM PDT 24
Peak memory 200512 kb
Host smart-7eb72e33-21e3-4c48-b59f-6f77fd4b4f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687334194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3687334194
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3362000849
Short name T216
Test name
Test status
Simulation time 2819252437 ps
CPU time 12.11 seconds
Started Aug 04 05:35:56 PM PDT 24
Finished Aug 04 05:36:08 PM PDT 24
Peak memory 200568 kb
Host smart-0fdd1b62-76ff-4bea-87d4-145e97f1cf86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362000849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3362000849
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2201905889
Short name T194
Test name
Test status
Simulation time 376700587 ps
CPU time 2.13 seconds
Started Aug 04 05:35:57 PM PDT 24
Finished Aug 04 05:36:00 PM PDT 24
Peak memory 200320 kb
Host smart-208045d0-c894-4d3e-9ce1-53d0465a7d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201905889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2201905889
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1166816006
Short name T435
Test name
Test status
Simulation time 58320236 ps
CPU time 0.74 seconds
Started Aug 04 05:36:00 PM PDT 24
Finished Aug 04 05:36:01 PM PDT 24
Peak memory 200376 kb
Host smart-8bb4e55f-638d-4bed-9530-850a0342d835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166816006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1166816006
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3824327330
Short name T398
Test name
Test status
Simulation time 84449029 ps
CPU time 0.82 seconds
Started Aug 04 05:35:56 PM PDT 24
Finished Aug 04 05:35:57 PM PDT 24
Peak memory 200160 kb
Host smart-c91a60aa-751a-4370-b5a8-5642a69adde3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824327330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3824327330
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1325492160
Short name T45
Test name
Test status
Simulation time 1227659484 ps
CPU time 5.66 seconds
Started Aug 04 05:36:03 PM PDT 24
Finished Aug 04 05:36:08 PM PDT 24
Peak memory 221676 kb
Host smart-e679e1b3-330f-4e09-8a5e-42d52422b8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325492160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1325492160
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2269581018
Short name T205
Test name
Test status
Simulation time 243787609 ps
CPU time 1.12 seconds
Started Aug 04 05:36:01 PM PDT 24
Finished Aug 04 05:36:03 PM PDT 24
Peak memory 217460 kb
Host smart-9cae0877-fb8a-4391-9b10-c4df06dadef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269581018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2269581018
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2630657466
Short name T542
Test name
Test status
Simulation time 166123701 ps
CPU time 0.93 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 199936 kb
Host smart-9318f6ef-daca-49df-8a3d-9a96fed2cb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630657466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2630657466
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2931160216
Short name T158
Test name
Test status
Simulation time 716910067 ps
CPU time 3.79 seconds
Started Aug 04 05:36:18 PM PDT 24
Finished Aug 04 05:36:22 PM PDT 24
Peak memory 200504 kb
Host smart-e350eb6a-2c28-405d-9344-1689c6f9166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931160216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2931160216
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3165113406
Short name T266
Test name
Test status
Simulation time 97946495 ps
CPU time 0.95 seconds
Started Aug 04 05:36:07 PM PDT 24
Finished Aug 04 05:36:08 PM PDT 24
Peak memory 200348 kb
Host smart-be7f14d1-58c0-4e9c-a555-92a61d89ab46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165113406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3165113406
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.794374175
Short name T516
Test name
Test status
Simulation time 120609439 ps
CPU time 1.21 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200440 kb
Host smart-ba686fae-9307-4ab9-82d9-296bde51a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794374175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.794374175
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3660586137
Short name T23
Test name
Test status
Simulation time 5510023392 ps
CPU time 20.06 seconds
Started Aug 04 05:36:16 PM PDT 24
Finished Aug 04 05:36:37 PM PDT 24
Peak memory 200640 kb
Host smart-f54a4d48-a766-4970-9a55-2aa7c02cbb98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660586137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3660586137
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.442350498
Short name T362
Test name
Test status
Simulation time 135903039 ps
CPU time 1.65 seconds
Started Aug 04 05:35:54 PM PDT 24
Finished Aug 04 05:35:55 PM PDT 24
Peak memory 200248 kb
Host smart-637b090c-1999-457c-85b3-8724858f0f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442350498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.442350498
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1914060805
Short name T199
Test name
Test status
Simulation time 128992003 ps
CPU time 1.12 seconds
Started Aug 04 05:36:28 PM PDT 24
Finished Aug 04 05:36:29 PM PDT 24
Peak memory 200296 kb
Host smart-fbb1acb0-814c-42e5-bd47-623edfc1bcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914060805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1914060805
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1032824975
Short name T464
Test name
Test status
Simulation time 72567419 ps
CPU time 0.77 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 200072 kb
Host smart-9118f716-5680-44be-94fd-1e1070042e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032824975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1032824975
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.169829487
Short name T44
Test name
Test status
Simulation time 2359515751 ps
CPU time 9.2 seconds
Started Aug 04 05:36:21 PM PDT 24
Finished Aug 04 05:36:30 PM PDT 24
Peak memory 229916 kb
Host smart-27facefd-120f-49cb-9af6-4272375cef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169829487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.169829487
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2792773513
Short name T256
Test name
Test status
Simulation time 243832582 ps
CPU time 1.09 seconds
Started Aug 04 05:36:13 PM PDT 24
Finished Aug 04 05:36:14 PM PDT 24
Peak memory 217460 kb
Host smart-e12db228-1443-430f-9703-2687a5b9baf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792773513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2792773513
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2509886274
Short name T515
Test name
Test status
Simulation time 90660475 ps
CPU time 0.75 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 200128 kb
Host smart-688a6cca-9e91-410b-8f70-0aa05299a8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509886274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2509886274
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1361030185
Short name T171
Test name
Test status
Simulation time 781493548 ps
CPU time 4.28 seconds
Started Aug 04 05:36:07 PM PDT 24
Finished Aug 04 05:36:11 PM PDT 24
Peak memory 200552 kb
Host smart-46a6d1d0-6d9f-4572-a58e-e94c46ad4d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361030185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1361030185
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.4175406464
Short name T379
Test name
Test status
Simulation time 103113476 ps
CPU time 0.99 seconds
Started Aug 04 05:36:13 PM PDT 24
Finished Aug 04 05:36:14 PM PDT 24
Peak memory 200332 kb
Host smart-f1c7d423-34f4-4ee9-8ca4-00d48089c699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175406464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.4175406464
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2398913590
Short name T187
Test name
Test status
Simulation time 199486209 ps
CPU time 1.29 seconds
Started Aug 04 05:35:54 PM PDT 24
Finished Aug 04 05:35:56 PM PDT 24
Peak memory 200520 kb
Host smart-fef7f015-b9dc-45c6-8855-694cb9c2f0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398913590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2398913590
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.823360892
Short name T400
Test name
Test status
Simulation time 3298469392 ps
CPU time 15.46 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200624 kb
Host smart-4a0cf54d-04cd-4c72-93a8-75e73056a2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823360892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.823360892
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.668103477
Short name T319
Test name
Test status
Simulation time 121274780 ps
CPU time 1.51 seconds
Started Aug 04 05:36:09 PM PDT 24
Finished Aug 04 05:36:10 PM PDT 24
Peak memory 200280 kb
Host smart-7d111ea2-ad42-4dcc-911f-2c17cc3f486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668103477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.668103477
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4118160171
Short name T11
Test name
Test status
Simulation time 163109368 ps
CPU time 1.14 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 200296 kb
Host smart-d14cc3d6-dfee-48dd-90b9-a0d06fe3494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118160171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4118160171
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2535891109
Short name T504
Test name
Test status
Simulation time 70869293 ps
CPU time 0.85 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200152 kb
Host smart-2f16b3a8-95e2-4d23-99a3-4f0786dbc072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535891109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2535891109
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2957168307
Short name T272
Test name
Test status
Simulation time 2154999313 ps
CPU time 7.72 seconds
Started Aug 04 05:36:18 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 221788 kb
Host smart-f622e5ff-8252-43c4-a3a5-ca7affcecd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957168307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2957168307
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1268325590
Short name T197
Test name
Test status
Simulation time 244874462 ps
CPU time 1.05 seconds
Started Aug 04 05:36:02 PM PDT 24
Finished Aug 04 05:36:04 PM PDT 24
Peak memory 217484 kb
Host smart-294eb28b-f88d-4926-b553-df91eaa67d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268325590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1268325590
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3430121946
Short name T383
Test name
Test status
Simulation time 185272948 ps
CPU time 0.88 seconds
Started Aug 04 05:36:06 PM PDT 24
Finished Aug 04 05:36:07 PM PDT 24
Peak memory 200172 kb
Host smart-ae9a3a99-9645-4f63-87f5-415bf2f69c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430121946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3430121946
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2816788304
Short name T385
Test name
Test status
Simulation time 1956511865 ps
CPU time 7.7 seconds
Started Aug 04 05:36:07 PM PDT 24
Finished Aug 04 05:36:15 PM PDT 24
Peak memory 200596 kb
Host smart-77d9fb60-702c-475d-a632-6e0a6b885711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816788304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2816788304
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2268877170
Short name T162
Test name
Test status
Simulation time 115480253 ps
CPU time 1 seconds
Started Aug 04 05:36:07 PM PDT 24
Finished Aug 04 05:36:08 PM PDT 24
Peak memory 200324 kb
Host smart-5369641b-f0f4-4982-808a-11ea65b5cc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268877170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2268877170
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3043661172
Short name T505
Test name
Test status
Simulation time 115452007 ps
CPU time 1.15 seconds
Started Aug 04 05:36:14 PM PDT 24
Finished Aug 04 05:36:15 PM PDT 24
Peak memory 200500 kb
Host smart-3fe2fc5a-7160-4653-9257-a33203bc5971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043661172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3043661172
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.4251905730
Short name T477
Test name
Test status
Simulation time 1041578325 ps
CPU time 4.92 seconds
Started Aug 04 05:36:06 PM PDT 24
Finished Aug 04 05:36:11 PM PDT 24
Peak memory 200528 kb
Host smart-54d93623-548d-4966-9077-556855f163d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251905730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.4251905730
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2179106151
Short name T61
Test name
Test status
Simulation time 125243961 ps
CPU time 1.47 seconds
Started Aug 04 05:36:04 PM PDT 24
Finished Aug 04 05:36:05 PM PDT 24
Peak memory 200324 kb
Host smart-9e085e59-5d10-44cd-a1c1-cc7661936a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179106151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2179106151
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4134176665
Short name T127
Test name
Test status
Simulation time 110831570 ps
CPU time 0.93 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:13 PM PDT 24
Peak memory 200348 kb
Host smart-6810a0a4-9cc2-4890-aca0-357622675fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134176665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4134176665
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3961217792
Short name T439
Test name
Test status
Simulation time 80278378 ps
CPU time 0.77 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 200152 kb
Host smart-4e2b9bab-f876-4037-a57a-65d7aa038237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961217792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3961217792
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3402953360
Short name T30
Test name
Test status
Simulation time 1891873851 ps
CPU time 7.73 seconds
Started Aug 04 05:36:09 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 221748 kb
Host smart-03a03af2-f70a-4414-8895-351a11e1e176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402953360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3402953360
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2116320253
Short name T249
Test name
Test status
Simulation time 244108061 ps
CPU time 1.14 seconds
Started Aug 04 05:36:03 PM PDT 24
Finished Aug 04 05:36:04 PM PDT 24
Peak memory 217460 kb
Host smart-70b57180-627e-4e1a-b564-d1489843260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116320253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2116320253
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1858744495
Short name T493
Test name
Test status
Simulation time 100540071 ps
CPU time 0.75 seconds
Started Aug 04 05:36:09 PM PDT 24
Finished Aug 04 05:36:10 PM PDT 24
Peak memory 200136 kb
Host smart-eabb5337-48c0-4511-bae5-2f8b3787d660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858744495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1858744495
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1094247106
Short name T370
Test name
Test status
Simulation time 1064089745 ps
CPU time 5.71 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 200532 kb
Host smart-fa003843-6955-417c-951f-5beb3aaf4a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094247106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1094247106
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.557235730
Short name T318
Test name
Test status
Simulation time 174650299 ps
CPU time 1.17 seconds
Started Aug 04 05:36:18 PM PDT 24
Finished Aug 04 05:36:19 PM PDT 24
Peak memory 200348 kb
Host smart-23aae5a6-910c-44d2-a16b-91c3de7dce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557235730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.557235730
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1984623644
Short name T307
Test name
Test status
Simulation time 205989530 ps
CPU time 1.47 seconds
Started Aug 04 05:36:00 PM PDT 24
Finished Aug 04 05:36:07 PM PDT 24
Peak memory 200528 kb
Host smart-7caaa3da-b63c-4948-9981-7db67f1203dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984623644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1984623644
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.534903597
Short name T330
Test name
Test status
Simulation time 11162207220 ps
CPU time 38.76 seconds
Started Aug 04 05:36:17 PM PDT 24
Finished Aug 04 05:36:55 PM PDT 24
Peak memory 208776 kb
Host smart-d8d620c8-5618-4cad-a72b-d57be29c4637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534903597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.534903597
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.864879313
Short name T355
Test name
Test status
Simulation time 433080102 ps
CPU time 2.36 seconds
Started Aug 04 05:36:21 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 208504 kb
Host smart-736606d7-254c-463c-a553-1955e69fe2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864879313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.864879313
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2072369065
Short name T518
Test name
Test status
Simulation time 122744319 ps
CPU time 0.97 seconds
Started Aug 04 05:36:17 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 200348 kb
Host smart-2f6f05c8-7b32-4c1f-89e4-b5adc94807b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072369065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2072369065
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2335340713
Short name T328
Test name
Test status
Simulation time 74690049 ps
CPU time 0.85 seconds
Started Aug 04 05:36:17 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 200132 kb
Host smart-4125a7de-c060-44cd-95e4-82cd74a26c8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335340713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2335340713
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3363114174
Short name T335
Test name
Test status
Simulation time 1899458668 ps
CPU time 7.2 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:33 PM PDT 24
Peak memory 217716 kb
Host smart-d160bfc2-4d88-4f6d-9463-79ad98b48774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363114174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3363114174
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1283487207
Short name T359
Test name
Test status
Simulation time 245482477 ps
CPU time 1.04 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 217492 kb
Host smart-88249d0b-60ab-497a-938d-eca4568281f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283487207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1283487207
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3917886605
Short name T454
Test name
Test status
Simulation time 108538427 ps
CPU time 0.79 seconds
Started Aug 04 05:35:59 PM PDT 24
Finished Aug 04 05:36:00 PM PDT 24
Peak memory 200152 kb
Host smart-09297260-2430-4481-8dd5-4014c7f5dd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917886605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3917886605
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.431731397
Short name T288
Test name
Test status
Simulation time 1419207941 ps
CPU time 5.01 seconds
Started Aug 04 05:36:07 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 200524 kb
Host smart-a59c7af2-2916-403f-8553-24c2563d880d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431731397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.431731397
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2323644174
Short name T144
Test name
Test status
Simulation time 142567168 ps
CPU time 1.07 seconds
Started Aug 04 05:36:06 PM PDT 24
Finished Aug 04 05:36:07 PM PDT 24
Peak memory 200352 kb
Host smart-f07c5d3c-e07d-48c5-bf31-25544f26da6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323644174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2323644174
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.1825333098
Short name T527
Test name
Test status
Simulation time 254031456 ps
CPU time 1.45 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:16 PM PDT 24
Peak memory 200488 kb
Host smart-af8f1d68-c29a-459c-9de4-10b426b5e367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825333098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1825333098
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.86654461
Short name T358
Test name
Test status
Simulation time 1889458055 ps
CPU time 6.67 seconds
Started Aug 04 05:36:21 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200472 kb
Host smart-72fb1dd6-d9d2-408b-a96a-261a9463a077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86654461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.86654461
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.913336298
Short name T255
Test name
Test status
Simulation time 137865197 ps
CPU time 1.69 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 200504 kb
Host smart-6aec19cb-231b-4c59-b08e-390980595c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913336298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.913336298
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1841367674
Short name T338
Test name
Test status
Simulation time 247708462 ps
CPU time 1.59 seconds
Started Aug 04 05:36:05 PM PDT 24
Finished Aug 04 05:36:07 PM PDT 24
Peak memory 200484 kb
Host smart-61d2bdee-4cef-4571-ae22-dd96a31ca3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841367674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1841367674
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3396377439
Short name T426
Test name
Test status
Simulation time 55317504 ps
CPU time 0.7 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 200064 kb
Host smart-f224fd7c-75f2-4437-8da8-712c1bb01618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396377439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3396377439
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1283552455
Short name T27
Test name
Test status
Simulation time 1227372414 ps
CPU time 5.36 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 221628 kb
Host smart-fb46e738-250c-4e87-ad1d-968385e711c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283552455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1283552455
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.710902800
Short name T530
Test name
Test status
Simulation time 245162802 ps
CPU time 1.05 seconds
Started Aug 04 05:36:14 PM PDT 24
Finished Aug 04 05:36:15 PM PDT 24
Peak memory 217536 kb
Host smart-f3651841-bea6-4fb0-ab96-f327af14a8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710902800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.710902800
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.605354728
Short name T413
Test name
Test status
Simulation time 121746478 ps
CPU time 0.81 seconds
Started Aug 04 05:36:14 PM PDT 24
Finished Aug 04 05:36:15 PM PDT 24
Peak memory 200152 kb
Host smart-080a17de-4f76-4cda-9226-df48dcadee0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605354728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.605354728
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1404715675
Short name T294
Test name
Test status
Simulation time 1257115530 ps
CPU time 5.08 seconds
Started Aug 04 05:36:01 PM PDT 24
Finished Aug 04 05:36:07 PM PDT 24
Peak memory 200536 kb
Host smart-c0dce5cd-d69e-4a11-8ece-a222f7984e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404715675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1404715675
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.593972563
Short name T534
Test name
Test status
Simulation time 113359080 ps
CPU time 1.04 seconds
Started Aug 04 05:36:02 PM PDT 24
Finished Aug 04 05:36:03 PM PDT 24
Peak memory 200336 kb
Host smart-a5a73f0e-22d8-4140-ac25-aa29efb64e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593972563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.593972563
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3976519974
Short name T421
Test name
Test status
Simulation time 188332912 ps
CPU time 1.3 seconds
Started Aug 04 05:36:20 PM PDT 24
Finished Aug 04 05:36:21 PM PDT 24
Peak memory 200552 kb
Host smart-d8b1236b-5a2f-42dd-a586-82cb8f0776fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976519974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3976519974
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2447418064
Short name T420
Test name
Test status
Simulation time 10158811168 ps
CPU time 32.63 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:45 PM PDT 24
Peak memory 200624 kb
Host smart-33cf257c-e19a-4744-9a78-d575e7216fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447418064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2447418064
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.49804723
Short name T348
Test name
Test status
Simulation time 325240989 ps
CPU time 1.95 seconds
Started Aug 04 05:36:08 PM PDT 24
Finished Aug 04 05:36:10 PM PDT 24
Peak memory 200300 kb
Host smart-5648b692-7e7a-4bae-a39c-0c3c03e8ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49804723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.49804723
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3688079462
Short name T186
Test name
Test status
Simulation time 261733180 ps
CPU time 1.43 seconds
Started Aug 04 05:36:14 PM PDT 24
Finished Aug 04 05:36:16 PM PDT 24
Peak memory 200548 kb
Host smart-f829eefd-3f0f-4faa-a432-baea543b9a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688079462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3688079462
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.519871218
Short name T138
Test name
Test status
Simulation time 58492279 ps
CPU time 0.76 seconds
Started Aug 04 05:36:08 PM PDT 24
Finished Aug 04 05:36:08 PM PDT 24
Peak memory 200160 kb
Host smart-b3342b15-1b54-4baa-b306-c56409895111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519871218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.519871218
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.923923771
Short name T337
Test name
Test status
Simulation time 1219619012 ps
CPU time 5.65 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:29 PM PDT 24
Peak memory 221712 kb
Host smart-f711a71c-a8eb-4826-bd08-f0a55eec47af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923923771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.923923771
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.4046575223
Short name T491
Test name
Test status
Simulation time 244698444 ps
CPU time 1.02 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 217504 kb
Host smart-10f721e1-2284-4780-88d9-b76dcd797696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046575223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.4046575223
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3452348645
Short name T499
Test name
Test status
Simulation time 84117966 ps
CPU time 0.76 seconds
Started Aug 04 05:36:19 PM PDT 24
Finished Aug 04 05:36:20 PM PDT 24
Peak memory 200156 kb
Host smart-993fa076-5024-4344-8a49-8afd04901772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452348645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3452348645
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.168856850
Short name T416
Test name
Test status
Simulation time 1557491853 ps
CPU time 5.77 seconds
Started Aug 04 05:36:18 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 200004 kb
Host smart-7a794229-8824-4323-97e5-fa57c44d3e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168856850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.168856850
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2019173814
Short name T443
Test name
Test status
Simulation time 102861761 ps
CPU time 1 seconds
Started Aug 04 05:36:14 PM PDT 24
Finished Aug 04 05:36:15 PM PDT 24
Peak memory 200308 kb
Host smart-108a8f56-edc7-4426-a044-9b07a0118414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019173814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2019173814
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1520178359
Short name T312
Test name
Test status
Simulation time 225372896 ps
CPU time 1.39 seconds
Started Aug 04 05:36:21 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 200480 kb
Host smart-6b2df512-3b13-458b-8f6f-90564a7d1bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520178359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1520178359
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2425649959
Short name T88
Test name
Test status
Simulation time 3906357028 ps
CPU time 13.66 seconds
Started Aug 04 05:36:20 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 208792 kb
Host smart-a678caee-f022-468b-8e09-8e6cb6c69f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425649959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2425649959
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2166404559
Short name T211
Test name
Test status
Simulation time 114161277 ps
CPU time 1.39 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200276 kb
Host smart-8defa9f2-7e70-49e8-8cc1-8708e5aa1799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166404559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2166404559
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3039673933
Short name T425
Test name
Test status
Simulation time 145990198 ps
CPU time 1.28 seconds
Started Aug 04 05:36:13 PM PDT 24
Finished Aug 04 05:36:15 PM PDT 24
Peak memory 200336 kb
Host smart-4e45bd74-1f1b-4d36-8a67-c8912a1333c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039673933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3039673933
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3511856400
Short name T151
Test name
Test status
Simulation time 55786090 ps
CPU time 0.72 seconds
Started Aug 04 05:36:18 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 200144 kb
Host smart-1b78170d-8ef6-4ca7-8cc1-b375e8aeda9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511856400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3511856400
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1926961326
Short name T475
Test name
Test status
Simulation time 1885000440 ps
CPU time 7.38 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 221748 kb
Host smart-c816b48d-fb41-448b-9e3e-7f6389b98ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926961326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1926961326
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.884284213
Short name T436
Test name
Test status
Simulation time 246358430 ps
CPU time 1.02 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:16 PM PDT 24
Peak memory 217468 kb
Host smart-837d7747-d61f-42fb-a4f5-df568c5a6f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884284213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.884284213
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1622715286
Short name T494
Test name
Test status
Simulation time 212155186 ps
CPU time 0.85 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 200148 kb
Host smart-ca393a02-6bd4-482c-b717-cf3ceb6a0cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622715286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1622715286
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1644954589
Short name T537
Test name
Test status
Simulation time 794952397 ps
CPU time 4.39 seconds
Started Aug 04 05:36:10 PM PDT 24
Finished Aug 04 05:36:15 PM PDT 24
Peak memory 200556 kb
Host smart-3c8a8417-9b3b-453b-97bb-f8f6be7fb2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644954589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1644954589
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.699946815
Short name T495
Test name
Test status
Simulation time 104037378 ps
CPU time 0.99 seconds
Started Aug 04 05:36:17 PM PDT 24
Finished Aug 04 05:36:19 PM PDT 24
Peak memory 200364 kb
Host smart-502b222d-e025-470d-bff5-afcfaf319e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699946815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.699946815
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3380934618
Short name T155
Test name
Test status
Simulation time 113236368 ps
CPU time 1.2 seconds
Started Aug 04 05:36:10 PM PDT 24
Finished Aug 04 05:36:11 PM PDT 24
Peak memory 200456 kb
Host smart-8ceeb4af-4e2d-417c-baf2-65871e5940e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380934618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3380934618
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.98422395
Short name T342
Test name
Test status
Simulation time 6646004460 ps
CPU time 22.82 seconds
Started Aug 04 05:36:19 PM PDT 24
Finished Aug 04 05:36:42 PM PDT 24
Peak memory 200592 kb
Host smart-f6318124-27a0-4263-a9c4-ea49d08fde52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98422395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.98422395
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1596060575
Short name T483
Test name
Test status
Simulation time 143196352 ps
CPU time 1.73 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200292 kb
Host smart-248b6111-66d4-496c-84fd-3cb1dbbad1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596060575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1596060575
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2765173280
Short name T146
Test name
Test status
Simulation time 132826141 ps
CPU time 1.03 seconds
Started Aug 04 05:36:20 PM PDT 24
Finished Aug 04 05:36:21 PM PDT 24
Peak memory 200352 kb
Host smart-c9bcebd5-e717-4291-ab19-1a32762418c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765173280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2765173280
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1617707654
Short name T418
Test name
Test status
Simulation time 54078615 ps
CPU time 0.74 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 200164 kb
Host smart-5d10186b-3163-4e48-b2cf-c653ffd9e598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617707654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1617707654
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4159524186
Short name T446
Test name
Test status
Simulation time 2364129657 ps
CPU time 7.68 seconds
Started Aug 04 05:35:32 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 217900 kb
Host smart-54ea5f55-4c46-4cfb-96aa-5508e68aebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159524186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4159524186
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3186017754
Short name T244
Test name
Test status
Simulation time 244580781 ps
CPU time 1.11 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 217504 kb
Host smart-562ac59a-70c0-4d2d-a994-fe83aa24f361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186017754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3186017754
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3006504004
Short name T169
Test name
Test status
Simulation time 225574125 ps
CPU time 1.02 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200120 kb
Host smart-6d11768a-a81e-4043-a5f1-2821678495e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006504004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3006504004
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3366443943
Short name T353
Test name
Test status
Simulation time 1129091181 ps
CPU time 4.71 seconds
Started Aug 04 05:35:19 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 200580 kb
Host smart-56ed4278-5e68-4260-9a1c-9106cf5b1807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366443943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3366443943
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2879084464
Short name T74
Test name
Test status
Simulation time 16706368699 ps
CPU time 24.03 seconds
Started Aug 04 05:35:21 PM PDT 24
Finished Aug 04 05:35:45 PM PDT 24
Peak memory 218252 kb
Host smart-7173fcd8-1008-4a8f-9e2b-4f2b833e4287
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879084464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2879084464
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1385072789
Short name T261
Test name
Test status
Simulation time 112146777 ps
CPU time 1.01 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 200244 kb
Host smart-d9916483-be8c-4454-9663-d1dd17af2a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385072789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1385072789
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3322073007
Short name T543
Test name
Test status
Simulation time 115239409 ps
CPU time 1.12 seconds
Started Aug 04 05:35:16 PM PDT 24
Finished Aug 04 05:35:18 PM PDT 24
Peak memory 200512 kb
Host smart-242dc6c3-5bff-488d-bd34-abc1220831a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322073007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3322073007
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3598185391
Short name T427
Test name
Test status
Simulation time 2509794813 ps
CPU time 9.74 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 208764 kb
Host smart-4c5fe75d-695d-4bdc-9010-76796cd703a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598185391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3598185391
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.693666649
Short name T480
Test name
Test status
Simulation time 117817157 ps
CPU time 1.41 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 200192 kb
Host smart-5c5ac590-c2a9-4e25-bae8-0dcdffa9162a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693666649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.693666649
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2024118136
Short name T423
Test name
Test status
Simulation time 124480197 ps
CPU time 1.06 seconds
Started Aug 04 05:35:18 PM PDT 24
Finished Aug 04 05:35:19 PM PDT 24
Peak memory 200312 kb
Host smart-9380f48f-5846-45aa-93ce-6804679fb8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024118136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2024118136
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2864767641
Short name T47
Test name
Test status
Simulation time 92156696 ps
CPU time 0.86 seconds
Started Aug 04 05:36:16 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 200136 kb
Host smart-ed67718a-c410-4a76-a664-6d8842792cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864767641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2864767641
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3715810513
Short name T31
Test name
Test status
Simulation time 2376015535 ps
CPU time 8.61 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:31 PM PDT 24
Peak memory 217204 kb
Host smart-8ddea8fd-f015-4c1b-be0c-97778cc10cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715810513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3715810513
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2432541716
Short name T314
Test name
Test status
Simulation time 243701189 ps
CPU time 1.17 seconds
Started Aug 04 05:36:14 PM PDT 24
Finished Aug 04 05:36:16 PM PDT 24
Peak memory 217528 kb
Host smart-cc8dee94-4b3c-41e6-b912-33c0e15ecaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432541716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2432541716
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3211016247
Short name T479
Test name
Test status
Simulation time 117156642 ps
CPU time 0.79 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:12 PM PDT 24
Peak memory 200112 kb
Host smart-5c7b8d1e-1ca8-4523-945c-e12decfa1fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211016247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3211016247
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.858738335
Short name T274
Test name
Test status
Simulation time 855032139 ps
CPU time 4.43 seconds
Started Aug 04 05:36:19 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 200548 kb
Host smart-3996b700-5ec8-4e19-b664-03683ff9a6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858738335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.858738335
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3782793931
Short name T129
Test name
Test status
Simulation time 181444121 ps
CPU time 1.18 seconds
Started Aug 04 05:36:13 PM PDT 24
Finished Aug 04 05:36:15 PM PDT 24
Peak memory 200320 kb
Host smart-8678a13d-664b-4a66-a142-fef9960818bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782793931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3782793931
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3669382130
Short name T215
Test name
Test status
Simulation time 118498579 ps
CPU time 1.19 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:14 PM PDT 24
Peak memory 200496 kb
Host smart-3a461822-e025-4a27-8420-f3cc6e3ccc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669382130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3669382130
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3652105527
Short name T228
Test name
Test status
Simulation time 7586976054 ps
CPU time 25.03 seconds
Started Aug 04 05:36:11 PM PDT 24
Finished Aug 04 05:36:37 PM PDT 24
Peak memory 200608 kb
Host smart-5b87d06d-54fc-4afd-b615-0582cc696d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652105527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3652105527
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.952655032
Short name T523
Test name
Test status
Simulation time 506614945 ps
CPU time 2.64 seconds
Started Aug 04 05:36:06 PM PDT 24
Finished Aug 04 05:36:09 PM PDT 24
Peak memory 200296 kb
Host smart-4ba34530-0eaa-4df7-b4e0-31872a7e5339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952655032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.952655032
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.264686168
Short name T512
Test name
Test status
Simulation time 75317713 ps
CPU time 0.79 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:16 PM PDT 24
Peak memory 200320 kb
Host smart-38dfbba8-eccd-4835-81c3-bde8cb834d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264686168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.264686168
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.34450938
Short name T179
Test name
Test status
Simulation time 63739718 ps
CPU time 0.73 seconds
Started Aug 04 05:36:17 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 200140 kb
Host smart-f05c7488-7ef6-4969-88a2-046afdc80fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34450938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.34450938
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1143041619
Short name T511
Test name
Test status
Simulation time 1225547612 ps
CPU time 6.03 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:29 PM PDT 24
Peak memory 217540 kb
Host smart-891713e3-697a-41b8-b4ca-aa2db4b8f795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143041619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1143041619
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1197969819
Short name T253
Test name
Test status
Simulation time 244238687 ps
CPU time 1.09 seconds
Started Aug 04 05:36:21 PM PDT 24
Finished Aug 04 05:36:22 PM PDT 24
Peak memory 217496 kb
Host smart-601c7964-1fb9-49f1-bef0-e03daf71ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197969819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1197969819
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.4142955408
Short name T203
Test name
Test status
Simulation time 142037220 ps
CPU time 0.81 seconds
Started Aug 04 05:36:09 PM PDT 24
Finished Aug 04 05:36:10 PM PDT 24
Peak memory 199624 kb
Host smart-7f39491c-93b9-42ed-9183-6bb770ad4830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142955408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4142955408
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3190719509
Short name T116
Test name
Test status
Simulation time 1900637189 ps
CPU time 7.2 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 200544 kb
Host smart-a46ad11d-420b-412d-a855-8bef25e9ef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190719509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3190719509
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1128705517
Short name T444
Test name
Test status
Simulation time 167781075 ps
CPU time 1.27 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 200316 kb
Host smart-30c3ba07-d51f-4129-a1c1-a9337b7abd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128705517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1128705517
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.3401151756
Short name T206
Test name
Test status
Simulation time 124120884 ps
CPU time 1.25 seconds
Started Aug 04 05:36:02 PM PDT 24
Finished Aug 04 05:36:04 PM PDT 24
Peak memory 200488 kb
Host smart-acde4145-519d-4f6f-83ef-2617ac7fb60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401151756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3401151756
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3962500114
Short name T178
Test name
Test status
Simulation time 1869378324 ps
CPU time 7.29 seconds
Started Aug 04 05:36:13 PM PDT 24
Finished Aug 04 05:36:21 PM PDT 24
Peak memory 208756 kb
Host smart-fce5d9ca-a111-4fb5-a7e4-37e537571acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962500114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3962500114
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1052690650
Short name T237
Test name
Test status
Simulation time 134857812 ps
CPU time 1.57 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 208480 kb
Host smart-5f504bf7-e994-4962-9c8d-6868c5de0b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052690650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1052690650
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.175019109
Short name T374
Test name
Test status
Simulation time 111451936 ps
CPU time 1.01 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200320 kb
Host smart-80938afa-512e-4b71-934a-3f88795a1132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175019109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.175019109
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.914496279
Short name T250
Test name
Test status
Simulation time 1901620165 ps
CPU time 7.42 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 220804 kb
Host smart-eedd5a4d-7039-4546-84cd-e89178dba865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914496279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.914496279
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.27413854
Short name T313
Test name
Test status
Simulation time 244617623 ps
CPU time 1.07 seconds
Started Aug 04 05:36:06 PM PDT 24
Finished Aug 04 05:36:07 PM PDT 24
Peak memory 217544 kb
Host smart-8f0608ad-59f8-4a2f-8742-adfe1484bf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27413854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.27413854
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.848534393
Short name T210
Test name
Test status
Simulation time 124205599 ps
CPU time 0.81 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200116 kb
Host smart-44d41b94-3d45-4253-8aa0-fdaba42aa588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848534393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.848534393
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2649222506
Short name T453
Test name
Test status
Simulation time 1914997573 ps
CPU time 6.98 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:30 PM PDT 24
Peak memory 200548 kb
Host smart-2f2b8393-8098-4fff-8941-9d5984fe289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649222506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2649222506
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1535900323
Short name T123
Test name
Test status
Simulation time 142442415 ps
CPU time 1.11 seconds
Started Aug 04 05:36:20 PM PDT 24
Finished Aug 04 05:36:21 PM PDT 24
Peak memory 200252 kb
Host smart-7d71baf5-719c-4e19-a33e-06e7346b02d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535900323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1535900323
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2543944339
Short name T192
Test name
Test status
Simulation time 189856907 ps
CPU time 1.31 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:14 PM PDT 24
Peak memory 200500 kb
Host smart-f512e040-1cc8-4cde-9fc3-355496b55a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543944339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2543944339
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2780488551
Short name T310
Test name
Test status
Simulation time 2158632184 ps
CPU time 9.63 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:35 PM PDT 24
Peak memory 200868 kb
Host smart-17fa7607-cb77-4b27-a67f-f4e9f3905cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780488551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2780488551
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3469557212
Short name T239
Test name
Test status
Simulation time 146655498 ps
CPU time 1.79 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200280 kb
Host smart-8c9202d6-f785-448a-8cc2-02b4dcd91949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469557212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3469557212
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.724262655
Short name T119
Test name
Test status
Simulation time 130440305 ps
CPU time 1.02 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:29 PM PDT 24
Peak memory 200316 kb
Host smart-cf3f735d-7191-4274-b8fd-f2a026096db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724262655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.724262655
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1632281924
Short name T357
Test name
Test status
Simulation time 90538606 ps
CPU time 0.84 seconds
Started Aug 04 05:36:17 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 200148 kb
Host smart-35b25d08-b1de-4283-8c89-569003e852e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632281924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1632281924
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1293112952
Short name T429
Test name
Test status
Simulation time 1226628053 ps
CPU time 5.55 seconds
Started Aug 04 05:36:12 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 221696 kb
Host smart-13ac8c13-b510-4a53-a553-72971f71e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293112952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1293112952
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2244568674
Short name T403
Test name
Test status
Simulation time 242787574 ps
CPU time 1.23 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 217484 kb
Host smart-e38c502b-472a-4e56-9e53-5ed35ca883d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244568674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2244568674
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.679321193
Short name T19
Test name
Test status
Simulation time 215898682 ps
CPU time 0.88 seconds
Started Aug 04 05:36:20 PM PDT 24
Finished Aug 04 05:36:21 PM PDT 24
Peak memory 200168 kb
Host smart-c378645f-4390-4a3b-b0bf-d857f1b895a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679321193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.679321193
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.249769454
Short name T196
Test name
Test status
Simulation time 1546623493 ps
CPU time 7.19 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:23 PM PDT 24
Peak memory 200580 kb
Host smart-73af841a-3323-441c-a0d3-521fdca0a9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249769454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.249769454
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.4210388432
Short name T539
Test name
Test status
Simulation time 104990714 ps
CPU time 0.95 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 200252 kb
Host smart-71a31724-2b0d-4eb1-91e8-b47c74a36c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210388432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.4210388432
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2351941793
Short name T397
Test name
Test status
Simulation time 251740045 ps
CPU time 1.74 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200548 kb
Host smart-6fceba63-4c2c-434a-b28f-85da44289335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351941793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2351941793
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2739578925
Short name T315
Test name
Test status
Simulation time 9225394893 ps
CPU time 41.11 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:37:08 PM PDT 24
Peak memory 208800 kb
Host smart-33fd0de0-bb23-4470-a6fc-ba2ccac21364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739578925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2739578925
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2145726487
Short name T434
Test name
Test status
Simulation time 133190738 ps
CPU time 1.7 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200300 kb
Host smart-6d3e3b79-1097-4e3e-bdbe-6b4be986363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145726487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2145726487
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3487274246
Short name T297
Test name
Test status
Simulation time 100200083 ps
CPU time 1 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 200308 kb
Host smart-38df4cd0-c068-4e50-b2d8-0711159e881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487274246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3487274246
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2300163048
Short name T380
Test name
Test status
Simulation time 71404727 ps
CPU time 0.75 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 200148 kb
Host smart-db393ca3-d0bf-4ea2-8f9e-189becd05eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300163048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2300163048
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1916308647
Short name T292
Test name
Test status
Simulation time 1906792680 ps
CPU time 7.3 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 217772 kb
Host smart-15b40154-f693-4e10-b58d-3176085ac9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916308647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1916308647
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3543810746
Short name T148
Test name
Test status
Simulation time 244161132 ps
CPU time 1.21 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 217732 kb
Host smart-6e5f94b4-7b8d-469c-8d57-f31fcaf717b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543810746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3543810746
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1797471414
Short name T402
Test name
Test status
Simulation time 118999161 ps
CPU time 0.83 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200120 kb
Host smart-743d7f58-cf2d-41d5-b4ea-691cd12baca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797471414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1797471414
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2014880805
Short name T232
Test name
Test status
Simulation time 1553535655 ps
CPU time 5.68 seconds
Started Aug 04 05:36:13 PM PDT 24
Finished Aug 04 05:36:18 PM PDT 24
Peak memory 200532 kb
Host smart-7dc937d6-73a8-44dd-a8c1-8140bc712586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014880805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2014880805
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1045467660
Short name T327
Test name
Test status
Simulation time 183900195 ps
CPU time 1.22 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200332 kb
Host smart-0de90048-2f8d-45f3-afa4-fed7c7dc0a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045467660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1045467660
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.4126731723
Short name T126
Test name
Test status
Simulation time 186413119 ps
CPU time 1.33 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200460 kb
Host smart-78ca6ae0-b4c2-4664-a6fa-f27f9229238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126731723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.4126731723
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.4176761971
Short name T412
Test name
Test status
Simulation time 3415340729 ps
CPU time 15.31 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:40 PM PDT 24
Peak memory 200564 kb
Host smart-f2e8a721-255e-442d-9f70-e5e9da748ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176761971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.4176761971
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3707907791
Short name T450
Test name
Test status
Simulation time 154791965 ps
CPU time 1.82 seconds
Started Aug 04 05:36:17 PM PDT 24
Finished Aug 04 05:36:19 PM PDT 24
Peak memory 200308 kb
Host smart-a9a8b613-6435-46a1-bba5-ff1234c14cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707907791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3707907791
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4012917987
Short name T317
Test name
Test status
Simulation time 159996727 ps
CPU time 1.14 seconds
Started Aug 04 05:36:20 PM PDT 24
Finished Aug 04 05:36:22 PM PDT 24
Peak memory 200360 kb
Host smart-ebd2bd25-aa14-446f-9878-0962156a353a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012917987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4012917987
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4268420739
Short name T271
Test name
Test status
Simulation time 66663605 ps
CPU time 0.79 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200140 kb
Host smart-e29a7ffa-fa6f-4f56-9b07-0fd8d6133b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268420739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4268420739
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1765493564
Short name T411
Test name
Test status
Simulation time 1221709054 ps
CPU time 5.68 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:31 PM PDT 24
Peak memory 217680 kb
Host smart-9b6b35e1-2257-4fbc-aade-eeb3d8c536cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765493564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1765493564
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2378694647
Short name T336
Test name
Test status
Simulation time 244981391 ps
CPU time 1.04 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 217452 kb
Host smart-eb95a2d3-d1f4-438c-8a0c-8a3d08668a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378694647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2378694647
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.4037204411
Short name T18
Test name
Test status
Simulation time 165439521 ps
CPU time 0.9 seconds
Started Aug 04 05:36:21 PM PDT 24
Finished Aug 04 05:36:22 PM PDT 24
Peak memory 200168 kb
Host smart-fd694d7d-ef91-4565-a394-2ef134cd222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037204411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.4037204411
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3941446025
Short name T115
Test name
Test status
Simulation time 1481341524 ps
CPU time 5.5 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200568 kb
Host smart-4ec136ed-2b3a-4476-aa9b-96dcc724e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941446025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3941446025
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.127947722
Short name T428
Test name
Test status
Simulation time 112499499 ps
CPU time 0.98 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200324 kb
Host smart-a059eb1f-cd07-4cf4-a04e-f59561a47332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127947722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.127947722
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1577884144
Short name T377
Test name
Test status
Simulation time 199363944 ps
CPU time 1.35 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 200472 kb
Host smart-24566ec7-6cf4-48b7-b0dd-b45cfde3ac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577884144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1577884144
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.751781330
Short name T195
Test name
Test status
Simulation time 2781936677 ps
CPU time 13.5 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:36 PM PDT 24
Peak memory 208996 kb
Host smart-acdd5d78-caaf-42e8-b4a7-519a79fd0cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751781330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.751781330
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1404226853
Short name T38
Test name
Test status
Simulation time 422624526 ps
CPU time 2.24 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 208544 kb
Host smart-3bc89942-e7ac-4bde-9198-3239182d64bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404226853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1404226853
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3861981664
Short name T165
Test name
Test status
Simulation time 93780349 ps
CPU time 0.88 seconds
Started Aug 04 05:36:19 PM PDT 24
Finished Aug 04 05:36:20 PM PDT 24
Peak memory 200352 kb
Host smart-79968d26-a40f-4980-9bae-e1a1a02826f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861981664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3861981664
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.588829158
Short name T311
Test name
Test status
Simulation time 62498681 ps
CPU time 0.78 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200068 kb
Host smart-5a130705-da9b-4853-988b-ee150bb0fd57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588829158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.588829158
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1140132597
Short name T422
Test name
Test status
Simulation time 1227002482 ps
CPU time 5.69 seconds
Started Aug 04 05:36:28 PM PDT 24
Finished Aug 04 05:36:34 PM PDT 24
Peak memory 216872 kb
Host smart-85aca8e5-c1b5-43ae-8b2f-9a6ed6d1a127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140132597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1140132597
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3919879620
Short name T484
Test name
Test status
Simulation time 245199238 ps
CPU time 1.05 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 217568 kb
Host smart-c471fb2d-64b3-4d8a-a052-5066e2bf30ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919879620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3919879620
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2626314638
Short name T462
Test name
Test status
Simulation time 199821819 ps
CPU time 0.88 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200152 kb
Host smart-133f5bde-ad8d-4a74-bc62-4ec129323ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626314638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2626314638
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.734247515
Short name T163
Test name
Test status
Simulation time 643412960 ps
CPU time 3.65 seconds
Started Aug 04 05:36:21 PM PDT 24
Finished Aug 04 05:36:24 PM PDT 24
Peak memory 200540 kb
Host smart-dcdea318-e011-4a80-9560-b4ac07eaf583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734247515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.734247515
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1375245989
Short name T390
Test name
Test status
Simulation time 144748504 ps
CPU time 1.08 seconds
Started Aug 04 05:36:23 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200332 kb
Host smart-b05c861e-cec2-4d08-85ef-ece1aafcd47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375245989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1375245989
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2272208843
Short name T305
Test name
Test status
Simulation time 225322787 ps
CPU time 1.44 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 200488 kb
Host smart-781bad21-9eb7-4181-933c-a2e0af7cc18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272208843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2272208843
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3326317181
Short name T234
Test name
Test status
Simulation time 9704948752 ps
CPU time 34.77 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:37:00 PM PDT 24
Peak memory 200600 kb
Host smart-0d4e3e07-ab61-43cf-8f08-8526e5bf61f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326317181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3326317181
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3620404381
Short name T270
Test name
Test status
Simulation time 136693796 ps
CPU time 1.64 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 208444 kb
Host smart-ec25548e-1c9d-46c6-98a2-880939b0d190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620404381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3620404381
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1807013861
Short name T132
Test name
Test status
Simulation time 140951603 ps
CPU time 1.04 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200352 kb
Host smart-89e2f2c4-93a5-41c5-9f6f-e37ce979c10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807013861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1807013861
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2648793107
Short name T230
Test name
Test status
Simulation time 76406810 ps
CPU time 0.8 seconds
Started Aug 04 05:36:16 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 200176 kb
Host smart-99207523-a08e-4744-a4c5-e60df2f38842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648793107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2648793107
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3674021712
Short name T498
Test name
Test status
Simulation time 1225959382 ps
CPU time 5.75 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:32 PM PDT 24
Peak memory 217740 kb
Host smart-c223bce9-aea8-4398-847b-707da219a43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674021712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3674021712
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.913232551
Short name T80
Test name
Test status
Simulation time 244946240 ps
CPU time 1.11 seconds
Started Aug 04 05:36:28 PM PDT 24
Finished Aug 04 05:36:29 PM PDT 24
Peak memory 217516 kb
Host smart-154ea72f-6e7b-4226-9d7d-7d697677e4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913232551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.913232551
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1867645233
Short name T519
Test name
Test status
Simulation time 153439206 ps
CPU time 0.86 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200168 kb
Host smart-73ffc147-f61f-4e2e-9cbe-2b10141cf81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867645233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1867645233
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2505183833
Short name T202
Test name
Test status
Simulation time 834652689 ps
CPU time 4.59 seconds
Started Aug 04 05:36:28 PM PDT 24
Finished Aug 04 05:36:32 PM PDT 24
Peak memory 200540 kb
Host smart-38c49875-16b0-449e-aaff-9695cbdd17f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505183833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2505183833
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1574376012
Short name T170
Test name
Test status
Simulation time 103451497 ps
CPU time 0.96 seconds
Started Aug 04 05:36:15 PM PDT 24
Finished Aug 04 05:36:17 PM PDT 24
Peak memory 200552 kb
Host smart-d20fee60-54a9-4820-a932-de403127ae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574376012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1574376012
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.602813257
Short name T14
Test name
Test status
Simulation time 246366020 ps
CPU time 1.43 seconds
Started Aug 04 05:36:28 PM PDT 24
Finished Aug 04 05:36:30 PM PDT 24
Peak memory 200492 kb
Host smart-5abb6e37-931b-4367-96e6-8f59b8d2ebd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602813257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.602813257
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1579393724
Short name T90
Test name
Test status
Simulation time 2359933681 ps
CPU time 8.91 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:33 PM PDT 24
Peak memory 208840 kb
Host smart-7d8eb27b-d735-4086-aefa-7be870cf6962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579393724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1579393724
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1147635402
Short name T387
Test name
Test status
Simulation time 370405702 ps
CPU time 2.4 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:30 PM PDT 24
Peak memory 200280 kb
Host smart-2aa4e349-0bc8-4878-99ba-4972ec160ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147635402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1147635402
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.103972396
Short name T189
Test name
Test status
Simulation time 149288677 ps
CPU time 1.13 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200336 kb
Host smart-6bccd020-c340-4c90-8f00-59b1ee6377d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103972396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.103972396
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1029976444
Short name T510
Test name
Test status
Simulation time 65276467 ps
CPU time 0.8 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200132 kb
Host smart-96971c3f-592d-4512-8ebb-8e14967126f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029976444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1029976444
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.428862964
Short name T289
Test name
Test status
Simulation time 1226998260 ps
CPU time 5.52 seconds
Started Aug 04 05:36:22 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 217728 kb
Host smart-c786486d-1fdd-4e50-a89c-26e2dd692e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428862964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.428862964
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.4290210909
Short name T467
Test name
Test status
Simulation time 244332833 ps
CPU time 1.16 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:26 PM PDT 24
Peak memory 217504 kb
Host smart-28bae447-bdba-4cc8-8cde-a5ca8388bd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290210909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.4290210909
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.510549146
Short name T214
Test name
Test status
Simulation time 116189913 ps
CPU time 0.83 seconds
Started Aug 04 05:36:30 PM PDT 24
Finished Aug 04 05:36:31 PM PDT 24
Peak memory 200128 kb
Host smart-488300ca-2193-4af3-8073-03ffe6510219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510549146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.510549146
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3133772794
Short name T535
Test name
Test status
Simulation time 931660832 ps
CPU time 4.24 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:31 PM PDT 24
Peak memory 200564 kb
Host smart-6c52e8f5-3dc7-499c-a23a-f46ee2e0cf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133772794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3133772794
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1135682042
Short name T166
Test name
Test status
Simulation time 102944001 ps
CPU time 0.98 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200344 kb
Host smart-b24f381d-47de-4132-9191-1d3b2c0b72e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135682042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1135682042
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2648877638
Short name T381
Test name
Test status
Simulation time 110738948 ps
CPU time 1.14 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200496 kb
Host smart-7a37d070-d093-442c-a32a-cd07add8dad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648877638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2648877638
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.484883143
Short name T24
Test name
Test status
Simulation time 3842274251 ps
CPU time 14.05 seconds
Started Aug 04 05:36:30 PM PDT 24
Finished Aug 04 05:36:44 PM PDT 24
Peak memory 208792 kb
Host smart-e992f07b-c24c-48e8-b403-116988588d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484883143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.484883143
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2749990569
Short name T461
Test name
Test status
Simulation time 154241655 ps
CPU time 2.32 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200320 kb
Host smart-817860f0-9d7e-4b97-afdc-88e930bc34d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749990569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2749990569
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1280149667
Short name T128
Test name
Test status
Simulation time 205275502 ps
CPU time 1.25 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:28 PM PDT 24
Peak memory 200316 kb
Host smart-4431df12-b61c-4b1b-a12e-6f7d1c6eada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280149667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1280149667
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2350187370
Short name T153
Test name
Test status
Simulation time 68609245 ps
CPU time 0.76 seconds
Started Aug 04 05:36:31 PM PDT 24
Finished Aug 04 05:36:32 PM PDT 24
Peak memory 200172 kb
Host smart-342a3c8f-52e2-458c-870a-de5ee3f5b07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350187370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2350187370
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1333908691
Short name T56
Test name
Test status
Simulation time 1221422192 ps
CPU time 5.88 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:32 PM PDT 24
Peak memory 221692 kb
Host smart-0ab80113-24c2-43eb-a0e5-8d7bf1b5e181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333908691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1333908691
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2083579639
Short name T350
Test name
Test status
Simulation time 244442517 ps
CPU time 1.08 seconds
Started Aug 04 05:36:25 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 217484 kb
Host smart-6b488c77-19e4-4ecf-a1ca-6b2db1d46daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083579639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2083579639
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1335487754
Short name T182
Test name
Test status
Simulation time 82913804 ps
CPU time 0.84 seconds
Started Aug 04 05:36:26 PM PDT 24
Finished Aug 04 05:36:27 PM PDT 24
Peak memory 200124 kb
Host smart-98a7ffbd-97c4-46aa-89d7-7647d9aa8a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335487754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1335487754
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3163851709
Short name T268
Test name
Test status
Simulation time 881959580 ps
CPU time 4.25 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:32 PM PDT 24
Peak memory 200568 kb
Host smart-44c6164f-28be-41e9-b38d-f8cb7b1a2fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163851709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3163851709
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3534214412
Short name T378
Test name
Test status
Simulation time 172827489 ps
CPU time 1.16 seconds
Started Aug 04 05:36:29 PM PDT 24
Finished Aug 04 05:36:30 PM PDT 24
Peak memory 200356 kb
Host smart-bb58edcf-00bc-46c2-95a0-d6578cec4fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534214412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3534214412
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1064253410
Short name T520
Test name
Test status
Simulation time 246981668 ps
CPU time 1.53 seconds
Started Aug 04 05:36:28 PM PDT 24
Finished Aug 04 05:36:29 PM PDT 24
Peak memory 200476 kb
Host smart-c91b928d-747d-4485-b457-fe25b49b2eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064253410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1064253410
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3339531188
Short name T36
Test name
Test status
Simulation time 5126733786 ps
CPU time 22.66 seconds
Started Aug 04 05:36:27 PM PDT 24
Finished Aug 04 05:36:50 PM PDT 24
Peak memory 200568 kb
Host smart-f9870aa4-2437-41b2-8f0a-7ff5c9c8e08c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339531188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3339531188
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2546882912
Short name T445
Test name
Test status
Simulation time 133120296 ps
CPU time 1.61 seconds
Started Aug 04 05:36:28 PM PDT 24
Finished Aug 04 05:36:30 PM PDT 24
Peak memory 200308 kb
Host smart-5098b1e2-d73b-4e57-b033-8fe22f0f2dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546882912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2546882912
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2450753321
Short name T264
Test name
Test status
Simulation time 101198650 ps
CPU time 0.89 seconds
Started Aug 04 05:36:24 PM PDT 24
Finished Aug 04 05:36:25 PM PDT 24
Peak memory 200336 kb
Host smart-95a7dd0c-c18a-474b-92b2-d355a20fff21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450753321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2450753321
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.997735983
Short name T136
Test name
Test status
Simulation time 73356916 ps
CPU time 0.85 seconds
Started Aug 04 05:35:23 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 200000 kb
Host smart-c02aabaa-1d3c-469c-90dd-616bfebfa80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997735983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.997735983
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.1579555168
Short name T344
Test name
Test status
Simulation time 1897257976 ps
CPU time 7.25 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 217496 kb
Host smart-9ed48d37-3a2d-42c7-88cf-a5a8919bf749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579555168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1579555168
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2567669820
Short name T457
Test name
Test status
Simulation time 244073482 ps
CPU time 1.08 seconds
Started Aug 04 05:35:23 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 217380 kb
Host smart-fdf26508-6c4a-4b11-b56e-b7a711ba9afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567669820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2567669820
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3769097601
Short name T22
Test name
Test status
Simulation time 134789495 ps
CPU time 0.8 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 200112 kb
Host smart-11a5e3dd-39b4-4917-b339-2efe04830fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769097601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3769097601
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2929237848
Short name T430
Test name
Test status
Simulation time 918039656 ps
CPU time 4.71 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:31 PM PDT 24
Peak memory 200532 kb
Host smart-acfc7cc6-c18f-4888-82b7-2b7ef08f655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929237848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2929237848
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1818956821
Short name T154
Test name
Test status
Simulation time 162909426 ps
CPU time 1.19 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 200344 kb
Host smart-6654d172-f22a-4cc8-a8ca-5ef4e9344e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818956821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1818956821
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2170598453
Short name T544
Test name
Test status
Simulation time 198707322 ps
CPU time 1.41 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 200496 kb
Host smart-3e94a232-8c07-44fe-8186-e5c1cdff6f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170598453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2170598453
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1519215655
Short name T278
Test name
Test status
Simulation time 6922796117 ps
CPU time 24.83 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:52 PM PDT 24
Peak memory 208804 kb
Host smart-97a67682-4c36-42b8-bc7c-f7738c002205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519215655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1519215655
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.29344936
Short name T279
Test name
Test status
Simulation time 260147997 ps
CPU time 1.78 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 200288 kb
Host smart-be71a22e-8246-4dba-bc6a-d7eb8776c867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29344936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.29344936
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1958400156
Short name T13
Test name
Test status
Simulation time 73120913 ps
CPU time 0.78 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 200352 kb
Host smart-b0b8f1f7-b48f-41d7-870f-44e58705071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958400156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1958400156
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1820438182
Short name T354
Test name
Test status
Simulation time 89820786 ps
CPU time 0.79 seconds
Started Aug 04 05:35:21 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 200140 kb
Host smart-dcc07fff-f228-41d1-a4b6-4f12c0b1c8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820438182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1820438182
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1719857697
Short name T424
Test name
Test status
Simulation time 1221659213 ps
CPU time 5.57 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 217712 kb
Host smart-4ccb2694-efa3-477c-a64e-07d5946c6d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719857697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1719857697
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.287083922
Short name T25
Test name
Test status
Simulation time 245533442 ps
CPU time 1.11 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:25 PM PDT 24
Peak memory 217528 kb
Host smart-d4428171-e7b7-4b11-ad06-c09111b3b85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287083922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.287083922
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3392507841
Short name T401
Test name
Test status
Simulation time 220948391 ps
CPU time 0.88 seconds
Started Aug 04 05:35:21 PM PDT 24
Finished Aug 04 05:35:22 PM PDT 24
Peak memory 200156 kb
Host smart-743b217d-d4b2-4450-b6de-ebb2846b06c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392507841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3392507841
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.620828681
Short name T526
Test name
Test status
Simulation time 843169025 ps
CPU time 4.46 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200600 kb
Host smart-bdf10996-2fb3-4974-a8f6-caac84cce1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620828681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.620828681
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2374732975
Short name T134
Test name
Test status
Simulation time 142736762 ps
CPU time 1.07 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 200320 kb
Host smart-f2adff10-cf1c-4414-9c26-7e246a5720a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374732975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2374732975
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3732983396
Short name T224
Test name
Test status
Simulation time 109822868 ps
CPU time 1.22 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200404 kb
Host smart-12caf7aa-4838-4763-9abb-ef7e4a26c352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732983396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3732983396
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.235410356
Short name T506
Test name
Test status
Simulation time 2762310357 ps
CPU time 10.16 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:36 PM PDT 24
Peak memory 200616 kb
Host smart-16335a0f-f541-448f-a7d5-1b16e16e3888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235410356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.235410356
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4079609753
Short name T452
Test name
Test status
Simulation time 149499903 ps
CPU time 1.84 seconds
Started Aug 04 05:35:21 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 200280 kb
Host smart-60f05367-356a-4d06-9b53-cee7bf84dbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079609753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4079609753
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2488914082
Short name T414
Test name
Test status
Simulation time 264911607 ps
CPU time 1.63 seconds
Started Aug 04 05:35:21 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 200488 kb
Host smart-1e7d0c18-2f68-4a5d-8f17-136a64550ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488914082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2488914082
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.4272457835
Short name T364
Test name
Test status
Simulation time 72700378 ps
CPU time 0.84 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200168 kb
Host smart-d29682ad-fd63-4086-b8fe-908bb6da5de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272457835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.4272457835
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.4125543594
Short name T298
Test name
Test status
Simulation time 1238332572 ps
CPU time 5.17 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:29 PM PDT 24
Peak memory 217704 kb
Host smart-c437377c-3df5-413d-883c-2a3da1288a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125543594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4125543594
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2155421939
Short name T190
Test name
Test status
Simulation time 244535215 ps
CPU time 1.02 seconds
Started Aug 04 05:35:21 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 217512 kb
Host smart-280aa024-e7de-4fa0-9997-8033e3b0346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155421939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2155421939
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.989481893
Short name T198
Test name
Test status
Simulation time 192862305 ps
CPU time 0.89 seconds
Started Aug 04 05:35:30 PM PDT 24
Finished Aug 04 05:35:31 PM PDT 24
Peak memory 200152 kb
Host smart-a09762cc-8806-4cec-bb86-674ffd85f1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989481893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.989481893
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3116629110
Short name T341
Test name
Test status
Simulation time 784374875 ps
CPU time 3.7 seconds
Started Aug 04 05:35:31 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200556 kb
Host smart-da8e0bea-a000-4825-a21d-ba1db54e8c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116629110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3116629110
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.956306753
Short name T300
Test name
Test status
Simulation time 105609934 ps
CPU time 1.03 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:23 PM PDT 24
Peak memory 200328 kb
Host smart-128a5182-b45c-4aab-98a0-95323d478522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956306753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.956306753
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2361674204
Short name T346
Test name
Test status
Simulation time 223997750 ps
CPU time 1.52 seconds
Started Aug 04 05:35:23 PM PDT 24
Finished Aug 04 05:35:24 PM PDT 24
Peak memory 200560 kb
Host smart-0797c056-5b35-4ce1-8675-70cb804fbdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361674204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2361674204
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3774345151
Short name T159
Test name
Test status
Simulation time 3876195740 ps
CPU time 16.82 seconds
Started Aug 04 05:35:22 PM PDT 24
Finished Aug 04 05:35:39 PM PDT 24
Peak memory 200636 kb
Host smart-c6ca465b-d39c-4480-a2a8-83d8afb7537c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774345151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3774345151
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1613556946
Short name T4
Test name
Test status
Simulation time 275584446 ps
CPU time 1.8 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200308 kb
Host smart-ce38f023-21d8-41ea-afef-921b6a7d2dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613556946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1613556946
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1279289830
Short name T476
Test name
Test status
Simulation time 143116793 ps
CPU time 1.13 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200324 kb
Host smart-b65f939d-942a-40cc-9c92-3a4e48114d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279289830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1279289830
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1809886993
Short name T369
Test name
Test status
Simulation time 70024129 ps
CPU time 0.87 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 200148 kb
Host smart-b76dd644-e9b6-47e2-9681-5ddd0a996b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809886993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1809886993
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3791839413
Short name T60
Test name
Test status
Simulation time 2161372789 ps
CPU time 7.95 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:34 PM PDT 24
Peak memory 217576 kb
Host smart-455211c4-1df2-4a98-938f-2f186556ec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791839413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3791839413
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1017000940
Short name T131
Test name
Test status
Simulation time 244527043 ps
CPU time 1.08 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:28 PM PDT 24
Peak memory 217540 kb
Host smart-eb98fa8a-d0dd-4ea3-9c07-b6c609e2dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017000940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1017000940
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.523285947
Short name T525
Test name
Test status
Simulation time 194241198 ps
CPU time 0.89 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:27 PM PDT 24
Peak memory 200152 kb
Host smart-fd9a2dd9-060e-4e2b-b8fe-cd1345383893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523285947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.523285947
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.836110372
Short name T360
Test name
Test status
Simulation time 731239389 ps
CPU time 3.7 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 200628 kb
Host smart-04f4773c-fea4-4f89-a74d-38de68b15d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836110372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.836110372
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3355437474
Short name T7
Test name
Test status
Simulation time 142482810 ps
CPU time 1.18 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:28 PM PDT 24
Peak memory 200204 kb
Host smart-871f8f50-c305-49e2-8b31-bed5894cea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355437474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3355437474
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2355260647
Short name T46
Test name
Test status
Simulation time 206446027 ps
CPU time 1.4 seconds
Started Aug 04 05:35:25 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200496 kb
Host smart-e38993f9-1c3f-4d80-bbcb-e402e560f46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355260647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2355260647
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3509172265
Short name T276
Test name
Test status
Simulation time 1381217233 ps
CPU time 7 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 208716 kb
Host smart-90c49383-4201-4df9-80ff-d333a147bb41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509172265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3509172265
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.734183459
Short name T117
Test name
Test status
Simulation time 527287765 ps
CPU time 3 seconds
Started Aug 04 05:35:35 PM PDT 24
Finished Aug 04 05:35:38 PM PDT 24
Peak memory 200280 kb
Host smart-6ac269c8-4095-486e-9888-14c719efcbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734183459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.734183459
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.902347919
Short name T351
Test name
Test status
Simulation time 285452692 ps
CPU time 1.49 seconds
Started Aug 04 05:35:24 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200504 kb
Host smart-9f36794b-ae6f-4d00-9bf4-7219608b390f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902347919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.902347919
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3897393236
Short name T37
Test name
Test status
Simulation time 53284763 ps
CPU time 0.75 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:26 PM PDT 24
Peak memory 200140 kb
Host smart-767849a6-7410-4ea3-8b5d-fcd3b9371b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897393236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3897393236
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1907234818
Short name T43
Test name
Test status
Simulation time 1226502668 ps
CPU time 5.81 seconds
Started Aug 04 05:35:26 PM PDT 24
Finished Aug 04 05:35:32 PM PDT 24
Peak memory 221668 kb
Host smart-9ceec208-461b-4b02-9729-87bba704b10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907234818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1907234818
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2351703285
Short name T524
Test name
Test status
Simulation time 244663570 ps
CPU time 1.11 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 217564 kb
Host smart-35edc8ed-508c-4dea-abf1-bf894095bcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351703285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2351703285
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.403664161
Short name T541
Test name
Test status
Simulation time 158111295 ps
CPU time 0.95 seconds
Started Aug 04 05:35:29 PM PDT 24
Finished Aug 04 05:35:30 PM PDT 24
Peak memory 200360 kb
Host smart-48f22224-2aa7-454d-8d96-25f2a4a6fc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403664161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.403664161
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.551910479
Short name T225
Test name
Test status
Simulation time 1614295973 ps
CPU time 6.35 seconds
Started Aug 04 05:35:27 PM PDT 24
Finished Aug 04 05:35:33 PM PDT 24
Peak memory 200536 kb
Host smart-f94ddf1a-6695-4a57-8c88-f69450c42be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551910479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.551910479
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.923100668
Short name T213
Test name
Test status
Simulation time 173691340 ps
CPU time 1.18 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200356 kb
Host smart-254ef648-471e-4d7b-95d2-7fe2d19b8d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923100668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.923100668
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3416606330
Short name T301
Test name
Test status
Simulation time 234407793 ps
CPU time 1.46 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200520 kb
Host smart-a7abbcb7-b48a-4180-8177-47d06e05cc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416606330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3416606330
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3312098807
Short name T8
Test name
Test status
Simulation time 1703635883 ps
CPU time 6.59 seconds
Started Aug 04 05:35:33 PM PDT 24
Finished Aug 04 05:35:40 PM PDT 24
Peak memory 200536 kb
Host smart-b5a89b98-604d-4485-83a0-8e3a8101b2c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312098807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3312098807
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2585717902
Short name T48
Test name
Test status
Simulation time 523194970 ps
CPU time 2.66 seconds
Started Aug 04 05:35:28 PM PDT 24
Finished Aug 04 05:35:31 PM PDT 24
Peak memory 200300 kb
Host smart-5025204d-767d-4b61-b8d0-2aa305333b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585717902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2585717902
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.854486678
Short name T207
Test name
Test status
Simulation time 149993813 ps
CPU time 1.17 seconds
Started Aug 04 05:35:34 PM PDT 24
Finished Aug 04 05:35:35 PM PDT 24
Peak memory 200320 kb
Host smart-13777e01-1a0c-431c-8d13-0e9ccb49fa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854486678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.854486678
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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