Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7752

1

T5

32

T6

157

T11

123

auto[1]

10902

1

T3

4

T5

25

T6

142

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5824	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6286	1			T1	1		T2	1		T3	2
reset_info_cp[2]	2822	1			T3	1		T5	11		T6	46
reset_info_cp[4]	3798	1			T3	1		T5	14		T6	71
reset_info_cp[8]	127	1			T6	1		T11	1		T63	1
reset_info_cp[16]	100	1			T6	2		T12	2		T63	2
reset_info_cp[32]	96	1			T11	3		T12	2		T63	2
reset_info_cp[64]	124	1			T6	2		T11	4		T12	5
reset_info_cp[128]	97	1			T6	1		T8	1		T12	3

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2992	1			T5	10		T6	54		T11	45
reset_info_cp[1]	auto[1]	2674	1			T3	1		T5	9		T6	53
reset_info_cp[2]	auto[0]	832	1			T5	2		T6	27		T11	15
reset_info_cp[2]	auto[1]	1990	1			T3	1		T5	9		T6	19
reset_info_cp[4]	auto[0]	1310	1			T5	11		T6	26		T11	22
reset_info_cp[4]	auto[1]	2488	1			T3	1		T5	3		T6	45
reset_info_cp[8]	auto[0]	52	1			T11	1		T39	1		T141	2
reset_info_cp[8]	auto[1]	75	1			T6	1		T63	1		T26	1
reset_info_cp[16]	auto[0]	40	1			T6	2		T12	1		T97	1
reset_info_cp[16]	auto[1]	60	1			T12	1		T63	2		T143	1
reset_info_cp[32]	auto[0]	41	1			T11	2		T12	1		T83	1
reset_info_cp[32]	auto[1]	55	1			T11	1		T12	1		T63	2
reset_info_cp[64]	auto[0]	47	1			T11	3		T12	2		T93	1
reset_info_cp[64]	auto[1]	77	1			T6	2		T11	1		T12	3
reset_info_cp[128]	auto[0]	35	1			T63	1		T141	1		T142	1
reset_info_cp[128]	auto[1]	62	1			T6	1		T8	1		T12	3