Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7834

1

T5

34

T6

155

T11

113

auto[1]

10820

1

T3

4

T5

23

T6

144

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5824	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6286	1			T1	1		T2	1		T3	2
reset_info_cp[2]	2822	1			T3	1		T5	11		T6	46
reset_info_cp[4]	3798	1			T3	1		T5	14		T6	71
reset_info_cp[8]	127	1			T6	1		T11	1		T63	1
reset_info_cp[16]	100	1			T6	2		T12	2		T63	2
reset_info_cp[32]	96	1			T11	3		T12	2		T63	2
reset_info_cp[64]	124	1			T6	2		T11	4		T12	5
reset_info_cp[128]	97	1			T6	1		T8	1		T12	3

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3026	1			T5	11		T6	57		T11	37
reset_info_cp[1]	auto[1]	2640	1			T3	1		T5	8		T6	50
reset_info_cp[2]	auto[0]	848	1			T5	7		T6	25		T11	14
reset_info_cp[2]	auto[1]	1974	1			T3	1		T5	4		T6	21
reset_info_cp[4]	auto[0]	1315	1			T5	8		T6	24		T11	26
reset_info_cp[4]	auto[1]	2483	1			T3	1		T5	6		T6	47
reset_info_cp[8]	auto[0]	50	1			T6	1		T11	1		T39	1
reset_info_cp[8]	auto[1]	77	1			T63	1		T26	1		T27	1
reset_info_cp[16]	auto[0]	36	1			T6	1		T12	1		T63	1
reset_info_cp[16]	auto[1]	64	1			T6	1		T12	1		T63	1
reset_info_cp[32]	auto[0]	44	1			T11	2		T12	2		T63	1
reset_info_cp[32]	auto[1]	52	1			T11	1		T63	1		T25	1
reset_info_cp[64]	auto[0]	57	1			T6	1		T11	3		T12	2
reset_info_cp[64]	auto[1]	67	1			T6	1		T11	1		T12	3
reset_info_cp[128]	auto[0]	39	1			T12	2		T141	1		T142	1
reset_info_cp[128]	auto[1]	58	1			T6	1		T8	1		T12	1