Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T539 /workspace/coverage/default/41.rstmgr_alert_test.2467093032 Aug 05 05:49:10 PM PDT 24 Aug 05 05:49:11 PM PDT 24 70450727 ps
T540 /workspace/coverage/default/26.rstmgr_sw_rst.3021915558 Aug 05 05:48:57 PM PDT 24 Aug 05 05:48:58 PM PDT 24 123949412 ps
T541 /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1004754664 Aug 05 05:48:29 PM PDT 24 Aug 05 05:48:30 PM PDT 24 168331104 ps
T542 /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3875837539 Aug 05 05:48:29 PM PDT 24 Aug 05 05:48:30 PM PDT 24 62900232 ps
T543 /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.719926188 Aug 05 05:48:58 PM PDT 24 Aug 05 05:48:59 PM PDT 24 245655391 ps
T60 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1611132153 Aug 05 06:07:13 PM PDT 24 Aug 05 06:07:16 PM PDT 24 355073666 ps
T54 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3110949805 Aug 05 06:07:15 PM PDT 24 Aug 05 06:07:15 PM PDT 24 63240833 ps
T55 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.145608322 Aug 05 06:07:41 PM PDT 24 Aug 05 06:07:43 PM PDT 24 180536062 ps
T56 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1395150266 Aug 05 06:07:08 PM PDT 24 Aug 05 06:07:13 PM PDT 24 1181088885 ps
T57 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2207828283 Aug 05 06:07:13 PM PDT 24 Aug 05 06:07:14 PM PDT 24 60620436 ps
T61 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2285979740 Aug 05 06:07:09 PM PDT 24 Aug 05 06:07:13 PM PDT 24 574031959 ps
T58 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.421051349 Aug 05 06:07:22 PM PDT 24 Aug 05 06:07:23 PM PDT 24 125523748 ps
T59 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3866011624 Aug 05 06:07:14 PM PDT 24 Aug 05 06:07:15 PM PDT 24 128606847 ps
T62 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2330188169 Aug 05 06:07:27 PM PDT 24 Aug 05 06:07:29 PM PDT 24 109997592 ps
T108 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1201813550 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:11 PM PDT 24 54361073 ps
T70 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1740771546 Aug 05 06:07:15 PM PDT 24 Aug 05 06:07:16 PM PDT 24 101405789 ps
T109 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.54635907 Aug 05 06:07:13 PM PDT 24 Aug 05 06:07:14 PM PDT 24 142109566 ps
T110 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1457811664 Aug 05 06:07:26 PM PDT 24 Aug 05 06:07:28 PM PDT 24 241369514 ps
T86 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1938249652 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:14 PM PDT 24 842711326 ps
T139 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1400816071 Aug 05 06:07:06 PM PDT 24 Aug 05 06:07:12 PM PDT 24 481445357 ps
T87 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1320122388 Aug 05 06:07:07 PM PDT 24 Aug 05 06:07:08 PM PDT 24 128540785 ps
T88 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1325667502 Aug 05 06:07:27 PM PDT 24 Aug 05 06:07:29 PM PDT 24 120522847 ps
T111 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3296809846 Aug 05 06:07:06 PM PDT 24 Aug 05 06:07:07 PM PDT 24 254777993 ps
T89 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.166850450 Aug 05 06:07:22 PM PDT 24 Aug 05 06:07:23 PM PDT 24 108607560 ps
T90 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3505086473 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:12 PM PDT 24 194370964 ps
T112 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2892267861 Aug 05 06:07:13 PM PDT 24 Aug 05 06:07:14 PM PDT 24 122999554 ps
T544 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2659547795 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:13 PM PDT 24 181192423 ps
T140 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1389795150 Aug 05 06:07:08 PM PDT 24 Aug 05 06:07:17 PM PDT 24 1982460128 ps
T116 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1236341258 Aug 05 06:07:20 PM PDT 24 Aug 05 06:07:22 PM PDT 24 429239355 ps
T113 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2215988321 Aug 05 06:07:22 PM PDT 24 Aug 05 06:07:23 PM PDT 24 74705141 ps
T114 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1550329422 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:22 PM PDT 24 56979604 ps
T115 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1353662950 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:22 PM PDT 24 82489956 ps
T545 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2497135932 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:11 PM PDT 24 92580928 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3461539991 Aug 05 06:07:09 PM PDT 24 Aug 05 06:07:10 PM PDT 24 83230556 ps
T547 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1286327318 Aug 05 06:07:20 PM PDT 24 Aug 05 06:07:21 PM PDT 24 206542378 ps
T117 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.520237602 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:14 PM PDT 24 515489075 ps
T136 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1533915846 Aug 05 06:07:14 PM PDT 24 Aug 05 06:07:17 PM PDT 24 813379491 ps
T548 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1056857652 Aug 05 06:07:23 PM PDT 24 Aug 05 06:07:24 PM PDT 24 129409199 ps
T120 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1766499611 Aug 05 06:07:15 PM PDT 24 Aug 05 06:07:17 PM PDT 24 490786078 ps
T121 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1637880849 Aug 05 06:07:16 PM PDT 24 Aug 05 06:07:18 PM PDT 24 153230403 ps
T96 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2463128110 Aug 05 06:07:05 PM PDT 24 Aug 05 06:07:06 PM PDT 24 141288913 ps
T119 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.19708803 Aug 05 06:07:20 PM PDT 24 Aug 05 06:07:23 PM PDT 24 895243428 ps
T549 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.941916800 Aug 05 06:07:25 PM PDT 24 Aug 05 06:07:27 PM PDT 24 640408328 ps
T550 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.322630801 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:23 PM PDT 24 197231051 ps
T124 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1481371535 Aug 05 06:07:08 PM PDT 24 Aug 05 06:07:10 PM PDT 24 430611112 ps
T551 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2673246712 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:22 PM PDT 24 95024984 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.866250637 Aug 05 06:07:06 PM PDT 24 Aug 05 06:07:09 PM PDT 24 801787194 ps
T553 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1372552087 Aug 05 06:07:13 PM PDT 24 Aug 05 06:07:13 PM PDT 24 66522952 ps
T554 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1963279195 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:13 PM PDT 24 135398765 ps
T555 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3802677966 Aug 05 06:07:25 PM PDT 24 Aug 05 06:07:28 PM PDT 24 401204350 ps
T556 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1652294559 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:22 PM PDT 24 72155168 ps
T557 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3989796786 Aug 05 06:07:31 PM PDT 24 Aug 05 06:07:34 PM PDT 24 293997456 ps
T558 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2781755677 Aug 05 06:07:19 PM PDT 24 Aug 05 06:07:23 PM PDT 24 557871497 ps
T559 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3704138105 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:12 PM PDT 24 295036921 ps
T560 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2836271338 Aug 05 06:07:19 PM PDT 24 Aug 05 06:07:20 PM PDT 24 164414070 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.452025547 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:14 PM PDT 24 251319359 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4136107112 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:15 PM PDT 24 320277215 ps
T563 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1513414478 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:23 PM PDT 24 265860832 ps
T564 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3518038621 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:12 PM PDT 24 118498218 ps
T565 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3204070804 Aug 05 06:07:22 PM PDT 24 Aug 05 06:07:26 PM PDT 24 604153682 ps
T566 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2335609754 Aug 05 06:07:22 PM PDT 24 Aug 05 06:07:23 PM PDT 24 84282055 ps
T567 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.727288913 Aug 05 06:07:23 PM PDT 24 Aug 05 06:07:24 PM PDT 24 76274460 ps
T568 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1084143049 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:13 PM PDT 24 215617060 ps
T569 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3251649931 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:11 PM PDT 24 73738575 ps
T570 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2693870487 Aug 05 06:07:14 PM PDT 24 Aug 05 06:07:16 PM PDT 24 245155557 ps
T571 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2634726225 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:11 PM PDT 24 81874438 ps
T572 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4063821351 Aug 05 06:07:09 PM PDT 24 Aug 05 06:07:11 PM PDT 24 191067666 ps
T573 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2471441931 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:17 PM PDT 24 720578595 ps
T574 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3163759613 Aug 05 06:07:19 PM PDT 24 Aug 05 06:07:20 PM PDT 24 56369102 ps
T575 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1741781350 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:23 PM PDT 24 133744467 ps
T576 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1524078686 Aug 05 06:07:06 PM PDT 24 Aug 05 06:07:07 PM PDT 24 140988321 ps
T137 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1496343797 Aug 05 06:07:07 PM PDT 24 Aug 05 06:07:09 PM PDT 24 430070624 ps
T577 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3072057284 Aug 05 06:07:08 PM PDT 24 Aug 05 06:07:09 PM PDT 24 138285527 ps
T118 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.655031254 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:15 PM PDT 24 785164327 ps
T578 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.647617060 Aug 05 06:07:15 PM PDT 24 Aug 05 06:07:16 PM PDT 24 85158392 ps
T579 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3109298540 Aug 05 06:07:14 PM PDT 24 Aug 05 06:07:16 PM PDT 24 289237365 ps
T580 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1349744039 Aug 05 06:07:20 PM PDT 24 Aug 05 06:07:21 PM PDT 24 80867434 ps
T122 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.482911204 Aug 05 06:07:20 PM PDT 24 Aug 05 06:07:23 PM PDT 24 976070607 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.123276521 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:11 PM PDT 24 73450703 ps
T582 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1165653803 Aug 05 06:07:16 PM PDT 24 Aug 05 06:07:18 PM PDT 24 139831101 ps
T583 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.42917099 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:24 PM PDT 24 911583976 ps
T123 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.338303964 Aug 05 06:07:22 PM PDT 24 Aug 05 06:07:24 PM PDT 24 474497107 ps
T584 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3784513661 Aug 05 06:07:23 PM PDT 24 Aug 05 06:07:25 PM PDT 24 101865248 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4234586343 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:11 PM PDT 24 150582192 ps
T586 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2148213705 Aug 05 06:07:20 PM PDT 24 Aug 05 06:07:21 PM PDT 24 60581735 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4196267284 Aug 05 06:07:08 PM PDT 24 Aug 05 06:07:10 PM PDT 24 165325908 ps
T588 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2826430968 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:22 PM PDT 24 133696253 ps
T589 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3957211465 Aug 05 06:07:20 PM PDT 24 Aug 05 06:07:21 PM PDT 24 199539092 ps
T590 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2204360247 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:12 PM PDT 24 162744511 ps
T591 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4269216433 Aug 05 06:07:09 PM PDT 24 Aug 05 06:07:11 PM PDT 24 207582585 ps
T592 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1790436011 Aug 05 06:07:15 PM PDT 24 Aug 05 06:07:17 PM PDT 24 116036472 ps
T593 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1474110703 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:13 PM PDT 24 54122344 ps
T594 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1713793918 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:15 PM PDT 24 266083186 ps
T595 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.936858873 Aug 05 06:07:34 PM PDT 24 Aug 05 06:07:36 PM PDT 24 98399679 ps
T596 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1378788849 Aug 05 06:07:34 PM PDT 24 Aug 05 06:07:36 PM PDT 24 427871337 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1645632645 Aug 05 06:07:14 PM PDT 24 Aug 05 06:07:16 PM PDT 24 208696867 ps
T598 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2379651497 Aug 05 06:07:22 PM PDT 24 Aug 05 06:07:23 PM PDT 24 79038147 ps
T599 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4174800408 Aug 05 06:07:12 PM PDT 24 Aug 05 06:07:14 PM PDT 24 129071880 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2489250877 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:13 PM PDT 24 322126254 ps
T601 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1337176075 Aug 05 06:07:19 PM PDT 24 Aug 05 06:07:20 PM PDT 24 141571120 ps
T602 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1870907873 Aug 05 06:07:07 PM PDT 24 Aug 05 06:07:08 PM PDT 24 268332790 ps
T603 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1576665805 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:24 PM PDT 24 494609174 ps
T604 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3269867626 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:12 PM PDT 24 199407418 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2395640558 Aug 05 06:07:06 PM PDT 24 Aug 05 06:07:08 PM PDT 24 139738667 ps
T606 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2001570447 Aug 05 06:07:09 PM PDT 24 Aug 05 06:07:10 PM PDT 24 79705049 ps
T607 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.332836789 Aug 05 06:07:14 PM PDT 24 Aug 05 06:07:16 PM PDT 24 488456765 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.306927654 Aug 05 06:07:25 PM PDT 24 Aug 05 06:07:27 PM PDT 24 434404973 ps
T609 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2717288303 Aug 05 06:07:10 PM PDT 24 Aug 05 06:07:13 PM PDT 24 777071126 ps
T610 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2830306399 Aug 05 06:07:28 PM PDT 24 Aug 05 06:07:29 PM PDT 24 73858675 ps
T138 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2542715698 Aug 05 06:07:13 PM PDT 24 Aug 05 06:07:15 PM PDT 24 426399812 ps
T611 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1182553370 Aug 05 06:07:08 PM PDT 24 Aug 05 06:07:10 PM PDT 24 366244408 ps
T612 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3223005499 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:23 PM PDT 24 158539793 ps
T613 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1759728973 Aug 05 06:07:19 PM PDT 24 Aug 05 06:07:20 PM PDT 24 68995623 ps
T614 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1964921998 Aug 05 06:07:14 PM PDT 24 Aug 05 06:07:15 PM PDT 24 81442940 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2622461855 Aug 05 06:07:09 PM PDT 24 Aug 05 06:07:11 PM PDT 24 205527593 ps
T616 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4146634236 Aug 05 06:07:08 PM PDT 24 Aug 05 06:07:10 PM PDT 24 154609475 ps
T617 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.203836594 Aug 05 06:07:21 PM PDT 24 Aug 05 06:07:24 PM PDT 24 922872655 ps
T618 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3061032071 Aug 05 06:07:09 PM PDT 24 Aug 05 06:07:12 PM PDT 24 269292376 ps
T619 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.269446880 Aug 05 06:07:14 PM PDT 24 Aug 05 06:07:15 PM PDT 24 81456491 ps
T620 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2562030505 Aug 05 06:07:15 PM PDT 24 Aug 05 06:07:17 PM PDT 24 188648035 ps

Test location /workspace/coverage/default/44.rstmgr_stress_all.3793288700
Short name T6
Test name
Test status
Simulation time 5282783986 ps
CPU time 23.09 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:47 PM PDT 24
Peak memory 200620 kb
Host smart-7ea97e34-c8be-44f1-8f0b-35eb9c193ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793288700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3793288700
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3630753749
Short name T130
Test name
Test status
Simulation time 336360759 ps
CPU time 2.07 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:20 PM PDT 24
Peak memory 200228 kb
Host smart-ebcba90b-5287-4921-a39b-6f721133125c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630753749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3630753749
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.145608322
Short name T55
Test name
Test status
Simulation time 180536062 ps
CPU time 1.82 seconds
Started Aug 05 06:07:41 PM PDT 24
Finished Aug 05 06:07:43 PM PDT 24
Peak memory 208528 kb
Host smart-cbd1b67c-581c-4ecd-ac3b-5ec64283d06d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145608322 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.145608322
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3978883247
Short name T68
Test name
Test status
Simulation time 59780611 ps
CPU time 0.75 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 200176 kb
Host smart-3233ba38-4684-4313-88f0-3debe7b197d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978883247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3978883247
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3481818202
Short name T71
Test name
Test status
Simulation time 17105675079 ps
CPU time 26.82 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:45 PM PDT 24
Peak memory 218236 kb
Host smart-5df7a165-c420-4e6a-840c-f973c2eb1843
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481818202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3481818202
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.4221037742
Short name T26
Test name
Test status
Simulation time 2359545342 ps
CPU time 8.75 seconds
Started Aug 05 05:48:40 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 217864 kb
Host smart-67fc2598-e1aa-4266-853a-8515140b3edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221037742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4221037742
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1938249652
Short name T86
Test name
Test status
Simulation time 842711326 ps
CPU time 2.88 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:14 PM PDT 24
Peak memory 200216 kb
Host smart-b4b54d43-41c9-4ff0-86b9-4b691de617dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938249652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1938249652
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.311922817
Short name T12
Test name
Test status
Simulation time 6017449510 ps
CPU time 27.25 seconds
Started Aug 05 05:48:46 PM PDT 24
Finished Aug 05 05:49:13 PM PDT 24
Peak memory 209660 kb
Host smart-6d8baae6-b5a5-4cde-84c2-8b24fa540fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311922817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.311922817
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1334647338
Short name T149
Test name
Test status
Simulation time 159314598 ps
CPU time 1.31 seconds
Started Aug 05 05:48:27 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 200280 kb
Host smart-9a45bd1e-106a-44a2-a533-1b4aafa9b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334647338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1334647338
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2606917466
Short name T28
Test name
Test status
Simulation time 1231203283 ps
CPU time 6.1 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 217796 kb
Host smart-19669138-a562-44ed-a9eb-2463fc1cab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606917466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2606917466
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4241804848
Short name T141
Test name
Test status
Simulation time 114899252 ps
CPU time 1.1 seconds
Started Aug 05 05:49:14 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 200348 kb
Host smart-89628e09-24fc-4b1a-97a2-fe3300a98efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241804848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4241804848
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2330188169
Short name T62
Test name
Test status
Simulation time 109997592 ps
CPU time 1.58 seconds
Started Aug 05 06:07:27 PM PDT 24
Finished Aug 05 06:07:29 PM PDT 24
Peak memory 208400 kb
Host smart-f1085ee1-1bf0-42a0-a168-7599ae27652a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330188169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2330188169
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.482911204
Short name T122
Test name
Test status
Simulation time 976070607 ps
CPU time 3.1 seconds
Started Aug 05 06:07:20 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 200220 kb
Host smart-c9a6b296-d889-4818-bb0f-2d0e600e82e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482911204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.482911204
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2198162378
Short name T125
Test name
Test status
Simulation time 3319219163 ps
CPU time 11.98 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:31 PM PDT 24
Peak memory 200584 kb
Host smart-898181c9-6d0f-4520-aec9-9f51959a12ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198162378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2198162378
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.19708803
Short name T119
Test name
Test status
Simulation time 895243428 ps
CPU time 2.9 seconds
Started Aug 05 06:07:20 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 200228 kb
Host smart-6f226a81-f424-4b82-8866-1ddf7efa9af3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19708803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.19708803
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1201813550
Short name T108
Test name
Test status
Simulation time 54361073 ps
CPU time 0.77 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 200008 kb
Host smart-973fbeb5-9bd0-4c02-8d8b-af8599abc68d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201813550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1201813550
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3829292451
Short name T1
Test name
Test status
Simulation time 119121384 ps
CPU time 0.81 seconds
Started Aug 05 05:48:32 PM PDT 24
Finished Aug 05 05:48:33 PM PDT 24
Peak memory 200148 kb
Host smart-62a07109-dbed-4f2b-8d2e-8f547a1cfa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829292451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3829292451
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1189165066
Short name T27
Test name
Test status
Simulation time 2335468247 ps
CPU time 8.09 seconds
Started Aug 05 05:48:26 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 221712 kb
Host smart-20fd4ea8-e533-487d-810c-f14aacac404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189165066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1189165066
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.655031254
Short name T118
Test name
Test status
Simulation time 785164327 ps
CPU time 2.78 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:15 PM PDT 24
Peak memory 200220 kb
Host smart-f01393e3-cd4e-445f-8c30-36b1f33ed724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655031254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.
655031254
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.452025547
Short name T561
Test name
Test status
Simulation time 251319359 ps
CPU time 1.66 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:14 PM PDT 24
Peak memory 200184 kb
Host smart-ebec30ed-18f1-498a-a0d6-cbe8bfbe0fbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452025547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.452025547
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1400816071
Short name T139
Test name
Test status
Simulation time 481445357 ps
CPU time 5.88 seconds
Started Aug 05 06:07:06 PM PDT 24
Finished Aug 05 06:07:12 PM PDT 24
Peak memory 216512 kb
Host smart-9b6dcc66-a751-41d0-b4e9-29bb0673a18a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400816071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
400816071
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1524078686
Short name T576
Test name
Test status
Simulation time 140988321 ps
CPU time 0.94 seconds
Started Aug 05 06:07:06 PM PDT 24
Finished Aug 05 06:07:07 PM PDT 24
Peak memory 200096 kb
Host smart-74743033-5629-407a-bc46-424d467a4cda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524078686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
524078686
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4234586343
Short name T585
Test name
Test status
Simulation time 150582192 ps
CPU time 1.37 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 208464 kb
Host smart-657535a4-521a-42d1-94fd-fd97a98641cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234586343 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.4234586343
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2634726225
Short name T571
Test name
Test status
Simulation time 81874438 ps
CPU time 0.87 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 200056 kb
Host smart-e404f244-38fe-4d89-b251-9852ba3a8255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634726225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2634726225
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3251649931
Short name T569
Test name
Test status
Simulation time 73738575 ps
CPU time 0.97 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 200100 kb
Host smart-0661180d-bfa8-420c-bc89-466220b1749f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251649931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3251649931
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2489250877
Short name T600
Test name
Test status
Simulation time 322126254 ps
CPU time 2.43 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 208344 kb
Host smart-1362b8d7-6446-4228-bb8a-4f44fa71c25f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489250877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2489250877
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1481371535
Short name T124
Test name
Test status
Simulation time 430611112 ps
CPU time 1.72 seconds
Started Aug 05 06:07:08 PM PDT 24
Finished Aug 05 06:07:10 PM PDT 24
Peak memory 200232 kb
Host smart-2ed912e1-47a5-4eca-a4ef-27fe019937a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481371535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1481371535
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1182553370
Short name T611
Test name
Test status
Simulation time 366244408 ps
CPU time 2.42 seconds
Started Aug 05 06:07:08 PM PDT 24
Finished Aug 05 06:07:10 PM PDT 24
Peak memory 200188 kb
Host smart-a919ea44-1244-45d8-b232-270027eb510a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182553370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
182553370
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3061032071
Short name T618
Test name
Test status
Simulation time 269292376 ps
CPU time 3.23 seconds
Started Aug 05 06:07:09 PM PDT 24
Finished Aug 05 06:07:12 PM PDT 24
Peak memory 208352 kb
Host smart-16309ca5-babc-47f3-babb-345f0c379906
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061032071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
061032071
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2395640558
Short name T605
Test name
Test status
Simulation time 139738667 ps
CPU time 0.98 seconds
Started Aug 05 06:07:06 PM PDT 24
Finished Aug 05 06:07:08 PM PDT 24
Peak memory 200060 kb
Host smart-6ed0be87-4525-484c-a35b-22f995a817e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395640558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
395640558
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4269216433
Short name T591
Test name
Test status
Simulation time 207582585 ps
CPU time 1.46 seconds
Started Aug 05 06:07:09 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 208392 kb
Host smart-ac3d69a4-21cc-4cac-9cd4-72fd556a4775
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269216433 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.4269216433
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1870907873
Short name T602
Test name
Test status
Simulation time 268332790 ps
CPU time 1.62 seconds
Started Aug 05 06:07:07 PM PDT 24
Finished Aug 05 06:07:08 PM PDT 24
Peak memory 200212 kb
Host smart-cd019fa9-c2a9-4ed2-be63-bddd817314fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870907873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1870907873
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3518038621
Short name T564
Test name
Test status
Simulation time 118498218 ps
CPU time 1.6 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:12 PM PDT 24
Peak memory 208344 kb
Host smart-6297c1a6-0b3e-4213-93de-ca79484d40f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518038621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3518038621
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2717288303
Short name T609
Test name
Test status
Simulation time 777071126 ps
CPU time 3.02 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 200212 kb
Host smart-b6e88da5-e4a2-43be-9dfa-2ca238a7c1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717288303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2717288303
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3866011624
Short name T59
Test name
Test status
Simulation time 128606847 ps
CPU time 1.03 seconds
Started Aug 05 06:07:14 PM PDT 24
Finished Aug 05 06:07:15 PM PDT 24
Peak memory 199360 kb
Host smart-fe523a4b-00ed-481f-8e66-78db3abbca0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866011624 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3866011624
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.647617060
Short name T578
Test name
Test status
Simulation time 85158392 ps
CPU time 0.83 seconds
Started Aug 05 06:07:15 PM PDT 24
Finished Aug 05 06:07:16 PM PDT 24
Peak memory 200028 kb
Host smart-8323d18e-f9ac-4911-914a-06a473b9b0b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647617060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.647617060
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.269446880
Short name T619
Test name
Test status
Simulation time 81456491 ps
CPU time 1 seconds
Started Aug 05 06:07:14 PM PDT 24
Finished Aug 05 06:07:15 PM PDT 24
Peak memory 200120 kb
Host smart-998665f9-06c9-4757-b222-983405ccb680
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269446880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.269446880
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2693870487
Short name T570
Test name
Test status
Simulation time 245155557 ps
CPU time 1.87 seconds
Started Aug 05 06:07:14 PM PDT 24
Finished Aug 05 06:07:16 PM PDT 24
Peak memory 211036 kb
Host smart-e00c8d04-79c8-4408-a08e-2b116ed65de1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693870487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2693870487
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1766499611
Short name T120
Test name
Test status
Simulation time 490786078 ps
CPU time 1.88 seconds
Started Aug 05 06:07:15 PM PDT 24
Finished Aug 05 06:07:17 PM PDT 24
Peak memory 200176 kb
Host smart-604319e7-ae97-477a-b052-a70242db8d41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766499611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1766499611
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1325667502
Short name T88
Test name
Test status
Simulation time 120522847 ps
CPU time 1.28 seconds
Started Aug 05 06:07:27 PM PDT 24
Finished Aug 05 06:07:29 PM PDT 24
Peak memory 208352 kb
Host smart-656b9ab8-72c4-443a-98e7-0a53234bb399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325667502 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1325667502
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1759728973
Short name T613
Test name
Test status
Simulation time 68995623 ps
CPU time 0.84 seconds
Started Aug 05 06:07:19 PM PDT 24
Finished Aug 05 06:07:20 PM PDT 24
Peak memory 200052 kb
Host smart-424a3983-9fff-455b-92ad-c4aa76f55337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759728973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1759728973
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2335609754
Short name T566
Test name
Test status
Simulation time 84282055 ps
CPU time 0.97 seconds
Started Aug 05 06:07:22 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 200132 kb
Host smart-76f7b2e6-e6bb-4b2e-81ca-9c6f64061dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335609754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2335609754
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3204070804
Short name T565
Test name
Test status
Simulation time 604153682 ps
CPU time 3.79 seconds
Started Aug 05 06:07:22 PM PDT 24
Finished Aug 05 06:07:26 PM PDT 24
Peak memory 208340 kb
Host smart-764eebf7-05f8-4ec1-9e3b-dbdc3aeb2c38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204070804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3204070804
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1652294559
Short name T556
Test name
Test status
Simulation time 72155168 ps
CPU time 0.78 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:22 PM PDT 24
Peak memory 200060 kb
Host smart-716e3201-83dc-4735-ad67-50bf10e85216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652294559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1652294559
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1286327318
Short name T547
Test name
Test status
Simulation time 206542378 ps
CPU time 1.41 seconds
Started Aug 05 06:07:20 PM PDT 24
Finished Aug 05 06:07:21 PM PDT 24
Peak memory 200268 kb
Host smart-322aad74-791e-4ad6-bbf2-e98446f5c182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286327318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1286327318
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1576665805
Short name T603
Test name
Test status
Simulation time 494609174 ps
CPU time 3.29 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:24 PM PDT 24
Peak memory 216436 kb
Host smart-7fadf565-7e16-4a92-9484-a8d2e5fc4a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576665805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1576665805
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.306927654
Short name T608
Test name
Test status
Simulation time 434404973 ps
CPU time 1.8 seconds
Started Aug 05 06:07:25 PM PDT 24
Finished Aug 05 06:07:27 PM PDT 24
Peak memory 200300 kb
Host smart-ceaf153a-fa03-425e-bff4-80c8acbcf0aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306927654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.306927654
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1741781350
Short name T575
Test name
Test status
Simulation time 133744467 ps
CPU time 1.18 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 208528 kb
Host smart-e1aef854-1758-41b3-80ea-455e265eba37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741781350 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1741781350
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1349744039
Short name T580
Test name
Test status
Simulation time 80867434 ps
CPU time 0.85 seconds
Started Aug 05 06:07:20 PM PDT 24
Finished Aug 05 06:07:21 PM PDT 24
Peak memory 200060 kb
Host smart-9fd58299-5cfe-4c5b-9146-f2691bd20764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349744039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1349744039
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1457811664
Short name T110
Test name
Test status
Simulation time 241369514 ps
CPU time 1.53 seconds
Started Aug 05 06:07:26 PM PDT 24
Finished Aug 05 06:07:28 PM PDT 24
Peak memory 200204 kb
Host smart-6c274cfc-b956-4e35-aa89-1c097388f967
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457811664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1457811664
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3223005499
Short name T612
Test name
Test status
Simulation time 158539793 ps
CPU time 1.55 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 208452 kb
Host smart-e64e8108-7740-4c71-a5cb-68a0ede646b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223005499 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3223005499
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2379651497
Short name T598
Test name
Test status
Simulation time 79038147 ps
CPU time 0.86 seconds
Started Aug 05 06:07:22 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 200028 kb
Host smart-8739c33f-65f4-407f-b51a-fe8b814e52fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379651497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2379651497
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2830306399
Short name T610
Test name
Test status
Simulation time 73858675 ps
CPU time 1.01 seconds
Started Aug 05 06:07:28 PM PDT 24
Finished Aug 05 06:07:29 PM PDT 24
Peak memory 200132 kb
Host smart-c4a2f917-d7e9-48be-8cf7-c84f8f1a503a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830306399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2830306399
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1637880849
Short name T121
Test name
Test status
Simulation time 153230403 ps
CPU time 2.05 seconds
Started Aug 05 06:07:16 PM PDT 24
Finished Aug 05 06:07:18 PM PDT 24
Peak memory 208296 kb
Host smart-45492496-d54c-414a-9402-80e2a4e58c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637880849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1637880849
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.203836594
Short name T617
Test name
Test status
Simulation time 922872655 ps
CPU time 3.09 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:24 PM PDT 24
Peak memory 200264 kb
Host smart-1fa0f35f-eae9-4df1-a578-0d361047fef0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203836594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.203836594
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1056857652
Short name T548
Test name
Test status
Simulation time 129409199 ps
CPU time 1.03 seconds
Started Aug 05 06:07:23 PM PDT 24
Finished Aug 05 06:07:24 PM PDT 24
Peak memory 200148 kb
Host smart-d3d93030-5a05-40e2-8bc0-21852142261a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056857652 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1056857652
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2148213705
Short name T586
Test name
Test status
Simulation time 60581735 ps
CPU time 0.83 seconds
Started Aug 05 06:07:20 PM PDT 24
Finished Aug 05 06:07:21 PM PDT 24
Peak memory 199948 kb
Host smart-0fdc24d6-17fc-47e8-a7d9-84083a2a7301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148213705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2148213705
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3784513661
Short name T584
Test name
Test status
Simulation time 101865248 ps
CPU time 1.24 seconds
Started Aug 05 06:07:23 PM PDT 24
Finished Aug 05 06:07:25 PM PDT 24
Peak memory 200216 kb
Host smart-1d463323-7fe3-48bc-8a74-aad536c0032a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784513661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3784513661
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3802677966
Short name T555
Test name
Test status
Simulation time 401204350 ps
CPU time 2.99 seconds
Started Aug 05 06:07:25 PM PDT 24
Finished Aug 05 06:07:28 PM PDT 24
Peak memory 211752 kb
Host smart-36c82aed-9884-4ec2-ad8f-0d3d6fa1cca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802677966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3802677966
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.941916800
Short name T549
Test name
Test status
Simulation time 640408328 ps
CPU time 2.2 seconds
Started Aug 05 06:07:25 PM PDT 24
Finished Aug 05 06:07:27 PM PDT 24
Peak memory 200220 kb
Host smart-91aff442-8965-4dec-8c80-9280a508de52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941916800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.941916800
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.322630801
Short name T550
Test name
Test status
Simulation time 197231051 ps
CPU time 2.08 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 208420 kb
Host smart-eb22c2b3-75d9-4cfd-bdff-deb6edd477d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322630801 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.322630801
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2215988321
Short name T113
Test name
Test status
Simulation time 74705141 ps
CPU time 0.83 seconds
Started Aug 05 06:07:22 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 199992 kb
Host smart-da5c1ff4-1e18-4116-bc12-206059fb7668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215988321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2215988321
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3957211465
Short name T589
Test name
Test status
Simulation time 199539092 ps
CPU time 1.49 seconds
Started Aug 05 06:07:20 PM PDT 24
Finished Aug 05 06:07:21 PM PDT 24
Peak memory 200280 kb
Host smart-59b3ecdf-ad04-4202-999d-eed78bddbbcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957211465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3957211465
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1513414478
Short name T563
Test name
Test status
Simulation time 265860832 ps
CPU time 2.12 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 211268 kb
Host smart-4394de33-5049-45a8-8753-94314139643c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513414478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1513414478
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.338303964
Short name T123
Test name
Test status
Simulation time 474497107 ps
CPU time 2.05 seconds
Started Aug 05 06:07:22 PM PDT 24
Finished Aug 05 06:07:24 PM PDT 24
Peak memory 200244 kb
Host smart-b941a8b7-425b-4119-a74c-f090e0e91edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338303964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.338303964
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2836271338
Short name T560
Test name
Test status
Simulation time 164414070 ps
CPU time 1.41 seconds
Started Aug 05 06:07:19 PM PDT 24
Finished Aug 05 06:07:20 PM PDT 24
Peak memory 208396 kb
Host smart-b5bd98d6-98f6-4f79-834d-90bbb3da9ba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836271338 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2836271338
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1550329422
Short name T114
Test name
Test status
Simulation time 56979604 ps
CPU time 0.83 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:22 PM PDT 24
Peak memory 200060 kb
Host smart-9dd92c11-fb71-455d-9c65-811de88019d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550329422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1550329422
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2826430968
Short name T588
Test name
Test status
Simulation time 133696253 ps
CPU time 1.27 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:22 PM PDT 24
Peak memory 200220 kb
Host smart-a63fbda8-5267-4e9f-ae0e-be724e4736a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826430968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2826430968
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2781755677
Short name T558
Test name
Test status
Simulation time 557871497 ps
CPU time 3.5 seconds
Started Aug 05 06:07:19 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 208328 kb
Host smart-db409d91-5d61-4ac2-9507-c224f129a359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781755677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2781755677
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1236341258
Short name T116
Test name
Test status
Simulation time 429239355 ps
CPU time 1.76 seconds
Started Aug 05 06:07:20 PM PDT 24
Finished Aug 05 06:07:22 PM PDT 24
Peak memory 200212 kb
Host smart-44a5c752-3f09-4e02-86cf-98e80923708c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236341258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1236341258
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.166850450
Short name T89
Test name
Test status
Simulation time 108607560 ps
CPU time 1.06 seconds
Started Aug 05 06:07:22 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 208340 kb
Host smart-3702dd20-6c6e-4492-93a2-75ed231cee09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166850450 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.166850450
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3163759613
Short name T574
Test name
Test status
Simulation time 56369102 ps
CPU time 0.75 seconds
Started Aug 05 06:07:19 PM PDT 24
Finished Aug 05 06:07:20 PM PDT 24
Peak memory 200060 kb
Host smart-0eec88ee-98d5-44e6-b4a7-849611699ad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163759613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3163759613
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2673246712
Short name T551
Test name
Test status
Simulation time 95024984 ps
CPU time 1.3 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:22 PM PDT 24
Peak memory 200224 kb
Host smart-5b58d0cf-5861-469f-a12d-ce200c6ba7b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673246712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2673246712
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3989796786
Short name T557
Test name
Test status
Simulation time 293997456 ps
CPU time 2.35 seconds
Started Aug 05 06:07:31 PM PDT 24
Finished Aug 05 06:07:34 PM PDT 24
Peak memory 208328 kb
Host smart-16cc675f-5541-4163-a174-d039fac60773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989796786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3989796786
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1378788849
Short name T596
Test name
Test status
Simulation time 427871337 ps
CPU time 1.78 seconds
Started Aug 05 06:07:34 PM PDT 24
Finished Aug 05 06:07:36 PM PDT 24
Peak memory 200188 kb
Host smart-8cacd506-7433-46d6-9f86-0f84c771e857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378788849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1378788849
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1337176075
Short name T601
Test name
Test status
Simulation time 141571120 ps
CPU time 1.08 seconds
Started Aug 05 06:07:19 PM PDT 24
Finished Aug 05 06:07:20 PM PDT 24
Peak memory 208304 kb
Host smart-27480157-1a9a-4e4a-ac94-de42902cf2a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337176075 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1337176075
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.727288913
Short name T567
Test name
Test status
Simulation time 76274460 ps
CPU time 0.87 seconds
Started Aug 05 06:07:23 PM PDT 24
Finished Aug 05 06:07:24 PM PDT 24
Peak memory 200056 kb
Host smart-755491d0-e742-434c-b17f-b559318619e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727288913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.727288913
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1353662950
Short name T115
Test name
Test status
Simulation time 82489956 ps
CPU time 0.98 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:22 PM PDT 24
Peak memory 200140 kb
Host smart-0036e92b-91e6-4285-89b5-37b10d4f3a10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353662950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1353662950
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.936858873
Short name T595
Test name
Test status
Simulation time 98399679 ps
CPU time 1.47 seconds
Started Aug 05 06:07:34 PM PDT 24
Finished Aug 05 06:07:36 PM PDT 24
Peak memory 210796 kb
Host smart-8e75834d-52bf-4f9d-9d0d-e0b25ba709cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936858873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.936858873
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.42917099
Short name T583
Test name
Test status
Simulation time 911583976 ps
CPU time 2.64 seconds
Started Aug 05 06:07:21 PM PDT 24
Finished Aug 05 06:07:24 PM PDT 24
Peak memory 200220 kb
Host smart-22ae3f8c-7f79-421e-af4d-a5abc98e3d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42917099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.42917099
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2622461855
Short name T615
Test name
Test status
Simulation time 205527593 ps
CPU time 1.54 seconds
Started Aug 05 06:07:09 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 200144 kb
Host smart-441b77ef-2778-445b-985e-8601adb49583
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622461855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
622461855
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1389795150
Short name T140
Test name
Test status
Simulation time 1982460128 ps
CPU time 8.73 seconds
Started Aug 05 06:07:08 PM PDT 24
Finished Aug 05 06:07:17 PM PDT 24
Peak memory 200132 kb
Host smart-f7af608f-5edd-4e9c-8b59-99c3332b812d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389795150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
389795150
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2497135932
Short name T545
Test name
Test status
Simulation time 92580928 ps
CPU time 0.89 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 200040 kb
Host smart-7c718741-433b-46e8-9566-3b351ac7ac53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497135932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
497135932
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1320122388
Short name T87
Test name
Test status
Simulation time 128540785 ps
CPU time 1.08 seconds
Started Aug 05 06:07:07 PM PDT 24
Finished Aug 05 06:07:08 PM PDT 24
Peak memory 208304 kb
Host smart-a74ec506-1ff8-4c4b-aa69-d85bd208e452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320122388 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1320122388
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.123276521
Short name T581
Test name
Test status
Simulation time 73450703 ps
CPU time 0.88 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 200060 kb
Host smart-288d0eee-1476-419a-a8fb-d805930bcbfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123276521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.123276521
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3296809846
Short name T111
Test name
Test status
Simulation time 254777993 ps
CPU time 1.66 seconds
Started Aug 05 06:07:06 PM PDT 24
Finished Aug 05 06:07:07 PM PDT 24
Peak memory 200076 kb
Host smart-e5eb2247-d2fd-47a9-8016-f10b58ada46c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296809846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3296809846
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3505086473
Short name T90
Test name
Test status
Simulation time 194370964 ps
CPU time 1.53 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:12 PM PDT 24
Peak memory 208196 kb
Host smart-946fa664-21d6-428d-9f87-753c500280d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505086473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3505086473
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4146634236
Short name T616
Test name
Test status
Simulation time 154609475 ps
CPU time 1.94 seconds
Started Aug 05 06:07:08 PM PDT 24
Finished Aug 05 06:07:10 PM PDT 24
Peak memory 200200 kb
Host smart-31134161-3ebf-441e-be59-9c919ac3e4e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146634236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4
146634236
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1395150266
Short name T56
Test name
Test status
Simulation time 1181088885 ps
CPU time 5.09 seconds
Started Aug 05 06:07:08 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 215868 kb
Host smart-dea67a75-1fad-49ad-9ec2-4b375e1c43e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395150266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
395150266
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3072057284
Short name T577
Test name
Test status
Simulation time 138285527 ps
CPU time 1.04 seconds
Started Aug 05 06:07:08 PM PDT 24
Finished Aug 05 06:07:09 PM PDT 24
Peak memory 200076 kb
Host smart-c2518620-7366-4ed2-9117-f0ca0091b771
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072057284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
072057284
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4196267284
Short name T587
Test name
Test status
Simulation time 165325908 ps
CPU time 1.5 seconds
Started Aug 05 06:07:08 PM PDT 24
Finished Aug 05 06:07:10 PM PDT 24
Peak memory 208412 kb
Host smart-8d3f9b64-5d09-435f-8b90-373ce588aa73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196267284 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.4196267284
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3461539991
Short name T546
Test name
Test status
Simulation time 83230556 ps
CPU time 0.84 seconds
Started Aug 05 06:07:09 PM PDT 24
Finished Aug 05 06:07:10 PM PDT 24
Peak memory 200064 kb
Host smart-166e3eeb-8780-43da-82d7-0a34c3314673
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461539991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3461539991
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1963279195
Short name T554
Test name
Test status
Simulation time 135398765 ps
CPU time 1.07 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 200064 kb
Host smart-1f069e65-61b3-4c42-8f1e-8bdf81f008ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963279195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1963279195
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2285979740
Short name T61
Test name
Test status
Simulation time 574031959 ps
CPU time 3.48 seconds
Started Aug 05 06:07:09 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 208356 kb
Host smart-c05e60cc-98f9-476e-a9db-d1c5e804d623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285979740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2285979740
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.866250637
Short name T552
Test name
Test status
Simulation time 801787194 ps
CPU time 2.9 seconds
Started Aug 05 06:07:06 PM PDT 24
Finished Aug 05 06:07:09 PM PDT 24
Peak memory 200216 kb
Host smart-ede321f7-706a-4f55-bb9b-2e5cadb2a555
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866250637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
866250637
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1645632645
Short name T597
Test name
Test status
Simulation time 208696867 ps
CPU time 1.56 seconds
Started Aug 05 06:07:14 PM PDT 24
Finished Aug 05 06:07:16 PM PDT 24
Peak memory 200128 kb
Host smart-fe94eadd-da3a-4a01-bf6b-d1182ad5a0b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645632645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
645632645
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1713793918
Short name T594
Test name
Test status
Simulation time 266083186 ps
CPU time 3.32 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:15 PM PDT 24
Peak memory 200020 kb
Host smart-4c4d013a-f668-4e7b-b476-168c676e3aab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713793918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
713793918
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2463128110
Short name T96
Test name
Test status
Simulation time 141288913 ps
CPU time 1 seconds
Started Aug 05 06:07:05 PM PDT 24
Finished Aug 05 06:07:06 PM PDT 24
Peak memory 200072 kb
Host smart-c38b4d0b-2bee-43f6-95a4-198fbace6aba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463128110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
463128110
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2204360247
Short name T590
Test name
Test status
Simulation time 162744511 ps
CPU time 1.57 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:12 PM PDT 24
Peak memory 208424 kb
Host smart-a9c4d333-95fc-4bea-a4e1-5c1347e2a2d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204360247 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2204360247
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2001570447
Short name T606
Test name
Test status
Simulation time 79705049 ps
CPU time 0.86 seconds
Started Aug 05 06:07:09 PM PDT 24
Finished Aug 05 06:07:10 PM PDT 24
Peak memory 200064 kb
Host smart-be1ada83-224a-487a-89c9-30767af5163f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001570447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2001570447
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.54635907
Short name T109
Test name
Test status
Simulation time 142109566 ps
CPU time 1.1 seconds
Started Aug 05 06:07:13 PM PDT 24
Finished Aug 05 06:07:14 PM PDT 24
Peak memory 200132 kb
Host smart-b9290be1-f061-4006-bf4a-b194ba4ec7a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54635907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same
_csr_outstanding.54635907
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3704138105
Short name T559
Test name
Test status
Simulation time 295036921 ps
CPU time 2.02 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:12 PM PDT 24
Peak memory 208348 kb
Host smart-6cdd84c6-f955-4d94-a500-22975233d92e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704138105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3704138105
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1496343797
Short name T137
Test name
Test status
Simulation time 430070624 ps
CPU time 1.92 seconds
Started Aug 05 06:07:07 PM PDT 24
Finished Aug 05 06:07:09 PM PDT 24
Peak memory 200248 kb
Host smart-2a42baf1-c0d1-46ae-af07-0aa5736c3b60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496343797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1496343797
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1084143049
Short name T568
Test name
Test status
Simulation time 215617060 ps
CPU time 1.43 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 200124 kb
Host smart-206f8b42-6c88-4ab1-a479-0571add6573e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084143049 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1084143049
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2207828283
Short name T57
Test name
Test status
Simulation time 60620436 ps
CPU time 0.73 seconds
Started Aug 05 06:07:13 PM PDT 24
Finished Aug 05 06:07:14 PM PDT 24
Peak memory 199916 kb
Host smart-6dc5ab1c-6374-4943-9386-3ff23d591225
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207828283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2207828283
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4063821351
Short name T572
Test name
Test status
Simulation time 191067666 ps
CPU time 1.46 seconds
Started Aug 05 06:07:09 PM PDT 24
Finished Aug 05 06:07:11 PM PDT 24
Peak memory 200216 kb
Host smart-34cc70b1-e333-4dec-acc0-9c04304ad282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063821351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4063821351
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1611132153
Short name T60
Test name
Test status
Simulation time 355073666 ps
CPU time 2.87 seconds
Started Aug 05 06:07:13 PM PDT 24
Finished Aug 05 06:07:16 PM PDT 24
Peak memory 216412 kb
Host smart-f9c22bdf-2ad6-4444-b857-6640b6f46c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611132153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1611132153
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.520237602
Short name T117
Test name
Test status
Simulation time 515489075 ps
CPU time 2.08 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:14 PM PDT 24
Peak memory 200260 kb
Host smart-9d24baba-3dca-412b-ab0a-3c59ebe5d374
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520237602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
520237602
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3269867626
Short name T604
Test name
Test status
Simulation time 199407418 ps
CPU time 1.51 seconds
Started Aug 05 06:07:10 PM PDT 24
Finished Aug 05 06:07:12 PM PDT 24
Peak memory 208320 kb
Host smart-f7e0199d-fa31-4764-b6a4-ee0d835c52a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269867626 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3269867626
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1372552087
Short name T553
Test name
Test status
Simulation time 66522952 ps
CPU time 0.77 seconds
Started Aug 05 06:07:13 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 200056 kb
Host smart-8d325246-8ebc-474e-a059-334167a49218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372552087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1372552087
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2892267861
Short name T112
Test name
Test status
Simulation time 122999554 ps
CPU time 1.06 seconds
Started Aug 05 06:07:13 PM PDT 24
Finished Aug 05 06:07:14 PM PDT 24
Peak memory 200132 kb
Host smart-39403c96-dd5f-4188-bc95-56a81b919deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892267861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2892267861
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3109298540
Short name T579
Test name
Test status
Simulation time 289237365 ps
CPU time 2.08 seconds
Started Aug 05 06:07:14 PM PDT 24
Finished Aug 05 06:07:16 PM PDT 24
Peak memory 208340 kb
Host smart-956b21e1-61b3-4c93-83d3-1af39bba5062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109298540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3109298540
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2542715698
Short name T138
Test name
Test status
Simulation time 426399812 ps
CPU time 1.86 seconds
Started Aug 05 06:07:13 PM PDT 24
Finished Aug 05 06:07:15 PM PDT 24
Peak memory 200244 kb
Host smart-f75843ac-209e-4735-ba45-789fbf80d728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542715698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2542715698
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1740771546
Short name T70
Test name
Test status
Simulation time 101405789 ps
CPU time 1.04 seconds
Started Aug 05 06:07:15 PM PDT 24
Finished Aug 05 06:07:16 PM PDT 24
Peak memory 208464 kb
Host smart-cd3db20c-b009-4c52-88ec-01647412a93b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740771546 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1740771546
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3110949805
Short name T54
Test name
Test status
Simulation time 63240833 ps
CPU time 0.76 seconds
Started Aug 05 06:07:15 PM PDT 24
Finished Aug 05 06:07:15 PM PDT 24
Peak memory 200048 kb
Host smart-58927838-71e7-42e7-86c1-6cf56c521f98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110949805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3110949805
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.421051349
Short name T58
Test name
Test status
Simulation time 125523748 ps
CPU time 0.99 seconds
Started Aug 05 06:07:22 PM PDT 24
Finished Aug 05 06:07:23 PM PDT 24
Peak memory 200096 kb
Host smart-6bfee4b1-ca7c-466e-bc42-784291f78aed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421051349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.421051349
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4136107112
Short name T562
Test name
Test status
Simulation time 320277215 ps
CPU time 2.37 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:15 PM PDT 24
Peak memory 211608 kb
Host smart-b4d9ac66-126b-4bda-9634-610e72a7feac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136107112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4136107112
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2659547795
Short name T544
Test name
Test status
Simulation time 181192423 ps
CPU time 1.25 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 200148 kb
Host smart-38e83d48-da16-43a6-adf7-a90365a4382e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659547795 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2659547795
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1474110703
Short name T593
Test name
Test status
Simulation time 54122344 ps
CPU time 0.75 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:13 PM PDT 24
Peak memory 199984 kb
Host smart-5ed6b993-5cd4-495a-a1a1-2505fe696c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474110703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1474110703
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1790436011
Short name T592
Test name
Test status
Simulation time 116036472 ps
CPU time 1.29 seconds
Started Aug 05 06:07:15 PM PDT 24
Finished Aug 05 06:07:17 PM PDT 24
Peak memory 200272 kb
Host smart-9edac1a2-17ea-4788-b404-4d70d16cf865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790436011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1790436011
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.4174800408
Short name T599
Test name
Test status
Simulation time 129071880 ps
CPU time 1.88 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:14 PM PDT 24
Peak memory 211692 kb
Host smart-0037cea9-79a2-4e5c-96b7-d6ee608729d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174800408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.4174800408
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.332836789
Short name T607
Test name
Test status
Simulation time 488456765 ps
CPU time 2.05 seconds
Started Aug 05 06:07:14 PM PDT 24
Finished Aug 05 06:07:16 PM PDT 24
Peak memory 200284 kb
Host smart-a2a585e6-5932-4360-bc5d-627ff0326934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332836789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
332836789
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2562030505
Short name T620
Test name
Test status
Simulation time 188648035 ps
CPU time 1.24 seconds
Started Aug 05 06:07:15 PM PDT 24
Finished Aug 05 06:07:17 PM PDT 24
Peak memory 200192 kb
Host smart-2e2b5602-755b-4ea5-a708-c987cd237836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562030505 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2562030505
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1964921998
Short name T614
Test name
Test status
Simulation time 81442940 ps
CPU time 0.84 seconds
Started Aug 05 06:07:14 PM PDT 24
Finished Aug 05 06:07:15 PM PDT 24
Peak memory 199176 kb
Host smart-138361c1-233d-4e9a-8a14-5993128699cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964921998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1964921998
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1165653803
Short name T582
Test name
Test status
Simulation time 139831101 ps
CPU time 1.19 seconds
Started Aug 05 06:07:16 PM PDT 24
Finished Aug 05 06:07:18 PM PDT 24
Peak memory 200096 kb
Host smart-ba8238d8-d156-42e0-8a4f-f7638e52d412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165653803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1165653803
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2471441931
Short name T573
Test name
Test status
Simulation time 720578595 ps
CPU time 4.37 seconds
Started Aug 05 06:07:12 PM PDT 24
Finished Aug 05 06:07:17 PM PDT 24
Peak memory 212612 kb
Host smart-1a88d5ce-8437-4eef-8e3d-ec0fb11874ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471441931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2471441931
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1533915846
Short name T136
Test name
Test status
Simulation time 813379491 ps
CPU time 2.87 seconds
Started Aug 05 06:07:14 PM PDT 24
Finished Aug 05 06:07:17 PM PDT 24
Peak memory 200200 kb
Host smart-ab5f2085-fb9e-4c80-8e8d-83953ff6c180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533915846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1533915846
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.967387776
Short name T320
Test name
Test status
Simulation time 55651127 ps
CPU time 0.69 seconds
Started Aug 05 05:48:12 PM PDT 24
Finished Aug 05 05:48:12 PM PDT 24
Peak memory 200160 kb
Host smart-0b6563fa-ac81-4f24-9f0b-6cb76a0c751b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967387776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.967387776
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3652067783
Short name T196
Test name
Test status
Simulation time 243819699 ps
CPU time 1.11 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 217492 kb
Host smart-f7b4338d-2c3c-4e59-98ae-31278b2c323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652067783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3652067783
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3385528031
Short name T504
Test name
Test status
Simulation time 171821523 ps
CPU time 0.93 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 200096 kb
Host smart-86c01612-a813-46b6-af14-f52502301ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385528031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3385528031
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2264073564
Short name T471
Test name
Test status
Simulation time 1252539673 ps
CPU time 4.63 seconds
Started Aug 05 05:48:22 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 200572 kb
Host smart-2925c853-e2ed-4c73-82b5-c7b533ac3558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264073564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2264073564
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2952890280
Short name T274
Test name
Test status
Simulation time 172822558 ps
CPU time 1.19 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 200320 kb
Host smart-aa4b23aa-23e2-4bbb-8eaf-61a9cde45e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952890280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2952890280
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3705437412
Short name T267
Test name
Test status
Simulation time 194953564 ps
CPU time 1.35 seconds
Started Aug 05 05:48:12 PM PDT 24
Finished Aug 05 05:48:14 PM PDT 24
Peak memory 200544 kb
Host smart-bfa4bba4-e642-4d78-b392-46159b8d0cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705437412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3705437412
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4092866662
Short name T393
Test name
Test status
Simulation time 6085046962 ps
CPU time 22.42 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:47 PM PDT 24
Peak memory 200672 kb
Host smart-c06bcaa1-adb6-420a-b994-8d40b529f867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092866662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4092866662
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3890778300
Short name T356
Test name
Test status
Simulation time 298074827 ps
CPU time 1.94 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 208392 kb
Host smart-c714d477-549b-4d07-bdad-1a8f24d029f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890778300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3890778300
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1490032387
Short name T445
Test name
Test status
Simulation time 96579227 ps
CPU time 0.96 seconds
Started Aug 05 05:48:02 PM PDT 24
Finished Aug 05 05:48:03 PM PDT 24
Peak memory 200348 kb
Host smart-2d2ef8cc-7e2d-46f2-8e31-1bd571c75149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490032387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1490032387
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1410304846
Short name T79
Test name
Test status
Simulation time 144525432 ps
CPU time 0.85 seconds
Started Aug 05 05:48:15 PM PDT 24
Finished Aug 05 05:48:16 PM PDT 24
Peak memory 200152 kb
Host smart-3f40fd6e-7673-4d43-a1e0-a68e0dea57c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410304846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1410304846
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.261471665
Short name T492
Test name
Test status
Simulation time 1229666250 ps
CPU time 5.85 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 216800 kb
Host smart-138f39f7-91d6-45d8-8cf9-b31bb0df0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261471665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.261471665
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1559212802
Short name T4
Test name
Test status
Simulation time 243613705 ps
CPU time 1.03 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 217464 kb
Host smart-bf042ccf-af5f-4607-bd27-ee98f4c053b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559212802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1559212802
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2236511906
Short name T472
Test name
Test status
Simulation time 174242641 ps
CPU time 0.93 seconds
Started Aug 05 05:48:04 PM PDT 24
Finished Aug 05 05:48:05 PM PDT 24
Peak memory 200040 kb
Host smart-190e1e4e-a99c-4240-9e8c-19e23033ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236511906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2236511906
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3453045328
Short name T227
Test name
Test status
Simulation time 829254139 ps
CPU time 4.24 seconds
Started Aug 05 05:48:09 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 200492 kb
Host smart-1d8d1e41-da91-4d06-8993-26dd1effd9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453045328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3453045328
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3054527146
Short name T66
Test name
Test status
Simulation time 8543392417 ps
CPU time 13.34 seconds
Started Aug 05 05:48:33 PM PDT 24
Finished Aug 05 05:48:47 PM PDT 24
Peak memory 217260 kb
Host smart-0dc790f3-c51f-4f36-86ce-3fc3b5cab8d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054527146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3054527146
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3604497381
Short name T437
Test name
Test status
Simulation time 105036255 ps
CPU time 1.02 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200344 kb
Host smart-026f6148-b023-43b5-87e8-8364d08db3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604497381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3604497381
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2484782670
Short name T439
Test name
Test status
Simulation time 181538370 ps
CPU time 1.49 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:48:08 PM PDT 24
Peak memory 200488 kb
Host smart-d854ab3d-bae1-4b71-9d92-291284bbc96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484782670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2484782670
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3610234847
Short name T271
Test name
Test status
Simulation time 343192675 ps
CPU time 1.9 seconds
Started Aug 05 05:48:22 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 200308 kb
Host smart-234807ff-4fbc-4ea6-9eda-539236ac0d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610234847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3610234847
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1115748160
Short name T347
Test name
Test status
Simulation time 118276512 ps
CPU time 1.15 seconds
Started Aug 05 05:48:12 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 200340 kb
Host smart-081f8a2e-af15-486a-aa4f-6155cc980f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115748160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1115748160
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1117930069
Short name T355
Test name
Test status
Simulation time 65814364 ps
CPU time 0.77 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 200160 kb
Host smart-20b67f0e-a6b6-43d4-b3d5-3bf5d15de537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117930069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1117930069
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3527370924
Short name T33
Test name
Test status
Simulation time 1232865635 ps
CPU time 6.36 seconds
Started Aug 05 05:48:46 PM PDT 24
Finished Aug 05 05:48:52 PM PDT 24
Peak memory 221688 kb
Host smart-c3965ed5-9286-46d8-bda6-6d1cad831843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527370924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3527370924
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3107944714
Short name T209
Test name
Test status
Simulation time 244204143 ps
CPU time 1.07 seconds
Started Aug 05 05:48:22 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 217560 kb
Host smart-bf18229b-b06e-49f0-8672-a804863352ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107944714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3107944714
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.632927645
Short name T212
Test name
Test status
Simulation time 167239827 ps
CPU time 0.88 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 200136 kb
Host smart-afdaa7f6-7406-4f1b-a8a6-9676332dd899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632927645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.632927645
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.166148283
Short name T181
Test name
Test status
Simulation time 1530341237 ps
CPU time 6.05 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 200436 kb
Host smart-21529af3-97da-4352-9615-4f0830290978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166148283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.166148283
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.516867708
Short name T326
Test name
Test status
Simulation time 174484834 ps
CPU time 1.13 seconds
Started Aug 05 05:48:28 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 200360 kb
Host smart-c68266ab-ad5c-4d3c-b14e-58c6cdccea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516867708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.516867708
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2565266395
Short name T256
Test name
Test status
Simulation time 246078500 ps
CPU time 1.49 seconds
Started Aug 05 05:48:33 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 200528 kb
Host smart-c0d73db6-0330-40ed-ab6f-e80e627cf6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565266395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2565266395
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1874283484
Short name T381
Test name
Test status
Simulation time 5879110642 ps
CPU time 25.37 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:45 PM PDT 24
Peak memory 208784 kb
Host smart-48c45133-29c0-4606-a824-20711fc6b9e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874283484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1874283484
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.4168718956
Short name T438
Test name
Test status
Simulation time 308909426 ps
CPU time 1.54 seconds
Started Aug 05 05:48:32 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 200496 kb
Host smart-85f9a29e-4e39-4afa-94bf-b8994ac004f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168718956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.4168718956
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.678535134
Short name T423
Test name
Test status
Simulation time 65866953 ps
CPU time 0.75 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 200140 kb
Host smart-5588d089-2230-4542-9b8b-6763b90b583e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678535134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.678535134
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1776076341
Short name T304
Test name
Test status
Simulation time 1883209285 ps
CPU time 7.64 seconds
Started Aug 05 05:48:44 PM PDT 24
Finished Aug 05 05:48:51 PM PDT 24
Peak memory 217844 kb
Host smart-1f2542b3-cbb2-4f32-a735-29f9758c04be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776076341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1776076341
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.110020524
Short name T512
Test name
Test status
Simulation time 243777842 ps
CPU time 1.05 seconds
Started Aug 05 05:48:32 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 217468 kb
Host smart-2ac2f7f0-c627-41ff-a52b-445f8b1dee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110020524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.110020524
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3570036581
Short name T389
Test name
Test status
Simulation time 148203901 ps
CPU time 0.82 seconds
Started Aug 05 05:48:27 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 200160 kb
Host smart-f5f6a09e-e845-42fb-80f1-dbf16927f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570036581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3570036581
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4152692635
Short name T485
Test name
Test status
Simulation time 1020462905 ps
CPU time 5.29 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200568 kb
Host smart-5239848c-5167-4f44-8ddf-dc35e426585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152692635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4152692635
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3520951223
Short name T162
Test name
Test status
Simulation time 98690971 ps
CPU time 0.99 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 200356 kb
Host smart-57184aec-3d84-4fe1-8a47-ca2da7189a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520951223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3520951223
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.399330538
Short name T398
Test name
Test status
Simulation time 250577796 ps
CPU time 1.5 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 200488 kb
Host smart-be412b22-64f0-4ce0-8db1-27983c2b39d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399330538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.399330538
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2791870601
Short name T410
Test name
Test status
Simulation time 1043707062 ps
CPU time 5.12 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 200556 kb
Host smart-f200a244-f65e-4512-b953-93563f5775ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791870601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2791870601
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1588272230
Short name T280
Test name
Test status
Simulation time 365363510 ps
CPU time 2.04 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 200288 kb
Host smart-8521f9d3-ce8f-4f3a-a6f3-85715ae1a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588272230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1588272230
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.314909411
Short name T373
Test name
Test status
Simulation time 97998747 ps
CPU time 0.94 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 200352 kb
Host smart-e5e5125e-6d45-42a0-838f-79f8e98161e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314909411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.314909411
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3519562559
Short name T150
Test name
Test status
Simulation time 80951810 ps
CPU time 0.79 seconds
Started Aug 05 05:48:30 PM PDT 24
Finished Aug 05 05:48:31 PM PDT 24
Peak memory 200168 kb
Host smart-463eb2ad-3dc6-4cea-87bc-508bf4c4dacd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519562559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3519562559
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.13753296
Short name T52
Test name
Test status
Simulation time 2349350084 ps
CPU time 7.91 seconds
Started Aug 05 05:48:28 PM PDT 24
Finished Aug 05 05:48:36 PM PDT 24
Peak memory 221744 kb
Host smart-dbe26083-e197-4d15-8d6d-cc3954ce298f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13753296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.13753296
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2685888331
Short name T199
Test name
Test status
Simulation time 244440345 ps
CPU time 1.11 seconds
Started Aug 05 05:48:36 PM PDT 24
Finished Aug 05 05:48:37 PM PDT 24
Peak memory 217560 kb
Host smart-ea83669c-ee72-4b36-8d52-99fc2016899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685888331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2685888331
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1546317166
Short name T391
Test name
Test status
Simulation time 95830218 ps
CPU time 0.77 seconds
Started Aug 05 05:48:30 PM PDT 24
Finished Aug 05 05:48:35 PM PDT 24
Peak memory 200160 kb
Host smart-611235a3-3e0d-4c66-bc5e-fa378f04e620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546317166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1546317166
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1884738339
Short name T399
Test name
Test status
Simulation time 1532418732 ps
CPU time 5.58 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200424 kb
Host smart-33589d16-95d1-4e9f-89da-474a4542fe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884738339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1884738339
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2580624701
Short name T74
Test name
Test status
Simulation time 110413344 ps
CPU time 1.06 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 200356 kb
Host smart-8a677451-de9b-4a5d-b7cc-be8b8f026978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580624701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2580624701
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.324725958
Short name T288
Test name
Test status
Simulation time 250250815 ps
CPU time 1.64 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 200532 kb
Host smart-5c7e98d3-0080-4533-bf82-972eab9791ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324725958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.324725958
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2384784488
Short name T503
Test name
Test status
Simulation time 5335568557 ps
CPU time 24.56 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 208792 kb
Host smart-10320d88-8ab3-4081-adfe-dcdba7832020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384784488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2384784488
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3508731409
Short name T245
Test name
Test status
Simulation time 134202248 ps
CPU time 1.68 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 200168 kb
Host smart-e41ac0b8-206b-4b23-9af4-5839b9c27a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508731409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3508731409
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3875837539
Short name T542
Test name
Test status
Simulation time 62900232 ps
CPU time 0.78 seconds
Started Aug 05 05:48:29 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 200356 kb
Host smart-831be4b9-8984-43ce-87dc-8ea075d794bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875837539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3875837539
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.1621729249
Short name T324
Test name
Test status
Simulation time 70653286 ps
CPU time 0.8 seconds
Started Aug 05 05:48:55 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 200144 kb
Host smart-ed1a9d77-b442-4945-97de-c6f9634f71bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621729249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1621729249
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2006800550
Short name T43
Test name
Test status
Simulation time 1890204386 ps
CPU time 6.97 seconds
Started Aug 05 05:48:22 PM PDT 24
Finished Aug 05 05:48:29 PM PDT 24
Peak memory 216868 kb
Host smart-bd2f5480-67e4-4118-8e3c-fdca3730b468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006800550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2006800550
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1426717497
Short name T376
Test name
Test status
Simulation time 244067725 ps
CPU time 1.15 seconds
Started Aug 05 05:48:26 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 217472 kb
Host smart-ff8a68db-e560-4ca0-b696-8f8f199a9204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426717497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1426717497
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1915492621
Short name T469
Test name
Test status
Simulation time 87913976 ps
CPU time 0.74 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:22 PM PDT 24
Peak memory 200148 kb
Host smart-c4e9b93e-6980-49a0-89f4-8ba7ef7df0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915492621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1915492621
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3719218982
Short name T407
Test name
Test status
Simulation time 2102663544 ps
CPU time 7 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 200544 kb
Host smart-829c2114-ec39-433d-8539-00fabbb28517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719218982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3719218982
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3187827050
Short name T164
Test name
Test status
Simulation time 152539545 ps
CPU time 1.15 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:22 PM PDT 24
Peak memory 200348 kb
Host smart-271e7759-5bf0-4b15-9f6a-6d410e2a3bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187827050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3187827050
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3362702110
Short name T508
Test name
Test status
Simulation time 249190831 ps
CPU time 1.68 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200524 kb
Host smart-ddc3591b-6e6e-4668-8200-10d627efa553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362702110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3362702110
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1669615461
Short name T128
Test name
Test status
Simulation time 2147919109 ps
CPU time 7.21 seconds
Started Aug 05 05:48:40 PM PDT 24
Finished Aug 05 05:48:48 PM PDT 24
Peak memory 200672 kb
Host smart-402da195-5630-4521-8052-f65a42fb541f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669615461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1669615461
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3217603186
Short name T78
Test name
Test status
Simulation time 260538658 ps
CPU time 1.82 seconds
Started Aug 05 05:48:17 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 200280 kb
Host smart-df2fc39e-3e82-4aae-b0e6-fc9a54a35301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217603186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3217603186
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3329260944
Short name T268
Test name
Test status
Simulation time 92416240 ps
CPU time 0.86 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 200324 kb
Host smart-0ded70a7-2d1d-4556-a17d-e97b174cf9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329260944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3329260944
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1834841632
Short name T77
Test name
Test status
Simulation time 73816313 ps
CPU time 0.82 seconds
Started Aug 05 05:48:42 PM PDT 24
Finished Aug 05 05:48:43 PM PDT 24
Peak memory 200144 kb
Host smart-a054a22b-3a0a-4f0d-a60f-be365cbcb849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834841632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1834841632
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.628055746
Short name T456
Test name
Test status
Simulation time 1899217504 ps
CPU time 7.4 seconds
Started Aug 05 05:48:33 PM PDT 24
Finished Aug 05 05:48:41 PM PDT 24
Peak memory 217740 kb
Host smart-677dbbcc-e08d-485d-868d-3433af739787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628055746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.628055746
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1729323359
Short name T234
Test name
Test status
Simulation time 244374935 ps
CPU time 1.07 seconds
Started Aug 05 05:48:45 PM PDT 24
Finished Aug 05 05:48:47 PM PDT 24
Peak memory 217496 kb
Host smart-9fe5c6e0-0855-4175-90d3-61f097fff9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729323359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1729323359
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1329669359
Short name T329
Test name
Test status
Simulation time 180653782 ps
CPU time 0.91 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 200148 kb
Host smart-434d924a-ae9f-431c-a36f-fa7a611e3b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329669359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1329669359
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.634085093
Short name T224
Test name
Test status
Simulation time 1212210652 ps
CPU time 4.74 seconds
Started Aug 05 05:48:33 PM PDT 24
Finished Aug 05 05:48:38 PM PDT 24
Peak memory 200568 kb
Host smart-76f0d919-a1d4-47f5-b59a-85628ad2dfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634085093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.634085093
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1886528855
Short name T175
Test name
Test status
Simulation time 103745117 ps
CPU time 0.95 seconds
Started Aug 05 05:48:32 PM PDT 24
Finished Aug 05 05:48:33 PM PDT 24
Peak memory 200208 kb
Host smart-7d2cbaaa-d6ee-4be8-8831-c88c766e81e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886528855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1886528855
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3849125107
Short name T185
Test name
Test status
Simulation time 191402082 ps
CPU time 1.37 seconds
Started Aug 05 05:48:26 PM PDT 24
Finished Aug 05 05:48:27 PM PDT 24
Peak memory 200540 kb
Host smart-f8e502d8-e054-42ab-8fd0-7266838477d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849125107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3849125107
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1479590071
Short name T486
Test name
Test status
Simulation time 3262300835 ps
CPU time 14.67 seconds
Started Aug 05 05:48:34 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 208804 kb
Host smart-4e4406cc-7db2-4b9b-93f8-b31ed1c142e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479590071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1479590071
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3977070704
Short name T525
Test name
Test status
Simulation time 379250792 ps
CPU time 2.47 seconds
Started Aug 05 05:48:53 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 200280 kb
Host smart-e8432fe6-c0af-44ba-bf41-b2190a5b370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977070704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3977070704
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1497714480
Short name T490
Test name
Test status
Simulation time 137408414 ps
CPU time 1.1 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 200348 kb
Host smart-3ba51fb6-34e6-44fc-8617-5471c6a6ab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497714480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1497714480
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.173891704
Short name T281
Test name
Test status
Simulation time 62955645 ps
CPU time 0.74 seconds
Started Aug 05 05:48:34 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 200172 kb
Host smart-86ad50c2-5702-47a6-8940-b779e02d3b3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173891704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.173891704
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1842045838
Short name T519
Test name
Test status
Simulation time 1895000209 ps
CPU time 7.11 seconds
Started Aug 05 05:48:44 PM PDT 24
Finished Aug 05 05:48:51 PM PDT 24
Peak memory 217532 kb
Host smart-ccc83700-e4ea-4b07-bb7e-9ef7d366f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842045838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1842045838
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1238586508
Short name T340
Test name
Test status
Simulation time 245524977 ps
CPU time 1.06 seconds
Started Aug 05 05:48:52 PM PDT 24
Finished Aug 05 05:48:54 PM PDT 24
Peak memory 217500 kb
Host smart-2430246e-ea4c-419a-b741-6fec95b54835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238586508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1238586508
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3902064629
Short name T220
Test name
Test status
Simulation time 171985936 ps
CPU time 0.87 seconds
Started Aug 05 05:48:49 PM PDT 24
Finished Aug 05 05:48:50 PM PDT 24
Peak memory 200160 kb
Host smart-7c9cd10c-215a-405b-abe3-b70424eb772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902064629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3902064629
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.801692654
Short name T180
Test name
Test status
Simulation time 1376377011 ps
CPU time 5.63 seconds
Started Aug 05 05:48:39 PM PDT 24
Finished Aug 05 05:48:45 PM PDT 24
Peak memory 200568 kb
Host smart-a12a9588-4bbe-47d0-8d67-13c6fbe51246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801692654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.801692654
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4052116273
Short name T226
Test name
Test status
Simulation time 141443441 ps
CPU time 1.09 seconds
Started Aug 05 05:48:41 PM PDT 24
Finished Aug 05 05:48:42 PM PDT 24
Peak memory 200356 kb
Host smart-c6b846b2-324a-415c-912a-c6392c3fe13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052116273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4052116273
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2432720594
Short name T332
Test name
Test status
Simulation time 244331852 ps
CPU time 1.53 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 200492 kb
Host smart-1fe98833-40e9-43c5-90a7-7d5d28938fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432720594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2432720594
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3835497161
Short name T446
Test name
Test status
Simulation time 7011120012 ps
CPU time 26.34 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:49:14 PM PDT 24
Peak memory 209904 kb
Host smart-326644ab-8b87-492a-9eed-d2902afbbc8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835497161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3835497161
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3462865355
Short name T500
Test name
Test status
Simulation time 329331727 ps
CPU time 2.05 seconds
Started Aug 05 05:48:45 PM PDT 24
Finished Aug 05 05:48:48 PM PDT 24
Peak memory 200308 kb
Host smart-196615c0-2265-43cf-8c25-f84c5d506fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462865355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3462865355
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2749952625
Short name T415
Test name
Test status
Simulation time 93773083 ps
CPU time 0.88 seconds
Started Aug 05 05:48:34 PM PDT 24
Finished Aug 05 05:48:35 PM PDT 24
Peak memory 200348 kb
Host smart-27dd669d-9dfb-4ef0-8301-561d768e714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749952625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2749952625
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1568862723
Short name T298
Test name
Test status
Simulation time 61440824 ps
CPU time 0.71 seconds
Started Aug 05 05:48:30 PM PDT 24
Finished Aug 05 05:48:31 PM PDT 24
Peak memory 200152 kb
Host smart-3db0ff02-44dc-4b38-9db9-465250c40784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568862723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1568862723
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.634576680
Short name T291
Test name
Test status
Simulation time 244791293 ps
CPU time 1.06 seconds
Started Aug 05 05:48:52 PM PDT 24
Finished Aug 05 05:48:53 PM PDT 24
Peak memory 217500 kb
Host smart-6484bf0e-5f3d-42af-8091-741e3c0ba01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634576680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.634576680
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.209747347
Short name T499
Test name
Test status
Simulation time 219369034 ps
CPU time 0.92 seconds
Started Aug 05 05:48:28 PM PDT 24
Finished Aug 05 05:48:29 PM PDT 24
Peak memory 200140 kb
Host smart-a3a8f47e-5431-4b2c-9b02-e5416c64e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209747347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.209747347
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.767679457
Short name T339
Test name
Test status
Simulation time 1239495285 ps
CPU time 4.93 seconds
Started Aug 05 05:48:28 PM PDT 24
Finished Aug 05 05:48:33 PM PDT 24
Peak memory 200516 kb
Host smart-f04422ef-b548-4a9e-8854-ed7065351b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767679457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.767679457
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3323766415
Short name T214
Test name
Test status
Simulation time 102497351 ps
CPU time 1.05 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 200340 kb
Host smart-4ee5c65f-6b65-4c0a-93cc-ff41441d1de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323766415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3323766415
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2432287784
Short name T455
Test name
Test status
Simulation time 127988105 ps
CPU time 1.26 seconds
Started Aug 05 05:48:38 PM PDT 24
Finished Aug 05 05:48:40 PM PDT 24
Peak memory 200468 kb
Host smart-e4fa8ef1-9f90-4591-8c19-2ffa87c76195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432287784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2432287784
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.294838220
Short name T143
Test name
Test status
Simulation time 128205578 ps
CPU time 1.05 seconds
Started Aug 05 05:48:41 PM PDT 24
Finished Aug 05 05:48:42 PM PDT 24
Peak memory 200352 kb
Host smart-dfe7e4e7-c9a6-4e26-b223-6c1174415c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294838220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.294838220
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2760633370
Short name T396
Test name
Test status
Simulation time 368777232 ps
CPU time 2.21 seconds
Started Aug 05 05:48:36 PM PDT 24
Finished Aug 05 05:48:38 PM PDT 24
Peak memory 200300 kb
Host smart-00bcd92b-ab8b-42f3-8604-1e3a477c868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760633370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2760633370
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.562825561
Short name T158
Test name
Test status
Simulation time 122492701 ps
CPU time 1.05 seconds
Started Aug 05 05:48:28 PM PDT 24
Finished Aug 05 05:48:29 PM PDT 24
Peak memory 200356 kb
Host smart-653761e0-8cff-41ca-ab62-39379d528b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562825561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.562825561
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3922145885
Short name T414
Test name
Test status
Simulation time 61984710 ps
CPU time 0.75 seconds
Started Aug 05 05:48:32 PM PDT 24
Finished Aug 05 05:48:33 PM PDT 24
Peak memory 200156 kb
Host smart-13b85448-c1b6-4538-97bd-a6b3795db769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922145885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3922145885
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3888898429
Short name T313
Test name
Test status
Simulation time 1219293676 ps
CPU time 5.66 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:48:54 PM PDT 24
Peak memory 216824 kb
Host smart-339310ef-a2d4-402a-ad7c-55b64b4da02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888898429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3888898429
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2841699719
Short name T502
Test name
Test status
Simulation time 245856674 ps
CPU time 1.07 seconds
Started Aug 05 05:49:04 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 217500 kb
Host smart-3136d6f6-e454-4581-97a9-dd7918c60074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841699719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2841699719
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1185814707
Short name T348
Test name
Test status
Simulation time 824418750 ps
CPU time 4.22 seconds
Started Aug 05 05:48:30 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 200544 kb
Host smart-18fb8b73-20f7-4b5c-a72c-45753064835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185814707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1185814707
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.986857901
Short name T433
Test name
Test status
Simulation time 100242500 ps
CPU time 0.98 seconds
Started Aug 05 05:48:28 PM PDT 24
Finished Aug 05 05:48:29 PM PDT 24
Peak memory 200348 kb
Host smart-3b208efb-3952-4785-b70a-bd7530521387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986857901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.986857901
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3648934237
Short name T330
Test name
Test status
Simulation time 110616651 ps
CPU time 1.12 seconds
Started Aug 05 05:48:45 PM PDT 24
Finished Aug 05 05:48:47 PM PDT 24
Peak memory 200532 kb
Host smart-e327acb1-2793-44d8-a9af-f34cd911d68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648934237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3648934237
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2211527037
Short name T100
Test name
Test status
Simulation time 9335807078 ps
CPU time 32.56 seconds
Started Aug 05 05:48:40 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 216952 kb
Host smart-406b3b22-2230-438d-88dc-086348cc2486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211527037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2211527037
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2459386244
Short name T248
Test name
Test status
Simulation time 306450361 ps
CPU time 2.22 seconds
Started Aug 05 05:48:30 PM PDT 24
Finished Aug 05 05:48:32 PM PDT 24
Peak memory 208364 kb
Host smart-5fafab9e-4735-492f-beec-80171f71a754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459386244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2459386244
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3055158015
Short name T435
Test name
Test status
Simulation time 92869316 ps
CPU time 0.82 seconds
Started Aug 05 05:48:32 PM PDT 24
Finished Aug 05 05:48:33 PM PDT 24
Peak memory 200348 kb
Host smart-432d7f31-5cdf-45c9-8b7b-3f54613c33c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055158015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3055158015
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3353173246
Short name T418
Test name
Test status
Simulation time 82243196 ps
CPU time 0.77 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200164 kb
Host smart-53e4353b-c826-453d-adec-53f8d80b4ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353173246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3353173246
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1282842401
Short name T32
Test name
Test status
Simulation time 1226331413 ps
CPU time 5.84 seconds
Started Aug 05 05:48:29 PM PDT 24
Finished Aug 05 05:48:35 PM PDT 24
Peak memory 217760 kb
Host smart-e2021b0c-eaa9-4783-94d8-c4af7c63ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282842401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1282842401
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4040195694
Short name T231
Test name
Test status
Simulation time 243696742 ps
CPU time 1.06 seconds
Started Aug 05 05:48:55 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 217500 kb
Host smart-e4798b8d-4112-4fee-b4d4-4cb9eddc1994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040195694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4040195694
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1051909835
Short name T18
Test name
Test status
Simulation time 127616458 ps
CPU time 0.85 seconds
Started Aug 05 05:48:36 PM PDT 24
Finished Aug 05 05:48:37 PM PDT 24
Peak memory 200256 kb
Host smart-e29d58e7-baf0-46b2-8b6b-b23926268d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051909835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1051909835
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.160459639
Short name T380
Test name
Test status
Simulation time 798754615 ps
CPU time 4.44 seconds
Started Aug 05 05:48:55 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200536 kb
Host smart-4c8ef534-d69b-4d68-ba3a-5ef1dc015d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160459639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.160459639
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.992372282
Short name T333
Test name
Test status
Simulation time 200455932 ps
CPU time 1.48 seconds
Started Aug 05 05:48:42 PM PDT 24
Finished Aug 05 05:48:43 PM PDT 24
Peak memory 200496 kb
Host smart-d07f8cd1-a2c1-489a-838f-a470e1b20895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992372282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.992372282
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2518642140
Short name T359
Test name
Test status
Simulation time 1525630277 ps
CPU time 6.54 seconds
Started Aug 05 05:48:38 PM PDT 24
Finished Aug 05 05:48:44 PM PDT 24
Peak memory 208752 kb
Host smart-2b96e33e-b56c-482f-b23f-3262719e93aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518642140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2518642140
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.282610247
Short name T10
Test name
Test status
Simulation time 366570909 ps
CPU time 2.44 seconds
Started Aug 05 05:48:57 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 200304 kb
Host smart-0659fa8e-f0ec-4907-b0df-7119f377badb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282610247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.282610247
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2867464966
Short name T159
Test name
Test status
Simulation time 108661773 ps
CPU time 0.93 seconds
Started Aug 05 05:48:30 PM PDT 24
Finished Aug 05 05:48:31 PM PDT 24
Peak memory 200340 kb
Host smart-0fa0d04a-5362-4cbd-969f-6d4278ef9f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867464966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2867464966
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1363094590
Short name T461
Test name
Test status
Simulation time 76359386 ps
CPU time 0.76 seconds
Started Aug 05 05:48:37 PM PDT 24
Finished Aug 05 05:48:38 PM PDT 24
Peak memory 199604 kb
Host smart-cfc9d078-ffa2-4188-aca6-b73afc1b0ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363094590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1363094590
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1456827914
Short name T387
Test name
Test status
Simulation time 2362222307 ps
CPU time 9.06 seconds
Started Aug 05 05:48:37 PM PDT 24
Finished Aug 05 05:48:46 PM PDT 24
Peak memory 221772 kb
Host smart-a884bfbc-62d7-46fc-a230-310235613d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456827914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1456827914
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3192806348
Short name T362
Test name
Test status
Simulation time 245375501 ps
CPU time 1.07 seconds
Started Aug 05 05:48:44 PM PDT 24
Finished Aug 05 05:48:45 PM PDT 24
Peak memory 217492 kb
Host smart-de7c8d05-a639-4b7e-9cef-57b87a32e83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192806348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3192806348
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1817392916
Short name T497
Test name
Test status
Simulation time 98328212 ps
CPU time 0.76 seconds
Started Aug 05 05:48:30 PM PDT 24
Finished Aug 05 05:48:36 PM PDT 24
Peak memory 200136 kb
Host smart-4a6318ce-bb18-4b38-9761-85865f2ac9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817392916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1817392916
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.4057216855
Short name T354
Test name
Test status
Simulation time 1279831373 ps
CPU time 5.39 seconds
Started Aug 05 05:48:31 PM PDT 24
Finished Aug 05 05:48:37 PM PDT 24
Peak memory 200556 kb
Host smart-5b4ebef5-7967-4b55-be0c-31b40fdc3e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057216855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4057216855
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1336195262
Short name T468
Test name
Test status
Simulation time 175439533 ps
CPU time 1.24 seconds
Started Aug 05 05:48:32 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 200348 kb
Host smart-33267f18-eb07-4acb-aa3f-183d6a4f02f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336195262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1336195262
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2034998094
Short name T202
Test name
Test status
Simulation time 120617690 ps
CPU time 1.19 seconds
Started Aug 05 05:48:29 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 200380 kb
Host smart-841437fb-1e0d-460a-a2f4-bd23694f8f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034998094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2034998094
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1760803306
Short name T495
Test name
Test status
Simulation time 1749714470 ps
CPU time 8.4 seconds
Started Aug 05 05:48:37 PM PDT 24
Finished Aug 05 05:48:45 PM PDT 24
Peak memory 208220 kb
Host smart-095840d9-4ef6-46f6-bd41-88e653aace5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760803306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1760803306
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2083329351
Short name T131
Test name
Test status
Simulation time 332573949 ps
CPU time 2.07 seconds
Started Aug 05 05:48:35 PM PDT 24
Finished Aug 05 05:48:37 PM PDT 24
Peak memory 200224 kb
Host smart-b3b236a7-1923-40d4-b6b6-d80722faee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083329351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2083329351
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1004754664
Short name T541
Test name
Test status
Simulation time 168331104 ps
CPU time 1.29 seconds
Started Aug 05 05:48:29 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 200380 kb
Host smart-f54a8967-3a34-458b-bc2a-06c138d2e318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004754664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1004754664
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2635010010
Short name T161
Test name
Test status
Simulation time 76108295 ps
CPU time 0.78 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 200156 kb
Host smart-7393efdc-83e7-4b21-8441-2a899973ac88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635010010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2635010010
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.41769346
Short name T41
Test name
Test status
Simulation time 1221633349 ps
CPU time 5.39 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:48:20 PM PDT 24
Peak memory 217100 kb
Host smart-ecafae8c-00a8-4894-aeed-9cb92b1df07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41769346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.41769346
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2474416609
Short name T253
Test name
Test status
Simulation time 244496890 ps
CPU time 1.16 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:08 PM PDT 24
Peak memory 217432 kb
Host smart-c62863ae-e36f-45dc-ab6b-80c433749925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474416609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2474416609
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2300448926
Short name T457
Test name
Test status
Simulation time 146909808 ps
CPU time 0.83 seconds
Started Aug 05 05:48:29 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 200156 kb
Host smart-4097dc0f-8c22-4392-ba55-43f8431c7858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300448926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2300448926
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3153361962
Short name T95
Test name
Test status
Simulation time 1289739496 ps
CPU time 4.79 seconds
Started Aug 05 05:48:09 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 200612 kb
Host smart-f04713b3-1fcb-44d6-9da0-5ab5650c90e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153361962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3153361962
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2460445880
Short name T72
Test name
Test status
Simulation time 17231501987 ps
CPU time 23.95 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:43 PM PDT 24
Peak memory 217256 kb
Host smart-820976d7-73bb-4e57-a7dc-717f9be4630a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460445880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2460445880
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3396605467
Short name T183
Test name
Test status
Simulation time 98442827 ps
CPU time 0.97 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:48:07 PM PDT 24
Peak memory 200352 kb
Host smart-7e6c17d2-a627-4718-8db2-2892f4248a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396605467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3396605467
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.327170372
Short name T327
Test name
Test status
Simulation time 195991582 ps
CPU time 1.38 seconds
Started Aug 05 05:48:15 PM PDT 24
Finished Aug 05 05:48:16 PM PDT 24
Peak memory 200492 kb
Host smart-f7d99ff8-47f0-44a5-8207-57027a2d455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327170372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.327170372
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2918385013
Short name T419
Test name
Test status
Simulation time 1874340747 ps
CPU time 7.33 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200560 kb
Host smart-7f75eec0-2468-413f-bae5-58974ceec7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918385013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2918385013
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1892837956
Short name T299
Test name
Test status
Simulation time 372157482 ps
CPU time 2.35 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 208464 kb
Host smart-4f2328c1-e687-43bd-9eca-65f28e57d557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892837956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1892837956
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4123297920
Short name T365
Test name
Test status
Simulation time 295152684 ps
CPU time 1.58 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 200380 kb
Host smart-4495b013-49f1-4455-a621-1bf62caf3134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123297920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4123297920
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2341709240
Short name T307
Test name
Test status
Simulation time 64899670 ps
CPU time 0.75 seconds
Started Aug 05 05:48:39 PM PDT 24
Finished Aug 05 05:48:39 PM PDT 24
Peak memory 200172 kb
Host smart-c2ca9f98-20f9-46f1-bb1a-a4501e30b5a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341709240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2341709240
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2981566806
Short name T464
Test name
Test status
Simulation time 1225544458 ps
CPU time 5.73 seconds
Started Aug 05 05:48:37 PM PDT 24
Finished Aug 05 05:48:42 PM PDT 24
Peak memory 220980 kb
Host smart-3ae21b86-5c5b-4298-b3cd-601ca9f8a50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981566806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2981566806
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2736378874
Short name T375
Test name
Test status
Simulation time 244905466 ps
CPU time 1.17 seconds
Started Aug 05 05:48:40 PM PDT 24
Finished Aug 05 05:48:41 PM PDT 24
Peak memory 217524 kb
Host smart-bc5e7b42-988f-484f-8d1d-5c887e1b459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736378874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2736378874
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2614727194
Short name T208
Test name
Test status
Simulation time 189620843 ps
CPU time 0.91 seconds
Started Aug 05 05:48:37 PM PDT 24
Finished Aug 05 05:48:38 PM PDT 24
Peak memory 200140 kb
Host smart-45baade0-a96c-4bf4-a05f-d58b6139ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614727194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2614727194
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2412427873
Short name T91
Test name
Test status
Simulation time 1345413981 ps
CPU time 5.12 seconds
Started Aug 05 05:48:33 PM PDT 24
Finished Aug 05 05:48:38 PM PDT 24
Peak memory 200564 kb
Host smart-809bd777-0808-49cf-a2d7-6e17756aa0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412427873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2412427873
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2786706130
Short name T258
Test name
Test status
Simulation time 150527034 ps
CPU time 1.15 seconds
Started Aug 05 05:48:49 PM PDT 24
Finished Aug 05 05:48:50 PM PDT 24
Peak memory 200324 kb
Host smart-d6a5abc6-421a-4021-9d56-8dffb7d1fff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786706130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2786706130
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3185250728
Short name T155
Test name
Test status
Simulation time 122318709 ps
CPU time 1.16 seconds
Started Aug 05 05:48:35 PM PDT 24
Finished Aug 05 05:48:36 PM PDT 24
Peak memory 200376 kb
Host smart-98a70c68-1c21-4606-a8f4-2407089c1713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185250728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3185250728
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1184022060
Short name T129
Test name
Test status
Simulation time 3669815082 ps
CPU time 13.44 seconds
Started Aug 05 05:48:49 PM PDT 24
Finished Aug 05 05:49:02 PM PDT 24
Peak memory 200624 kb
Host smart-95efc56d-05ef-4868-9b29-fb7959e81199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184022060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1184022060
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1218639584
Short name T325
Test name
Test status
Simulation time 134991014 ps
CPU time 1.75 seconds
Started Aug 05 05:48:44 PM PDT 24
Finished Aug 05 05:48:46 PM PDT 24
Peak memory 200296 kb
Host smart-c4437304-6ec1-425f-90be-6143f222d8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218639584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1218639584
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1473803269
Short name T451
Test name
Test status
Simulation time 229647642 ps
CPU time 1.44 seconds
Started Aug 05 05:48:35 PM PDT 24
Finished Aug 05 05:48:36 PM PDT 24
Peak memory 200344 kb
Host smart-2d3929bf-2b40-45c8-83ce-4cf6927162c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473803269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1473803269
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.184447582
Short name T308
Test name
Test status
Simulation time 72403568 ps
CPU time 0.75 seconds
Started Aug 05 05:48:39 PM PDT 24
Finished Aug 05 05:48:40 PM PDT 24
Peak memory 200156 kb
Host smart-4866b763-10a1-4185-81dc-ef603d1c1a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184447582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.184447582
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3346434002
Short name T31
Test name
Test status
Simulation time 1218674233 ps
CPU time 6.09 seconds
Started Aug 05 05:48:49 PM PDT 24
Finished Aug 05 05:48:55 PM PDT 24
Peak memory 217372 kb
Host smart-1435decb-e522-46ce-ad33-3b66af9a2fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346434002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3346434002
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2983241985
Short name T400
Test name
Test status
Simulation time 244078656 ps
CPU time 1.08 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 217496 kb
Host smart-63b4506a-fb8c-40a7-82ec-7f11549b5ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983241985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2983241985
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3084953621
Short name T205
Test name
Test status
Simulation time 186205193 ps
CPU time 0.85 seconds
Started Aug 05 05:48:44 PM PDT 24
Finished Aug 05 05:48:45 PM PDT 24
Peak memory 200136 kb
Host smart-007f88e1-ff08-4ef3-9dcc-4ab634ef994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084953621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3084953621
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2870550885
Short name T93
Test name
Test status
Simulation time 2154887144 ps
CPU time 8 seconds
Started Aug 05 05:48:57 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 200620 kb
Host smart-4ea2c4ae-dfc8-4117-ac2d-292a27714304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870550885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2870550885
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1678732801
Short name T230
Test name
Test status
Simulation time 143773969 ps
CPU time 1.11 seconds
Started Aug 05 05:48:37 PM PDT 24
Finished Aug 05 05:48:39 PM PDT 24
Peak memory 200344 kb
Host smart-414b6bf7-d68f-4c03-8cab-6c4c96df24ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678732801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1678732801
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3539941200
Short name T165
Test name
Test status
Simulation time 187991900 ps
CPU time 1.28 seconds
Started Aug 05 05:48:35 PM PDT 24
Finished Aug 05 05:48:36 PM PDT 24
Peak memory 200476 kb
Host smart-84b17889-e392-46fe-bea3-75963bda7e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539941200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3539941200
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1503958929
Short name T235
Test name
Test status
Simulation time 4237642143 ps
CPU time 18.32 seconds
Started Aug 05 05:48:39 PM PDT 24
Finished Aug 05 05:48:57 PM PDT 24
Peak memory 208808 kb
Host smart-0aab4129-ad59-4b19-9d53-873ed1d67443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503958929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1503958929
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.870913861
Short name T275
Test name
Test status
Simulation time 134526769 ps
CPU time 1.61 seconds
Started Aug 05 05:48:53 PM PDT 24
Finished Aug 05 05:48:55 PM PDT 24
Peak memory 208496 kb
Host smart-56207e4e-1d9b-4f42-9a3b-1cbac41869fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870913861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.870913861
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3842210703
Short name T478
Test name
Test status
Simulation time 99156291 ps
CPU time 0.88 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 200300 kb
Host smart-4b52a964-e526-4df9-84bb-804c5b48ce18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842210703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3842210703
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2867611736
Short name T301
Test name
Test status
Simulation time 73873908 ps
CPU time 0.77 seconds
Started Aug 05 05:48:50 PM PDT 24
Finished Aug 05 05:48:51 PM PDT 24
Peak memory 200160 kb
Host smart-d6d66669-c042-44c7-b687-a72ba65a7bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867611736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2867611736
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.1893723849
Short name T30
Test name
Test status
Simulation time 1235836273 ps
CPU time 5.43 seconds
Started Aug 05 05:48:50 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 221352 kb
Host smart-ff27eb28-ae67-4b9e-b61b-9ec62e08ea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893723849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1893723849
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1635293581
Short name T206
Test name
Test status
Simulation time 244821049 ps
CPU time 1.05 seconds
Started Aug 05 05:48:47 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 217456 kb
Host smart-1c36b680-36a0-4b85-8040-49b021bd2f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635293581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1635293581
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2306382106
Short name T358
Test name
Test status
Simulation time 91943647 ps
CPU time 0.78 seconds
Started Aug 05 05:48:45 PM PDT 24
Finished Aug 05 05:48:46 PM PDT 24
Peak memory 200140 kb
Host smart-568b6481-3d0c-4eac-8927-c685edd00555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306382106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2306382106
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1880383475
Short name T97
Test name
Test status
Simulation time 1162702625 ps
CPU time 5.1 seconds
Started Aug 05 05:48:38 PM PDT 24
Finished Aug 05 05:48:44 PM PDT 24
Peak memory 200540 kb
Host smart-0f5def83-4cc5-48e8-a585-44ca2fe6ca86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880383475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1880383475
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.959237653
Short name T14
Test name
Test status
Simulation time 101538161 ps
CPU time 1 seconds
Started Aug 05 05:48:49 PM PDT 24
Finished Aug 05 05:48:50 PM PDT 24
Peak memory 200340 kb
Host smart-ab319344-fd85-4b25-b3dc-10765ce624fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959237653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.959237653
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3676746145
Short name T241
Test name
Test status
Simulation time 119406839 ps
CPU time 1.22 seconds
Started Aug 05 05:48:37 PM PDT 24
Finished Aug 05 05:48:38 PM PDT 24
Peak memory 200476 kb
Host smart-f7ce60f4-09a7-4fe6-8d89-518fe8c729db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676746145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3676746145
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1761263430
Short name T515
Test name
Test status
Simulation time 2749835636 ps
CPU time 10.91 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 200544 kb
Host smart-3a816cd9-c146-4bea-9188-14e6a996e7c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761263430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1761263430
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.819477531
Short name T244
Test name
Test status
Simulation time 376318833 ps
CPU time 2.03 seconds
Started Aug 05 05:48:52 PM PDT 24
Finished Aug 05 05:48:54 PM PDT 24
Peak memory 200304 kb
Host smart-7166ec2f-8382-4d65-8196-ffdb4d986f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819477531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.819477531
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.248412122
Short name T506
Test name
Test status
Simulation time 137858326 ps
CPU time 1.15 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200352 kb
Host smart-124fdfe4-58fe-47c0-a235-5866c6738067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248412122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.248412122
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3702701113
Short name T213
Test name
Test status
Simulation time 54537582 ps
CPU time 0.71 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:57 PM PDT 24
Peak memory 200168 kb
Host smart-4a84bb7a-a90d-4296-9090-626302f71162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702701113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3702701113
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.2214322335
Short name T420
Test name
Test status
Simulation time 1227822796 ps
CPU time 5.26 seconds
Started Aug 05 05:48:40 PM PDT 24
Finished Aug 05 05:48:46 PM PDT 24
Peak memory 217376 kb
Host smart-14b7d14e-b555-4fd5-9ead-c63e8259cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214322335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.2214322335
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2308777186
Short name T386
Test name
Test status
Simulation time 244361232 ps
CPU time 1.13 seconds
Started Aug 05 05:48:50 PM PDT 24
Finished Aug 05 05:48:52 PM PDT 24
Peak memory 217564 kb
Host smart-5fbd21bb-ecf5-4ebd-beaa-879cc4a8383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308777186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2308777186
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.590110515
Short name T321
Test name
Test status
Simulation time 169815362 ps
CPU time 0.88 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200156 kb
Host smart-086e0d14-39aa-4754-b1b1-fc7b9bc98e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590110515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.590110515
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2308712143
Short name T346
Test name
Test status
Simulation time 910990130 ps
CPU time 4.52 seconds
Started Aug 05 05:48:45 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 200556 kb
Host smart-c7ff312e-e9fa-45a7-9d30-0ffcc21b7321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308712143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2308712143
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1059488947
Short name T436
Test name
Test status
Simulation time 96064105 ps
CPU time 0.95 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200356 kb
Host smart-9a731700-f941-4536-a61e-50d043f4a8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059488947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1059488947
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2700981270
Short name T536
Test name
Test status
Simulation time 220624254 ps
CPU time 1.43 seconds
Started Aug 05 05:48:51 PM PDT 24
Finished Aug 05 05:48:52 PM PDT 24
Peak memory 200452 kb
Host smart-6a776cfc-1cae-42b1-adb3-94967aadfdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700981270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2700981270
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3429044315
Short name T460
Test name
Test status
Simulation time 6391369842 ps
CPU time 22.58 seconds
Started Aug 05 05:49:04 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 200620 kb
Host smart-87bc8d35-c38c-421c-bfcc-362f0f9b637b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429044315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3429044315
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.988860717
Short name T237
Test name
Test status
Simulation time 152583052 ps
CPU time 1.8 seconds
Started Aug 05 05:48:47 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 200292 kb
Host smart-5e32a29f-c492-41f9-bad0-4deb39480d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988860717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.988860717
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2541915046
Short name T309
Test name
Test status
Simulation time 64568007 ps
CPU time 0.8 seconds
Started Aug 05 05:48:51 PM PDT 24
Finished Aug 05 05:48:52 PM PDT 24
Peak memory 200312 kb
Host smart-498d7706-fba0-4335-add6-9d0528c7a66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541915046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2541915046
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1564640571
Short name T395
Test name
Test status
Simulation time 68372620 ps
CPU time 0.77 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 200248 kb
Host smart-406ef667-bbb1-46c6-83a5-4e21e4f52c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564640571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1564640571
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2104619497
Short name T467
Test name
Test status
Simulation time 1227371537 ps
CPU time 5.81 seconds
Started Aug 05 05:48:47 PM PDT 24
Finished Aug 05 05:48:53 PM PDT 24
Peak memory 217744 kb
Host smart-62d3bd57-85ab-4e59-9e06-b7920542c83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104619497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2104619497
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.185022909
Short name T184
Test name
Test status
Simulation time 243407371 ps
CPU time 1.12 seconds
Started Aug 05 05:48:40 PM PDT 24
Finished Aug 05 05:48:41 PM PDT 24
Peak memory 217452 kb
Host smart-bc16cd20-f235-4763-8bc3-bc18a0a2258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185022909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.185022909
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2469571281
Short name T186
Test name
Test status
Simulation time 156038185 ps
CPU time 0.85 seconds
Started Aug 05 05:48:54 PM PDT 24
Finished Aug 05 05:48:55 PM PDT 24
Peak memory 200120 kb
Host smart-827f0c5e-08b3-458d-9406-dada3c44623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469571281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2469571281
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3200271937
Short name T264
Test name
Test status
Simulation time 655415101 ps
CPU time 3.74 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:49:02 PM PDT 24
Peak memory 200508 kb
Host smart-6347c973-a4ee-46a5-a540-32f0286aaea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200271937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3200271937
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2845055813
Short name T510
Test name
Test status
Simulation time 175899457 ps
CPU time 1.22 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 200324 kb
Host smart-e9af50cb-47e8-4f52-bfd8-d45f903c0c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845055813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2845055813
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4095565543
Short name T279
Test name
Test status
Simulation time 193207997 ps
CPU time 1.34 seconds
Started Aug 05 05:48:47 PM PDT 24
Finished Aug 05 05:48:48 PM PDT 24
Peak memory 200532 kb
Host smart-f716ecaa-99b3-4871-adeb-5a8e1bbf4ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095565543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4095565543
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2029473204
Short name T247
Test name
Test status
Simulation time 5999170985 ps
CPU time 22.72 seconds
Started Aug 05 05:48:38 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200656 kb
Host smart-899e86cc-e4bc-4313-83e6-461ae2faa96b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029473204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2029473204
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1124217152
Short name T344
Test name
Test status
Simulation time 111942650 ps
CPU time 1.41 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:58 PM PDT 24
Peak memory 200308 kb
Host smart-0c2db241-7f77-4843-a8e4-95b9d5851729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124217152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1124217152
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.417125851
Short name T531
Test name
Test status
Simulation time 161272596 ps
CPU time 1.44 seconds
Started Aug 05 05:48:49 PM PDT 24
Finished Aug 05 05:48:50 PM PDT 24
Peak memory 200512 kb
Host smart-124f170c-e0a6-4b34-b4bc-9aa28c39ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417125851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.417125851
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1243865492
Short name T521
Test name
Test status
Simulation time 77315074 ps
CPU time 0.79 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 200128 kb
Host smart-3855a936-2fce-4fa9-aff5-98e73e934ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243865492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1243865492
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3801130325
Short name T484
Test name
Test status
Simulation time 2191586734 ps
CPU time 7.4 seconds
Started Aug 05 05:48:53 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 221752 kb
Host smart-b2e17928-8d7f-4db1-9f6c-50ce84ebfb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801130325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3801130325
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2572225373
Short name T262
Test name
Test status
Simulation time 244245234 ps
CPU time 1.1 seconds
Started Aug 05 05:48:44 PM PDT 24
Finished Aug 05 05:48:45 PM PDT 24
Peak memory 217524 kb
Host smart-d3aa318e-78a1-48f2-8ac7-967b69fc01fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572225373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2572225373
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3106815915
Short name T20
Test name
Test status
Simulation time 98274588 ps
CPU time 0.85 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 200156 kb
Host smart-df55b8ef-7a26-4d39-88cd-1da1f3667254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106815915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3106815915
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3411588221
Short name T252
Test name
Test status
Simulation time 1128955631 ps
CPU time 4.81 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 200524 kb
Host smart-1f4d5238-8fed-4af9-aa33-6e34c6183dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411588221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3411588221
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2764025989
Short name T384
Test name
Test status
Simulation time 172605715 ps
CPU time 1.13 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200356 kb
Host smart-d4a00381-7b15-4e34-b3f5-4da593d9f7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764025989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2764025989
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1977827535
Short name T336
Test name
Test status
Simulation time 255112991 ps
CPU time 1.44 seconds
Started Aug 05 05:48:44 PM PDT 24
Finished Aug 05 05:48:45 PM PDT 24
Peak memory 200484 kb
Host smart-d85ea06d-bc9d-4017-ae43-138915bade76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977827535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1977827535
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2827913318
Short name T106
Test name
Test status
Simulation time 2987342616 ps
CPU time 12.86 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 208860 kb
Host smart-12cfe15e-4dbe-4c74-982c-81892df723e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827913318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2827913318
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.356984698
Short name T318
Test name
Test status
Simulation time 141416523 ps
CPU time 1.71 seconds
Started Aug 05 05:48:55 PM PDT 24
Finished Aug 05 05:48:57 PM PDT 24
Peak memory 200300 kb
Host smart-cf72c2f7-7f50-4517-a44c-9751ec2ca8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356984698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.356984698
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.741075193
Short name T296
Test name
Test status
Simulation time 190943797 ps
CPU time 1.2 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200352 kb
Host smart-34a80420-6482-4091-bf52-7fb135983db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741075193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.741075193
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4173503882
Short name T372
Test name
Test status
Simulation time 73321111 ps
CPU time 0.85 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200160 kb
Host smart-a3548072-9720-4592-bd48-7731992a53b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173503882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4173503882
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1704856530
Short name T49
Test name
Test status
Simulation time 2347048694 ps
CPU time 8.42 seconds
Started Aug 05 05:48:47 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 217872 kb
Host smart-9666ff06-7484-4181-8e89-1c952ec6bad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704856530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1704856530
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2535378721
Short name T37
Test name
Test status
Simulation time 244611194 ps
CPU time 1.1 seconds
Started Aug 05 05:48:55 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 217532 kb
Host smart-3604e269-1312-466c-bdd0-6b178d20104a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535378721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2535378721
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3475622708
Short name T13
Test name
Test status
Simulation time 146403952 ps
CPU time 0.85 seconds
Started Aug 05 05:48:48 PM PDT 24
Finished Aug 05 05:48:49 PM PDT 24
Peak memory 200028 kb
Host smart-ac2b23ef-448b-4de6-bad1-6a2bd32ecf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475622708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3475622708
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.662701973
Short name T92
Test name
Test status
Simulation time 1280793226 ps
CPU time 4.84 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 200572 kb
Host smart-d703dc28-e2b3-491c-9ce8-435d5580c7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662701973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.662701973
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4059980735
Short name T534
Test name
Test status
Simulation time 186072431 ps
CPU time 1.19 seconds
Started Aug 05 05:49:01 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200356 kb
Host smart-5dca644f-e5fb-40c4-8026-fe1238998921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059980735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4059980735
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1989989394
Short name T441
Test name
Test status
Simulation time 111232624 ps
CPU time 1.2 seconds
Started Aug 05 05:48:45 PM PDT 24
Finished Aug 05 05:48:46 PM PDT 24
Peak memory 200456 kb
Host smart-8edaf396-10ce-4006-bebe-d26a5b755890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989989394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1989989394
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3021915558
Short name T540
Test name
Test status
Simulation time 123949412 ps
CPU time 1.6 seconds
Started Aug 05 05:48:57 PM PDT 24
Finished Aug 05 05:48:58 PM PDT 24
Peak memory 200308 kb
Host smart-40ee8ea8-b7c6-4530-a140-3d916ea18af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021915558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3021915558
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3098241708
Short name T424
Test name
Test status
Simulation time 279620157 ps
CPU time 1.7 seconds
Started Aug 05 05:48:49 PM PDT 24
Finished Aug 05 05:48:50 PM PDT 24
Peak memory 200460 kb
Host smart-2d9acb2f-37e5-4f51-b4a7-052761ce7a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098241708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3098241708
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2261064400
Short name T243
Test name
Test status
Simulation time 72606941 ps
CPU time 0.83 seconds
Started Aug 05 05:48:52 PM PDT 24
Finished Aug 05 05:48:53 PM PDT 24
Peak memory 200160 kb
Host smart-94556f1a-d4ae-48cc-a860-15b558d53c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261064400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2261064400
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.990074377
Short name T401
Test name
Test status
Simulation time 1222115909 ps
CPU time 5.71 seconds
Started Aug 05 05:48:47 PM PDT 24
Finished Aug 05 05:48:53 PM PDT 24
Peak memory 216816 kb
Host smart-a739c4b2-c270-454e-80a2-83e3b8739ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990074377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.990074377
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3913133295
Short name T2
Test name
Test status
Simulation time 244777296 ps
CPU time 1.08 seconds
Started Aug 05 05:48:49 PM PDT 24
Finished Aug 05 05:48:50 PM PDT 24
Peak memory 217532 kb
Host smart-b56ff6a5-80e4-4d3e-baad-6e9e6536062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913133295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3913133295
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3581443254
Short name T479
Test name
Test status
Simulation time 155607972 ps
CPU time 0.93 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200160 kb
Host smart-a1a9b36a-26e5-4ec8-8dbf-848df1ef56df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581443254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3581443254
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1289556941
Short name T360
Test name
Test status
Simulation time 1179700285 ps
CPU time 5.59 seconds
Started Aug 05 05:48:50 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 200548 kb
Host smart-2d610071-7f99-488f-a09c-a302d4c0629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289556941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1289556941
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3582325036
Short name T342
Test name
Test status
Simulation time 108118850 ps
CPU time 0.99 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200356 kb
Host smart-e3892725-ce68-489a-a27e-f9088a991340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582325036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3582325036
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.4083061338
Short name T166
Test name
Test status
Simulation time 120857548 ps
CPU time 1.32 seconds
Started Aug 05 05:48:45 PM PDT 24
Finished Aug 05 05:48:46 PM PDT 24
Peak memory 200488 kb
Host smart-9c10aa47-0708-4600-8d92-36fd7a88d36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083061338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.4083061338
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.542863790
Short name T535
Test name
Test status
Simulation time 4754109654 ps
CPU time 17.99 seconds
Started Aug 05 05:48:51 PM PDT 24
Finished Aug 05 05:49:09 PM PDT 24
Peak memory 200636 kb
Host smart-5aacede5-77e5-4408-8000-9962f799229a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542863790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.542863790
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2711431932
Short name T46
Test name
Test status
Simulation time 453785348 ps
CPU time 2.47 seconds
Started Aug 05 05:48:51 PM PDT 24
Finished Aug 05 05:48:54 PM PDT 24
Peak memory 200292 kb
Host smart-4cbe4b37-bf6b-4fc8-bd1c-36bd179c1937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711431932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2711431932
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2868415335
Short name T315
Test name
Test status
Simulation time 116282743 ps
CPU time 1.05 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 200352 kb
Host smart-114dace2-c1c2-4070-acac-781177647dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868415335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2868415335
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.487401353
Short name T421
Test name
Test status
Simulation time 102290085 ps
CPU time 0.91 seconds
Started Aug 05 05:48:53 PM PDT 24
Finished Aug 05 05:48:54 PM PDT 24
Peak memory 200160 kb
Host smart-6dbfb96c-4dfe-4253-9ea9-7ad128897e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487401353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.487401353
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2327868225
Short name T397
Test name
Test status
Simulation time 1229376060 ps
CPU time 5.83 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 217476 kb
Host smart-64da7d09-2cd7-42b4-9ec7-f926fd2b8141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327868225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2327868225
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1057649593
Short name T238
Test name
Test status
Simulation time 244370567 ps
CPU time 1.12 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 217488 kb
Host smart-ced5448c-2dc6-4801-a5b8-5de94d995a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057649593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1057649593
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2696139219
Short name T276
Test name
Test status
Simulation time 123773024 ps
CPU time 0.78 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 200156 kb
Host smart-62867a74-5029-4a00-8d57-573b08d3997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696139219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2696139219
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2905057830
Short name T361
Test name
Test status
Simulation time 798913286 ps
CPU time 3.96 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200576 kb
Host smart-49a6d08f-5128-468e-89ff-ff3606886b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905057830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2905057830
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3820509388
Short name T378
Test name
Test status
Simulation time 153242157 ps
CPU time 1.09 seconds
Started Aug 05 05:48:57 PM PDT 24
Finished Aug 05 05:48:58 PM PDT 24
Peak memory 200356 kb
Host smart-bf922754-1b27-4a79-a89f-2da037d9c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820509388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3820509388
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3902528536
Short name T173
Test name
Test status
Simulation time 123241076 ps
CPU time 1.18 seconds
Started Aug 05 05:49:01 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200500 kb
Host smart-4eb6f385-1071-4a65-b7b1-64538e9a0778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902528536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3902528536
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2663029673
Short name T283
Test name
Test status
Simulation time 11664322906 ps
CPU time 40.04 seconds
Started Aug 05 05:48:54 PM PDT 24
Finished Aug 05 05:49:34 PM PDT 24
Peak memory 200648 kb
Host smart-93ec5669-c027-4fbd-88b8-e3760dc12c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663029673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2663029673
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.471202015
Short name T53
Test name
Test status
Simulation time 363528980 ps
CPU time 2.38 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200300 kb
Host smart-b4470842-e87d-4e16-8bf1-d82b1be29a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471202015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.471202015
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1747769151
Short name T403
Test name
Test status
Simulation time 197909165 ps
CPU time 1.2 seconds
Started Aug 05 05:48:50 PM PDT 24
Finished Aug 05 05:48:51 PM PDT 24
Peak memory 200352 kb
Host smart-98359f2c-f397-43e9-a891-fc9c9f89d741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747769151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1747769151
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.4016080384
Short name T221
Test name
Test status
Simulation time 64275694 ps
CPU time 0.76 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200164 kb
Host smart-5c564426-cdcb-45cd-8992-443cababfdfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016080384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4016080384
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1780555437
Short name T480
Test name
Test status
Simulation time 1223299478 ps
CPU time 5.99 seconds
Started Aug 05 05:48:52 PM PDT 24
Finished Aug 05 05:48:58 PM PDT 24
Peak memory 217588 kb
Host smart-41d90145-f67d-4243-8509-fab590a8088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780555437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1780555437
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.719926188
Short name T543
Test name
Test status
Simulation time 245655391 ps
CPU time 1.06 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 217524 kb
Host smart-9fcd5afe-9079-4621-aa99-ef12e1e72941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719926188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.719926188
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.4232158001
Short name T188
Test name
Test status
Simulation time 87956325 ps
CPU time 0.76 seconds
Started Aug 05 05:48:55 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 200184 kb
Host smart-96cce316-14f3-445c-9acf-3d5b83fe4cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232158001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.4232158001
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2834778403
Short name T102
Test name
Test status
Simulation time 908836630 ps
CPU time 4.8 seconds
Started Aug 05 05:48:57 PM PDT 24
Finished Aug 05 05:49:02 PM PDT 24
Peak memory 200508 kb
Host smart-7f77e8f9-66fa-4067-a13e-1b8ee555925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834778403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2834778403
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3415721938
Short name T351
Test name
Test status
Simulation time 181074536 ps
CPU time 1.3 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 200312 kb
Host smart-b0605941-ff4c-49e3-9d3f-1765eade04ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415721938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3415721938
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3449761666
Short name T152
Test name
Test status
Simulation time 124525106 ps
CPU time 1.21 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:58 PM PDT 24
Peak memory 200360 kb
Host smart-eea2ff99-fffc-441c-aa42-b7ca52f2e7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449761666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3449761666
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1675065012
Short name T317
Test name
Test status
Simulation time 3589150037 ps
CPU time 13.13 seconds
Started Aug 05 05:49:03 PM PDT 24
Finished Aug 05 05:49:16 PM PDT 24
Peak memory 200604 kb
Host smart-3349fd79-cfa8-4c6e-92d9-9744ec65faec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675065012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1675065012
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.415446566
Short name T409
Test name
Test status
Simulation time 495360705 ps
CPU time 2.65 seconds
Started Aug 05 05:48:53 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 200324 kb
Host smart-004e540e-8452-4c63-ab4c-ad45633ae631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415446566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.415446566
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3752511297
Short name T233
Test name
Test status
Simulation time 232958537 ps
CPU time 1.26 seconds
Started Aug 05 05:49:05 PM PDT 24
Finished Aug 05 05:49:06 PM PDT 24
Peak memory 200324 kb
Host smart-3d8454ed-8bae-45ef-bc11-24c8439a3ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752511297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3752511297
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.4206502949
Short name T319
Test name
Test status
Simulation time 69899626 ps
CPU time 0.79 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 200168 kb
Host smart-104ad750-a546-4936-ac99-d5122fe91819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206502949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.4206502949
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1467349939
Short name T135
Test name
Test status
Simulation time 1899420189 ps
CPU time 7.72 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:30 PM PDT 24
Peak memory 221668 kb
Host smart-5a7df61f-1199-4fab-81ae-5dc733989a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467349939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1467349939
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1289207400
Short name T334
Test name
Test status
Simulation time 244904919 ps
CPU time 1.07 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 217468 kb
Host smart-e6a9e203-4a4f-4f36-b755-fefd789339c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289207400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1289207400
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3614857170
Short name T462
Test name
Test status
Simulation time 201375222 ps
CPU time 0.89 seconds
Started Aug 05 05:48:05 PM PDT 24
Finished Aug 05 05:48:05 PM PDT 24
Peak memory 200148 kb
Host smart-43a86dda-76bd-4652-bd8a-18f8eda026ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614857170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3614857170
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2724472725
Short name T505
Test name
Test status
Simulation time 1520627079 ps
CPU time 6.42 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:48:20 PM PDT 24
Peak memory 200568 kb
Host smart-ebfa453e-31ab-4fc4-8f50-2cb8217659bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724472725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2724472725
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.4290664911
Short name T65
Test name
Test status
Simulation time 16522077754 ps
CPU time 29.43 seconds
Started Aug 05 05:48:31 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 221376 kb
Host smart-5716c7a9-e15d-4ca2-97e9-fcf652bd8bdd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290664911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.4290664911
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.392257411
Short name T228
Test name
Test status
Simulation time 143441357 ps
CPU time 1.19 seconds
Started Aug 05 05:48:05 PM PDT 24
Finished Aug 05 05:48:06 PM PDT 24
Peak memory 200352 kb
Host smart-b521d78d-6080-4b42-9937-2f39f8ee59a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392257411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.392257411
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3592658915
Short name T466
Test name
Test status
Simulation time 121623601 ps
CPU time 1.17 seconds
Started Aug 05 05:48:06 PM PDT 24
Finished Aug 05 05:48:07 PM PDT 24
Peak memory 200456 kb
Host smart-55fde8a5-c144-4e10-b01e-b8f6aa75f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592658915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3592658915
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.413694843
Short name T498
Test name
Test status
Simulation time 6814082110 ps
CPU time 29.81 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:50 PM PDT 24
Peak memory 200464 kb
Host smart-1b1f8179-3613-4397-98bd-a61d135eb10e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413694843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.413694843
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3145148574
Short name T36
Test name
Test status
Simulation time 489418137 ps
CPU time 2.75 seconds
Started Aug 05 05:48:13 PM PDT 24
Finished Aug 05 05:48:16 PM PDT 24
Peak memory 200368 kb
Host smart-2299c401-37d4-4193-9620-af848ea52c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145148574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3145148574
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2843222993
Short name T537
Test name
Test status
Simulation time 153198336 ps
CPU time 1.14 seconds
Started Aug 05 05:48:16 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 200488 kb
Host smart-b6671f89-6039-4ed1-b7e2-ffbc89bd0903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843222993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2843222993
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1054720154
Short name T322
Test name
Test status
Simulation time 83195109 ps
CPU time 0.8 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 200168 kb
Host smart-201d2e35-67f6-4be7-a853-25c7592314a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054720154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1054720154
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1197807531
Short name T444
Test name
Test status
Simulation time 1885344160 ps
CPU time 7.48 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 217644 kb
Host smart-c966ef44-6a0d-476f-9545-c1fcd5ff380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197807531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1197807531
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3191469925
Short name T429
Test name
Test status
Simulation time 244447732 ps
CPU time 1.13 seconds
Started Aug 05 05:48:55 PM PDT 24
Finished Aug 05 05:48:56 PM PDT 24
Peak memory 217580 kb
Host smart-59ef5fb0-29d1-40e7-8ded-a62091a6297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191469925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3191469925
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.2997204801
Short name T16
Test name
Test status
Simulation time 200000245 ps
CPU time 0.93 seconds
Started Aug 05 05:49:03 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 200160 kb
Host smart-8e170ff1-51b7-497d-8008-b658cc501488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997204801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2997204801
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1531263762
Short name T204
Test name
Test status
Simulation time 806737003 ps
CPU time 3.85 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:06 PM PDT 24
Peak memory 200560 kb
Host smart-7e44a0f0-b30e-442a-9ad2-2585d5bf54d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531263762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1531263762
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3410962889
Short name T216
Test name
Test status
Simulation time 107236770 ps
CPU time 0.96 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200348 kb
Host smart-c1c42fad-ba5c-4874-b671-556800a542c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410962889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3410962889
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.228050385
Short name T133
Test name
Test status
Simulation time 240031335 ps
CPU time 1.56 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:02 PM PDT 24
Peak memory 200464 kb
Host smart-4d49bcb9-3e18-466e-8aff-fdff8456578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228050385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.228050385
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3844273179
Short name T470
Test name
Test status
Simulation time 6166655633 ps
CPU time 21.05 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:22 PM PDT 24
Peak memory 200616 kb
Host smart-a0d50818-1c93-462b-aa4f-5de82ff9f050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844273179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3844273179
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2432589015
Short name T132
Test name
Test status
Simulation time 430325914 ps
CPU time 2.52 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 208484 kb
Host smart-456a0a9b-c092-427f-a44a-3782b377b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432589015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2432589015
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.442511067
Short name T496
Test name
Test status
Simulation time 164414411 ps
CPU time 1.25 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 200496 kb
Host smart-3cc6d707-2781-4846-9ff8-b63a60fee581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442511067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.442511067
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2396867438
Short name T249
Test name
Test status
Simulation time 81486806 ps
CPU time 0.78 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200160 kb
Host smart-6981ffa5-2d0a-44c9-ab4f-ebc87016aef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396867438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2396867438
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2367502147
Short name T295
Test name
Test status
Simulation time 1220713753 ps
CPU time 5.88 seconds
Started Aug 05 05:49:01 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 217728 kb
Host smart-79cd0e33-c6aa-4eb2-b7d6-cf232543a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367502147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2367502147
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3069851205
Short name T394
Test name
Test status
Simulation time 243875253 ps
CPU time 1.13 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:57 PM PDT 24
Peak memory 217396 kb
Host smart-df58e88a-eda1-4788-8353-462fc2663284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069851205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3069851205
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2203557049
Short name T526
Test name
Test status
Simulation time 198458880 ps
CPU time 0.96 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:57 PM PDT 24
Peak memory 200112 kb
Host smart-df019ac5-4fe1-43ed-873f-c0e419551ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203557049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2203557049
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1089186474
Short name T126
Test name
Test status
Simulation time 2030830803 ps
CPU time 7.22 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:09 PM PDT 24
Peak memory 200556 kb
Host smart-734b8f5f-65f8-4d57-b3e7-28ae418f1f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089186474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1089186474
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.339339979
Short name T278
Test name
Test status
Simulation time 149490555 ps
CPU time 1.12 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200308 kb
Host smart-032e7851-bfea-4b00-af0b-45b3bc160e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339339979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.339339979
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1405099200
Short name T379
Test name
Test status
Simulation time 252281433 ps
CPU time 1.54 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200496 kb
Host smart-fadca06d-4252-4af8-947d-c6dab2f3be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405099200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1405099200
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.770617485
Short name T270
Test name
Test status
Simulation time 306494064 ps
CPU time 1.53 seconds
Started Aug 05 05:48:52 PM PDT 24
Finished Aug 05 05:48:54 PM PDT 24
Peak memory 200524 kb
Host smart-f49a04d3-aa1e-424e-9cb2-b2339560bb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770617485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.770617485
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3478010085
Short name T311
Test name
Test status
Simulation time 485249224 ps
CPU time 2.67 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200308 kb
Host smart-62695c14-5cbf-466d-a9f5-62dc0279c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478010085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3478010085
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.892234912
Short name T489
Test name
Test status
Simulation time 182365823 ps
CPU time 1.43 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 200496 kb
Host smart-49e94013-221d-4945-956b-a1016d271c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892234912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.892234912
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3427391868
Short name T9
Test name
Test status
Simulation time 80788026 ps
CPU time 0.79 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:23 PM PDT 24
Peak memory 200128 kb
Host smart-b638cce0-12d5-44cb-83c4-bbd3549b1efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427391868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3427391868
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1337639804
Short name T369
Test name
Test status
Simulation time 1220373010 ps
CPU time 5.2 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:06 PM PDT 24
Peak memory 217444 kb
Host smart-4daeca44-2303-452b-867d-a9ee7923797d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337639804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1337639804
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3936698805
Short name T364
Test name
Test status
Simulation time 244531341 ps
CPU time 1.06 seconds
Started Aug 05 05:49:03 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 217532 kb
Host smart-9d304627-817f-43bd-9e1a-a0b05e4cf926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936698805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3936698805
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.813651702
Short name T514
Test name
Test status
Simulation time 204571131 ps
CPU time 0.9 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200336 kb
Host smart-2c2298da-16aa-41d7-8f94-1e5934f37b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813651702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.813651702
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1225162940
Short name T335
Test name
Test status
Simulation time 1343078620 ps
CPU time 5.23 seconds
Started Aug 05 05:48:54 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 200628 kb
Host smart-2cb59ad4-d294-4a12-aaa4-84598fae46d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225162940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1225162940
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3466580400
Short name T287
Test name
Test status
Simulation time 176583219 ps
CPU time 1.15 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:02 PM PDT 24
Peak memory 200348 kb
Host smart-602398f4-b747-4cd9-a27c-f6149d856043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466580400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3466580400
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1479538325
Short name T75
Test name
Test status
Simulation time 255110398 ps
CPU time 1.71 seconds
Started Aug 05 05:48:56 PM PDT 24
Finished Aug 05 05:48:58 PM PDT 24
Peak memory 200484 kb
Host smart-49c38d10-6892-4923-975a-08bde7650dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479538325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1479538325
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1873321388
Short name T63
Test name
Test status
Simulation time 11862672379 ps
CPU time 41.34 seconds
Started Aug 05 05:49:03 PM PDT 24
Finished Aug 05 05:49:44 PM PDT 24
Peak memory 208860 kb
Host smart-bac81106-2132-4a9d-ab3a-fe25f2aea527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873321388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1873321388
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3509785262
Short name T257
Test name
Test status
Simulation time 156115725 ps
CPU time 1.91 seconds
Started Aug 05 05:48:53 PM PDT 24
Finished Aug 05 05:48:55 PM PDT 24
Peak memory 200292 kb
Host smart-a852ccce-28af-470a-b017-3f88e2163ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509785262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3509785262
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1698894329
Short name T83
Test name
Test status
Simulation time 176039540 ps
CPU time 1.34 seconds
Started Aug 05 05:48:55 PM PDT 24
Finished Aug 05 05:48:57 PM PDT 24
Peak memory 200452 kb
Host smart-dbcf1f4c-551e-47c3-8d32-3b3200cb4f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698894329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1698894329
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1738880127
Short name T382
Test name
Test status
Simulation time 85237606 ps
CPU time 0.83 seconds
Started Aug 05 05:48:57 PM PDT 24
Finished Aug 05 05:48:58 PM PDT 24
Peak memory 200152 kb
Host smart-adf7d77d-b8fc-415f-8902-3bcf960429fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738880127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1738880127
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.1736834039
Short name T453
Test name
Test status
Simulation time 1217703142 ps
CPU time 5.85 seconds
Started Aug 05 05:49:04 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 217824 kb
Host smart-e6213574-d602-493c-b9c2-15cbc549e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736834039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1736834039
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3129286042
Short name T425
Test name
Test status
Simulation time 244954777 ps
CPU time 1.18 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 217584 kb
Host smart-01094b44-20c3-4481-8dfe-a9eda8721f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129286042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3129286042
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1527678515
Short name T529
Test name
Test status
Simulation time 193412132 ps
CPU time 0.96 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200256 kb
Host smart-5c539b0a-da70-4d9a-97f2-bcc49857f888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527678515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1527678515
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2067256414
Short name T105
Test name
Test status
Simulation time 1056249398 ps
CPU time 5.25 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200592 kb
Host smart-7336f798-9140-4d81-a110-31b976ece659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067256414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2067256414
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.985848278
Short name T156
Test name
Test status
Simulation time 110913706 ps
CPU time 1.03 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200344 kb
Host smart-fbf27610-6874-444d-ae39-75ba4173f340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985848278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.985848278
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2515138706
Short name T416
Test name
Test status
Simulation time 121495082 ps
CPU time 1.23 seconds
Started Aug 05 05:49:01 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200488 kb
Host smart-ef64bb7f-75a0-4ba7-8a45-3e74a32614bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515138706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2515138706
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.3273618247
Short name T103
Test name
Test status
Simulation time 4794442721 ps
CPU time 16.6 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:19 PM PDT 24
Peak memory 200620 kb
Host smart-310195cd-3e52-48c5-89dc-372ac95ef196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273618247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3273618247
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2899122171
Short name T85
Test name
Test status
Simulation time 118942290 ps
CPU time 1.56 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:02 PM PDT 24
Peak memory 200292 kb
Host smart-fb56c275-541e-4b43-996c-db2c6d896b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899122171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2899122171
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.674599754
Short name T69
Test name
Test status
Simulation time 89240653 ps
CPU time 0.94 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 200136 kb
Host smart-0121ec0f-5418-4694-9238-7d1db7de1fcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674599754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.674599754
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1577115052
Short name T34
Test name
Test status
Simulation time 2179748580 ps
CPU time 8.52 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 217816 kb
Host smart-c40d70e0-e494-4d03-a5b5-6eaf76b8f8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577115052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1577115052
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.165470988
Short name T191
Test name
Test status
Simulation time 243666614 ps
CPU time 1.14 seconds
Started Aug 05 05:49:05 PM PDT 24
Finished Aug 05 05:49:06 PM PDT 24
Peak memory 217488 kb
Host smart-c63379f5-4977-42be-ac78-eb42966401be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165470988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.165470988
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1223055105
Short name T426
Test name
Test status
Simulation time 191414791 ps
CPU time 0.95 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200160 kb
Host smart-083feb29-123c-4029-8489-70a6332c32d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223055105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1223055105
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.838984073
Short name T463
Test name
Test status
Simulation time 1054336349 ps
CPU time 5.16 seconds
Started Aug 05 05:49:01 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 200528 kb
Host smart-711e2679-fca6-4849-b41b-95ed6adf5bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838984073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.838984073
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3226998021
Short name T284
Test name
Test status
Simulation time 160983347 ps
CPU time 1.18 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:23 PM PDT 24
Peak memory 200352 kb
Host smart-71ebf02b-fa49-4c1c-80a0-76cfd54aafb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226998021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3226998021
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2869421
Short name T527
Test name
Test status
Simulation time 186901840 ps
CPU time 1.33 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200488 kb
Host smart-a7c68fc6-677c-4400-a367-44a8c399699d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2869421
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.31978096
Short name T99
Test name
Test status
Simulation time 5008450828 ps
CPU time 22.32 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:22 PM PDT 24
Peak memory 200624 kb
Host smart-12477771-fb86-4fb5-8801-4be2d7b9161a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31978096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.31978096
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.2256889510
Short name T474
Test name
Test status
Simulation time 122039099 ps
CPU time 1.47 seconds
Started Aug 05 05:48:57 PM PDT 24
Finished Aug 05 05:48:58 PM PDT 24
Peak memory 200304 kb
Host smart-40297829-9fe2-4ddf-aa5a-d339f247e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256889510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2256889510
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3620909137
Short name T343
Test name
Test status
Simulation time 90734103 ps
CPU time 0.95 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 200352 kb
Host smart-6de9ca83-c833-4a07-a75b-ce8541fcd837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620909137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3620909137
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3670469045
Short name T357
Test name
Test status
Simulation time 69272457 ps
CPU time 0.75 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200168 kb
Host smart-502f64d8-aabd-4271-92f7-f0316daa2e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670469045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3670469045
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3959016394
Short name T45
Test name
Test status
Simulation time 2361600267 ps
CPU time 7.97 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:18 PM PDT 24
Peak memory 217784 kb
Host smart-a59c8dc8-5fe6-4717-93b3-fb8ad8608683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959016394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3959016394
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.885031193
Short name T447
Test name
Test status
Simulation time 244245288 ps
CPU time 1.17 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 217524 kb
Host smart-bbde5a47-2656-43dc-b6fe-840c9f876a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885031193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.885031193
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2557476609
Short name T353
Test name
Test status
Simulation time 125190258 ps
CPU time 0.81 seconds
Started Aug 05 05:49:05 PM PDT 24
Finished Aug 05 05:49:06 PM PDT 24
Peak memory 200156 kb
Host smart-e01bc531-b300-4f5f-b3ce-7ac2349124fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557476609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2557476609
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3777849119
Short name T277
Test name
Test status
Simulation time 1170705042 ps
CPU time 4.78 seconds
Started Aug 05 05:49:03 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 200564 kb
Host smart-c445090f-969b-4ea1-af9f-0299b85f7bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777849119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3777849119
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1270060068
Short name T76
Test name
Test status
Simulation time 146029331 ps
CPU time 1.08 seconds
Started Aug 05 05:49:15 PM PDT 24
Finished Aug 05 05:49:16 PM PDT 24
Peak memory 200352 kb
Host smart-921fd858-3ca0-4dbb-aaa1-e4fba11c8f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270060068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1270060068
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1129253398
Short name T292
Test name
Test status
Simulation time 201788966 ps
CPU time 1.37 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:03 PM PDT 24
Peak memory 200536 kb
Host smart-a55bde1c-0ba4-4443-88ec-8aed68f086b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129253398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1129253398
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1794920343
Short name T406
Test name
Test status
Simulation time 2618085586 ps
CPU time 11.25 seconds
Started Aug 05 05:49:06 PM PDT 24
Finished Aug 05 05:49:17 PM PDT 24
Peak memory 208812 kb
Host smart-a45ec2aa-9fff-41ce-b23c-48e090f17aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794920343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1794920343
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.78036646
Short name T174
Test name
Test status
Simulation time 120996047 ps
CPU time 1.47 seconds
Started Aug 05 05:49:15 PM PDT 24
Finished Aug 05 05:49:17 PM PDT 24
Peak memory 200304 kb
Host smart-c4516d16-08a6-4ff4-8351-1580e0c3dfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78036646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.78036646
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.4002607600
Short name T179
Test name
Test status
Simulation time 176026837 ps
CPU time 1.17 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 200348 kb
Host smart-446a85cb-ed32-4933-b9e4-047473726795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002607600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.4002607600
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1159122814
Short name T458
Test name
Test status
Simulation time 110029510 ps
CPU time 0.87 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 200164 kb
Host smart-b525fe5a-b62d-4662-a7d8-4d9dd6e3e1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159122814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1159122814
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.167489821
Short name T51
Test name
Test status
Simulation time 1234086815 ps
CPU time 6.14 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:06 PM PDT 24
Peak memory 221672 kb
Host smart-b230f83f-a2a1-4da6-83b3-b43f273dcfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167489821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.167489821
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3645163137
Short name T427
Test name
Test status
Simulation time 244524511 ps
CPU time 1.12 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 217496 kb
Host smart-a01da7a9-0bc3-47cf-bd2d-67e573e1acc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645163137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3645163137
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3202549584
Short name T21
Test name
Test status
Simulation time 107235406 ps
CPU time 0.79 seconds
Started Aug 05 05:49:08 PM PDT 24
Finished Aug 05 05:49:09 PM PDT 24
Peak memory 200256 kb
Host smart-b56c650f-489b-441f-89bb-e8413fc328b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202549584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3202549584
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2130868535
Short name T107
Test name
Test status
Simulation time 1541668835 ps
CPU time 6.36 seconds
Started Aug 05 05:49:01 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 200708 kb
Host smart-330d5738-1b74-490c-90c0-89a2a325ea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130868535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2130868535
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2206110222
Short name T263
Test name
Test status
Simulation time 108624951 ps
CPU time 1.03 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 200280 kb
Host smart-3a6780e2-8cd0-4391-b546-2796f8780862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206110222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2206110222
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3286636787
Short name T254
Test name
Test status
Simulation time 252659867 ps
CPU time 1.56 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:02 PM PDT 24
Peak memory 200512 kb
Host smart-0cb166cb-cf8b-43ed-89a4-0e2949345a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286636787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3286636787
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1624393704
Short name T310
Test name
Test status
Simulation time 4937488713 ps
CPU time 22.08 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:31 PM PDT 24
Peak memory 208852 kb
Host smart-ab87ae85-32c0-4463-b33b-aef0670ff8c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624393704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1624393704
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2321372500
Short name T385
Test name
Test status
Simulation time 125612143 ps
CPU time 1.68 seconds
Started Aug 05 05:49:03 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 208548 kb
Host smart-7d0cfc15-f400-450b-a56e-7923fe9316ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321372500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2321372500
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2476645938
Short name T523
Test name
Test status
Simulation time 69030489 ps
CPU time 0.73 seconds
Started Aug 05 05:49:06 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 200352 kb
Host smart-395c85b3-6e19-4ed6-8344-3dfa8f958bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476645938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2476645938
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.982604562
Short name T146
Test name
Test status
Simulation time 83113641 ps
CPU time 0.82 seconds
Started Aug 05 05:49:04 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 200172 kb
Host smart-c450116e-cbe2-4d86-be71-d696bd213afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982604562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.982604562
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2557795464
Short name T47
Test name
Test status
Simulation time 1891386242 ps
CPU time 7.76 seconds
Started Aug 05 05:49:01 PM PDT 24
Finished Aug 05 05:49:09 PM PDT 24
Peak memory 217712 kb
Host smart-62384000-50a7-47eb-b39b-58be26e0de1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557795464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2557795464
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.842750692
Short name T477
Test name
Test status
Simulation time 244036823 ps
CPU time 1.16 seconds
Started Aug 05 05:48:58 PM PDT 24
Finished Aug 05 05:48:59 PM PDT 24
Peak memory 217576 kb
Host smart-9ec31350-f458-4109-b727-0c7fcc0bbb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842750692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.842750692
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3845529176
Short name T218
Test name
Test status
Simulation time 235790669 ps
CPU time 1.06 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:01 PM PDT 24
Peak memory 200144 kb
Host smart-3d0d0dca-5aea-4d83-9c9f-e19654216c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845529176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3845529176
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.454604077
Short name T331
Test name
Test status
Simulation time 1205129572 ps
CPU time 5.12 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 200776 kb
Host smart-126f899b-4cc2-441d-8629-f7521c33fc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454604077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.454604077
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.631284565
Short name T452
Test name
Test status
Simulation time 174993689 ps
CPU time 1.18 seconds
Started Aug 05 05:48:59 PM PDT 24
Finished Aug 05 05:49:00 PM PDT 24
Peak memory 200336 kb
Host smart-4c33d1bc-a7fb-4344-87c6-16346c0f24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631284565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.631284565
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1122694383
Short name T178
Test name
Test status
Simulation time 245568271 ps
CPU time 1.53 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 200536 kb
Host smart-3af6389b-0f47-4be0-9d9d-89fc38badd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122694383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1122694383
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4110315771
Short name T101
Test name
Test status
Simulation time 5817043177 ps
CPU time 24.96 seconds
Started Aug 05 05:49:00 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 200620 kb
Host smart-59b3cc54-3976-469c-8a09-55b4337c36d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110315771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4110315771
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1931854661
Short name T312
Test name
Test status
Simulation time 466118581 ps
CPU time 2.58 seconds
Started Aug 05 05:49:01 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 200272 kb
Host smart-ee5fa58a-d4f0-4347-80bd-2f43d04a9ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931854661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1931854661
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1399170067
Short name T195
Test name
Test status
Simulation time 94313514 ps
CPU time 0.91 seconds
Started Aug 05 05:49:20 PM PDT 24
Finished Aug 05 05:49:21 PM PDT 24
Peak memory 200352 kb
Host smart-76d57e1b-2ada-412c-ba68-b3d397f9df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399170067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1399170067
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3444954893
Short name T148
Test name
Test status
Simulation time 75205144 ps
CPU time 0.78 seconds
Started Aug 05 05:49:15 PM PDT 24
Finished Aug 05 05:49:16 PM PDT 24
Peak memory 200112 kb
Host smart-693f9030-6bdf-4c26-a037-eaf9a506cd59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444954893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3444954893
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2853576381
Short name T25
Test name
Test status
Simulation time 1225868448 ps
CPU time 5.38 seconds
Started Aug 05 05:49:15 PM PDT 24
Finished Aug 05 05:49:20 PM PDT 24
Peak memory 217436 kb
Host smart-54916530-7aa0-4a65-9fce-825b3526feb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853576381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2853576381
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2792134734
Short name T494
Test name
Test status
Simulation time 245499370 ps
CPU time 1.02 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 217516 kb
Host smart-b12eef42-ce96-474e-84fd-beb1fa931d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792134734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2792134734
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1361563416
Short name T488
Test name
Test status
Simulation time 143791840 ps
CPU time 0.86 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 200148 kb
Host smart-0d042e73-92b7-4fc1-8331-3367fa06846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361563416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1361563416
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3726483313
Short name T323
Test name
Test status
Simulation time 1827162217 ps
CPU time 7.44 seconds
Started Aug 05 05:49:13 PM PDT 24
Finished Aug 05 05:49:21 PM PDT 24
Peak memory 200508 kb
Host smart-2771bca5-9a6e-416a-9ab7-4dd599b54e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726483313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3726483313
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.642046867
Short name T282
Test name
Test status
Simulation time 109203959 ps
CPU time 1.04 seconds
Started Aug 05 05:49:17 PM PDT 24
Finished Aug 05 05:49:18 PM PDT 24
Peak memory 200336 kb
Host smart-56a4bc92-1943-4a79-af71-550e481d2b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642046867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.642046867
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.43604563
Short name T232
Test name
Test status
Simulation time 253074788 ps
CPU time 1.55 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:09 PM PDT 24
Peak memory 200528 kb
Host smart-d2290cb9-b05c-425e-af44-bcdc3975feec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43604563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.43604563
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1291741609
Short name T11
Test name
Test status
Simulation time 6736128733 ps
CPU time 27.55 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:48 PM PDT 24
Peak memory 208820 kb
Host smart-a873a85c-1ee8-4747-956c-91e98e59789a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291741609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1291741609
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2676372343
Short name T476
Test name
Test status
Simulation time 480993525 ps
CPU time 2.66 seconds
Started Aug 05 05:49:05 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 208504 kb
Host smart-c81884c1-4391-46bd-a1e0-af84851dfb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676372343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2676372343
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2997109358
Short name T187
Test name
Test status
Simulation time 145106206 ps
CPU time 1.3 seconds
Started Aug 05 05:49:06 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 200484 kb
Host smart-a8524ec2-2008-425f-a131-b70af9ef8f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997109358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2997109358
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2860584909
Short name T522
Test name
Test status
Simulation time 65371604 ps
CPU time 0.75 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 200156 kb
Host smart-887e56d6-87dd-4bb0-b4bf-21d9b62976de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860584909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2860584909
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2640938850
Short name T368
Test name
Test status
Simulation time 1887513546 ps
CPU time 7.38 seconds
Started Aug 05 05:49:03 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 221740 kb
Host smart-4c837e31-c70c-494a-8851-fb186f9d8990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640938850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2640938850
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1858602395
Short name T532
Test name
Test status
Simulation time 244000805 ps
CPU time 1.14 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 217588 kb
Host smart-527c36a6-d8be-4b1e-9e60-4d26da7d8eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858602395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1858602395
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2981767505
Short name T259
Test name
Test status
Simulation time 166236514 ps
CPU time 0.94 seconds
Started Aug 05 05:49:06 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 200164 kb
Host smart-cf29c950-e19a-4c81-80c4-08acbeae3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981767505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2981767505
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1962057508
Short name T377
Test name
Test status
Simulation time 837865445 ps
CPU time 4.46 seconds
Started Aug 05 05:49:05 PM PDT 24
Finished Aug 05 05:49:09 PM PDT 24
Peak memory 200564 kb
Host smart-511cd7e2-4670-4f95-a512-5f9334c71d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962057508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1962057508
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3375616421
Short name T7
Test name
Test status
Simulation time 172567566 ps
CPU time 1.11 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 200356 kb
Host smart-630972f5-c7d1-42e3-8a07-46a72a6d690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375616421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3375616421
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2516497967
Short name T349
Test name
Test status
Simulation time 121324413 ps
CPU time 1.14 seconds
Started Aug 05 05:49:24 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 200488 kb
Host smart-7c6e2fdc-45ef-4abb-a9b8-1a9419ec94b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516497967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2516497967
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1474779704
Short name T412
Test name
Test status
Simulation time 3888437712 ps
CPU time 17 seconds
Started Aug 05 05:49:02 PM PDT 24
Finished Aug 05 05:49:19 PM PDT 24
Peak memory 200656 kb
Host smart-ad582b53-c412-47a9-a739-008eac6cdfd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474779704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1474779704
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2731360536
Short name T172
Test name
Test status
Simulation time 258736087 ps
CPU time 1.94 seconds
Started Aug 05 05:49:11 PM PDT 24
Finished Aug 05 05:49:13 PM PDT 24
Peak memory 200200 kb
Host smart-5f3418b3-257a-4d77-a48e-893258fc4ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731360536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2731360536
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3762279249
Short name T402
Test name
Test status
Simulation time 79114225 ps
CPU time 0.82 seconds
Started Aug 05 05:49:14 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 200332 kb
Host smart-71f0b09a-4e63-40c5-bdba-c2e91ce1a6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762279249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3762279249
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.979445508
Short name T430
Test name
Test status
Simulation time 79903475 ps
CPU time 0.88 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 199984 kb
Host smart-f63839b9-0c1e-4fb0-9a93-effcbe4265af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979445508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.979445508
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.4162338802
Short name T404
Test name
Test status
Simulation time 1898926625 ps
CPU time 7.6 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 216936 kb
Host smart-d196ae20-c2e1-425c-aceb-582b8a153977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162338802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4162338802
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1463092658
Short name T487
Test name
Test status
Simulation time 244404284 ps
CPU time 1.19 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 217388 kb
Host smart-ca26d18e-5afd-455c-a001-d1887de112d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463092658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1463092658
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.799501227
Short name T524
Test name
Test status
Simulation time 198580774 ps
CPU time 0.87 seconds
Started Aug 05 05:48:09 PM PDT 24
Finished Aug 05 05:48:10 PM PDT 24
Peak memory 200164 kb
Host smart-f3a0fca4-6ff5-41e7-9dea-6967998a0b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799501227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.799501227
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3145223235
Short name T40
Test name
Test status
Simulation time 964374715 ps
CPU time 4.61 seconds
Started Aug 05 05:48:12 PM PDT 24
Finished Aug 05 05:48:17 PM PDT 24
Peak memory 200780 kb
Host smart-9416ab2b-503b-4b81-9110-de247328f38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145223235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3145223235
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2842220859
Short name T67
Test name
Test status
Simulation time 16534871835 ps
CPU time 30.92 seconds
Started Aug 05 05:48:33 PM PDT 24
Finished Aug 05 05:49:04 PM PDT 24
Peak memory 217424 kb
Host smart-7dc5610d-806d-40dc-932f-448a88b43f5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842220859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2842220859
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2945198764
Short name T413
Test name
Test status
Simulation time 107068805 ps
CPU time 1.06 seconds
Started Aug 05 05:48:05 PM PDT 24
Finished Aug 05 05:48:07 PM PDT 24
Peak memory 200352 kb
Host smart-9ed0f57e-c70d-4719-a0c8-34c6f106127d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945198764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2945198764
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3873004907
Short name T211
Test name
Test status
Simulation time 190038561 ps
CPU time 1.43 seconds
Started Aug 05 05:48:09 PM PDT 24
Finished Aug 05 05:48:11 PM PDT 24
Peak memory 200532 kb
Host smart-44afedcf-288d-4261-89bc-04266ec8e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873004907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3873004907
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2937966780
Short name T303
Test name
Test status
Simulation time 5038481540 ps
CPU time 24.13 seconds
Started Aug 05 05:48:28 PM PDT 24
Finished Aug 05 05:48:52 PM PDT 24
Peak memory 208804 kb
Host smart-b3306d57-75e3-4c9a-be4a-dc278401521e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937966780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2937966780
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1233642564
Short name T266
Test name
Test status
Simulation time 123910048 ps
CPU time 1.44 seconds
Started Aug 05 05:48:22 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 200308 kb
Host smart-72386c67-2c0c-42e3-9aa8-1f7d9c7b57a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233642564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1233642564
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1357445478
Short name T434
Test name
Test status
Simulation time 124737581 ps
CPU time 1.11 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:09 PM PDT 24
Peak memory 200344 kb
Host smart-2a6c13c1-00e9-4168-ade4-8b8a8b50495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357445478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1357445478
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1987160680
Short name T169
Test name
Test status
Simulation time 70155929 ps
CPU time 0.83 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:22 PM PDT 24
Peak memory 200088 kb
Host smart-c5c39f26-2d50-4ca6-a7d6-92a3937ccd55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987160680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1987160680
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3789946042
Short name T48
Test name
Test status
Simulation time 1885251945 ps
CPU time 7.96 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:18 PM PDT 24
Peak memory 221632 kb
Host smart-c76acac5-af7e-4c6c-b3e1-5cf731c9f9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789946042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3789946042
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2707904993
Short name T189
Test name
Test status
Simulation time 244206575 ps
CPU time 1.06 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 217472 kb
Host smart-294eb8a7-aff4-4191-834e-2cd311c8ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707904993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2707904993
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1718220369
Short name T507
Test name
Test status
Simulation time 139819933 ps
CPU time 0.84 seconds
Started Aug 05 05:49:04 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 200156 kb
Host smart-960bed8f-fe2d-48e5-b733-576508c0e744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718220369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1718220369
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3295788663
Short name T501
Test name
Test status
Simulation time 1760624976 ps
CPU time 6.68 seconds
Started Aug 05 05:49:11 PM PDT 24
Finished Aug 05 05:49:18 PM PDT 24
Peak memory 200444 kb
Host smart-14622f9a-f3b5-4e6d-9223-0558dd4f13b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295788663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3295788663
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.877920011
Short name T35
Test name
Test status
Simulation time 186745165 ps
CPU time 1.18 seconds
Started Aug 05 05:49:13 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 200356 kb
Host smart-18964cbb-44a6-4df7-8ed0-c3a2fa0b5c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877920011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.877920011
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3645789978
Short name T215
Test name
Test status
Simulation time 115991418 ps
CPU time 1.37 seconds
Started Aug 05 05:49:12 PM PDT 24
Finished Aug 05 05:49:14 PM PDT 24
Peak memory 200456 kb
Host smart-3cddc628-0b55-474f-8a69-db2058479d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645789978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3645789978
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2378741809
Short name T251
Test name
Test status
Simulation time 472623613 ps
CPU time 2.59 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 200416 kb
Host smart-597f6543-c364-46db-981d-a419dbbf0eeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378741809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2378741809
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2161921362
Short name T294
Test name
Test status
Simulation time 121364399 ps
CPU time 1.53 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:09 PM PDT 24
Peak memory 200292 kb
Host smart-680cec69-b726-4720-8cdd-801bbe00f6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161921362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2161921362
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3400820581
Short name T142
Test name
Test status
Simulation time 90774764 ps
CPU time 0.93 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 200340 kb
Host smart-3b430e8f-a033-4a4d-a581-41b219435c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400820581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3400820581
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2467093032
Short name T539
Test name
Test status
Simulation time 70450727 ps
CPU time 0.82 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 200112 kb
Host smart-4591b3db-0c95-4201-94cb-ae1583774522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467093032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2467093032
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1918423858
Short name T239
Test name
Test status
Simulation time 2365544203 ps
CPU time 8.67 seconds
Started Aug 05 05:49:06 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 217848 kb
Host smart-dea2a133-4fe4-4c57-9be4-da1598557f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918423858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1918423858
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.364524017
Short name T517
Test name
Test status
Simulation time 246207940 ps
CPU time 1.05 seconds
Started Aug 05 05:49:12 PM PDT 24
Finished Aug 05 05:49:13 PM PDT 24
Peak memory 217420 kb
Host smart-aa026ab8-4e3f-448a-9383-483343b4fc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364524017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.364524017
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.204291520
Short name T255
Test name
Test status
Simulation time 132539162 ps
CPU time 0.83 seconds
Started Aug 05 05:49:24 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 200080 kb
Host smart-6625b55f-a928-44df-88cd-4b5d1fad7525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204291520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.204291520
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.233944964
Short name T390
Test name
Test status
Simulation time 776004234 ps
CPU time 3.96 seconds
Started Aug 05 05:49:06 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 200596 kb
Host smart-4913f25c-b7ab-401e-a872-e722b3879716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233944964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.233944964
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.181215824
Short name T225
Test name
Test status
Simulation time 139499144 ps
CPU time 1.14 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 200280 kb
Host smart-9c1c94ce-eaa3-4e7c-b4a6-31d6bcd23c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181215824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.181215824
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2950640423
Short name T217
Test name
Test status
Simulation time 240318254 ps
CPU time 1.71 seconds
Started Aug 05 05:49:13 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 200488 kb
Host smart-87679c7f-83dc-4eb0-b280-1f54cfc3a06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950640423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2950640423
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1006589257
Short name T290
Test name
Test status
Simulation time 2392840173 ps
CPU time 9.3 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:17 PM PDT 24
Peak memory 200612 kb
Host smart-d16f418d-b8ad-490d-9e6b-82ac2a35c497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006589257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1006589257
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2417516156
Short name T261
Test name
Test status
Simulation time 345659693 ps
CPU time 1.95 seconds
Started Aug 05 05:49:24 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 200232 kb
Host smart-819bd42a-694a-4938-8a3d-4085eebffaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417516156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2417516156
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.639247242
Short name T516
Test name
Test status
Simulation time 138367048 ps
CPU time 1.16 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:23 PM PDT 24
Peak memory 200348 kb
Host smart-737f5df8-c646-4179-b828-eca228138f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639247242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.639247242
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2747636523
Short name T363
Test name
Test status
Simulation time 67904856 ps
CPU time 0.79 seconds
Started Aug 05 05:49:13 PM PDT 24
Finished Aug 05 05:49:14 PM PDT 24
Peak memory 200112 kb
Host smart-1ee44184-f82c-4650-bd13-4ffdd2df00fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747636523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2747636523
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2660439973
Short name T352
Test name
Test status
Simulation time 2354841286 ps
CPU time 8.2 seconds
Started Aug 05 05:49:19 PM PDT 24
Finished Aug 05 05:49:28 PM PDT 24
Peak memory 221784 kb
Host smart-c14e48b5-7944-4b26-8fb1-f9f423e87afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660439973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2660439973
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.945663949
Short name T73
Test name
Test status
Simulation time 243905504 ps
CPU time 1.07 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:08 PM PDT 24
Peak memory 217528 kb
Host smart-90383a2a-3a6d-443e-8c57-6508d9c668d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945663949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.945663949
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3074523098
Short name T193
Test name
Test status
Simulation time 214364918 ps
CPU time 0.91 seconds
Started Aug 05 05:49:04 PM PDT 24
Finished Aug 05 05:49:05 PM PDT 24
Peak memory 200136 kb
Host smart-d66921a9-e744-44f5-8876-52723cf62a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074523098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3074523098
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.4117079073
Short name T5
Test name
Test status
Simulation time 1947841247 ps
CPU time 6.61 seconds
Started Aug 05 05:49:12 PM PDT 24
Finished Aug 05 05:49:19 PM PDT 24
Peak memory 200552 kb
Host smart-f9282212-a7e4-4021-8fde-a3136d224bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117079073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.4117079073
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1668075063
Short name T293
Test name
Test status
Simulation time 176371404 ps
CPU time 1.23 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 200280 kb
Host smart-47be0cc4-9831-4b70-ab74-f8c374c74f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668075063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1668075063
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3544276289
Short name T197
Test name
Test status
Simulation time 114780820 ps
CPU time 1.14 seconds
Started Aug 05 05:49:20 PM PDT 24
Finished Aug 05 05:49:21 PM PDT 24
Peak memory 200528 kb
Host smart-761689ed-9261-4a79-bb3c-913a608d93d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544276289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3544276289
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4018633558
Short name T289
Test name
Test status
Simulation time 1885877124 ps
CPU time 8.85 seconds
Started Aug 05 05:49:11 PM PDT 24
Finished Aug 05 05:49:20 PM PDT 24
Peak memory 200468 kb
Host smart-17524dc5-02e4-4531-81e8-962f3a3d7feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018633558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4018633558
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3202153695
Short name T513
Test name
Test status
Simulation time 129155598 ps
CPU time 1.72 seconds
Started Aug 05 05:49:13 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 208444 kb
Host smart-794e5729-d71d-4853-89f9-2684564e071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202153695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3202153695
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3425173387
Short name T314
Test name
Test status
Simulation time 150648947 ps
CPU time 1.18 seconds
Started Aug 05 05:49:06 PM PDT 24
Finished Aug 05 05:49:07 PM PDT 24
Peak memory 200348 kb
Host smart-0730c28b-c534-44f1-9c76-85e913324c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425173387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3425173387
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2410266164
Short name T520
Test name
Test status
Simulation time 62276705 ps
CPU time 0.73 seconds
Started Aug 05 05:49:12 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 200136 kb
Host smart-fa60eece-51a1-4bef-bfd8-a0781d69a0e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410266164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2410266164
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2815428300
Short name T370
Test name
Test status
Simulation time 1228501468 ps
CPU time 5.6 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 216784 kb
Host smart-8ea5f6f2-ff2e-4c47-b775-8fe6de900119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815428300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2815428300
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1356948259
Short name T459
Test name
Test status
Simulation time 244328396 ps
CPU time 1.15 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 217492 kb
Host smart-a6c20232-75b0-4ebd-9f6c-1d8cfa43c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356948259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1356948259
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3061761841
Short name T182
Test name
Test status
Simulation time 241662458 ps
CPU time 1.01 seconds
Started Aug 05 05:49:14 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 200104 kb
Host smart-2eb191e5-27cb-4043-9561-7b12b9e87c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061761841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3061761841
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1043125688
Short name T528
Test name
Test status
Simulation time 822695998 ps
CPU time 4.22 seconds
Started Aug 05 05:49:07 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 200556 kb
Host smart-97e611a8-cc82-443b-b89c-1bfb40602a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043125688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1043125688
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1604224205
Short name T367
Test name
Test status
Simulation time 145329810 ps
CPU time 1.13 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 200216 kb
Host smart-9d3bb89e-a293-47b1-80cd-f290d3303ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604224205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1604224205
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.504524171
Short name T350
Test name
Test status
Simulation time 120576040 ps
CPU time 1.21 seconds
Started Aug 05 05:49:20 PM PDT 24
Finished Aug 05 05:49:22 PM PDT 24
Peak memory 200424 kb
Host smart-59b29ada-d9a0-42bb-8967-2a4962aa6335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504524171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.504524171
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3138551872
Short name T127
Test name
Test status
Simulation time 7894558300 ps
CPU time 28.58 seconds
Started Aug 05 05:49:20 PM PDT 24
Finished Aug 05 05:49:49 PM PDT 24
Peak memory 210692 kb
Host smart-e7b336b7-7cef-4cd7-a4f8-e6e9adc0f2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138551872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3138551872
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2793493501
Short name T482
Test name
Test status
Simulation time 366243361 ps
CPU time 2.44 seconds
Started Aug 05 05:49:15 PM PDT 24
Finished Aug 05 05:49:18 PM PDT 24
Peak memory 200308 kb
Host smart-8e2828ca-9247-4aa7-867c-63bdec5483f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793493501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2793493501
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.835218029
Short name T167
Test name
Test status
Simulation time 101831415 ps
CPU time 0.92 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 200312 kb
Host smart-07a335cd-3e67-42ac-ad4e-b6420610e37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835218029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.835218029
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3651886854
Short name T203
Test name
Test status
Simulation time 70314975 ps
CPU time 0.82 seconds
Started Aug 05 05:49:11 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 200156 kb
Host smart-066d9443-0441-461f-88b6-93263b5583b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651886854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3651886854
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.656257894
Short name T491
Test name
Test status
Simulation time 1221995636 ps
CPU time 5.52 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 221664 kb
Host smart-91a9251f-ce94-4531-81d1-01d70b04bba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656257894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.656257894
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3456036905
Short name T297
Test name
Test status
Simulation time 244208452 ps
CPU time 1.15 seconds
Started Aug 05 05:49:08 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 217584 kb
Host smart-4acfed9f-17ce-4169-a4b4-901913cc8ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456036905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3456036905
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1783746203
Short name T509
Test name
Test status
Simulation time 127191827 ps
CPU time 0.84 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 200144 kb
Host smart-8385a9ec-1b3b-42ba-9603-3006642db588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783746203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1783746203
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1170471318
Short name T345
Test name
Test status
Simulation time 838919966 ps
CPU time 4.12 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 200460 kb
Host smart-c24bcc99-066a-4cef-8b8f-e7bda00aeecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170471318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1170471318
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.719164198
Short name T265
Test name
Test status
Simulation time 159230429 ps
CPU time 1.2 seconds
Started Aug 05 05:49:08 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 200348 kb
Host smart-47e72641-42c7-4dca-aa8b-bfb471add692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719164198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.719164198
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.195848432
Short name T8
Test name
Test status
Simulation time 198325750 ps
CPU time 1.34 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 200524 kb
Host smart-7c5cab9c-f8ba-4997-ad1b-910cc79ab4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195848432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.195848432
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3727814336
Short name T154
Test name
Test status
Simulation time 260620635 ps
CPU time 1.78 seconds
Started Aug 05 05:49:17 PM PDT 24
Finished Aug 05 05:49:19 PM PDT 24
Peak memory 200276 kb
Host smart-095610a9-0ae0-4f42-aef1-e8e557a4a23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727814336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3727814336
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.4014347489
Short name T222
Test name
Test status
Simulation time 103692554 ps
CPU time 0.93 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 200344 kb
Host smart-b85a4101-49fe-4ac3-b759-11179b09bba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014347489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.4014347489
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3769647981
Short name T432
Test name
Test status
Simulation time 68490862 ps
CPU time 0.77 seconds
Started Aug 05 05:49:11 PM PDT 24
Finished Aug 05 05:49:12 PM PDT 24
Peak memory 200164 kb
Host smart-87cb0702-7aca-485c-bc33-90da26c6c2c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769647981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3769647981
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.884179107
Short name T338
Test name
Test status
Simulation time 1894918156 ps
CPU time 7.02 seconds
Started Aug 05 05:49:15 PM PDT 24
Finished Aug 05 05:49:22 PM PDT 24
Peak memory 221728 kb
Host smart-a8438979-e483-46d2-8c24-eb224cb6b3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884179107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.884179107
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1489712496
Short name T300
Test name
Test status
Simulation time 245039465 ps
CPU time 1.09 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:23 PM PDT 24
Peak memory 217472 kb
Host smart-d282f2ce-9186-4bef-9f37-6654465c0ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489712496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1489712496
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1039087099
Short name T19
Test name
Test status
Simulation time 187320900 ps
CPU time 0.84 seconds
Started Aug 05 05:49:17 PM PDT 24
Finished Aug 05 05:49:18 PM PDT 24
Peak memory 200136 kb
Host smart-538fd321-074a-43b1-adf8-674184d052ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039087099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1039087099
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3920265750
Short name T371
Test name
Test status
Simulation time 1386708150 ps
CPU time 5.57 seconds
Started Aug 05 05:49:12 PM PDT 24
Finished Aug 05 05:49:18 PM PDT 24
Peak memory 200524 kb
Host smart-e49ec854-8db8-460f-bfe1-0e18c2cec515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920265750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3920265750
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.393864823
Short name T511
Test name
Test status
Simulation time 97993851 ps
CPU time 0.96 seconds
Started Aug 05 05:49:24 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 200360 kb
Host smart-98aeb428-172f-4946-ac7f-9d4cfd66e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393864823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.393864823
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1906715424
Short name T157
Test name
Test status
Simulation time 109200260 ps
CPU time 1.21 seconds
Started Aug 05 05:49:19 PM PDT 24
Finished Aug 05 05:49:21 PM PDT 24
Peak memory 200492 kb
Host smart-b3e157ea-2f29-4abb-8208-70e08e2e429a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906715424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1906715424
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.554594273
Short name T493
Test name
Test status
Simulation time 6092832648 ps
CPU time 22.88 seconds
Started Aug 05 05:49:13 PM PDT 24
Finished Aug 05 05:49:36 PM PDT 24
Peak memory 200580 kb
Host smart-5d7d3848-d369-4e86-b362-f47872df5725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554594273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.554594273
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1334294834
Short name T388
Test name
Test status
Simulation time 140777161 ps
CPU time 1.74 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 200312 kb
Host smart-fa17cb7c-1da4-49ae-adea-52ffbce9ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334294834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1334294834
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2083838310
Short name T39
Test name
Test status
Simulation time 137494894 ps
CPU time 1.08 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:22 PM PDT 24
Peak memory 200212 kb
Host smart-4576c2d0-2a45-4605-9585-4486ec19947a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083838310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2083838310
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.938785172
Short name T518
Test name
Test status
Simulation time 62274985 ps
CPU time 0.73 seconds
Started Aug 05 05:49:18 PM PDT 24
Finished Aug 05 05:49:18 PM PDT 24
Peak memory 200172 kb
Host smart-e35d3b72-8b64-4e4d-a164-35d5df1cb9c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938785172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.938785172
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2647465255
Short name T44
Test name
Test status
Simulation time 1896833399 ps
CPU time 7.76 seconds
Started Aug 05 05:49:15 PM PDT 24
Finished Aug 05 05:49:23 PM PDT 24
Peak memory 221680 kb
Host smart-4947b8ad-e667-4ac6-98e1-62f34d947a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647465255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2647465255
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3168859454
Short name T171
Test name
Test status
Simulation time 244625774 ps
CPU time 1.06 seconds
Started Aug 05 05:49:29 PM PDT 24
Finished Aug 05 05:49:30 PM PDT 24
Peak memory 217556 kb
Host smart-ab27a820-149b-485d-b257-344a0402e539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168859454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3168859454
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2511115651
Short name T337
Test name
Test status
Simulation time 95774611 ps
CPU time 0.79 seconds
Started Aug 05 05:49:20 PM PDT 24
Finished Aug 05 05:49:21 PM PDT 24
Peak memory 200160 kb
Host smart-5ad8f156-a003-4da2-95b7-489e8ea5a786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511115651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2511115651
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1666642573
Short name T483
Test name
Test status
Simulation time 1177457228 ps
CPU time 4.87 seconds
Started Aug 05 05:49:20 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 200552 kb
Host smart-59854a72-d4bc-4b53-9e1f-70cdc8beb0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666642573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1666642573
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1278583220
Short name T210
Test name
Test status
Simulation time 105736992 ps
CPU time 1.11 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 200344 kb
Host smart-51cef812-612c-44a5-82e6-dce19e2a8538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278583220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1278583220
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1617663489
Short name T190
Test name
Test status
Simulation time 118947999 ps
CPU time 1.31 seconds
Started Aug 05 05:49:13 PM PDT 24
Finished Aug 05 05:49:14 PM PDT 24
Peak memory 200444 kb
Host smart-e7576747-6122-4818-a22b-0255dbdd3d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617663489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1617663489
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2134599532
Short name T475
Test name
Test status
Simulation time 6974749476 ps
CPU time 24.56 seconds
Started Aug 05 05:49:17 PM PDT 24
Finished Aug 05 05:49:41 PM PDT 24
Peak memory 200620 kb
Host smart-e1724193-cf9f-48d6-be2d-6077a0fcf537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134599532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2134599532
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3068087557
Short name T242
Test name
Test status
Simulation time 478122821 ps
CPU time 2.75 seconds
Started Aug 05 05:49:12 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 200184 kb
Host smart-4e35e19a-6d60-4576-b9b2-d96eab7e9338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068087557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3068087557
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.4116724951
Short name T286
Test name
Test status
Simulation time 70607880 ps
CPU time 0.81 seconds
Started Aug 05 05:49:12 PM PDT 24
Finished Aug 05 05:49:13 PM PDT 24
Peak memory 200236 kb
Host smart-9809a51f-7877-4b81-bc3d-7f6b98b43ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116724951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4116724951
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.73965812
Short name T465
Test name
Test status
Simulation time 97783629 ps
CPU time 0.94 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 200140 kb
Host smart-270f59de-6758-4775-b0a7-f19b30d00016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73965812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.73965812
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.526559179
Short name T366
Test name
Test status
Simulation time 1225532647 ps
CPU time 5.92 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:29 PM PDT 24
Peak memory 217744 kb
Host smart-4fa2f10a-cab3-40ae-abe0-a5de81e55554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526559179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.526559179
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3738245896
Short name T448
Test name
Test status
Simulation time 245231357 ps
CPU time 1.06 seconds
Started Aug 05 05:49:18 PM PDT 24
Finished Aug 05 05:49:20 PM PDT 24
Peak memory 217496 kb
Host smart-caabf047-acf6-498f-bc28-08f374e39930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738245896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3738245896
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2646367448
Short name T176
Test name
Test status
Simulation time 102401055 ps
CPU time 0.76 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:10 PM PDT 24
Peak memory 200116 kb
Host smart-b535ecfa-301e-48a2-bee2-c888c1637bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646367448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2646367448
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3459064259
Short name T168
Test name
Test status
Simulation time 1153203990 ps
CPU time 4.68 seconds
Started Aug 05 05:49:10 PM PDT 24
Finished Aug 05 05:49:15 PM PDT 24
Peak memory 200592 kb
Host smart-b7427298-46c5-40d2-8d4e-e1c96cb29ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459064259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3459064259
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.963700849
Short name T23
Test name
Test status
Simulation time 150993304 ps
CPU time 1.21 seconds
Started Aug 05 05:49:20 PM PDT 24
Finished Aug 05 05:49:21 PM PDT 24
Peak memory 200336 kb
Host smart-adc27b8d-71fa-4c64-b53e-547316e1d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963700849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.963700849
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1377816135
Short name T147
Test name
Test status
Simulation time 112822819 ps
CPU time 1.32 seconds
Started Aug 05 05:49:13 PM PDT 24
Finished Aug 05 05:49:14 PM PDT 24
Peak memory 200460 kb
Host smart-231fcfae-022a-4476-93c1-da8b75cb473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377816135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1377816135
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3891915550
Short name T443
Test name
Test status
Simulation time 6416173449 ps
CPU time 22.6 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:45 PM PDT 24
Peak memory 208808 kb
Host smart-94109ceb-e560-4895-a314-41c3ce1c9906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891915550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3891915550
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1981932431
Short name T341
Test name
Test status
Simulation time 307696879 ps
CPU time 1.98 seconds
Started Aug 05 05:49:09 PM PDT 24
Finished Aug 05 05:49:11 PM PDT 24
Peak memory 208480 kb
Host smart-f1f059de-2338-488c-a039-ff24412c556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981932431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1981932431
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2123783824
Short name T219
Test name
Test status
Simulation time 176907324 ps
CPU time 1.19 seconds
Started Aug 05 05:49:11 PM PDT 24
Finished Aug 05 05:49:13 PM PDT 24
Peak memory 200336 kb
Host smart-0d9cb7c2-7a7b-4c29-a270-bfcebc12f18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123783824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2123783824
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3730962242
Short name T177
Test name
Test status
Simulation time 74081282 ps
CPU time 0.79 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:22 PM PDT 24
Peak memory 200168 kb
Host smart-a1e69f80-d4c4-4086-adb7-90864d6ef1cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730962242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3730962242
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2467759526
Short name T42
Test name
Test status
Simulation time 2365211546 ps
CPU time 8.39 seconds
Started Aug 05 05:49:24 PM PDT 24
Finished Aug 05 05:49:32 PM PDT 24
Peak memory 217620 kb
Host smart-e146f7f9-6677-42f8-8c0e-eb15b75ae5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467759526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2467759526
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1236438103
Short name T201
Test name
Test status
Simulation time 244202895 ps
CPU time 1.12 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:23 PM PDT 24
Peak memory 217496 kb
Host smart-cba56eba-e73f-4e3c-8b3d-6340c3578cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236438103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1236438103
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.547207680
Short name T431
Test name
Test status
Simulation time 126822068 ps
CPU time 0.83 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:23 PM PDT 24
Peak memory 200152 kb
Host smart-0df9f49c-6243-4bb8-8fb7-61a4cba70637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547207680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.547207680
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.4228147869
Short name T538
Test name
Test status
Simulation time 1057284391 ps
CPU time 4.48 seconds
Started Aug 05 05:49:21 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 200552 kb
Host smart-016d1afa-b1e1-47a1-921b-c72eefee1373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228147869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.4228147869
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.599089905
Short name T450
Test name
Test status
Simulation time 108398614 ps
CPU time 1 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 200236 kb
Host smart-69fa8e74-ee10-4e29-a453-b670c61b0a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599089905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.599089905
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2060053418
Short name T440
Test name
Test status
Simulation time 249871220 ps
CPU time 1.56 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 200520 kb
Host smart-47427e15-cdb9-46e0-802c-a2174dc493da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060053418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2060053418
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.43207662
Short name T170
Test name
Test status
Simulation time 503460194 ps
CPU time 2.48 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 200452 kb
Host smart-c83febe1-4e64-4470-887b-3a202d617125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43207662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.43207662
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2522265972
Short name T240
Test name
Test status
Simulation time 444031082 ps
CPU time 2.41 seconds
Started Aug 05 05:49:19 PM PDT 24
Finished Aug 05 05:49:21 PM PDT 24
Peak memory 200296 kb
Host smart-44454faa-9024-4581-8375-e324a2c7bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522265972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2522265972
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2875153298
Short name T151
Test name
Test status
Simulation time 136649309 ps
CPU time 1.19 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 200348 kb
Host smart-c3bbfdb9-b84a-4509-a26f-de29843d04da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875153298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2875153298
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.575881339
Short name T163
Test name
Test status
Simulation time 70940083 ps
CPU time 0.78 seconds
Started Aug 05 05:49:25 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 200144 kb
Host smart-138242b3-4a6d-4f69-a0ce-4bfff0d9b2f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575881339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.575881339
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3348711802
Short name T305
Test name
Test status
Simulation time 1223365330 ps
CPU time 5.37 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 217716 kb
Host smart-7a930f5e-fda3-4b22-af91-372c9e0166a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348711802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3348711802
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.746312077
Short name T207
Test name
Test status
Simulation time 245696839 ps
CPU time 1.1 seconds
Started Aug 05 05:49:24 PM PDT 24
Finished Aug 05 05:49:25 PM PDT 24
Peak memory 217524 kb
Host smart-8de99a02-1bb5-4ccd-ba64-88fab33bfb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746312077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.746312077
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.423219719
Short name T428
Test name
Test status
Simulation time 123697150 ps
CPU time 0.8 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 200116 kb
Host smart-450a4f61-089e-4b42-8c8c-08cbedb412e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423219719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.423219719
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2812612873
Short name T316
Test name
Test status
Simulation time 1138201468 ps
CPU time 5.17 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 200556 kb
Host smart-85c4b805-e540-40c3-a192-2ec85cca8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812612873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2812612873
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3776832984
Short name T145
Test name
Test status
Simulation time 155523115 ps
CPU time 1.16 seconds
Started Aug 05 05:49:26 PM PDT 24
Finished Aug 05 05:49:27 PM PDT 24
Peak memory 200340 kb
Host smart-06e609ab-8b02-4ccd-b435-9f362c9b85df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776832984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3776832984
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.218202348
Short name T405
Test name
Test status
Simulation time 129498839 ps
CPU time 1.18 seconds
Started Aug 05 05:49:23 PM PDT 24
Finished Aug 05 05:49:24 PM PDT 24
Peak memory 200500 kb
Host smart-2f0198c6-af01-4783-9303-ff3fb233cf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218202348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.218202348
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3420592396
Short name T236
Test name
Test status
Simulation time 7933546801 ps
CPU time 30.48 seconds
Started Aug 05 05:49:22 PM PDT 24
Finished Aug 05 05:49:53 PM PDT 24
Peak memory 208808 kb
Host smart-4cf6370c-6817-446e-b07a-eec0631d63b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420592396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3420592396
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3484427229
Short name T246
Test name
Test status
Simulation time 119285735 ps
CPU time 1.58 seconds
Started Aug 05 05:49:20 PM PDT 24
Finished Aug 05 05:49:21 PM PDT 24
Peak memory 200308 kb
Host smart-b5b53ffe-2340-494d-a278-9b3e14b0595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484427229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3484427229
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1537045745
Short name T272
Test name
Test status
Simulation time 141369427 ps
CPU time 1.23 seconds
Started Aug 05 05:49:24 PM PDT 24
Finished Aug 05 05:49:26 PM PDT 24
Peak memory 200476 kb
Host smart-06abbcf3-ef28-4467-8413-8a060565870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537045745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1537045745
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.517282050
Short name T153
Test name
Test status
Simulation time 59949542 ps
CPU time 0.75 seconds
Started Aug 05 05:48:45 PM PDT 24
Finished Aug 05 05:48:46 PM PDT 24
Peak memory 200160 kb
Host smart-63a32f7a-2441-4f4e-b622-1727bed54dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517282050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.517282050
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2703583586
Short name T417
Test name
Test status
Simulation time 1892583673 ps
CPU time 6.78 seconds
Started Aug 05 05:48:26 PM PDT 24
Finished Aug 05 05:48:33 PM PDT 24
Peak memory 221676 kb
Host smart-4ccb5eed-357c-4452-b0be-20fd6e56d86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703583586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2703583586
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3181168457
Short name T38
Test name
Test status
Simulation time 245207711 ps
CPU time 1.04 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:19 PM PDT 24
Peak memory 217476 kb
Host smart-140b1d12-dd38-45df-94de-c4822d552b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181168457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3181168457
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2714875420
Short name T422
Test name
Test status
Simulation time 194539688 ps
CPU time 0.94 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:20 PM PDT 24
Peak memory 200156 kb
Host smart-ca3c2eda-82e1-4451-8910-be66c0b50891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714875420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2714875420
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1108107977
Short name T328
Test name
Test status
Simulation time 893410987 ps
CPU time 4.58 seconds
Started Aug 05 05:48:08 PM PDT 24
Finished Aug 05 05:48:13 PM PDT 24
Peak memory 200568 kb
Host smart-36ab9ac3-adcf-4abb-81ee-31b4a551191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108107977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1108107977
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.416197501
Short name T3
Test name
Test status
Simulation time 150360306 ps
CPU time 1.13 seconds
Started Aug 05 05:48:07 PM PDT 24
Finished Aug 05 05:48:08 PM PDT 24
Peak memory 200376 kb
Host smart-983f6588-2258-40c4-b612-dc9d790bb9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416197501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.416197501
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1698095669
Short name T198
Test name
Test status
Simulation time 120563937 ps
CPU time 1.2 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 200324 kb
Host smart-0443fe41-0d27-4fd1-b323-95800b31d113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698095669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1698095669
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3290389360
Short name T383
Test name
Test status
Simulation time 3158635354 ps
CPU time 14.58 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 200596 kb
Host smart-7fcc8a9f-d84b-4264-b1a1-55faf7cf7f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290389360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3290389360
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.715562252
Short name T84
Test name
Test status
Simulation time 258199860 ps
CPU time 1.76 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 200292 kb
Host smart-13ec0b96-f429-4604-88fb-2fac79bc5be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715562252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.715562252
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2120100942
Short name T374
Test name
Test status
Simulation time 85191586 ps
CPU time 0.86 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 200284 kb
Host smart-094c33f1-dc24-4e45-bd1f-149531da311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120100942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2120100942
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2567488436
Short name T194
Test name
Test status
Simulation time 72498868 ps
CPU time 0.82 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200172 kb
Host smart-8253bfab-ca7b-4190-9539-c7ad5800df6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567488436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2567488436
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3694879883
Short name T530
Test name
Test status
Simulation time 2192669136 ps
CPU time 7.56 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:32 PM PDT 24
Peak memory 221736 kb
Host smart-508ab3a2-e430-407a-875f-5b4aab606a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694879883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3694879883
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.344641595
Short name T442
Test name
Test status
Simulation time 243864671 ps
CPU time 1.15 seconds
Started Aug 05 05:48:24 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 217536 kb
Host smart-68d8ef19-d3e9-4e08-800e-26d018bdc83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344641595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.344641595
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.766695509
Short name T15
Test name
Test status
Simulation time 190949487 ps
CPU time 0.88 seconds
Started Aug 05 05:48:22 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 199412 kb
Host smart-60c34f1e-8984-449c-a74a-a5c87f1597bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766695509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.766695509
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.866158471
Short name T104
Test name
Test status
Simulation time 1875661721 ps
CPU time 6.77 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200520 kb
Host smart-797cec5b-6a44-4079-b3b5-0bc85290a131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866158471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.866158471
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.93485179
Short name T160
Test name
Test status
Simulation time 148739019 ps
CPU time 1.07 seconds
Started Aug 05 05:48:11 PM PDT 24
Finished Aug 05 05:48:12 PM PDT 24
Peak memory 200368 kb
Host smart-6f88d472-3efd-4fc1-9d1b-304c8666a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93485179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.93485179
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3332407569
Short name T134
Test name
Test status
Simulation time 245276995 ps
CPU time 1.53 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 200460 kb
Host smart-9b3e7d13-a2b8-4029-9eb4-e2d44375c8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332407569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3332407569
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.3342646629
Short name T98
Test name
Test status
Simulation time 3332880962 ps
CPU time 15.29 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:38 PM PDT 24
Peak memory 200628 kb
Host smart-038e62c0-eed3-4eda-bf8e-db5259240e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342646629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3342646629
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2644674839
Short name T392
Test name
Test status
Simulation time 143820475 ps
CPU time 1.87 seconds
Started Aug 05 05:48:23 PM PDT 24
Finished Aug 05 05:48:25 PM PDT 24
Peak memory 200136 kb
Host smart-55ca2ec6-8f8c-42c6-8bd5-795c7b1471fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644674839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2644674839
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.525287561
Short name T81
Test name
Test status
Simulation time 141400276 ps
CPU time 1.1 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200352 kb
Host smart-c508566e-0029-46c4-a0d0-316910e36be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525287561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.525287561
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1597081444
Short name T50
Test name
Test status
Simulation time 1888882710 ps
CPU time 7.54 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:33 PM PDT 24
Peak memory 217808 kb
Host smart-7b569c68-eb94-49ca-a065-2fa045de8cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597081444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1597081444
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3183218252
Short name T64
Test name
Test status
Simulation time 244581978 ps
CPU time 1.07 seconds
Started Aug 05 05:48:15 PM PDT 24
Finished Aug 05 05:48:16 PM PDT 24
Peak memory 217412 kb
Host smart-f87f6476-9604-4897-be37-796af71f368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183218252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3183218252
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2766193423
Short name T22
Test name
Test status
Simulation time 90149292 ps
CPU time 0.72 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:18 PM PDT 24
Peak memory 200136 kb
Host smart-e4ee483a-f54e-4290-99b3-165cfe176ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766193423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2766193423
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.510761577
Short name T449
Test name
Test status
Simulation time 2075675846 ps
CPU time 7.33 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:32 PM PDT 24
Peak memory 200560 kb
Host smart-4d8abcc5-ebc3-4ca7-8b6d-0225f5f31c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510761577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.510761577
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2224471638
Short name T473
Test name
Test status
Simulation time 168907924 ps
CPU time 1.15 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:23 PM PDT 24
Peak memory 200360 kb
Host smart-89eb41ec-a88d-472b-b8f5-d1c80e765dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224471638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2224471638
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.81700561
Short name T24
Test name
Test status
Simulation time 126230344 ps
CPU time 1.24 seconds
Started Aug 05 05:48:22 PM PDT 24
Finished Aug 05 05:48:24 PM PDT 24
Peak memory 199648 kb
Host smart-916bdfdf-fbf7-459f-a2aa-c9ab6c78e107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81700561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.81700561
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3154327862
Short name T533
Test name
Test status
Simulation time 7636261342 ps
CPU time 28.52 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:54 PM PDT 24
Peak memory 208824 kb
Host smart-5566f3a2-5e77-4a21-942f-207c3246f8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154327862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3154327862
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1222635943
Short name T82
Test name
Test status
Simulation time 412281733 ps
CPU time 2.33 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 200308 kb
Host smart-43bedf52-dc0f-4e59-b85f-be0fda8de800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222635943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1222635943
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3950252295
Short name T229
Test name
Test status
Simulation time 158736319 ps
CPU time 1.1 seconds
Started Aug 05 05:48:25 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200360 kb
Host smart-1d874814-9808-42cf-96c1-ab3747b6d505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950252295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3950252295
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.473864023
Short name T273
Test name
Test status
Simulation time 71860185 ps
CPU time 0.77 seconds
Started Aug 05 05:48:35 PM PDT 24
Finished Aug 05 05:48:36 PM PDT 24
Peak memory 200168 kb
Host smart-5c99eb79-37c8-4b78-8d86-8f138a8db14e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473864023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.473864023
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1358476112
Short name T29
Test name
Test status
Simulation time 1898666378 ps
CPU time 8.29 seconds
Started Aug 05 05:48:44 PM PDT 24
Finished Aug 05 05:48:52 PM PDT 24
Peak memory 221744 kb
Host smart-07ebcd31-b30a-4e82-98e2-f5fb09124fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358476112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1358476112
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2965686018
Short name T302
Test name
Test status
Simulation time 243831516 ps
CPU time 1.11 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 217516 kb
Host smart-7ab436f3-ecb0-41fe-95cb-85eab38e9c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965686018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2965686018
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1959820830
Short name T17
Test name
Test status
Simulation time 125290717 ps
CPU time 0.78 seconds
Started Aug 05 05:48:39 PM PDT 24
Finished Aug 05 05:48:39 PM PDT 24
Peak memory 200156 kb
Host smart-a65ef2bb-23da-4582-827e-3026e22c4677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959820830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1959820830
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4012282239
Short name T200
Test name
Test status
Simulation time 1656337094 ps
CPU time 7.08 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:26 PM PDT 24
Peak memory 200488 kb
Host smart-ce518854-56ce-4a4d-95ec-2e6ae8a480fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012282239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4012282239
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3143117237
Short name T80
Test name
Test status
Simulation time 101953169 ps
CPU time 0.96 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:22 PM PDT 24
Peak memory 200356 kb
Host smart-a5cc27bd-0894-4a0b-a98b-69447d0ce87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143117237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3143117237
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.607209715
Short name T306
Test name
Test status
Simulation time 255359814 ps
CPU time 1.54 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 200488 kb
Host smart-996fb149-093b-4512-9447-14d3c18bd2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607209715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.607209715
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.317554615
Short name T260
Test name
Test status
Simulation time 7476218021 ps
CPU time 31.71 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:53 PM PDT 24
Peak memory 200620 kb
Host smart-f323ad4e-2595-4d15-9197-6418995c75c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317554615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.317554615
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2874025529
Short name T269
Test name
Test status
Simulation time 265248816 ps
CPU time 1.79 seconds
Started Aug 05 05:48:18 PM PDT 24
Finished Aug 05 05:48:20 PM PDT 24
Peak memory 200300 kb
Host smart-ef38e58c-1f34-4f7d-be99-70ff09048342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874025529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2874025529
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1766573329
Short name T223
Test name
Test status
Simulation time 78986463 ps
CPU time 0.83 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:22 PM PDT 24
Peak memory 200348 kb
Host smart-044d97bd-1415-4394-aee4-3fad94d23f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766573329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1766573329
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1494960210
Short name T192
Test name
Test status
Simulation time 66498622 ps
CPU time 0.74 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:20 PM PDT 24
Peak memory 200152 kb
Host smart-1d7fa26d-4641-4493-90f0-431c97a0727b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494960210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1494960210
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2243001566
Short name T454
Test name
Test status
Simulation time 243481325 ps
CPU time 1.09 seconds
Started Aug 05 05:48:19 PM PDT 24
Finished Aug 05 05:48:20 PM PDT 24
Peak memory 217440 kb
Host smart-6f37d7a8-64ec-4cf7-a305-edc15582b4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243001566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2243001566
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.4261798387
Short name T408
Test name
Test status
Simulation time 172616570 ps
CPU time 0.82 seconds
Started Aug 05 05:48:20 PM PDT 24
Finished Aug 05 05:48:21 PM PDT 24
Peak memory 200148 kb
Host smart-c11a6d90-f26f-4acf-a133-ef587bafa011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261798387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.4261798387
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.201495441
Short name T94
Test name
Test status
Simulation time 1300997967 ps
CPU time 5.56 seconds
Started Aug 05 05:48:22 PM PDT 24
Finished Aug 05 05:48:28 PM PDT 24
Peak memory 200616 kb
Host smart-0f8388f8-4f46-48ae-823b-416dea265109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201495441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.201495441
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3239128387
Short name T144
Test name
Test status
Simulation time 140702031 ps
CPU time 1.12 seconds
Started Aug 05 05:48:21 PM PDT 24
Finished Aug 05 05:48:22 PM PDT 24
Peak memory 200348 kb
Host smart-eac9f95b-51fd-4216-b077-cfba2e8c1689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239128387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3239128387
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2696754622
Short name T411
Test name
Test status
Simulation time 201068963 ps
CPU time 1.42 seconds
Started Aug 05 05:48:33 PM PDT 24
Finished Aug 05 05:48:34 PM PDT 24
Peak memory 200544 kb
Host smart-d6d651f5-0ad3-4bbd-bfdc-f3ec4b8b1dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696754622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2696754622
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3730365461
Short name T481
Test name
Test status
Simulation time 5509822041 ps
CPU time 22.64 seconds
Started Aug 05 05:48:14 PM PDT 24
Finished Aug 05 05:48:37 PM PDT 24
Peak memory 200528 kb
Host smart-3a0b0940-5000-4d6c-b256-9b0a3ca9aba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730365461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3730365461
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4110727187
Short name T250
Test name
Test status
Simulation time 141078060 ps
CPU time 1.87 seconds
Started Aug 05 05:48:15 PM PDT 24
Finished Aug 05 05:48:17 PM PDT 24
Peak memory 200168 kb
Host smart-1a738c67-4ce6-45ac-be26-7a9a61d738da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110727187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4110727187
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.869966557
Short name T285
Test name
Test status
Simulation time 168524856 ps
CPU time 1.3 seconds
Started Aug 05 05:48:42 PM PDT 24
Finished Aug 05 05:48:43 PM PDT 24
Peak memory 200496 kb
Host smart-0fe59b36-1b76-4229-aaa9-f6396b5cd40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869966557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.869966557
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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