Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8488

1

T1

36

T5

19

T6

158

auto[1]

11243

1

T1

27

T3

4

T5

82

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6075	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6562	1			T1	14		T2	1		T3	2
reset_info_cp[2]	3188	1			T1	12		T3	1		T5	19
reset_info_cp[4]	3947	1			T1	15		T3	1		T5	13
reset_info_cp[8]	133	1			T5	1		T6	1		T13	1
reset_info_cp[16]	124	1			T3	1		T27	1		T89	3
reset_info_cp[32]	112	1			T6	3		T16	2		T27	1
reset_info_cp[64]	102	1			T1	1		T5	1		T6	2
reset_info_cp[128]	108	1			T1	1		T5	1		T10	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3166	1			T1	6		T5	19		T6	55
reset_info_cp[1]	auto[1]	2776	1			T1	7		T3	1		T5	7
reset_info_cp[2]	auto[0]	1037	1			T1	8		T6	22		T29	4
reset_info_cp[2]	auto[1]	2151	1			T1	4		T3	1		T5	19
reset_info_cp[4]	auto[0]	1457	1			T1	5		T6	34		T29	8
reset_info_cp[4]	auto[1]	2490	1			T1	10		T3	1		T5	13
reset_info_cp[8]	auto[0]	63	1			T27	1		T33	2		T91	1
reset_info_cp[8]	auto[1]	70	1			T5	1		T6	1		T13	1
reset_info_cp[16]	auto[0]	49	1			T27	1		T89	1		T93	1
reset_info_cp[16]	auto[1]	75	1			T3	1		T89	2		T90	1
reset_info_cp[32]	auto[0]	43	1			T16	2		T27	1		T102	1
reset_info_cp[32]	auto[1]	69	1			T6	3		T89	1		T91	1
reset_info_cp[64]	auto[0]	43	1			T1	1		T10	1		T89	1
reset_info_cp[64]	auto[1]	59	1			T5	1		T6	2		T56	1
reset_info_cp[128]	auto[0]	45	1			T1	1		T10	1		T33	1
reset_info_cp[128]	auto[1]	63	1			T5	1		T32	1		T89	2