Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T540 /workspace/coverage/default/16.rstmgr_sw_rst.4285183708 Aug 06 07:47:09 PM PDT 24 Aug 06 07:47:11 PM PDT 24 266041526 ps
T541 /workspace/coverage/default/15.rstmgr_sw_rst.3097862035 Aug 06 07:47:06 PM PDT 24 Aug 06 07:47:09 PM PDT 24 444614949 ps
T542 /workspace/coverage/default/28.rstmgr_stress_all.2435552367 Aug 06 07:47:25 PM PDT 24 Aug 06 07:48:04 PM PDT 24 10752952429 ps
T543 /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1609566174 Aug 06 07:47:41 PM PDT 24 Aug 06 07:47:50 PM PDT 24 2341128301 ps
T78 /workspace/coverage/default/1.rstmgr_sec_cm.210869672 Aug 06 07:46:28 PM PDT 24 Aug 06 07:46:53 PM PDT 24 16743210563 ps
T64 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2511872914 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:50 PM PDT 24 491661648 ps
T65 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.655734438 Aug 06 07:25:50 PM PDT 24 Aug 06 07:25:51 PM PDT 24 168151673 ps
T66 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2346019016 Aug 06 07:26:57 PM PDT 24 Aug 06 07:26:58 PM PDT 24 135778669 ps
T67 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4168323881 Aug 06 07:25:58 PM PDT 24 Aug 06 07:26:00 PM PDT 24 178408921 ps
T68 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1547757409 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:36 PM PDT 24 138413286 ps
T111 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.491453179 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:37 PM PDT 24 125730591 ps
T69 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3298911616 Aug 06 07:26:15 PM PDT 24 Aug 06 07:26:16 PM PDT 24 191999541 ps
T70 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2257112258 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:00 PM PDT 24 183278373 ps
T112 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3195992965 Aug 06 07:26:57 PM PDT 24 Aug 06 07:26:58 PM PDT 24 64157125 ps
T113 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.620353626 Aug 06 07:26:17 PM PDT 24 Aug 06 07:26:19 PM PDT 24 131997759 ps
T114 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4169766633 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:01 PM PDT 24 155361740 ps
T115 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3359883771 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:45 PM PDT 24 119900029 ps
T71 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2757971566 Aug 06 07:26:37 PM PDT 24 Aug 06 07:26:40 PM PDT 24 823120508 ps
T544 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1822272873 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:45 PM PDT 24 67204646 ps
T72 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.645406451 Aug 06 07:25:57 PM PDT 24 Aug 06 07:26:00 PM PDT 24 159150572 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3431211509 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:00 PM PDT 24 136076731 ps
T94 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2162788720 Aug 06 07:26:17 PM PDT 24 Aug 06 07:26:19 PM PDT 24 175913645 ps
T95 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2605669497 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:36 PM PDT 24 135816376 ps
T116 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1500859155 Aug 06 07:26:37 PM PDT 24 Aug 06 07:26:38 PM PDT 24 68066527 ps
T119 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2145955016 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:18 PM PDT 24 502944166 ps
T96 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2817178714 Aug 06 07:26:35 PM PDT 24 Aug 06 07:26:36 PM PDT 24 99830953 ps
T98 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.624731542 Aug 06 07:25:45 PM PDT 24 Aug 06 07:25:47 PM PDT 24 484404468 ps
T97 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1500858549 Aug 06 07:27:00 PM PDT 24 Aug 06 07:27:02 PM PDT 24 188691957 ps
T125 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1491579446 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:00 PM PDT 24 194617573 ps
T117 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2815662364 Aug 06 07:25:58 PM PDT 24 Aug 06 07:26:00 PM PDT 24 279110620 ps
T118 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2549644235 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:36 PM PDT 24 193397556 ps
T128 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3138726783 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:36 PM PDT 24 435527046 ps
T123 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2898420373 Aug 06 07:26:17 PM PDT 24 Aug 06 07:26:20 PM PDT 24 973532730 ps
T546 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2542433347 Aug 06 07:26:55 PM PDT 24 Aug 06 07:26:57 PM PDT 24 215832970 ps
T547 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1172294230 Aug 06 07:25:45 PM PDT 24 Aug 06 07:25:47 PM PDT 24 211537659 ps
T548 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.608178908 Aug 06 07:26:35 PM PDT 24 Aug 06 07:26:36 PM PDT 24 284149765 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.580913972 Aug 06 07:26:18 PM PDT 24 Aug 06 07:26:19 PM PDT 24 57991320 ps
T550 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4085113622 Aug 06 07:26:37 PM PDT 24 Aug 06 07:26:38 PM PDT 24 61700581 ps
T120 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3091174766 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:38 PM PDT 24 199324651 ps
T551 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2883423290 Aug 06 07:26:55 PM PDT 24 Aug 06 07:26:56 PM PDT 24 157775864 ps
T552 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2310396916 Aug 06 07:26:55 PM PDT 24 Aug 06 07:26:56 PM PDT 24 189204340 ps
T146 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3696569542 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:01 PM PDT 24 430440982 ps
T553 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3039002735 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:36 PM PDT 24 209578263 ps
T554 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2634193765 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:20 PM PDT 24 578199315 ps
T555 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2551206430 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:00 PM PDT 24 128023528 ps
T556 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2370875989 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:38 PM PDT 24 194484328 ps
T127 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2861362419 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:18 PM PDT 24 194247718 ps
T557 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2694534503 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:37 PM PDT 24 91192435 ps
T558 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.965488858 Aug 06 07:26:15 PM PDT 24 Aug 06 07:26:18 PM PDT 24 879291870 ps
T121 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.823310493 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:39 PM PDT 24 823697030 ps
T559 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3362443851 Aug 06 07:26:55 PM PDT 24 Aug 06 07:26:57 PM PDT 24 197064574 ps
T560 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2102981376 Aug 06 07:26:17 PM PDT 24 Aug 06 07:26:19 PM PDT 24 426041382 ps
T561 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2916828847 Aug 06 07:26:55 PM PDT 24 Aug 06 07:26:55 PM PDT 24 72234284 ps
T562 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3252737564 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:00 PM PDT 24 81324137 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2230193091 Aug 06 07:25:28 PM PDT 24 Aug 06 07:25:31 PM PDT 24 212154505 ps
T564 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2980707521 Aug 06 07:26:55 PM PDT 24 Aug 06 07:26:57 PM PDT 24 474235148 ps
T565 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3845536887 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:17 PM PDT 24 105410244 ps
T126 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1254257623 Aug 06 07:26:35 PM PDT 24 Aug 06 07:26:37 PM PDT 24 329485767 ps
T566 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2650387117 Aug 06 07:25:58 PM PDT 24 Aug 06 07:26:03 PM PDT 24 813652395 ps
T567 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1304233399 Aug 06 07:26:54 PM PDT 24 Aug 06 07:26:55 PM PDT 24 119070163 ps
T568 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1576111040 Aug 06 07:26:02 PM PDT 24 Aug 06 07:26:04 PM PDT 24 259278946 ps
T569 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2699501461 Aug 06 07:26:35 PM PDT 24 Aug 06 07:26:36 PM PDT 24 107574024 ps
T570 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2860263712 Aug 06 07:26:03 PM PDT 24 Aug 06 07:26:04 PM PDT 24 54902320 ps
T571 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2743895160 Aug 06 07:25:45 PM PDT 24 Aug 06 07:25:46 PM PDT 24 251359915 ps
T572 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1883630530 Aug 06 07:26:17 PM PDT 24 Aug 06 07:26:21 PM PDT 24 472081670 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2331956088 Aug 06 07:25:33 PM PDT 24 Aug 06 07:25:34 PM PDT 24 148327101 ps
T122 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2301773770 Aug 06 07:26:17 PM PDT 24 Aug 06 07:26:20 PM PDT 24 793659919 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4254775326 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:00 PM PDT 24 181402415 ps
T575 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3960560904 Aug 06 07:26:15 PM PDT 24 Aug 06 07:26:16 PM PDT 24 176785027 ps
T576 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3004305983 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:53 PM PDT 24 1560581633 ps
T577 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3399256989 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:45 PM PDT 24 207201725 ps
T578 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1057962814 Aug 06 07:26:56 PM PDT 24 Aug 06 07:26:58 PM PDT 24 113535947 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3024926020 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:36 PM PDT 24 161110580 ps
T580 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1250224817 Aug 06 07:26:37 PM PDT 24 Aug 06 07:26:38 PM PDT 24 131453830 ps
T581 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1390481115 Aug 06 07:25:50 PM PDT 24 Aug 06 07:25:51 PM PDT 24 270203995 ps
T582 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3652103024 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:39 PM PDT 24 341572782 ps
T583 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1013592842 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:37 PM PDT 24 78246196 ps
T584 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2637198341 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:19 PM PDT 24 380733473 ps
T585 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3301929065 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:36 PM PDT 24 416945808 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3515968067 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:01 PM PDT 24 166237975 ps
T587 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3846788711 Aug 06 07:25:43 PM PDT 24 Aug 06 07:25:48 PM PDT 24 799996003 ps
T588 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1109235606 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:36 PM PDT 24 465608983 ps
T589 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.975033218 Aug 06 07:26:56 PM PDT 24 Aug 06 07:26:58 PM PDT 24 502875500 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2471630652 Aug 06 07:25:47 PM PDT 24 Aug 06 07:25:48 PM PDT 24 127032409 ps
T591 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1362160741 Aug 06 07:25:27 PM PDT 24 Aug 06 07:25:28 PM PDT 24 58611730 ps
T124 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2300445471 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:47 PM PDT 24 937413299 ps
T592 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3550820093 Aug 06 07:25:57 PM PDT 24 Aug 06 07:26:00 PM PDT 24 175899768 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2520370913 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:46 PM PDT 24 201290969 ps
T594 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1000277280 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:01 PM PDT 24 479196653 ps
T595 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1493435687 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:18 PM PDT 24 250490087 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.704393044 Aug 06 07:25:57 PM PDT 24 Aug 06 07:25:58 PM PDT 24 94741802 ps
T597 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1117926981 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:17 PM PDT 24 75570690 ps
T598 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.212378184 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:01 PM PDT 24 238535387 ps
T599 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.290507352 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:17 PM PDT 24 68772938 ps
T600 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.370792750 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:38 PM PDT 24 203285037 ps
T601 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4284210180 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:05 PM PDT 24 1023126045 ps
T602 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2327278077 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:46 PM PDT 24 180038182 ps
T603 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.535572185 Aug 06 07:26:56 PM PDT 24 Aug 06 07:26:57 PM PDT 24 55072486 ps
T604 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1446228885 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:45 PM PDT 24 150361981 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3943077180 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:47 PM PDT 24 194734690 ps
T606 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1094976623 Aug 06 07:25:58 PM PDT 24 Aug 06 07:26:00 PM PDT 24 119201056 ps
T607 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1005838349 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:17 PM PDT 24 75661572 ps
T147 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1612915744 Aug 06 07:26:04 PM PDT 24 Aug 06 07:26:07 PM PDT 24 789916215 ps
T144 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3242180281 Aug 06 07:26:03 PM PDT 24 Aug 06 07:26:05 PM PDT 24 629577630 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.708993548 Aug 06 07:25:57 PM PDT 24 Aug 06 07:26:00 PM PDT 24 357746609 ps
T609 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2409928213 Aug 06 07:26:33 PM PDT 24 Aug 06 07:26:34 PM PDT 24 82788483 ps
T610 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.744268118 Aug 06 07:26:36 PM PDT 24 Aug 06 07:26:37 PM PDT 24 64370245 ps
T611 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3768181583 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:45 PM PDT 24 80374183 ps
T612 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.896865566 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:37 PM PDT 24 760908482 ps
T613 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3272893788 Aug 06 07:26:34 PM PDT 24 Aug 06 07:26:35 PM PDT 24 139648444 ps
T614 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.490745917 Aug 06 07:26:16 PM PDT 24 Aug 06 07:26:17 PM PDT 24 75773513 ps
T615 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.195722140 Aug 06 07:26:04 PM PDT 24 Aug 06 07:26:04 PM PDT 24 58701235 ps
T616 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1672730553 Aug 06 07:25:46 PM PDT 24 Aug 06 07:25:47 PM PDT 24 119980690 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1146789535 Aug 06 07:25:46 PM PDT 24 Aug 06 07:25:47 PM PDT 24 99623268 ps
T145 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2431682441 Aug 06 07:25:33 PM PDT 24 Aug 06 07:25:35 PM PDT 24 501204915 ps
T100 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3187762537 Aug 06 07:26:15 PM PDT 24 Aug 06 07:26:16 PM PDT 24 60120741 ps
T618 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.715885056 Aug 06 07:25:59 PM PDT 24 Aug 06 07:26:00 PM PDT 24 91539560 ps
T619 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1813952215 Aug 06 07:26:35 PM PDT 24 Aug 06 07:26:36 PM PDT 24 236778080 ps
T620 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.760531268 Aug 06 07:26:17 PM PDT 24 Aug 06 07:26:19 PM PDT 24 243064422 ps
T101 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1352367630 Aug 06 07:25:44 PM PDT 24 Aug 06 07:25:46 PM PDT 24 152441874 ps

Test location /workspace/coverage/default/49.rstmgr_stress_all.138141380
Short name T6
Test name
Test status
Simulation time 5342155158 ps
CPU time 25.74 seconds
Started Aug 06 07:48:15 PM PDT 24
Finished Aug 06 07:48:40 PM PDT 24
Peak memory 200624 kb
Host smart-0a111b74-5057-4196-a8f1-0f2339e176bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138141380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.138141380
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1865972821
Short name T7
Test name
Test status
Simulation time 483287901 ps
CPU time 2.7 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200296 kb
Host smart-b3606c58-2077-4d59-a21c-23b8d26c59b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865972821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1865972821
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4168323881
Short name T67
Test name
Test status
Simulation time 178408921 ps
CPU time 1.8 seconds
Started Aug 06 07:25:58 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 208440 kb
Host smart-748c62ef-83a1-42ad-b2c8-1015507b2430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168323881 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4168323881
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.669450839
Short name T75
Test name
Test status
Simulation time 8416524645 ps
CPU time 13.26 seconds
Started Aug 06 07:46:29 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 217280 kb
Host smart-ddaf5a4f-2221-4e49-8fd0-7106f6e469bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669450839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.669450839
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1970248336
Short name T5
Test name
Test status
Simulation time 1221504319 ps
CPU time 6.08 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:18 PM PDT 24
Peak memory 217472 kb
Host smart-1105f297-45b1-4e89-8ea6-0b1508d745c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970248336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1970248336
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.624731542
Short name T98
Test name
Test status
Simulation time 484404468 ps
CPU time 2.15 seconds
Started Aug 06 07:25:45 PM PDT 24
Finished Aug 06 07:25:47 PM PDT 24
Peak memory 200196 kb
Host smart-7ae10431-ea9c-4b3f-94b8-61b6096118f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624731542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
624731542
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1392914451
Short name T93
Test name
Test status
Simulation time 6055444244 ps
CPU time 23.17 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:47:06 PM PDT 24
Peak memory 200596 kb
Host smart-eeb89eec-bd2a-4b35-9654-a934b7722d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392914451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1392914451
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2078373489
Short name T158
Test name
Test status
Simulation time 75573033 ps
CPU time 0.8 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 200176 kb
Host smart-104281e2-5ca6-4095-a14e-edc0890631d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078373489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2078373489
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4233425309
Short name T160
Test name
Test status
Simulation time 139579084 ps
CPU time 1.08 seconds
Started Aug 06 07:46:39 PM PDT 24
Finished Aug 06 07:46:40 PM PDT 24
Peak memory 200360 kb
Host smart-3ed794d3-f3c1-4688-bdd2-d5975c92c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233425309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4233425309
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2882035430
Short name T153
Test name
Test status
Simulation time 166406409 ps
CPU time 1.25 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 200228 kb
Host smart-980488c5-8447-4c9f-88dd-ec283b2c9bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882035430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2882035430
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2262875365
Short name T36
Test name
Test status
Simulation time 1891799224 ps
CPU time 6.87 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 217424 kb
Host smart-8f3b6cd0-b531-4370-9f6b-1d658a79cac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262875365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2262875365
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2230193091
Short name T563
Test name
Test status
Simulation time 212154505 ps
CPU time 3.2 seconds
Started Aug 06 07:25:28 PM PDT 24
Finished Aug 06 07:25:31 PM PDT 24
Peak memory 208324 kb
Host smart-4df682de-99c5-419c-9d4b-7b86cdea4b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230193091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2230193091
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3359883771
Short name T115
Test name
Test status
Simulation time 119900029 ps
CPU time 1.09 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:45 PM PDT 24
Peak memory 200132 kb
Host smart-ec33cf30-4ab0-4194-bb3f-155700d85c6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359883771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3359883771
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.281640347
Short name T57
Test name
Test status
Simulation time 1213504390 ps
CPU time 6.18 seconds
Started Aug 06 07:47:14 PM PDT 24
Finished Aug 06 07:47:21 PM PDT 24
Peak memory 221636 kb
Host smart-288baac1-d7cd-4a9a-ab56-2380140e2e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281640347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.281640347
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.3809163073
Short name T107
Test name
Test status
Simulation time 3922529679 ps
CPU time 13.5 seconds
Started Aug 06 07:46:47 PM PDT 24
Finished Aug 06 07:47:00 PM PDT 24
Peak memory 200644 kb
Host smart-eabb0b87-6088-4784-b919-fb8c20a248b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809163073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.3809163073
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2431682441
Short name T145
Test name
Test status
Simulation time 501204915 ps
CPU time 1.95 seconds
Started Aug 06 07:25:33 PM PDT 24
Finished Aug 06 07:25:35 PM PDT 24
Peak memory 200144 kb
Host smart-4c6737d5-10af-4f8a-bb30-9ba521f72a67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431682441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2431682441
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2301773770
Short name T122
Test name
Test status
Simulation time 793659919 ps
CPU time 2.89 seconds
Started Aug 06 07:26:17 PM PDT 24
Finished Aug 06 07:26:20 PM PDT 24
Peak memory 200204 kb
Host smart-93b16e74-f782-4c0e-bfa1-3544b5fd5c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301773770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2301773770
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1822080089
Short name T26
Test name
Test status
Simulation time 204199071 ps
CPU time 0.9 seconds
Started Aug 06 07:47:04 PM PDT 24
Finished Aug 06 07:47:05 PM PDT 24
Peak memory 200040 kb
Host smart-70d91f03-7819-4328-af6c-90b28974dcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822080089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1822080089
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3528187204
Short name T14
Test name
Test status
Simulation time 2363472887 ps
CPU time 8.4 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 217872 kb
Host smart-1cc43551-623d-417f-8dfe-df68f65062df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528187204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3528187204
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3943077180
Short name T605
Test name
Test status
Simulation time 194734690 ps
CPU time 2.91 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:47 PM PDT 24
Peak memory 208328 kb
Host smart-ac066fdd-a229-4e6a-ad2c-9260bd94db16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943077180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3943077180
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.823310493
Short name T121
Test name
Test status
Simulation time 823697030 ps
CPU time 2.74 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:39 PM PDT 24
Peak memory 200256 kb
Host smart-bfa000f2-ed2c-42b6-9f68-3298737fbb5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823310493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.823310493
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2300445471
Short name T124
Test name
Test status
Simulation time 937413299 ps
CPU time 3.4 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:47 PM PDT 24
Peak memory 200264 kb
Host smart-bbdd5409-158a-4268-8de9-b93b77b5fd39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300445471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2300445471
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1172294230
Short name T547
Test name
Test status
Simulation time 211537659 ps
CPU time 1.6 seconds
Started Aug 06 07:25:45 PM PDT 24
Finished Aug 06 07:25:47 PM PDT 24
Peak memory 200300 kb
Host smart-20654bd7-a3b7-474d-a99c-9a4ed2249f48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172294230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
172294230
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3846788711
Short name T587
Test name
Test status
Simulation time 799996003 ps
CPU time 4.77 seconds
Started Aug 06 07:25:43 PM PDT 24
Finished Aug 06 07:25:48 PM PDT 24
Peak memory 208336 kb
Host smart-cd0b42cc-b568-4309-9e46-e075bd770414
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846788711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
846788711
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2331956088
Short name T573
Test name
Test status
Simulation time 148327101 ps
CPU time 1.02 seconds
Started Aug 06 07:25:33 PM PDT 24
Finished Aug 06 07:25:34 PM PDT 24
Peak memory 200008 kb
Host smart-8d942dec-c301-4e62-af78-6a5027e8b3e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331956088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
331956088
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2327278077
Short name T602
Test name
Test status
Simulation time 180038182 ps
CPU time 1.17 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:46 PM PDT 24
Peak memory 208396 kb
Host smart-b898aca5-7020-4e85-8ec8-a4e397f71f58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327278077 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.2327278077
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1362160741
Short name T591
Test name
Test status
Simulation time 58611730 ps
CPU time 0.74 seconds
Started Aug 06 07:25:27 PM PDT 24
Finished Aug 06 07:25:28 PM PDT 24
Peak memory 199980 kb
Host smart-fa377c79-89c9-4e48-bc14-2479c3955435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362160741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1362160741
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1352367630
Short name T101
Test name
Test status
Simulation time 152441874 ps
CPU time 2.03 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:46 PM PDT 24
Peak memory 200128 kb
Host smart-6cec09da-8868-4f48-8ca5-1c2def9b1213
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352367630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
352367630
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2511872914
Short name T64
Test name
Test status
Simulation time 491661648 ps
CPU time 5.44 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:50 PM PDT 24
Peak memory 200088 kb
Host smart-51fa35a8-7e62-494c-8455-aeb8094d3c20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511872914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
511872914
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1446228885
Short name T604
Test name
Test status
Simulation time 150361981 ps
CPU time 0.98 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:45 PM PDT 24
Peak memory 200028 kb
Host smart-a825b859-94df-4d8e-9f70-3ac925491b6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446228885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
446228885
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3399256989
Short name T577
Test name
Test status
Simulation time 207201725 ps
CPU time 1.39 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:45 PM PDT 24
Peak memory 208364 kb
Host smart-86f6fb51-6e4d-49e6-bce1-0440f06ce84e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399256989 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3399256989
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1822272873
Short name T544
Test name
Test status
Simulation time 67204646 ps
CPU time 0.8 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:45 PM PDT 24
Peak memory 199964 kb
Host smart-0d2718ce-4a57-41d5-a723-bdb2f11d6fcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822272873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1822272873
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.655734438
Short name T65
Test name
Test status
Simulation time 168151673 ps
CPU time 1.37 seconds
Started Aug 06 07:25:50 PM PDT 24
Finished Aug 06 07:25:51 PM PDT 24
Peak memory 200156 kb
Host smart-2a699eb5-7725-458d-a08a-d8b1b39d000e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655734438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.655734438
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3298911616
Short name T69
Test name
Test status
Simulation time 191999541 ps
CPU time 1.17 seconds
Started Aug 06 07:26:15 PM PDT 24
Finished Aug 06 07:26:16 PM PDT 24
Peak memory 200156 kb
Host smart-374a08b2-8d53-451c-9b9c-d419cb983f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298911616 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3298911616
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.490745917
Short name T614
Test name
Test status
Simulation time 75773513 ps
CPU time 0.79 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:17 PM PDT 24
Peak memory 200008 kb
Host smart-57eee5b8-e537-4a08-be2c-28fb48a598c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490745917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.490745917
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1117926981
Short name T597
Test name
Test status
Simulation time 75570690 ps
CPU time 0.95 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:17 PM PDT 24
Peak memory 200112 kb
Host smart-68ce668f-860a-44e0-bbfa-e81bad5fbf16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117926981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1117926981
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2861362419
Short name T127
Test name
Test status
Simulation time 194247718 ps
CPU time 1.54 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:18 PM PDT 24
Peak memory 210228 kb
Host smart-541d825e-0652-4eca-9634-4b7775d84395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861362419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2861362419
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3272893788
Short name T613
Test name
Test status
Simulation time 139648444 ps
CPU time 1.12 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:35 PM PDT 24
Peak memory 208500 kb
Host smart-03951f22-16dc-4477-9f62-60d979ce43e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272893788 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3272893788
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.580913972
Short name T549
Test name
Test status
Simulation time 57991320 ps
CPU time 0.87 seconds
Started Aug 06 07:26:18 PM PDT 24
Finished Aug 06 07:26:19 PM PDT 24
Peak memory 200064 kb
Host smart-324fb5d4-f60b-457a-aa46-103f97de1bdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580913972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.580913972
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1813952215
Short name T619
Test name
Test status
Simulation time 236778080 ps
CPU time 1.55 seconds
Started Aug 06 07:26:35 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200148 kb
Host smart-ec4f446f-90dd-4153-841b-6e8322a68287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813952215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1813952215
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1883630530
Short name T572
Test name
Test status
Simulation time 472081670 ps
CPU time 3.68 seconds
Started Aug 06 07:26:17 PM PDT 24
Finished Aug 06 07:26:21 PM PDT 24
Peak memory 208292 kb
Host smart-00d38fd4-b575-4691-a603-e7ecc101d857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883630530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1883630530
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2102981376
Short name T560
Test name
Test status
Simulation time 426041382 ps
CPU time 2.04 seconds
Started Aug 06 07:26:17 PM PDT 24
Finished Aug 06 07:26:19 PM PDT 24
Peak memory 200204 kb
Host smart-be7f586e-6c7f-4dff-b534-800d735e8dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102981376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2102981376
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.370792750
Short name T600
Test name
Test status
Simulation time 203285037 ps
CPU time 1.45 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:38 PM PDT 24
Peak memory 208436 kb
Host smart-bf6bb070-93d0-4f12-8226-8490f320cd9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370792750 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.370792750
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.744268118
Short name T610
Test name
Test status
Simulation time 64370245 ps
CPU time 0.82 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:37 PM PDT 24
Peak memory 200068 kb
Host smart-9b706626-53a5-4318-966b-d1452025023a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744268118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.744268118
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3039002735
Short name T553
Test name
Test status
Simulation time 209578263 ps
CPU time 1.58 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200188 kb
Host smart-ec15ab32-a39b-41cc-8e5e-81f2d7949f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039002735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3039002735
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1250224817
Short name T580
Test name
Test status
Simulation time 131453830 ps
CPU time 1.75 seconds
Started Aug 06 07:26:37 PM PDT 24
Finished Aug 06 07:26:38 PM PDT 24
Peak memory 208328 kb
Host smart-505bf6b1-95a6-441c-9f58-11f38b29020e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250224817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1250224817
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2757971566
Short name T71
Test name
Test status
Simulation time 823120508 ps
CPU time 2.86 seconds
Started Aug 06 07:26:37 PM PDT 24
Finished Aug 06 07:26:40 PM PDT 24
Peak memory 200188 kb
Host smart-f0790ccd-e7ce-4dfa-9f54-90dac6ce8079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757971566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2757971566
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2370875989
Short name T556
Test name
Test status
Simulation time 194484328 ps
CPU time 1.26 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:38 PM PDT 24
Peak memory 200144 kb
Host smart-f4c3f358-e1b4-480e-ab8d-879c3d0953bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370875989 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2370875989
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1500859155
Short name T116
Test name
Test status
Simulation time 68066527 ps
CPU time 0.8 seconds
Started Aug 06 07:26:37 PM PDT 24
Finished Aug 06 07:26:38 PM PDT 24
Peak memory 199716 kb
Host smart-3b057d2c-9b00-4143-8cd2-80db8d9d7296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500859155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1500859155
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.491453179
Short name T111
Test name
Test status
Simulation time 125730591 ps
CPU time 1.05 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:37 PM PDT 24
Peak memory 200056 kb
Host smart-93af7f21-a2be-4d4b-94cd-2571aae117f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491453179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.491453179
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3652103024
Short name T582
Test name
Test status
Simulation time 341572782 ps
CPU time 2.35 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:39 PM PDT 24
Peak memory 208340 kb
Host smart-b5aa73a0-4a7f-4786-a06c-e466bf766753
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652103024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3652103024
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3301929065
Short name T585
Test name
Test status
Simulation time 416945808 ps
CPU time 1.76 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200204 kb
Host smart-57937dcb-332f-4d89-8b29-a2f09bc2006e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301929065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3301929065
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2817178714
Short name T96
Test name
Test status
Simulation time 99830953 ps
CPU time 0.94 seconds
Started Aug 06 07:26:35 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200352 kb
Host smart-130dfe85-4f3c-4063-8997-13e3f35c4ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817178714 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2817178714
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2694534503
Short name T557
Test name
Test status
Simulation time 91192435 ps
CPU time 0.87 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:37 PM PDT 24
Peak memory 200040 kb
Host smart-fd55cf35-a2c6-4ee2-9886-90a6d3182614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694534503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2694534503
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1013592842
Short name T583
Test name
Test status
Simulation time 78246196 ps
CPU time 0.97 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:37 PM PDT 24
Peak memory 200132 kb
Host smart-4abb30a1-d1ad-4833-8302-a3dcc686e4e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013592842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1013592842
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.1254257623
Short name T126
Test name
Test status
Simulation time 329485767 ps
CPU time 2.44 seconds
Started Aug 06 07:26:35 PM PDT 24
Finished Aug 06 07:26:37 PM PDT 24
Peak memory 208292 kb
Host smart-afa81808-9895-4230-a908-e76b5a43125e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254257623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1254257623
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3138726783
Short name T128
Test name
Test status
Simulation time 435527046 ps
CPU time 1.83 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200140 kb
Host smart-e2735409-0f3c-4b09-a22a-54e8a783422d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138726783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3138726783
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1547757409
Short name T68
Test name
Test status
Simulation time 138413286 ps
CPU time 1.07 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 208428 kb
Host smart-c4707830-6113-4194-b0f1-91452f9807fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547757409 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.1547757409
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4085113622
Short name T550
Test name
Test status
Simulation time 61700581 ps
CPU time 0.78 seconds
Started Aug 06 07:26:37 PM PDT 24
Finished Aug 06 07:26:38 PM PDT 24
Peak memory 199788 kb
Host smart-115295ab-bf42-48ba-a1a5-361c146315cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085113622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.4085113622
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.608178908
Short name T548
Test name
Test status
Simulation time 284149765 ps
CPU time 1.54 seconds
Started Aug 06 07:26:35 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200188 kb
Host smart-1f57ee46-c482-4451-b439-66e93a7c2b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608178908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sa
me_csr_outstanding.608178908
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2605669497
Short name T95
Test name
Test status
Simulation time 135816376 ps
CPU time 1.93 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 208336 kb
Host smart-c7387d18-070c-4617-b228-ab2f4781b1d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605669497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2605669497
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2699501461
Short name T569
Test name
Test status
Simulation time 107574024 ps
CPU time 1 seconds
Started Aug 06 07:26:35 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200200 kb
Host smart-463952fe-1584-4b48-9b4d-a00b52d645e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699501461 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2699501461
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2409928213
Short name T609
Test name
Test status
Simulation time 82788483 ps
CPU time 0.86 seconds
Started Aug 06 07:26:33 PM PDT 24
Finished Aug 06 07:26:34 PM PDT 24
Peak memory 199976 kb
Host smart-3ed03ff2-9bee-4052-ad80-4376d6dac4bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409928213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2409928213
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2549644235
Short name T118
Test name
Test status
Simulation time 193397556 ps
CPU time 1.58 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200132 kb
Host smart-7f95f879-4033-484e-b69f-70b562bfd568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549644235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2549644235
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3091174766
Short name T120
Test name
Test status
Simulation time 199324651 ps
CPU time 2.72 seconds
Started Aug 06 07:26:36 PM PDT 24
Finished Aug 06 07:26:38 PM PDT 24
Peak memory 208320 kb
Host smart-23e47586-0155-412a-ad97-45356d3302f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091174766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3091174766
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1109235606
Short name T588
Test name
Test status
Simulation time 465608983 ps
CPU time 1.82 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 200120 kb
Host smart-08e44c53-551a-4259-84d0-a4725f782031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109235606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1109235606
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3362443851
Short name T559
Test name
Test status
Simulation time 197064574 ps
CPU time 1.27 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 208396 kb
Host smart-d97e7b0e-7b84-467f-91ac-7c25019c06e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362443851 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3362443851
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.535572185
Short name T603
Test name
Test status
Simulation time 55072486 ps
CPU time 0.77 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 199976 kb
Host smart-ea5b5f45-fa56-4b3e-a4cd-c19f1cabace8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535572185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.535572185
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2883423290
Short name T551
Test name
Test status
Simulation time 157775864 ps
CPU time 1.15 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 200072 kb
Host smart-da795368-a664-4b46-9a4a-ce9bdd6f6dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883423290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2883423290
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3024926020
Short name T579
Test name
Test status
Simulation time 161110580 ps
CPU time 1.48 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:36 PM PDT 24
Peak memory 216180 kb
Host smart-59591c15-fe14-47b4-89b8-bbbb0722d1c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024926020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3024926020
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.896865566
Short name T612
Test name
Test status
Simulation time 760908482 ps
CPU time 2.85 seconds
Started Aug 06 07:26:34 PM PDT 24
Finished Aug 06 07:26:37 PM PDT 24
Peak memory 200188 kb
Host smart-89eb634a-54a4-4938-8069-8314c2510aba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896865566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.896865566
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2542433347
Short name T546
Test name
Test status
Simulation time 215832970 ps
CPU time 1.46 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 208352 kb
Host smart-9e13e500-db09-4cd4-af7d-03817bb09393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542433347 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2542433347
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3195992965
Short name T112
Test name
Test status
Simulation time 64157125 ps
CPU time 0.8 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 200060 kb
Host smart-edaa850d-9117-4ddb-b831-25db4465b734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195992965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3195992965
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1304233399
Short name T567
Test name
Test status
Simulation time 119070163 ps
CPU time 1.03 seconds
Started Aug 06 07:26:54 PM PDT 24
Finished Aug 06 07:26:55 PM PDT 24
Peak memory 200080 kb
Host smart-a8476a74-1ffe-4cb5-a2d8-942176da7e56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304233399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1304233399
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1500858549
Short name T97
Test name
Test status
Simulation time 188691957 ps
CPU time 1.66 seconds
Started Aug 06 07:27:00 PM PDT 24
Finished Aug 06 07:27:02 PM PDT 24
Peak memory 208364 kb
Host smart-1cb182d6-ad54-4f5e-a94b-18a1774377a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500858549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1500858549
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.975033218
Short name T589
Test name
Test status
Simulation time 502875500 ps
CPU time 2 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 200192 kb
Host smart-a101e0db-6de5-48c5-b29a-65c9a99138a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975033218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.975033218
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2310396916
Short name T552
Test name
Test status
Simulation time 189204340 ps
CPU time 1.2 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:56 PM PDT 24
Peak memory 208340 kb
Host smart-50ea73d4-d8e6-43d0-8c16-960a039eb853
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310396916 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2310396916
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2916828847
Short name T561
Test name
Test status
Simulation time 72234284 ps
CPU time 0.77 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:55 PM PDT 24
Peak memory 199984 kb
Host smart-3d83348b-9668-4f6c-b9a2-411c01efd5bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916828847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2916828847
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2346019016
Short name T66
Test name
Test status
Simulation time 135778669 ps
CPU time 1.27 seconds
Started Aug 06 07:26:57 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 200192 kb
Host smart-5c5529b9-5929-4133-8cfb-b910743fd206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346019016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2346019016
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1057962814
Short name T578
Test name
Test status
Simulation time 113535947 ps
CPU time 1.51 seconds
Started Aug 06 07:26:56 PM PDT 24
Finished Aug 06 07:26:58 PM PDT 24
Peak memory 210636 kb
Host smart-06ea9a83-eea5-45ef-8128-0126e192ee7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057962814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1057962814
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2980707521
Short name T564
Test name
Test status
Simulation time 474235148 ps
CPU time 1.98 seconds
Started Aug 06 07:26:55 PM PDT 24
Finished Aug 06 07:26:57 PM PDT 24
Peak memory 200280 kb
Host smart-ac0f8df8-7860-4664-999a-fa1291d49faa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980707521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2980707521
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2743895160
Short name T571
Test name
Test status
Simulation time 251359915 ps
CPU time 1.74 seconds
Started Aug 06 07:25:45 PM PDT 24
Finished Aug 06 07:25:46 PM PDT 24
Peak memory 200132 kb
Host smart-6ce7a8a9-0653-4c55-b8ba-ac2c0cb8a8f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743895160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
743895160
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3004305983
Short name T576
Test name
Test status
Simulation time 1560581633 ps
CPU time 8.74 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:53 PM PDT 24
Peak memory 200188 kb
Host smart-f8e4e2a6-d14e-4055-9e7f-41d00c34383b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004305983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
004305983
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1146789535
Short name T617
Test name
Test status
Simulation time 99623268 ps
CPU time 0.91 seconds
Started Aug 06 07:25:46 PM PDT 24
Finished Aug 06 07:25:47 PM PDT 24
Peak memory 200008 kb
Host smart-3b5787fc-835d-440e-8827-db554a94d8fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146789535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
146789535
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1672730553
Short name T616
Test name
Test status
Simulation time 119980690 ps
CPU time 0.98 seconds
Started Aug 06 07:25:46 PM PDT 24
Finished Aug 06 07:25:47 PM PDT 24
Peak memory 200160 kb
Host smart-e3a6cd69-d2db-4e6a-bfce-f397faced4bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672730553 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1672730553
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3768181583
Short name T611
Test name
Test status
Simulation time 80374183 ps
CPU time 0.87 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:45 PM PDT 24
Peak memory 200068 kb
Host smart-fb4254ce-7b9b-419b-b324-b637c612e61a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768181583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3768181583
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1390481115
Short name T581
Test name
Test status
Simulation time 270203995 ps
CPU time 1.51 seconds
Started Aug 06 07:25:50 PM PDT 24
Finished Aug 06 07:25:51 PM PDT 24
Peak memory 200156 kb
Host smart-9b41681e-d8bc-482b-a2e1-b5d020257ab4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390481115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1390481115
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2471630652
Short name T590
Test name
Test status
Simulation time 127032409 ps
CPU time 1.79 seconds
Started Aug 06 07:25:47 PM PDT 24
Finished Aug 06 07:25:48 PM PDT 24
Peak memory 216400 kb
Host smart-9970e543-7f4f-449d-86d3-30960a797506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471630652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2471630652
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3515968067
Short name T586
Test name
Test status
Simulation time 166237975 ps
CPU time 1.97 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:01 PM PDT 24
Peak memory 200124 kb
Host smart-d8046abb-d3eb-4c0d-b7d0-f38259aa7791
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515968067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
515968067
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2650387117
Short name T566
Test name
Test status
Simulation time 813652395 ps
CPU time 4.52 seconds
Started Aug 06 07:25:58 PM PDT 24
Finished Aug 06 07:26:03 PM PDT 24
Peak memory 200308 kb
Host smart-22397d78-fc8e-45ed-8fcb-5bf48800b51e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650387117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
650387117
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.704393044
Short name T596
Test name
Test status
Simulation time 94741802 ps
CPU time 0.85 seconds
Started Aug 06 07:25:57 PM PDT 24
Finished Aug 06 07:25:58 PM PDT 24
Peak memory 199960 kb
Host smart-da46eaa6-f4f2-43c7-9095-74e163759d8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704393044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.704393044
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.4254775326
Short name T574
Test name
Test status
Simulation time 181402415 ps
CPU time 1.23 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 200188 kb
Host smart-e36960f4-3912-4e44-806b-1dc927496bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254775326 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.4254775326
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.195722140
Short name T615
Test name
Test status
Simulation time 58701235 ps
CPU time 0.76 seconds
Started Aug 06 07:26:04 PM PDT 24
Finished Aug 06 07:26:04 PM PDT 24
Peak memory 199956 kb
Host smart-dfc136f5-d22f-42a0-a784-0d3ae4e0234c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195722140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.195722140
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2815662364
Short name T117
Test name
Test status
Simulation time 279110620 ps
CPU time 1.69 seconds
Started Aug 06 07:25:58 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 200244 kb
Host smart-7e75f746-dacf-4db3-b10c-7137739a0a4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815662364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2815662364
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2520370913
Short name T593
Test name
Test status
Simulation time 201290969 ps
CPU time 1.66 seconds
Started Aug 06 07:25:44 PM PDT 24
Finished Aug 06 07:25:46 PM PDT 24
Peak memory 200120 kb
Host smart-a2afcd06-5979-4e6b-8595-ac679389b5f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520370913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2520370913
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3696569542
Short name T146
Test name
Test status
Simulation time 430440982 ps
CPU time 1.85 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:01 PM PDT 24
Peak memory 200172 kb
Host smart-e136c131-4645-4a1b-b327-752cb84e74dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696569542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3696569542
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.708993548
Short name T608
Test name
Test status
Simulation time 357746609 ps
CPU time 2.55 seconds
Started Aug 06 07:25:57 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 200108 kb
Host smart-b2e2deff-d22a-49b0-8358-313b81c6e025
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708993548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.708993548
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4284210180
Short name T601
Test name
Test status
Simulation time 1023126045 ps
CPU time 5.22 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:05 PM PDT 24
Peak memory 200140 kb
Host smart-9001947b-6b41-462b-8ae5-9da06cf890e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284210180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4
284210180
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3431211509
Short name T545
Test name
Test status
Simulation time 136076731 ps
CPU time 1 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 200072 kb
Host smart-7eaabbe4-04a2-4a6b-af25-0ebae960bc0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431211509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3
431211509
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2257112258
Short name T70
Test name
Test status
Simulation time 183278373 ps
CPU time 1.28 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 200140 kb
Host smart-6c224611-a9d8-41ac-9fdf-020586246bf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257112258 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2257112258
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2860263712
Short name T570
Test name
Test status
Simulation time 54902320 ps
CPU time 0.71 seconds
Started Aug 06 07:26:03 PM PDT 24
Finished Aug 06 07:26:04 PM PDT 24
Peak memory 199960 kb
Host smart-e2712425-4e6c-4e76-ad75-6d22bdf5cc89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860263712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2860263712
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2551206430
Short name T555
Test name
Test status
Simulation time 128023528 ps
CPU time 1.09 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 200012 kb
Host smart-2afea899-93bc-4f47-b1a2-b76fd8e235cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551206430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2551206430
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1094976623
Short name T606
Test name
Test status
Simulation time 119201056 ps
CPU time 1.59 seconds
Started Aug 06 07:25:58 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 208328 kb
Host smart-cf973024-81b2-43f2-a66c-1ff06e25bb2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094976623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1094976623
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1000277280
Short name T594
Test name
Test status
Simulation time 479196653 ps
CPU time 1.87 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:01 PM PDT 24
Peak memory 200272 kb
Host smart-35ba5ce8-8ef7-4d49-899a-3ebdafbfbaa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000277280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1000277280
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3252737564
Short name T562
Test name
Test status
Simulation time 81324137 ps
CPU time 0.89 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 200040 kb
Host smart-a56898e3-ccea-4a06-a37b-fd842d393f33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252737564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3252737564
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4169766633
Short name T114
Test name
Test status
Simulation time 155361740 ps
CPU time 1.12 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:01 PM PDT 24
Peak memory 200060 kb
Host smart-0c925a2d-dbfd-423e-9b49-12ec8f3e21b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169766633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4169766633
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.212378184
Short name T598
Test name
Test status
Simulation time 238535387 ps
CPU time 2.02 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:01 PM PDT 24
Peak memory 200112 kb
Host smart-085e053a-f193-4186-b8dc-8d93fc776b31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212378184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.212378184
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1612915744
Short name T147
Test name
Test status
Simulation time 789916215 ps
CPU time 3.14 seconds
Started Aug 06 07:26:04 PM PDT 24
Finished Aug 06 07:26:07 PM PDT 24
Peak memory 200108 kb
Host smart-81a363fd-878c-4944-8d16-6e331ebbb372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612915744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1612915744
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1491579446
Short name T125
Test name
Test status
Simulation time 194617573 ps
CPU time 1.43 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 208408 kb
Host smart-8d45cc34-f8a8-4142-b877-a55650f99835
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491579446 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1491579446
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.715885056
Short name T618
Test name
Test status
Simulation time 91539560 ps
CPU time 0.94 seconds
Started Aug 06 07:25:59 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 200044 kb
Host smart-e23f9c2c-658c-4c52-b8d9-a880e02bafc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715885056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.715885056
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1576111040
Short name T568
Test name
Test status
Simulation time 259278946 ps
CPU time 1.7 seconds
Started Aug 06 07:26:02 PM PDT 24
Finished Aug 06 07:26:04 PM PDT 24
Peak memory 200104 kb
Host smart-8d537c2e-193e-475b-a1c4-41e6e6f074e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576111040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1576111040
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3550820093
Short name T592
Test name
Test status
Simulation time 175899768 ps
CPU time 2.6 seconds
Started Aug 06 07:25:57 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 208320 kb
Host smart-b4e0580e-93ce-4cbc-abef-795a6d107191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550820093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3550820093
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3242180281
Short name T144
Test name
Test status
Simulation time 629577630 ps
CPU time 2.1 seconds
Started Aug 06 07:26:03 PM PDT 24
Finished Aug 06 07:26:05 PM PDT 24
Peak memory 200092 kb
Host smart-1768bf26-5f42-4f0e-90a9-c2895cfb0d16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242180281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3242180281
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3960560904
Short name T575
Test name
Test status
Simulation time 176785027 ps
CPU time 1.25 seconds
Started Aug 06 07:26:15 PM PDT 24
Finished Aug 06 07:26:16 PM PDT 24
Peak memory 208368 kb
Host smart-6fd47d40-9a5d-4390-b0f2-995713149b6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960560904 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3960560904
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1005838349
Short name T607
Test name
Test status
Simulation time 75661572 ps
CPU time 0.79 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:17 PM PDT 24
Peak memory 199992 kb
Host smart-6194288f-c9e0-4c7c-9bfa-ec6207933a53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005838349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1005838349
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1493435687
Short name T595
Test name
Test status
Simulation time 250490087 ps
CPU time 1.55 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:18 PM PDT 24
Peak memory 200136 kb
Host smart-d4935bb8-868a-4ddb-aa2a-05bbbdc1e312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493435687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1493435687
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.645406451
Short name T72
Test name
Test status
Simulation time 159150572 ps
CPU time 2.34 seconds
Started Aug 06 07:25:57 PM PDT 24
Finished Aug 06 07:26:00 PM PDT 24
Peak memory 208188 kb
Host smart-dd45b396-e2db-4892-b224-7bfa1de78d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645406451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.645406451
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2145955016
Short name T119
Test name
Test status
Simulation time 502944166 ps
CPU time 1.95 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:18 PM PDT 24
Peak memory 200264 kb
Host smart-6d92d81c-c8a0-4636-b244-40d19a954aca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145955016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2145955016
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3845536887
Short name T565
Test name
Test status
Simulation time 105410244 ps
CPU time 0.97 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:17 PM PDT 24
Peak memory 200120 kb
Host smart-b3e81709-99a0-4e56-9d91-64edecb03440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845536887 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3845536887
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.290507352
Short name T599
Test name
Test status
Simulation time 68772938 ps
CPU time 0.8 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:17 PM PDT 24
Peak memory 200052 kb
Host smart-a0a65689-628e-4925-bd74-66f755151e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290507352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.290507352
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.760531268
Short name T620
Test name
Test status
Simulation time 243064422 ps
CPU time 1.48 seconds
Started Aug 06 07:26:17 PM PDT 24
Finished Aug 06 07:26:19 PM PDT 24
Peak memory 200200 kb
Host smart-3b9bd4f6-1cce-4a27-95b7-294bbfc06e7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760531268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.760531268
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2637198341
Short name T584
Test name
Test status
Simulation time 380733473 ps
CPU time 2.86 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:19 PM PDT 24
Peak memory 208392 kb
Host smart-e52aea93-6090-4c0d-95ad-93a6b10a2364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637198341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2637198341
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.965488858
Short name T558
Test name
Test status
Simulation time 879291870 ps
CPU time 3.05 seconds
Started Aug 06 07:26:15 PM PDT 24
Finished Aug 06 07:26:18 PM PDT 24
Peak memory 200104 kb
Host smart-ae4771c6-9223-45b4-b296-a58080bdb937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965488858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
965488858
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2162788720
Short name T94
Test name
Test status
Simulation time 175913645 ps
CPU time 1.12 seconds
Started Aug 06 07:26:17 PM PDT 24
Finished Aug 06 07:26:19 PM PDT 24
Peak memory 200168 kb
Host smart-70015f37-88fb-493d-9256-7fd0c99997da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162788720 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2162788720
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3187762537
Short name T100
Test name
Test status
Simulation time 60120741 ps
CPU time 0.77 seconds
Started Aug 06 07:26:15 PM PDT 24
Finished Aug 06 07:26:16 PM PDT 24
Peak memory 200056 kb
Host smart-ee9637a0-6d10-4c0b-b0ce-36cc610ddc8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187762537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3187762537
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.620353626
Short name T113
Test name
Test status
Simulation time 131997759 ps
CPU time 1.35 seconds
Started Aug 06 07:26:17 PM PDT 24
Finished Aug 06 07:26:19 PM PDT 24
Peak memory 200160 kb
Host smart-789d9e32-6ed3-4d3c-81a3-77de30d4c4d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620353626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.620353626
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2634193765
Short name T554
Test name
Test status
Simulation time 578199315 ps
CPU time 3.87 seconds
Started Aug 06 07:26:16 PM PDT 24
Finished Aug 06 07:26:20 PM PDT 24
Peak memory 211076 kb
Host smart-7c9d7b18-2e8c-4e06-a904-037bce680970
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634193765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2634193765
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2898420373
Short name T123
Test name
Test status
Simulation time 973532730 ps
CPU time 3.14 seconds
Started Aug 06 07:26:17 PM PDT 24
Finished Aug 06 07:26:20 PM PDT 24
Peak memory 200216 kb
Host smart-e2c7f755-2453-460b-875e-005db211c130
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898420373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2898420373
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.4055320237
Short name T407
Test name
Test status
Simulation time 1222745995 ps
CPU time 5.25 seconds
Started Aug 06 07:46:24 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 221712 kb
Host smart-0387482c-94f9-4f70-8830-6d37512b6bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055320237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4055320237
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3856824333
Short name T470
Test name
Test status
Simulation time 246530495 ps
CPU time 1.08 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 217508 kb
Host smart-27062e21-6975-4d49-afb3-713ee74e418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856824333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3856824333
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.205587001
Short name T387
Test name
Test status
Simulation time 165274910 ps
CPU time 0.84 seconds
Started Aug 06 07:46:25 PM PDT 24
Finished Aug 06 07:46:26 PM PDT 24
Peak memory 200204 kb
Host smart-263bc7a7-2a92-4a90-9e23-730b9b679e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205587001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.205587001
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.44489974
Short name T334
Test name
Test status
Simulation time 1473792018 ps
CPU time 5.31 seconds
Started Aug 06 07:46:22 PM PDT 24
Finished Aug 06 07:46:28 PM PDT 24
Peak memory 200576 kb
Host smart-c27e63d1-b388-4c8b-9e2c-8703020e8149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44489974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.44489974
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.1410931463
Short name T427
Test name
Test status
Simulation time 206481452 ps
CPU time 1.41 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:27 PM PDT 24
Peak memory 200468 kb
Host smart-2b066572-1ecb-4e51-bbaa-91caa11636f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410931463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1410931463
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.906201815
Short name T204
Test name
Test status
Simulation time 8967184895 ps
CPU time 33.1 seconds
Started Aug 06 07:46:29 PM PDT 24
Finished Aug 06 07:47:03 PM PDT 24
Peak memory 200608 kb
Host smart-a731988f-25a4-4e5d-85fc-07033096692a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906201815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.906201815
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3647207668
Short name T226
Test name
Test status
Simulation time 547611980 ps
CPU time 3.03 seconds
Started Aug 06 07:46:26 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 200304 kb
Host smart-425b403a-80c8-48c1-a957-5a1ffff4687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647207668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3647207668
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.939725286
Short name T184
Test name
Test status
Simulation time 121775625 ps
CPU time 1.08 seconds
Started Aug 06 07:46:25 PM PDT 24
Finished Aug 06 07:46:26 PM PDT 24
Peak memory 200296 kb
Host smart-13810467-2500-4dd5-9109-4f0faa4c88e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939725286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.939725286
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.836945334
Short name T171
Test name
Test status
Simulation time 68825526 ps
CPU time 0.76 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 200136 kb
Host smart-225dc958-44bc-4d91-a2bc-f8c381aa6e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836945334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.836945334
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3727538297
Short name T511
Test name
Test status
Simulation time 1870514059 ps
CPU time 7.68 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:38 PM PDT 24
Peak memory 217392 kb
Host smart-33bb8044-b70e-4250-aa83-f0fae83b2d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727538297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3727538297
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1290177984
Short name T289
Test name
Test status
Simulation time 244696499 ps
CPU time 1.15 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:32 PM PDT 24
Peak memory 217564 kb
Host smart-16039583-8427-491e-bc65-4becfa939aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290177984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1290177984
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2380119982
Short name T533
Test name
Test status
Simulation time 177777580 ps
CPU time 0.94 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 200136 kb
Host smart-dbc43ceb-bdca-4add-b43c-127b9ee82e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380119982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2380119982
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1493846465
Short name T521
Test name
Test status
Simulation time 1101712219 ps
CPU time 5.01 seconds
Started Aug 06 07:46:29 PM PDT 24
Finished Aug 06 07:46:34 PM PDT 24
Peak memory 200568 kb
Host smart-be822a13-3031-4360-b1ca-aced73b1b733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493846465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1493846465
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.210869672
Short name T78
Test name
Test status
Simulation time 16743210563 ps
CPU time 24.14 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:53 PM PDT 24
Peak memory 217688 kb
Host smart-5c8f26ad-5af1-404a-a0a0-eb11d98e3a2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210869672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.210869672
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1164346452
Short name T3
Test name
Test status
Simulation time 104235229 ps
CPU time 1.03 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 200296 kb
Host smart-7ba111ab-92ac-4e66-a7ec-86dbbd4e8753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164346452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1164346452
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3931465539
Short name T139
Test name
Test status
Simulation time 249527679 ps
CPU time 1.58 seconds
Started Aug 06 07:46:29 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 200504 kb
Host smart-8c8ed67c-2f22-4fcd-9d18-e50ae2ea5009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931465539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3931465539
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2829433624
Short name T90
Test name
Test status
Simulation time 3461650125 ps
CPU time 14.06 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:44 PM PDT 24
Peak memory 200556 kb
Host smart-842603d7-5e58-4954-abf8-3fd9b8dc7d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829433624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2829433624
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2301149061
Short name T81
Test name
Test status
Simulation time 125239158 ps
CPU time 1.58 seconds
Started Aug 06 07:46:29 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 200240 kb
Host smart-5286a68c-603d-4bdf-8136-f3b052711930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301149061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2301149061
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2196656275
Short name T455
Test name
Test status
Simulation time 173366789 ps
CPU time 1.08 seconds
Started Aug 06 07:46:31 PM PDT 24
Finished Aug 06 07:46:32 PM PDT 24
Peak memory 200200 kb
Host smart-812a3703-5775-492b-a4b8-dacc7cf8fff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196656275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2196656275
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3048868890
Short name T281
Test name
Test status
Simulation time 70956919 ps
CPU time 0.75 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200088 kb
Host smart-ad21af74-b48c-45b1-94df-8ada0b4255dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048868890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3048868890
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.502829217
Short name T514
Test name
Test status
Simulation time 1221955334 ps
CPU time 5.68 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:13 PM PDT 24
Peak memory 217732 kb
Host smart-b62d9765-2046-481a-9128-f6fe72875730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502829217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.502829217
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3657393139
Short name T155
Test name
Test status
Simulation time 244498741 ps
CPU time 1.07 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 217468 kb
Host smart-390259fe-21ca-4568-b27e-610bd884812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657393139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3657393139
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1220090162
Short name T400
Test name
Test status
Simulation time 192736899 ps
CPU time 1.04 seconds
Started Aug 06 07:47:02 PM PDT 24
Finished Aug 06 07:47:04 PM PDT 24
Peak memory 200072 kb
Host smart-0706bae4-080e-4694-b483-d882752a983f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220090162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1220090162
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2614801217
Short name T102
Test name
Test status
Simulation time 1596288510 ps
CPU time 6.97 seconds
Started Aug 06 07:47:02 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200540 kb
Host smart-ec3d7dfa-1297-4b19-8091-0996945c34fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614801217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2614801217
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2025494777
Short name T509
Test name
Test status
Simulation time 150829522 ps
CPU time 1.15 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:07 PM PDT 24
Peak memory 200332 kb
Host smart-b46db34e-4cbe-42b6-b97c-a8d7381dfec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025494777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2025494777
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1389138535
Short name T461
Test name
Test status
Simulation time 189323586 ps
CPU time 1.33 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200476 kb
Host smart-752d84c3-29b2-4d56-8824-b0f74131f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389138535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1389138535
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4236827717
Short name T199
Test name
Test status
Simulation time 4963783847 ps
CPU time 16.94 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:22 PM PDT 24
Peak memory 208760 kb
Host smart-c0f77b6b-c722-4cd3-be92-a576324135c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236827717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4236827717
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1513189411
Short name T233
Test name
Test status
Simulation time 436947278 ps
CPU time 2.32 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 208452 kb
Host smart-b3eee10f-57dd-4a27-9a10-785d425aa226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513189411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1513189411
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.402836658
Short name T421
Test name
Test status
Simulation time 176028375 ps
CPU time 1.16 seconds
Started Aug 06 07:47:03 PM PDT 24
Finished Aug 06 07:47:04 PM PDT 24
Peak memory 200324 kb
Host smart-a5fdfdce-f828-42d8-afaa-a88e84ce66f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402836658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.402836658
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2421008205
Short name T172
Test name
Test status
Simulation time 88662826 ps
CPU time 0.81 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200068 kb
Host smart-4b616dc8-dce5-4047-afb0-62b90fe2905f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421008205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2421008205
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1801165104
Short name T488
Test name
Test status
Simulation time 1900703122 ps
CPU time 8 seconds
Started Aug 06 07:47:03 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 217680 kb
Host smart-ee2d637f-0d42-41a2-9fac-53b81e13b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801165104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1801165104
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.4037443663
Short name T269
Test name
Test status
Simulation time 244792409 ps
CPU time 1.22 seconds
Started Aug 06 07:47:03 PM PDT 24
Finished Aug 06 07:47:05 PM PDT 24
Peak memory 217480 kb
Host smart-0a36910d-a6e6-42ba-ad26-0c0616b1b113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037443663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.4037443663
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.187015435
Short name T416
Test name
Test status
Simulation time 187072300 ps
CPU time 0.86 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200156 kb
Host smart-eeec5f0f-50e0-416e-9d80-9762e2e55bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187015435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.187015435
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.757212902
Short name T33
Test name
Test status
Simulation time 1599668327 ps
CPU time 6.07 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 200596 kb
Host smart-c3abb1a6-d38f-4325-8a6e-a58351199d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757212902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.757212902
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3563231245
Short name T151
Test name
Test status
Simulation time 98691571 ps
CPU time 1.02 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200540 kb
Host smart-68813a70-4555-4fb5-99e0-95fbb43e6213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563231245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3563231245
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.951483081
Short name T312
Test name
Test status
Simulation time 113489581 ps
CPU time 1.18 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200448 kb
Host smart-50c54988-4226-47a0-86d0-f77c5e1773fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951483081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.951483081
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1822441196
Short name T486
Test name
Test status
Simulation time 2306708938 ps
CPU time 10.35 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:17 PM PDT 24
Peak memory 208788 kb
Host smart-1a254122-35d8-4c9e-b4ac-15530ea753a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822441196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1822441196
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.4069469955
Short name T159
Test name
Test status
Simulation time 283791033 ps
CPU time 2.02 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200280 kb
Host smart-8ed5afa3-013b-4a6c-900c-62968ae15e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069469955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.4069469955
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.86331057
Short name T386
Test name
Test status
Simulation time 186198441 ps
CPU time 1.28 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200336 kb
Host smart-53cac17c-5330-4bc6-ac9c-2b36daca7235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86331057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.86331057
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3688785434
Short name T530
Test name
Test status
Simulation time 62289649 ps
CPU time 0.74 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200148 kb
Host smart-b336051d-253b-4ec8-90cc-88330bebab4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688785434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3688785434
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.4215666182
Short name T474
Test name
Test status
Simulation time 2149747065 ps
CPU time 7.37 seconds
Started Aug 06 07:47:03 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 221712 kb
Host smart-06052159-06ef-4671-8068-3e360c45bafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215666182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.4215666182
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.708996505
Short name T275
Test name
Test status
Simulation time 244740995 ps
CPU time 1.03 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:06 PM PDT 24
Peak memory 217544 kb
Host smart-56d99b65-b432-43fa-bb1b-3315f90795bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708996505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.708996505
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.772550252
Short name T231
Test name
Test status
Simulation time 87326936 ps
CPU time 0.76 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:06 PM PDT 24
Peak memory 200144 kb
Host smart-6e79d1d3-0f17-4c99-b215-dcb7fd0fa40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772550252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.772550252
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2052455623
Short name T328
Test name
Test status
Simulation time 1040952755 ps
CPU time 4.98 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200556 kb
Host smart-c108b663-2160-4ae1-b0be-7128e207c546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052455623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2052455623
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1443335030
Short name T465
Test name
Test status
Simulation time 103748263 ps
CPU time 1.04 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200332 kb
Host smart-bdd7ac96-ffe4-4298-9bbd-21fe2f7bc9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443335030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1443335030
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1281786235
Short name T482
Test name
Test status
Simulation time 203495102 ps
CPU time 1.33 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200564 kb
Host smart-d7da9b61-fd3b-4fa1-a2f3-4a22e03d4555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281786235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1281786235
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2756660344
Short name T392
Test name
Test status
Simulation time 5737203373 ps
CPU time 23.68 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:32 PM PDT 24
Peak memory 208772 kb
Host smart-4c150305-b72a-4d28-b1f3-4005c9848ed2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756660344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2756660344
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3079289063
Short name T212
Test name
Test status
Simulation time 312876244 ps
CPU time 2.04 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200276 kb
Host smart-b2346576-f539-41be-be8b-a7dfdc3e9ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079289063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3079289063
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3220264097
Short name T438
Test name
Test status
Simulation time 250700925 ps
CPU time 1.43 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200356 kb
Host smart-e254f0f2-ef05-4698-8a6c-e8dc7d16e851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220264097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3220264097
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3525969167
Short name T255
Test name
Test status
Simulation time 89691432 ps
CPU time 0.86 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200148 kb
Host smart-762323c7-1582-4ceb-8d78-6229d9a04260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525969167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3525969167
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.593472522
Short name T13
Test name
Test status
Simulation time 1887209814 ps
CPU time 7.26 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:16 PM PDT 24
Peak memory 217728 kb
Host smart-5a5d5d17-5803-4fda-9c3d-be258a55e987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593472522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.593472522
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2037302279
Short name T464
Test name
Test status
Simulation time 244067327 ps
CPU time 1.14 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:06 PM PDT 24
Peak memory 217540 kb
Host smart-b9b1bd80-e3c3-47fd-960c-a2cf3fb06e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037302279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2037302279
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1734193170
Short name T510
Test name
Test status
Simulation time 875289238 ps
CPU time 4.51 seconds
Started Aug 06 07:47:12 PM PDT 24
Finished Aug 06 07:47:17 PM PDT 24
Peak memory 200532 kb
Host smart-005ba7df-9262-4908-b18b-6b3a10dac296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734193170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1734193170
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.742307487
Short name T406
Test name
Test status
Simulation time 152942381 ps
CPU time 1.16 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200356 kb
Host smart-9494cae3-e24d-45c7-a590-42ae345186c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742307487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.742307487
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1941995589
Short name T181
Test name
Test status
Simulation time 205823449 ps
CPU time 1.47 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200464 kb
Host smart-57a69ea4-937e-48ce-8f9e-8af918cf5960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941995589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1941995589
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3208135459
Short name T220
Test name
Test status
Simulation time 1661994415 ps
CPU time 8.73 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 200588 kb
Host smart-cd50baab-17e4-47a1-8134-530dc2971fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208135459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3208135459
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.182380118
Short name T142
Test name
Test status
Simulation time 441834295 ps
CPU time 2.49 seconds
Started Aug 06 07:47:02 PM PDT 24
Finished Aug 06 07:47:04 PM PDT 24
Peak memory 200288 kb
Host smart-1d3d3c06-9fb5-476e-9b21-74db1da107ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182380118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.182380118
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1676450649
Short name T493
Test name
Test status
Simulation time 133206382 ps
CPU time 1.18 seconds
Started Aug 06 07:46:59 PM PDT 24
Finished Aug 06 07:47:01 PM PDT 24
Peak memory 200272 kb
Host smart-913a9519-33f7-4ffc-a0f3-5de3d5ed97e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676450649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1676450649
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1844504182
Short name T379
Test name
Test status
Simulation time 80208061 ps
CPU time 0.8 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200144 kb
Host smart-ed4f4c14-f064-4c3f-bff2-f87568dbcea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844504182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1844504182
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2651757474
Short name T39
Test name
Test status
Simulation time 1903752951 ps
CPU time 6.77 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 216780 kb
Host smart-6231dfbe-e467-42eb-893b-14d803ff35bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651757474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2651757474
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2236503085
Short name T366
Test name
Test status
Simulation time 245625378 ps
CPU time 1.07 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:06 PM PDT 24
Peak memory 217448 kb
Host smart-b44688a7-c007-4e77-aa0e-b579077fc393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236503085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2236503085
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1479479064
Short name T316
Test name
Test status
Simulation time 170324067 ps
CPU time 0.84 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200140 kb
Host smart-5044c6ee-2286-44e9-8f96-aa905b082ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479479064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1479479064
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1582362221
Short name T454
Test name
Test status
Simulation time 892903138 ps
CPU time 4.66 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 200576 kb
Host smart-25f5b73a-80c3-40d8-9e55-82c2efecb03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582362221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1582362221
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3032085596
Short name T393
Test name
Test status
Simulation time 144523560 ps
CPU time 1.06 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200260 kb
Host smart-9647490b-fb67-42e2-925e-6756f20292ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032085596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3032085596
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.381543887
Short name T31
Test name
Test status
Simulation time 193570941 ps
CPU time 1.35 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200472 kb
Host smart-336ab52a-a403-4f2c-a74b-0f12f8fb2746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381543887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.381543887
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3964269006
Short name T191
Test name
Test status
Simulation time 4361934216 ps
CPU time 16.79 seconds
Started Aug 06 07:47:13 PM PDT 24
Finished Aug 06 07:47:30 PM PDT 24
Peak memory 200704 kb
Host smart-a45ff203-b373-414f-ac0f-47847d8aa3aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964269006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3964269006
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3984620242
Short name T246
Test name
Test status
Simulation time 113242918 ps
CPU time 1.49 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200276 kb
Host smart-74d8d38c-a2b9-4a21-aad1-585a2deecc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984620242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3984620242
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2612627377
Short name T458
Test name
Test status
Simulation time 164234407 ps
CPU time 1.19 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200328 kb
Host smart-4279b88a-6849-4a82-b569-51f600750023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612627377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2612627377
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3511763545
Short name T391
Test name
Test status
Simulation time 69119564 ps
CPU time 0.81 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:07 PM PDT 24
Peak memory 200140 kb
Host smart-f64c09b2-44bb-4999-9bdb-e0bfeda207d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511763545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3511763545
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3134509275
Short name T350
Test name
Test status
Simulation time 1232326824 ps
CPU time 5.62 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:16 PM PDT 24
Peak memory 217748 kb
Host smart-44f2c294-a368-4322-831f-56aba754515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134509275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3134509275
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.113507742
Short name T182
Test name
Test status
Simulation time 244822801 ps
CPU time 1.03 seconds
Started Aug 06 07:47:12 PM PDT 24
Finished Aug 06 07:47:13 PM PDT 24
Peak memory 217504 kb
Host smart-071bc29d-c18f-4e7d-bdd4-437c3fe1551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113507742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.113507742
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.524751025
Short name T241
Test name
Test status
Simulation time 178691460 ps
CPU time 0.83 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200164 kb
Host smart-3e85d6d9-5ee9-46bd-a505-b28425c88bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524751025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.524751025
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.228005962
Short name T401
Test name
Test status
Simulation time 1751381387 ps
CPU time 7.03 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 200608 kb
Host smart-d59dc512-bcef-47a3-8c99-be22afdcde74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228005962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.228005962
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.54934714
Short name T185
Test name
Test status
Simulation time 178524125 ps
CPU time 1.22 seconds
Started Aug 06 07:47:13 PM PDT 24
Finished Aug 06 07:47:14 PM PDT 24
Peak memory 200328 kb
Host smart-20657c0d-447c-4d66-99cb-30de4de86a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54934714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.54934714
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1154716354
Short name T460
Test name
Test status
Simulation time 114160441 ps
CPU time 1.22 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200516 kb
Host smart-32ec781f-ddf6-42f4-9be8-1d5f6f55a74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154716354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1154716354
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.306979801
Short name T388
Test name
Test status
Simulation time 10412690746 ps
CPU time 44.45 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:51 PM PDT 24
Peak memory 208868 kb
Host smart-02bea6b9-b10b-4b61-97fd-033e0dff8d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306979801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.306979801
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.3097862035
Short name T541
Test name
Test status
Simulation time 444614949 ps
CPU time 2.29 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200336 kb
Host smart-da8fcc2a-b3bb-46c6-8cd3-5b05cba12918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097862035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3097862035
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.4001688547
Short name T527
Test name
Test status
Simulation time 134070274 ps
CPU time 1.05 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200336 kb
Host smart-aca1c319-bde5-40bb-b891-809465cd65c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001688547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.4001688547
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3597316629
Short name T505
Test name
Test status
Simulation time 55956419 ps
CPU time 0.71 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200148 kb
Host smart-cded7299-a7c1-4532-895d-7c367d7ddda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597316629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3597316629
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2047266761
Short name T310
Test name
Test status
Simulation time 1225506818 ps
CPU time 5.76 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:17 PM PDT 24
Peak memory 217756 kb
Host smart-f507335c-95d2-4d2e-9e1c-b7aaf5025a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047266761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2047266761
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3226540691
Short name T483
Test name
Test status
Simulation time 243701203 ps
CPU time 1.06 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 217500 kb
Host smart-916bd7db-af3b-4ffe-8dd4-14284151fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226540691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3226540691
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2890514680
Short name T339
Test name
Test status
Simulation time 194779789 ps
CPU time 0.97 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200132 kb
Host smart-043eba3b-4c1e-4871-9d37-599202f4cf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890514680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2890514680
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2232296352
Short name T104
Test name
Test status
Simulation time 878710867 ps
CPU time 4.43 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200524 kb
Host smart-7b36581b-fad4-45c6-91cf-e1e7593def3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232296352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2232296352
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.4096460862
Short name T214
Test name
Test status
Simulation time 178862629 ps
CPU time 1.24 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200192 kb
Host smart-0f731ba7-9250-4e2c-b8c9-e99633993da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096460862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.4096460862
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1744516730
Short name T367
Test name
Test status
Simulation time 200362581 ps
CPU time 1.36 seconds
Started Aug 06 07:47:03 PM PDT 24
Finished Aug 06 07:47:05 PM PDT 24
Peak memory 200540 kb
Host smart-21d9ce14-ceba-41ab-ab7a-7e1da3574e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744516730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1744516730
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1802545323
Short name T495
Test name
Test status
Simulation time 2398642791 ps
CPU time 9.74 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 200532 kb
Host smart-4f31c4d9-7f68-45f9-b2b3-ce1d205651b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802545323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1802545323
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4285183708
Short name T540
Test name
Test status
Simulation time 266041526 ps
CPU time 1.77 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200268 kb
Host smart-38c7cbc2-b53a-4911-9d9e-a61298b386ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285183708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4285183708
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2823889572
Short name T79
Test name
Test status
Simulation time 193616027 ps
CPU time 1.29 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200256 kb
Host smart-57f7070b-ae8b-4006-abb1-460a8ba44076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823889572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2823889572
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2985910445
Short name T8
Test name
Test status
Simulation time 89076678 ps
CPU time 0.79 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200148 kb
Host smart-a8a742fb-d4d6-4b7a-96c5-349fd6d07e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985910445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2985910445
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1073811586
Short name T440
Test name
Test status
Simulation time 1900546868 ps
CPU time 7.17 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 217932 kb
Host smart-e3036336-c1b8-41bc-ba54-b93d9325d515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073811586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1073811586
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1651071113
Short name T165
Test name
Test status
Simulation time 244955337 ps
CPU time 1.1 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 217496 kb
Host smart-fe23ee36-8264-4900-9021-0994d58041db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651071113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1651071113
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1099724519
Short name T441
Test name
Test status
Simulation time 128606668 ps
CPU time 0.84 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200140 kb
Host smart-33072d00-b893-4b3b-b5d9-98ca306f9c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099724519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1099724519
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.1005232378
Short name T449
Test name
Test status
Simulation time 1027121806 ps
CPU time 5.15 seconds
Started Aug 06 07:47:14 PM PDT 24
Finished Aug 06 07:47:19 PM PDT 24
Peak memory 200560 kb
Host smart-b916c898-0f08-4e3d-9481-c49341385884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005232378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1005232378
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3340314018
Short name T148
Test name
Test status
Simulation time 143080936 ps
CPU time 1.12 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200356 kb
Host smart-d9214c1d-6e88-406e-ac7d-bf9af714406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340314018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3340314018
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.4086773279
Short name T157
Test name
Test status
Simulation time 128622766 ps
CPU time 1.17 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200516 kb
Host smart-82104a9b-50c8-40c0-8c1e-737ce1397cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086773279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4086773279
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2066458963
Short name T420
Test name
Test status
Simulation time 4649279703 ps
CPU time 19.3 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 216944 kb
Host smart-b4478cf7-f2ef-409c-84c7-84ed6ec8e777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066458963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2066458963
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2061678787
Short name T186
Test name
Test status
Simulation time 112915231 ps
CPU time 1.56 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:13 PM PDT 24
Peak memory 200276 kb
Host smart-2e063cca-1abb-4248-8f96-70103815a5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061678787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2061678787
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2632011364
Short name T300
Test name
Test status
Simulation time 139366598 ps
CPU time 1.22 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200540 kb
Host smart-079bca91-00e3-4aee-bc78-7fad4601dc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632011364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2632011364
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.950756061
Short name T9
Test name
Test status
Simulation time 74194580 ps
CPU time 0.76 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200140 kb
Host smart-e836d9db-23db-4143-8741-643df3969245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950756061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.950756061
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1550943310
Short name T349
Test name
Test status
Simulation time 244738686 ps
CPU time 1.05 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:06 PM PDT 24
Peak memory 217432 kb
Host smart-6a398c17-c972-4ded-bc7e-f5decfece34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550943310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1550943310
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1308517167
Short name T305
Test name
Test status
Simulation time 186912522 ps
CPU time 0.94 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200184 kb
Host smart-5b42aaff-08ef-498d-b734-e7c41eb7a60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308517167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1308517167
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.1855941969
Short name T317
Test name
Test status
Simulation time 1389795178 ps
CPU time 5.42 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:14 PM PDT 24
Peak memory 200584 kb
Host smart-7f52bc59-0afe-4ed6-933b-d252f1b2a7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855941969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1855941969
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1865219253
Short name T210
Test name
Test status
Simulation time 168614095 ps
CPU time 1.16 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200328 kb
Host smart-e866d8bb-4270-4a18-b9d1-ce27edff24cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865219253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1865219253
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.4037596451
Short name T375
Test name
Test status
Simulation time 258663577 ps
CPU time 1.55 seconds
Started Aug 06 07:47:12 PM PDT 24
Finished Aug 06 07:47:14 PM PDT 24
Peak memory 200488 kb
Host smart-b377ec39-7cde-41ff-bf6a-a6945e73b685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037596451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.4037596451
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.4246109859
Short name T429
Test name
Test status
Simulation time 2784552285 ps
CPU time 12.72 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:18 PM PDT 24
Peak memory 200596 kb
Host smart-025127e0-e4bc-4353-bfad-72629d5f53f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246109859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4246109859
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3155906125
Short name T196
Test name
Test status
Simulation time 143487854 ps
CPU time 1.14 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200352 kb
Host smart-eec83faf-b511-4a82-a415-7dc8ee467f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155906125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3155906125
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1278894311
Short name T395
Test name
Test status
Simulation time 57399227 ps
CPU time 0.73 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200068 kb
Host smart-909504cd-ad72-4dbf-bf4b-8a754c80ad3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278894311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1278894311
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3107294583
Short name T346
Test name
Test status
Simulation time 1878843658 ps
CPU time 7.19 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:17 PM PDT 24
Peak memory 221644 kb
Host smart-0f05d379-690a-473e-8292-da885b539283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107294583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3107294583
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3651191487
Short name T414
Test name
Test status
Simulation time 244445336 ps
CPU time 1.13 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 217540 kb
Host smart-4c8c4016-75eb-49ef-963d-8a1df67c47f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651191487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3651191487
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3351088478
Short name T15
Test name
Test status
Simulation time 195705497 ps
CPU time 1 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200136 kb
Host smart-66319905-4156-467b-880c-d522d3677e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351088478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3351088478
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.532868419
Short name T472
Test name
Test status
Simulation time 1540618496 ps
CPU time 5.64 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200532 kb
Host smart-a9fc46af-fcd8-4b8e-bc1f-53d02ec04f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532868419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.532868419
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.935734627
Short name T242
Test name
Test status
Simulation time 185414557 ps
CPU time 1.23 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200300 kb
Host smart-ccae280d-7523-41d1-8a41-3ab40d74fd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935734627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.935734627
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3793442781
Short name T253
Test name
Test status
Simulation time 123938599 ps
CPU time 1.19 seconds
Started Aug 06 07:47:05 PM PDT 24
Finished Aug 06 07:47:06 PM PDT 24
Peak memory 200420 kb
Host smart-70f441e8-8cf4-4e2f-9c05-1bab096788cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793442781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3793442781
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4012348039
Short name T491
Test name
Test status
Simulation time 1152130945 ps
CPU time 6.04 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:16 PM PDT 24
Peak memory 200500 kb
Host smart-a206aea1-1998-4e8e-9ce9-197fd66edd96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012348039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4012348039
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4109855246
Short name T294
Test name
Test status
Simulation time 314900302 ps
CPU time 2.1 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 208472 kb
Host smart-9c44c078-e82d-4492-8331-67c905f78770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109855246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4109855246
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1819747009
Short name T201
Test name
Test status
Simulation time 173106170 ps
CPU time 1.19 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200256 kb
Host smart-8fd83164-1b95-4b71-9c28-889319b27686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819747009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1819747009
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.197811559
Short name T299
Test name
Test status
Simulation time 72826126 ps
CPU time 0.8 seconds
Started Aug 06 07:46:46 PM PDT 24
Finished Aug 06 07:46:47 PM PDT 24
Peak memory 200132 kb
Host smart-21d693f8-c736-44ab-ab0c-79b5620f1eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197811559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.197811559
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2332346396
Short name T409
Test name
Test status
Simulation time 1235994725 ps
CPU time 5.53 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:36 PM PDT 24
Peak memory 221516 kb
Host smart-bd03c988-afd5-45bb-b9fe-bb2cd7e9c9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332346396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2332346396
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3593286199
Short name T402
Test name
Test status
Simulation time 243457757 ps
CPU time 1.08 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 217472 kb
Host smart-921c0833-d3f5-49b9-8117-9b747d2e66d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593286199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3593286199
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3001306139
Short name T20
Test name
Test status
Simulation time 88908418 ps
CPU time 0.8 seconds
Started Aug 06 07:46:31 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 200160 kb
Host smart-04836aaa-3129-47a2-bdbf-b4f91cd99206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001306139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3001306139
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1318590670
Short name T50
Test name
Test status
Simulation time 868750702 ps
CPU time 4.49 seconds
Started Aug 06 07:46:27 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 200484 kb
Host smart-6ad446aa-212f-4d64-af93-df1eb691424a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318590670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1318590670
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3134108367
Short name T73
Test name
Test status
Simulation time 16552879600 ps
CPU time 26.76 seconds
Started Aug 06 07:46:45 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 217364 kb
Host smart-70c1f7c3-31a3-4df5-ba95-a8d9785cadc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134108367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3134108367
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3799664253
Short name T424
Test name
Test status
Simulation time 171911199 ps
CPU time 1.17 seconds
Started Aug 06 07:46:28 PM PDT 24
Finished Aug 06 07:46:29 PM PDT 24
Peak memory 200332 kb
Host smart-0a7966fb-6524-44bc-bcb6-ce291f052fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799664253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3799664253
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1516824937
Short name T353
Test name
Test status
Simulation time 248954044 ps
CPU time 1.51 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:32 PM PDT 24
Peak memory 200496 kb
Host smart-a852503d-2250-4f84-9f04-23dca0eb4dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516824937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1516824937
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1256781636
Short name T265
Test name
Test status
Simulation time 138940194 ps
CPU time 1.7 seconds
Started Aug 06 07:46:31 PM PDT 24
Finished Aug 06 07:46:32 PM PDT 24
Peak memory 200144 kb
Host smart-4702c696-62b3-451a-bf70-ae0a64deebe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256781636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1256781636
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1211307196
Short name T291
Test name
Test status
Simulation time 135323642 ps
CPU time 1.03 seconds
Started Aug 06 07:46:30 PM PDT 24
Finished Aug 06 07:46:31 PM PDT 24
Peak memory 200200 kb
Host smart-7ed58ea2-5d60-4627-92fd-6c7bfb89c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211307196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1211307196
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2369925083
Short name T254
Test name
Test status
Simulation time 67776993 ps
CPU time 0.75 seconds
Started Aug 06 07:47:12 PM PDT 24
Finished Aug 06 07:47:13 PM PDT 24
Peak memory 200144 kb
Host smart-4bfbab33-b84d-42cb-9423-61043ad2bbf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369925083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2369925083
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.410983616
Short name T169
Test name
Test status
Simulation time 244281196 ps
CPU time 1.18 seconds
Started Aug 06 07:47:12 PM PDT 24
Finished Aug 06 07:47:14 PM PDT 24
Peak memory 217508 kb
Host smart-b994e3e9-6371-4cab-ae4c-702c360a7e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410983616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.410983616
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2672212557
Short name T190
Test name
Test status
Simulation time 147033008 ps
CPU time 0.88 seconds
Started Aug 06 07:47:12 PM PDT 24
Finished Aug 06 07:47:13 PM PDT 24
Peak memory 200160 kb
Host smart-1ed904bc-7e1a-448b-9fc3-ff3dbcbdcc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672212557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2672212557
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3648223873
Short name T337
Test name
Test status
Simulation time 1688919717 ps
CPU time 6.26 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:18 PM PDT 24
Peak memory 200540 kb
Host smart-6a989772-3f2a-4142-9c27-679aaf0191f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648223873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3648223873
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.745026386
Short name T351
Test name
Test status
Simulation time 110493949 ps
CPU time 1.03 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200332 kb
Host smart-285751ac-b35b-4460-ba70-12fb36adb5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745026386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.745026386
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3450022859
Short name T277
Test name
Test status
Simulation time 185070339 ps
CPU time 1.32 seconds
Started Aug 06 07:47:12 PM PDT 24
Finished Aug 06 07:47:13 PM PDT 24
Peak memory 200492 kb
Host smart-d83cf531-3bf4-4c22-9148-16ad9e730a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450022859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3450022859
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.944224805
Short name T32
Test name
Test status
Simulation time 217444807 ps
CPU time 1.32 seconds
Started Aug 06 07:47:12 PM PDT 24
Finished Aug 06 07:47:14 PM PDT 24
Peak memory 200320 kb
Host smart-c4296376-0405-4999-8562-13f2f4855237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944224805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.944224805
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3653257319
Short name T382
Test name
Test status
Simulation time 298871729 ps
CPU time 2.14 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 208476 kb
Host smart-74fc5003-1bdd-4780-a350-ef8885ab4cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653257319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3653257319
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2093438559
Short name T236
Test name
Test status
Simulation time 76575862 ps
CPU time 0.8 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200336 kb
Host smart-ee5958f7-abbf-4895-bec7-56ddb424a364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093438559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2093438559
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1048997219
Short name T352
Test name
Test status
Simulation time 82156152 ps
CPU time 0.82 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200168 kb
Host smart-7c8f7138-8edf-4d37-9745-3c2926d5a586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048997219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1048997219
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3098050954
Short name T537
Test name
Test status
Simulation time 2168681440 ps
CPU time 7.56 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 217820 kb
Host smart-7fe061f5-e88d-4b1f-bd94-c45141773fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098050954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3098050954
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.868063724
Short name T314
Test name
Test status
Simulation time 248111929 ps
CPU time 1.04 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 217516 kb
Host smart-bf42b4a7-5a4d-4639-9f76-8f3c07a56489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868063724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.868063724
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3885107873
Short name T408
Test name
Test status
Simulation time 195166787 ps
CPU time 0.93 seconds
Started Aug 06 07:47:08 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200132 kb
Host smart-f913c1bb-cb3f-4a6a-85ef-a136eaf59a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885107873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3885107873
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2467994172
Short name T499
Test name
Test status
Simulation time 741451090 ps
CPU time 4.18 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:14 PM PDT 24
Peak memory 200536 kb
Host smart-91c2ef1d-7a2f-4537-948e-625dbcb39d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467994172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2467994172
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3929972268
Short name T46
Test name
Test status
Simulation time 111533970 ps
CPU time 1.01 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:10 PM PDT 24
Peak memory 200340 kb
Host smart-9a419b8f-dfd2-48c3-b6e7-3ad9a65f8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929972268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3929972268
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1603803763
Short name T355
Test name
Test status
Simulation time 106911409 ps
CPU time 1.19 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200516 kb
Host smart-60fc4146-f459-4b52-9e67-9ad9c0013600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603803763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1603803763
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3309761473
Short name T206
Test name
Test status
Simulation time 12460256090 ps
CPU time 43.7 seconds
Started Aug 06 07:47:10 PM PDT 24
Finished Aug 06 07:47:54 PM PDT 24
Peak memory 208796 kb
Host smart-2a7ffbdf-913c-4f6f-a9b1-0edb1ce546d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309761473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3309761473
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2548235465
Short name T422
Test name
Test status
Simulation time 271036047 ps
CPU time 1.98 seconds
Started Aug 06 07:47:09 PM PDT 24
Finished Aug 06 07:47:11 PM PDT 24
Peak memory 200284 kb
Host smart-af69f49b-2752-45b6-b8e9-eff5f5f1b279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548235465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2548235465
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2929956254
Short name T343
Test name
Test status
Simulation time 95605132 ps
CPU time 0.88 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200328 kb
Host smart-4dcec6ff-7c2d-42c4-a617-0039f2165854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929956254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2929956254
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3905297375
Short name T222
Test name
Test status
Simulation time 72864381 ps
CPU time 0.78 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:06 PM PDT 24
Peak memory 200096 kb
Host smart-eeae6c81-5084-4ae0-a01a-ab5ff04135be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905297375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3905297375
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1042185013
Short name T230
Test name
Test status
Simulation time 244119734 ps
CPU time 1.07 seconds
Started Aug 06 07:47:14 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 217464 kb
Host smart-52a2ad57-20c5-4cab-b382-4da86c7ce33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042185013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1042185013
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3241461262
Short name T376
Test name
Test status
Simulation time 151864777 ps
CPU time 0.88 seconds
Started Aug 06 07:47:14 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 200128 kb
Host smart-225fe33e-67cb-4354-bf6e-9f387abc9fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241461262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3241461262
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1654472940
Short name T192
Test name
Test status
Simulation time 1379465587 ps
CPU time 5.46 seconds
Started Aug 06 07:47:15 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 200540 kb
Host smart-3fac3c07-6f45-4f34-8bd2-85c40e05909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654472940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1654472940
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.623266455
Short name T425
Test name
Test status
Simulation time 102155946 ps
CPU time 1 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:08 PM PDT 24
Peak memory 200292 kb
Host smart-e7d29bfc-e35c-43bb-91c0-8651c0ef1a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623266455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.623266455
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.662071089
Short name T175
Test name
Test status
Simulation time 112700407 ps
CPU time 1.27 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200520 kb
Host smart-bd2e4edf-3686-49b6-acaa-6939623c21e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662071089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.662071089
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2832834436
Short name T106
Test name
Test status
Simulation time 4139887316 ps
CPU time 13.81 seconds
Started Aug 06 07:47:15 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 200588 kb
Host smart-99678ae7-cfbf-4758-9b5d-a235d4a76b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832834436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2832834436
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.567462777
Short name T177
Test name
Test status
Simulation time 297538119 ps
CPU time 1.96 seconds
Started Aug 06 07:47:15 PM PDT 24
Finished Aug 06 07:47:17 PM PDT 24
Peak memory 200268 kb
Host smart-17a56f79-985a-47ea-98e8-9d304e21868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567462777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.567462777
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3405135233
Short name T325
Test name
Test status
Simulation time 110362220 ps
CPU time 1.14 seconds
Started Aug 06 07:47:11 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 200376 kb
Host smart-1485dec9-0705-4863-a6d0-d6eef20319ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405135233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3405135233
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.24392390
Short name T76
Test name
Test status
Simulation time 68398793 ps
CPU time 0.79 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:24 PM PDT 24
Peak memory 200156 kb
Host smart-290975f2-3175-4096-b185-765ad0c61ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24392390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.24392390
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1893232246
Short name T53
Test name
Test status
Simulation time 2361716427 ps
CPU time 9.07 seconds
Started Aug 06 07:47:22 PM PDT 24
Finished Aug 06 07:47:31 PM PDT 24
Peak memory 221812 kb
Host smart-0eedec46-052f-4048-b2e0-b547e683c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893232246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1893232246
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2406184550
Short name T389
Test name
Test status
Simulation time 243731949 ps
CPU time 1.14 seconds
Started Aug 06 07:47:22 PM PDT 24
Finished Aug 06 07:47:23 PM PDT 24
Peak memory 217572 kb
Host smart-ec176146-d4f1-41d6-bf8f-af0b80e0164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406184550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2406184550
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.532136566
Short name T501
Test name
Test status
Simulation time 179279467 ps
CPU time 0.82 seconds
Started Aug 06 07:47:18 PM PDT 24
Finished Aug 06 07:47:19 PM PDT 24
Peak memory 200148 kb
Host smart-643e9923-f6b6-439c-8d5a-ff776a4e2edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532136566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.532136566
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3964062819
Short name T357
Test name
Test status
Simulation time 1619998824 ps
CPU time 6.41 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200540 kb
Host smart-fb6067c9-73c4-4dc4-b220-9154c4b1f726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964062819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3964062819
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.976849295
Short name T503
Test name
Test status
Simulation time 158109078 ps
CPU time 1.11 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 200296 kb
Host smart-f0631689-9f7f-4b42-8b39-c4b8a5deee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976849295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.976849295
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4006502636
Short name T347
Test name
Test status
Simulation time 125980988 ps
CPU time 1.24 seconds
Started Aug 06 07:47:24 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200412 kb
Host smart-6270758b-6ffb-4067-a5c5-b8a217ec67ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006502636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4006502636
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1019111621
Short name T133
Test name
Test status
Simulation time 13331340687 ps
CPU time 48.35 seconds
Started Aug 06 07:47:24 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 208816 kb
Host smart-62ba39ce-27ca-4d1d-b6fa-97fb3726900f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019111621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1019111621
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3645448291
Short name T166
Test name
Test status
Simulation time 340615259 ps
CPU time 2.2 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:22 PM PDT 24
Peak memory 200316 kb
Host smart-add8a48d-6b26-4d6f-a0d8-7e0e123342b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645448291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3645448291
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1817683792
Short name T167
Test name
Test status
Simulation time 230858020 ps
CPU time 1.49 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:22 PM PDT 24
Peak memory 200472 kb
Host smart-7faae7c7-ca66-48eb-ae12-f58e0cc0df45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817683792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1817683792
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1534427720
Short name T502
Test name
Test status
Simulation time 84662406 ps
CPU time 0.84 seconds
Started Aug 06 07:47:25 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 200112 kb
Host smart-440f5d47-ec74-46ff-9e34-50239b490797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534427720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1534427720
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2114760942
Short name T40
Test name
Test status
Simulation time 1216871820 ps
CPU time 5.55 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 221624 kb
Host smart-3d3f9aa1-a53e-43ac-a2c9-092891ad527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114760942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2114760942
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.502158136
Short name T335
Test name
Test status
Simulation time 244153229 ps
CPU time 1.11 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 217508 kb
Host smart-11012cd0-1f1c-480e-bfbf-952c3560b0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502158136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.502158136
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2645788798
Short name T313
Test name
Test status
Simulation time 106412068 ps
CPU time 0.8 seconds
Started Aug 06 07:47:27 PM PDT 24
Finished Aug 06 07:47:28 PM PDT 24
Peak memory 200112 kb
Host smart-c8cb6f5e-0b5b-4255-83e4-5362b4f23281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645788798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2645788798
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3083410827
Short name T260
Test name
Test status
Simulation time 923416031 ps
CPU time 4.91 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:31 PM PDT 24
Peak memory 200508 kb
Host smart-0ae6a4b4-7a9e-4b2f-8278-88af3d58141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083410827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3083410827
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3324295138
Short name T270
Test name
Test status
Simulation time 97075678 ps
CPU time 0.99 seconds
Started Aug 06 07:47:24 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200348 kb
Host smart-5b1f0360-888c-429d-8d68-57bf2269e209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324295138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3324295138
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3814817569
Short name T264
Test name
Test status
Simulation time 115032630 ps
CPU time 1.16 seconds
Started Aug 06 07:47:14 PM PDT 24
Finished Aug 06 07:47:15 PM PDT 24
Peak memory 200488 kb
Host smart-2dd6c61d-31de-4129-b241-3862efadcae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814817569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3814817569
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.361563966
Short name T105
Test name
Test status
Simulation time 5884082759 ps
CPU time 26.63 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:50 PM PDT 24
Peak memory 210964 kb
Host smart-d5cf4dbe-e88a-4fef-a696-fc4284ec7b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361563966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.361563966
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.670774768
Short name T47
Test name
Test status
Simulation time 250206543 ps
CPU time 1.82 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200216 kb
Host smart-35ffc3fa-a370-452d-9bfb-c4d2db23e6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670774768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.670774768
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2384645168
Short name T168
Test name
Test status
Simulation time 185328342 ps
CPU time 1.22 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 200348 kb
Host smart-7822072f-1ce2-417e-9425-c59fdaa88c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384645168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2384645168
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2697700970
Short name T187
Test name
Test status
Simulation time 82367565 ps
CPU time 0.81 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 200140 kb
Host smart-e0586e01-60c7-47f3-85ba-febf2097c17a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697700970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2697700970
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2692482396
Short name T38
Test name
Test status
Simulation time 1225258573 ps
CPU time 5.97 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 221688 kb
Host smart-1a6029fb-64b4-4499-91f6-81109812b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692482396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2692482396
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1943810338
Short name T288
Test name
Test status
Simulation time 243867729 ps
CPU time 1.07 seconds
Started Aug 06 07:47:25 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 217520 kb
Host smart-c9618d06-173b-4b00-867a-20a595d19c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943810338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1943810338
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3137401635
Short name T23
Test name
Test status
Simulation time 92994888 ps
CPU time 0.73 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 200112 kb
Host smart-3a216bfe-56f4-4e08-a3d8-0fb73e246386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137401635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3137401635
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.184264111
Short name T443
Test name
Test status
Simulation time 1590758302 ps
CPU time 5.79 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200552 kb
Host smart-bcbf5923-49ad-4d02-8aa0-d0d1c1933245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184264111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.184264111
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3098551718
Short name T315
Test name
Test status
Simulation time 94492236 ps
CPU time 1.03 seconds
Started Aug 06 07:47:18 PM PDT 24
Finished Aug 06 07:47:19 PM PDT 24
Peak memory 200336 kb
Host smart-f4ef5324-9d8c-4b72-ab37-e65893a57d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098551718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3098551718
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2224277411
Short name T404
Test name
Test status
Simulation time 124778788 ps
CPU time 1.15 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:21 PM PDT 24
Peak memory 200416 kb
Host smart-d35771d4-e174-4202-853b-50fde22d7cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224277411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2224277411
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1603518710
Short name T445
Test name
Test status
Simulation time 9484320539 ps
CPU time 34.7 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:54 PM PDT 24
Peak memory 208816 kb
Host smart-52da38ac-c89e-40b4-8994-c37a9a659aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603518710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1603518710
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.4140658708
Short name T261
Test name
Test status
Simulation time 268581497 ps
CPU time 1.88 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200220 kb
Host smart-053eac07-2af4-4d40-a4ea-bc22459c7d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140658708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4140658708
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2878729717
Short name T10
Test name
Test status
Simulation time 171742049 ps
CPU time 1.11 seconds
Started Aug 06 07:47:25 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 200300 kb
Host smart-814bcb8d-c392-4f7a-9081-b380565b9cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878729717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2878729717
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4006948506
Short name T149
Test name
Test status
Simulation time 63565866 ps
CPU time 0.74 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 200168 kb
Host smart-e67ea2af-c011-43d7-aabb-7d4ed6502269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006948506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4006948506
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2523090432
Short name T62
Test name
Test status
Simulation time 2353882500 ps
CPU time 8.58 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:34 PM PDT 24
Peak memory 217848 kb
Host smart-30f91915-4d5f-4317-a5a7-3c5da9b9eb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523090432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2523090432
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.459307307
Short name T338
Test name
Test status
Simulation time 244903624 ps
CPU time 1.07 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 217520 kb
Host smart-6d3ca576-5a53-48dc-beca-0a2fea765aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459307307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.459307307
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3806294129
Short name T238
Test name
Test status
Simulation time 133413851 ps
CPU time 0.81 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 200188 kb
Host smart-95082d4f-39b1-4b6a-ac04-0de8d6e2cf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806294129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3806294129
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2837375481
Short name T29
Test name
Test status
Simulation time 1332161220 ps
CPU time 5.59 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 200444 kb
Host smart-78dd19b3-8864-41ab-b4bc-11a9a2733029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837375481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2837375481
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.931665306
Short name T250
Test name
Test status
Simulation time 184495738 ps
CPU time 1.14 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:21 PM PDT 24
Peak memory 200328 kb
Host smart-f02881b8-ec14-4131-9ba1-6b662f3ddf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931665306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.931665306
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1659901825
Short name T329
Test name
Test status
Simulation time 195285035 ps
CPU time 1.37 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:24 PM PDT 24
Peak memory 200484 kb
Host smart-98dbc2f0-370e-483b-9b6a-a82ee79be5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659901825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1659901825
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.427545618
Short name T108
Test name
Test status
Simulation time 7860677716 ps
CPU time 28.43 seconds
Started Aug 06 07:47:25 PM PDT 24
Finished Aug 06 07:47:53 PM PDT 24
Peak memory 200548 kb
Host smart-4699994d-8d0e-4eee-8889-8c5b73d304b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427545618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.427545618
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3383734596
Short name T412
Test name
Test status
Simulation time 260736087 ps
CPU time 1.98 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:22 PM PDT 24
Peak memory 200276 kb
Host smart-59d818e9-62ac-4eb9-ab8c-5331af305f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383734596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3383734596
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.3231820354
Short name T205
Test name
Test status
Simulation time 93791223 ps
CPU time 0.88 seconds
Started Aug 06 07:47:17 PM PDT 24
Finished Aug 06 07:47:18 PM PDT 24
Peak memory 200240 kb
Host smart-5bf7ee09-b309-48b4-b9ff-412c087c763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231820354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3231820354
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1205364654
Short name T257
Test name
Test status
Simulation time 72368972 ps
CPU time 0.84 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 200156 kb
Host smart-5eca4d69-39ed-4f9f-a27d-1711bda4841b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205364654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1205364654
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1199023491
Short name T55
Test name
Test status
Simulation time 2362719662 ps
CPU time 8.27 seconds
Started Aug 06 07:47:27 PM PDT 24
Finished Aug 06 07:47:35 PM PDT 24
Peak memory 217452 kb
Host smart-ad94322c-2566-45a3-a24c-d0f91ccf9baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199023491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1199023491
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.735287670
Short name T340
Test name
Test status
Simulation time 244153751 ps
CPU time 1.05 seconds
Started Aug 06 07:47:27 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 217588 kb
Host smart-ab4c2bd4-d26e-4b4e-af09-181fc8477bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735287670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.735287670
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3793800318
Short name T435
Test name
Test status
Simulation time 173124109 ps
CPU time 0.86 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:21 PM PDT 24
Peak memory 200128 kb
Host smart-370fe04d-32b2-4fb5-ab8b-be0772638b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793800318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3793800318
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1058122940
Short name T439
Test name
Test status
Simulation time 1546093302 ps
CPU time 6.21 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 200536 kb
Host smart-5a6cd115-253e-48f1-85fa-80c42e7b63f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058122940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1058122940
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.47224439
Short name T198
Test name
Test status
Simulation time 144373999 ps
CPU time 1.08 seconds
Started Aug 06 07:47:24 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200348 kb
Host smart-d2291162-f1ef-4deb-acf6-c6766a47dd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47224439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.47224439
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.85074534
Short name T528
Test name
Test status
Simulation time 121023268 ps
CPU time 1.19 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 200500 kb
Host smart-216a5173-94af-4cff-8d57-397386a2344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85074534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.85074534
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.672757024
Short name T485
Test name
Test status
Simulation time 7621343405 ps
CPU time 36.07 seconds
Started Aug 06 07:47:25 PM PDT 24
Finished Aug 06 07:48:02 PM PDT 24
Peak memory 208868 kb
Host smart-d74c7794-2c8e-4134-a72c-a49b6d91aa29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672757024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.672757024
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.333085495
Short name T235
Test name
Test status
Simulation time 447947804 ps
CPU time 2.38 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 200248 kb
Host smart-109d77f2-284e-47bc-8204-1af8daefa941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333085495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.333085495
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3703981619
Short name T292
Test name
Test status
Simulation time 89451668 ps
CPU time 0.84 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:21 PM PDT 24
Peak memory 200356 kb
Host smart-63a40f99-e765-494e-9c06-4ee1bdd9b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703981619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3703981619
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.464028865
Short name T202
Test name
Test status
Simulation time 80619134 ps
CPU time 0.75 seconds
Started Aug 06 07:47:21 PM PDT 24
Finished Aug 06 07:47:22 PM PDT 24
Peak memory 200100 kb
Host smart-88ee03e5-7765-4dd2-ae3d-11441aa49abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464028865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.464028865
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1516422812
Short name T42
Test name
Test status
Simulation time 1213788459 ps
CPU time 5.72 seconds
Started Aug 06 07:47:21 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 217708 kb
Host smart-4cb24c6d-1fa6-4a5e-bd20-dcff5a38eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516422812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1516422812
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1784949538
Short name T272
Test name
Test status
Simulation time 244651503 ps
CPU time 1.05 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:20 PM PDT 24
Peak memory 217432 kb
Host smart-9197d15f-dbdb-46da-96ac-d0e32f274512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784949538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1784949538
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4000088373
Short name T381
Test name
Test status
Simulation time 197874425 ps
CPU time 0.97 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:21 PM PDT 24
Peak memory 200040 kb
Host smart-7fe51168-5520-4f48-a0e4-79f08f3106ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000088373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4000088373
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3552650026
Short name T342
Test name
Test status
Simulation time 1804460760 ps
CPU time 7.65 seconds
Started Aug 06 07:47:25 PM PDT 24
Finished Aug 06 07:47:33 PM PDT 24
Peak memory 200504 kb
Host smart-c00f46d8-5550-47a7-a87a-89006e7fd1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552650026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3552650026
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2768714015
Short name T507
Test name
Test status
Simulation time 95399831 ps
CPU time 0.94 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 200312 kb
Host smart-d82b90f6-5562-42b0-8497-72a749811d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768714015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2768714015
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.358956491
Short name T526
Test name
Test status
Simulation time 189870589 ps
CPU time 1.39 seconds
Started Aug 06 07:47:21 PM PDT 24
Finished Aug 06 07:47:23 PM PDT 24
Peak memory 200432 kb
Host smart-3b0114ed-c892-40a3-a66f-f48cec906112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358956491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.358956491
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2435552367
Short name T542
Test name
Test status
Simulation time 10752952429 ps
CPU time 38.48 seconds
Started Aug 06 07:47:25 PM PDT 24
Finished Aug 06 07:48:04 PM PDT 24
Peak memory 200608 kb
Host smart-01a50e78-ea5f-49a7-b70e-fd0d9cc9d953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435552367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2435552367
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3380188311
Short name T86
Test name
Test status
Simulation time 377122596 ps
CPU time 2.5 seconds
Started Aug 06 07:47:24 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 200300 kb
Host smart-a059d118-e0eb-46b4-885c-3a692e0eb9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380188311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3380188311
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.209680764
Short name T506
Test name
Test status
Simulation time 214364051 ps
CPU time 1.33 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 200300 kb
Host smart-6634985f-b448-496e-b342-ddf9e85d02db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209680764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.209680764
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3256969461
Short name T364
Test name
Test status
Simulation time 58786424 ps
CPU time 0.78 seconds
Started Aug 06 07:47:28 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 200128 kb
Host smart-3c8480fc-5cf9-4797-8ee0-d00c7ab64aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256969461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3256969461
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2247400058
Short name T326
Test name
Test status
Simulation time 2369600226 ps
CPU time 8.22 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:35 PM PDT 24
Peak memory 217892 kb
Host smart-790375df-ea26-4cf2-b958-ec9aabaa1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247400058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2247400058
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3262186695
Short name T17
Test name
Test status
Simulation time 244951653 ps
CPU time 1.01 seconds
Started Aug 06 07:47:27 PM PDT 24
Finished Aug 06 07:47:28 PM PDT 24
Peak memory 217516 kb
Host smart-82244998-fde5-4f7e-a9fc-1f780e1e061c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262186695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3262186695
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2892546888
Short name T433
Test name
Test status
Simulation time 201110566 ps
CPU time 0.87 seconds
Started Aug 06 07:47:22 PM PDT 24
Finished Aug 06 07:47:23 PM PDT 24
Peak memory 200104 kb
Host smart-89835335-8674-4496-bb4e-c3edaf46c544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892546888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2892546888
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2502372588
Short name T419
Test name
Test status
Simulation time 952366523 ps
CPU time 4.51 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200516 kb
Host smart-5f03d6a2-4a9c-4f5c-bee5-36a5d6bd2fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502372588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2502372588
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3281521818
Short name T82
Test name
Test status
Simulation time 164737611 ps
CPU time 1.25 seconds
Started Aug 06 07:47:28 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 200324 kb
Host smart-c6edb2f3-b15b-4007-ac3f-a4f0cc848ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281521818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3281521818
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1254192858
Short name T320
Test name
Test status
Simulation time 123855119 ps
CPU time 1.22 seconds
Started Aug 06 07:47:24 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200540 kb
Host smart-1927c197-c29f-44b0-8c92-fff3161b0c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254192858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1254192858
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1480768797
Short name T216
Test name
Test status
Simulation time 5574483041 ps
CPU time 23.29 seconds
Started Aug 06 07:47:21 PM PDT 24
Finished Aug 06 07:47:44 PM PDT 24
Peak memory 200552 kb
Host smart-56e2574a-d5b5-403b-b3bd-7cda5df4b951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480768797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1480768797
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1935742769
Short name T164
Test name
Test status
Simulation time 362904201 ps
CPU time 2.24 seconds
Started Aug 06 07:47:19 PM PDT 24
Finished Aug 06 07:47:21 PM PDT 24
Peak memory 208436 kb
Host smart-a4f00487-9088-4973-a1b0-ce3b53ced400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935742769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1935742769
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2701258635
Short name T500
Test name
Test status
Simulation time 91314746 ps
CPU time 0.91 seconds
Started Aug 06 07:47:24 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200272 kb
Host smart-9ddb2ba8-e1da-4d17-9e04-0377061b95de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701258635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2701258635
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3330491998
Short name T369
Test name
Test status
Simulation time 66692347 ps
CPU time 0.75 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:44 PM PDT 24
Peak memory 200124 kb
Host smart-6adb6bbf-6abc-41be-9d3d-1cc3b588c3f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330491998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3330491998
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.4050495312
Short name T61
Test name
Test status
Simulation time 2363261154 ps
CPU time 8.21 seconds
Started Aug 06 07:46:46 PM PDT 24
Finished Aug 06 07:46:55 PM PDT 24
Peak memory 217820 kb
Host smart-8d2da751-bc8b-4ce9-8244-9a07cf715169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050495312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.4050495312
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.124987735
Short name T432
Test name
Test status
Simulation time 244785373 ps
CPU time 1.09 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 217444 kb
Host smart-ff8b3c79-4e3a-41e7-9979-d12be6bc26dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124987735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.124987735
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.4283214843
Short name T478
Test name
Test status
Simulation time 182230651 ps
CPU time 0.9 seconds
Started Aug 06 07:46:42 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200160 kb
Host smart-0d7f071e-e03c-4f35-a2b4-00af0470a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283214843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.4283214843
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.261578161
Short name T163
Test name
Test status
Simulation time 1042905999 ps
CPU time 5.31 seconds
Started Aug 06 07:46:39 PM PDT 24
Finished Aug 06 07:46:44 PM PDT 24
Peak memory 200552 kb
Host smart-a8b0b4c4-faec-4ded-995b-ae08c5cfd8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261578161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.261578161
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1039421571
Short name T74
Test name
Test status
Simulation time 8361393802 ps
CPU time 12.31 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:55 PM PDT 24
Peak memory 217704 kb
Host smart-f3d2440e-44c9-4eab-a75f-7dd62827dbde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039421571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1039421571
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3838249593
Short name T232
Test name
Test status
Simulation time 162579069 ps
CPU time 1.18 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 200352 kb
Host smart-d715bd4e-3ec6-4ad2-b2d5-4285ddc0eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838249593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3838249593
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2911232407
Short name T354
Test name
Test status
Simulation time 120582606 ps
CPU time 1.22 seconds
Started Aug 06 07:46:39 PM PDT 24
Finished Aug 06 07:46:40 PM PDT 24
Peak memory 200388 kb
Host smart-0f07b660-488b-490d-b175-de1182d4d4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911232407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2911232407
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3526583845
Short name T398
Test name
Test status
Simulation time 7345048619 ps
CPU time 24.96 seconds
Started Aug 06 07:46:42 PM PDT 24
Finished Aug 06 07:47:07 PM PDT 24
Peak memory 200560 kb
Host smart-653e10be-7772-415a-9d70-e9e3fed3f5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526583845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3526583845
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4100490656
Short name T207
Test name
Test status
Simulation time 536534446 ps
CPU time 2.62 seconds
Started Aug 06 07:46:44 PM PDT 24
Finished Aug 06 07:46:47 PM PDT 24
Peak memory 200284 kb
Host smart-36599a20-e65d-4334-bba5-704d4e4449fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100490656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4100490656
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3862465143
Short name T520
Test name
Test status
Simulation time 98864270 ps
CPU time 0.97 seconds
Started Aug 06 07:46:39 PM PDT 24
Finished Aug 06 07:46:40 PM PDT 24
Peak memory 200336 kb
Host smart-62ca2d4e-50f0-4a1e-aac2-1a3ddb2f688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862465143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3862465143
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3555656501
Short name T538
Test name
Test status
Simulation time 62652920 ps
CPU time 0.72 seconds
Started Aug 06 07:47:22 PM PDT 24
Finished Aug 06 07:47:23 PM PDT 24
Peak memory 200348 kb
Host smart-1c80546b-f3eb-4a21-9e67-945d91959cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555656501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3555656501
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.988619256
Short name T59
Test name
Test status
Simulation time 1225490015 ps
CPU time 5.33 seconds
Started Aug 06 07:47:22 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 221644 kb
Host smart-87674c2d-ee22-475e-ba9e-9d8b43393177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988619256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.988619256
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3408019413
Short name T293
Test name
Test status
Simulation time 245064789 ps
CPU time 1.01 seconds
Started Aug 06 07:47:27 PM PDT 24
Finished Aug 06 07:47:28 PM PDT 24
Peak memory 217584 kb
Host smart-35cf055d-2811-432a-9ee2-90b041ef1a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408019413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3408019413
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1554521161
Short name T415
Test name
Test status
Simulation time 208789060 ps
CPU time 0.97 seconds
Started Aug 06 07:47:21 PM PDT 24
Finished Aug 06 07:47:22 PM PDT 24
Peak memory 200072 kb
Host smart-4a0e622e-25f2-4f16-87d7-889cf241dbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554521161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1554521161
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1032249802
Short name T49
Test name
Test status
Simulation time 1976472278 ps
CPU time 7.4 seconds
Started Aug 06 07:47:21 PM PDT 24
Finished Aug 06 07:47:28 PM PDT 24
Peak memory 200520 kb
Host smart-44c519db-e1ce-464a-932e-4609005e0429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032249802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1032249802
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2557745411
Short name T413
Test name
Test status
Simulation time 113242275 ps
CPU time 0.96 seconds
Started Aug 06 07:47:24 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200356 kb
Host smart-67efa37e-c1df-4cac-9572-35463bc46034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557745411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2557745411
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3837440459
Short name T228
Test name
Test status
Simulation time 114454186 ps
CPU time 1.16 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:28 PM PDT 24
Peak memory 200440 kb
Host smart-3e2e6185-1066-472c-bd62-e3c3c3e1d1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837440459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3837440459
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3863033680
Short name T274
Test name
Test status
Simulation time 640701550 ps
CPU time 2.63 seconds
Started Aug 06 07:47:27 PM PDT 24
Finished Aug 06 07:47:30 PM PDT 24
Peak memory 200568 kb
Host smart-a5e31224-27ba-42a9-b9af-05b552efaf34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863033680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3863033680
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4070416968
Short name T92
Test name
Test status
Simulation time 369524950 ps
CPU time 2.48 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:26 PM PDT 24
Peak memory 200296 kb
Host smart-11a0ec75-9b63-4caf-9124-f10a5c0eaf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070416968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4070416968
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2765071666
Short name T134
Test name
Test status
Simulation time 149864353 ps
CPU time 1.24 seconds
Started Aug 06 07:47:27 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 200516 kb
Host smart-c3c8f451-04e0-4147-b197-261bc0faade7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765071666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2765071666
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.1444657802
Short name T307
Test name
Test status
Simulation time 68077777 ps
CPU time 0.81 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:24 PM PDT 24
Peak memory 200076 kb
Host smart-4c3db62f-e2ad-4aee-bd22-2dece99cc353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444657802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1444657802
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3412361179
Short name T37
Test name
Test status
Simulation time 1225834413 ps
CPU time 5.35 seconds
Started Aug 06 07:47:20 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 217676 kb
Host smart-f8be4073-906a-4868-a5a6-e3f3515b07ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412361179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3412361179
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3747773411
Short name T362
Test name
Test status
Simulation time 245616684 ps
CPU time 1 seconds
Started Aug 06 07:47:22 PM PDT 24
Finished Aug 06 07:47:24 PM PDT 24
Peak memory 217684 kb
Host smart-bf288c74-cd8e-44b9-b14f-a79a592796d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747773411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3747773411
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.74261359
Short name T469
Test name
Test status
Simulation time 161624426 ps
CPU time 0.91 seconds
Started Aug 06 07:47:28 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 200100 kb
Host smart-d5ce5150-0453-4e4d-8bec-35ded390db25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74261359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.74261359
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.1877937912
Short name T103
Test name
Test status
Simulation time 1674634775 ps
CPU time 6.39 seconds
Started Aug 06 07:47:27 PM PDT 24
Finished Aug 06 07:47:34 PM PDT 24
Peak memory 200520 kb
Host smart-6fe8206b-8c9d-467b-a69c-dd17285f4a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877937912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1877937912
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1591975128
Short name T360
Test name
Test status
Simulation time 152907930 ps
CPU time 1.16 seconds
Started Aug 06 07:47:28 PM PDT 24
Finished Aug 06 07:47:29 PM PDT 24
Peak memory 200296 kb
Host smart-9f966264-feba-4b6f-ba18-717d0230696a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591975128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1591975128
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3730327218
Short name T243
Test name
Test status
Simulation time 251738953 ps
CPU time 1.41 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:28 PM PDT 24
Peak memory 200512 kb
Host smart-561e87cb-8452-4d76-ac7b-1afca8b1851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730327218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3730327218
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.4166412085
Short name T83
Test name
Test status
Simulation time 1629920531 ps
CPU time 6.35 seconds
Started Aug 06 07:47:22 PM PDT 24
Finished Aug 06 07:47:28 PM PDT 24
Peak memory 200496 kb
Host smart-c3b90c19-bcc5-4fc6-881e-fe11f5b90699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166412085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4166412085
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.235318451
Short name T225
Test name
Test status
Simulation time 147206051 ps
CPU time 1.77 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:25 PM PDT 24
Peak memory 200240 kb
Host smart-7458a19e-b045-4e89-b00e-d9dbc3d40a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235318451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.235318451
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3614838643
Short name T373
Test name
Test status
Simulation time 223205372 ps
CPU time 1.32 seconds
Started Aug 06 07:47:26 PM PDT 24
Finished Aug 06 07:47:27 PM PDT 24
Peak memory 200296 kb
Host smart-9b64fdba-2959-4ebd-b2aa-d870fd9d7883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614838643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3614838643
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.422351132
Short name T154
Test name
Test status
Simulation time 62490442 ps
CPU time 0.76 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200168 kb
Host smart-fba48a8c-f176-4ff7-a136-7c083fd01a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422351132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.422351132
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.715594473
Short name T34
Test name
Test status
Simulation time 2174216594 ps
CPU time 7.87 seconds
Started Aug 06 07:47:37 PM PDT 24
Finished Aug 06 07:47:45 PM PDT 24
Peak memory 220984 kb
Host smart-3783c885-c879-4a35-8de3-a86ea184df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715594473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.715594473
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.862542756
Short name T399
Test name
Test status
Simulation time 243832643 ps
CPU time 1.12 seconds
Started Aug 06 07:47:33 PM PDT 24
Finished Aug 06 07:47:34 PM PDT 24
Peak memory 217684 kb
Host smart-3c594289-ceca-4091-b2a1-bd7968283b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862542756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.862542756
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3609899245
Short name T442
Test name
Test status
Simulation time 116121840 ps
CPU time 0.83 seconds
Started Aug 06 07:47:37 PM PDT 24
Finished Aug 06 07:47:38 PM PDT 24
Peak memory 200136 kb
Host smart-51ced5e2-8edd-4265-817b-21c8b41770c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609899245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3609899245
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1425662168
Short name T403
Test name
Test status
Simulation time 1936056046 ps
CPU time 6.69 seconds
Started Aug 06 07:47:31 PM PDT 24
Finished Aug 06 07:47:38 PM PDT 24
Peak memory 200584 kb
Host smart-25272768-1e60-4c80-85d8-b1e2488054b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425662168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1425662168
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.437385071
Short name T430
Test name
Test status
Simulation time 144201735 ps
CPU time 1.21 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200368 kb
Host smart-3fbae7aa-43a2-4c9e-b59d-67f20b5628e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437385071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.437385071
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.637688978
Short name T30
Test name
Test status
Simulation time 204073037 ps
CPU time 1.3 seconds
Started Aug 06 07:47:23 PM PDT 24
Finished Aug 06 07:47:24 PM PDT 24
Peak memory 200516 kb
Host smart-7864df98-2cb4-49f4-b2c9-3516457ae380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637688978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.637688978
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.4145249581
Short name T211
Test name
Test status
Simulation time 2971675558 ps
CPU time 13.12 seconds
Started Aug 06 07:47:32 PM PDT 24
Finished Aug 06 07:47:45 PM PDT 24
Peak memory 208788 kb
Host smart-12dbdfb6-1e3d-4951-8c14-fc670032f98a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145249581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4145249581
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3116103710
Short name T332
Test name
Test status
Simulation time 117448526 ps
CPU time 1.5 seconds
Started Aug 06 07:47:32 PM PDT 24
Finished Aug 06 07:47:34 PM PDT 24
Peak memory 200296 kb
Host smart-30cc348e-2b22-4756-896b-0d3c4333d033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116103710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3116103710
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2366306624
Short name T296
Test name
Test status
Simulation time 255322626 ps
CPU time 1.4 seconds
Started Aug 06 07:47:32 PM PDT 24
Finished Aug 06 07:47:34 PM PDT 24
Peak memory 200540 kb
Host smart-58e2bad4-adca-4a8c-b426-d24a577756c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366306624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2366306624
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1915267614
Short name T475
Test name
Test status
Simulation time 67698900 ps
CPU time 0.79 seconds
Started Aug 06 07:47:33 PM PDT 24
Finished Aug 06 07:47:34 PM PDT 24
Peak memory 200136 kb
Host smart-eaa5f5fe-0eaf-4fb8-abf6-8709c97b460b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915267614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1915267614
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.544742000
Short name T143
Test name
Test status
Simulation time 1220243717 ps
CPU time 5.71 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:45 PM PDT 24
Peak memory 217656 kb
Host smart-12a100c3-1f20-4f61-8533-11294993862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544742000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.544742000
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3640763046
Short name T517
Test name
Test status
Simulation time 244981294 ps
CPU time 1.05 seconds
Started Aug 06 07:47:38 PM PDT 24
Finished Aug 06 07:47:39 PM PDT 24
Peak memory 217528 kb
Host smart-b0aa255b-bd0a-4e81-b020-eabd02414e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640763046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3640763046
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2350954415
Short name T25
Test name
Test status
Simulation time 213448195 ps
CPU time 0.84 seconds
Started Aug 06 07:47:31 PM PDT 24
Finished Aug 06 07:47:32 PM PDT 24
Peak memory 200132 kb
Host smart-83fe6f96-a817-4ab4-9417-f8858ed09ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350954415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2350954415
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2343507930
Short name T56
Test name
Test status
Simulation time 1040005020 ps
CPU time 5.05 seconds
Started Aug 06 07:47:38 PM PDT 24
Finished Aug 06 07:47:43 PM PDT 24
Peak memory 200608 kb
Host smart-0c5cbd7c-0dc6-4144-bb00-72ea46123397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343507930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2343507930
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3888700316
Short name T417
Test name
Test status
Simulation time 113828190 ps
CPU time 1.02 seconds
Started Aug 06 07:47:31 PM PDT 24
Finished Aug 06 07:47:33 PM PDT 24
Peak memory 200296 kb
Host smart-4db3be7d-17e2-4885-8273-5872337f3e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888700316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3888700316
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.954769184
Short name T282
Test name
Test status
Simulation time 194111364 ps
CPU time 1.38 seconds
Started Aug 06 07:47:44 PM PDT 24
Finished Aug 06 07:47:45 PM PDT 24
Peak memory 200464 kb
Host smart-8f6910b2-7023-4f28-a523-95e8a9d6c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954769184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.954769184
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1346370900
Short name T467
Test name
Test status
Simulation time 4374730097 ps
CPU time 15.95 seconds
Started Aug 06 07:47:32 PM PDT 24
Finished Aug 06 07:47:48 PM PDT 24
Peak memory 200568 kb
Host smart-e18756bd-b061-477b-8359-6208d624c0ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346370900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1346370900
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1405676837
Short name T63
Test name
Test status
Simulation time 314334729 ps
CPU time 2.07 seconds
Started Aug 06 07:47:38 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 208408 kb
Host smart-a5b0a1f0-0af9-4abd-aa51-db1db4e3e17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405676837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1405676837
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.937907449
Short name T209
Test name
Test status
Simulation time 128035834 ps
CPU time 1.11 seconds
Started Aug 06 07:47:41 PM PDT 24
Finished Aug 06 07:47:43 PM PDT 24
Peak memory 200304 kb
Host smart-6d581668-2424-43e7-baa6-44e881e36810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937907449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.937907449
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2576072006
Short name T136
Test name
Test status
Simulation time 76576084 ps
CPU time 0.83 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200176 kb
Host smart-7be40470-d84a-48f2-a4c7-d37431e0df94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576072006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2576072006
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.876720063
Short name T263
Test name
Test status
Simulation time 1878799233 ps
CPU time 7.64 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:48 PM PDT 24
Peak memory 217368 kb
Host smart-9609fc04-5247-4e0a-850d-3aa47930ae28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876720063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.876720063
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1451750218
Short name T523
Test name
Test status
Simulation time 245744033 ps
CPU time 1.05 seconds
Started Aug 06 07:47:46 PM PDT 24
Finished Aug 06 07:47:47 PM PDT 24
Peak memory 217500 kb
Host smart-fb070ad7-657d-4f5b-85fa-3d877d1e5cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451750218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1451750218
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.810711859
Short name T193
Test name
Test status
Simulation time 219655448 ps
CPU time 0.94 seconds
Started Aug 06 07:47:37 PM PDT 24
Finished Aug 06 07:47:38 PM PDT 24
Peak memory 200136 kb
Host smart-5042fbc4-418b-4bdc-976c-266d720f693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810711859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.810711859
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.228728409
Short name T462
Test name
Test status
Simulation time 707792192 ps
CPU time 3.96 seconds
Started Aug 06 07:47:31 PM PDT 24
Finished Aug 06 07:47:35 PM PDT 24
Peak memory 200516 kb
Host smart-71c4c5ed-b057-4768-936e-6383447792e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228728409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.228728409
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1638331189
Short name T287
Test name
Test status
Simulation time 102285541 ps
CPU time 0.96 seconds
Started Aug 06 07:47:37 PM PDT 24
Finished Aug 06 07:47:38 PM PDT 24
Peak memory 200336 kb
Host smart-584fcd46-1fb7-436e-b0d5-6ca99eb86eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638331189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1638331189
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1305818212
Short name T266
Test name
Test status
Simulation time 199196876 ps
CPU time 1.37 seconds
Started Aug 06 07:47:41 PM PDT 24
Finished Aug 06 07:47:43 PM PDT 24
Peak memory 200444 kb
Host smart-eb6ab2c4-1d28-468d-868f-dd795ffa3946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305818212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1305818212
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2515204793
Short name T91
Test name
Test status
Simulation time 14768940509 ps
CPU time 55.12 seconds
Started Aug 06 07:47:38 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 200596 kb
Host smart-d3ffb751-fdb5-4709-b322-3da37c6093ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515204793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2515204793
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1964023129
Short name T180
Test name
Test status
Simulation time 403416232 ps
CPU time 2.2 seconds
Started Aug 06 07:47:33 PM PDT 24
Finished Aug 06 07:47:36 PM PDT 24
Peak memory 200272 kb
Host smart-0f0d7e16-d67e-4939-af3b-8cb5ea67d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964023129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1964023129
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1530690775
Short name T138
Test name
Test status
Simulation time 302785885 ps
CPU time 1.57 seconds
Started Aug 06 07:47:31 PM PDT 24
Finished Aug 06 07:47:33 PM PDT 24
Peak memory 200472 kb
Host smart-aebd3ffb-2d62-4c07-8be0-0882b64951b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530690775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1530690775
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2480191642
Short name T194
Test name
Test status
Simulation time 70778753 ps
CPU time 0.8 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200172 kb
Host smart-2fc1cb33-3983-49cc-9e38-d2026cf1bd06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480191642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2480191642
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1609566174
Short name T543
Test name
Test status
Simulation time 2341128301 ps
CPU time 8.78 seconds
Started Aug 06 07:47:41 PM PDT 24
Finished Aug 06 07:47:50 PM PDT 24
Peak memory 217852 kb
Host smart-a5b6d773-4dbd-43c2-99d7-4971bef47aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609566174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1609566174
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2806410082
Short name T447
Test name
Test status
Simulation time 244706269 ps
CPU time 1.04 seconds
Started Aug 06 07:47:46 PM PDT 24
Finished Aug 06 07:47:48 PM PDT 24
Peak memory 217476 kb
Host smart-719ddb80-e565-42d4-bd2a-5bea58f8465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806410082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2806410082
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2798461341
Short name T372
Test name
Test status
Simulation time 171859094 ps
CPU time 0.87 seconds
Started Aug 06 07:47:32 PM PDT 24
Finished Aug 06 07:47:33 PM PDT 24
Peak memory 200092 kb
Host smart-3a506879-62a0-47ac-86b8-6a4a021a139f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798461341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2798461341
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2741528157
Short name T219
Test name
Test status
Simulation time 1459908626 ps
CPU time 6.32 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:46 PM PDT 24
Peak memory 200468 kb
Host smart-2971b5b8-709a-4748-936b-537e7b92c6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741528157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2741528157
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4137327646
Short name T223
Test name
Test status
Simulation time 99203952 ps
CPU time 0.95 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200292 kb
Host smart-048f6110-7603-4c36-8349-08bf1335a620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137327646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4137327646
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2266117292
Short name T356
Test name
Test status
Simulation time 258534217 ps
CPU time 1.43 seconds
Started Aug 06 07:47:34 PM PDT 24
Finished Aug 06 07:47:35 PM PDT 24
Peak memory 200456 kb
Host smart-5e041a4e-d55c-4532-85ec-2651b2534573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266117292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2266117292
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3464829006
Short name T512
Test name
Test status
Simulation time 2411469608 ps
CPU time 8.63 seconds
Started Aug 06 07:47:33 PM PDT 24
Finished Aug 06 07:47:41 PM PDT 24
Peak memory 208856 kb
Host smart-ff69501c-d5e3-43d8-8c85-7b9e320ebfd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464829006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3464829006
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4008164751
Short name T140
Test name
Test status
Simulation time 467164223 ps
CPU time 2.48 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:42 PM PDT 24
Peak memory 200216 kb
Host smart-2a57609f-a7f8-4a64-b672-6fc69c8df77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008164751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4008164751
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.308702272
Short name T258
Test name
Test status
Simulation time 74661284 ps
CPU time 0.79 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200292 kb
Host smart-dec44afa-7489-49e5-822c-55e65f7fb881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308702272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.308702272
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3408138949
Short name T283
Test name
Test status
Simulation time 64036624 ps
CPU time 0.74 seconds
Started Aug 06 07:47:46 PM PDT 24
Finished Aug 06 07:47:47 PM PDT 24
Peak memory 200112 kb
Host smart-c04605c7-70a7-4c0d-83d3-fe0f41a0f933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408138949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3408138949
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.4179018027
Short name T41
Test name
Test status
Simulation time 1902131061 ps
CPU time 7.38 seconds
Started Aug 06 07:47:45 PM PDT 24
Finished Aug 06 07:47:52 PM PDT 24
Peak memory 217760 kb
Host smart-5949b87a-3f73-41c3-9e12-e7ec07a48360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179018027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.4179018027
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3338048641
Short name T278
Test name
Test status
Simulation time 243737084 ps
CPU time 1.17 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:41 PM PDT 24
Peak memory 217408 kb
Host smart-19ed6535-5c04-4075-89a7-081f69feb082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338048641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3338048641
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3145803627
Short name T480
Test name
Test status
Simulation time 191034181 ps
CPU time 0.97 seconds
Started Aug 06 07:47:38 PM PDT 24
Finished Aug 06 07:47:39 PM PDT 24
Peak memory 200168 kb
Host smart-362beffd-14c2-400d-9ebf-d59d91dda2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145803627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3145803627
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1666677699
Short name T215
Test name
Test status
Simulation time 618170582 ps
CPU time 3.49 seconds
Started Aug 06 07:47:37 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200560 kb
Host smart-16390e15-6dee-4657-8979-ac86c256a48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666677699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1666677699
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3877468300
Short name T248
Test name
Test status
Simulation time 103492974 ps
CPU time 1 seconds
Started Aug 06 07:47:44 PM PDT 24
Finished Aug 06 07:47:46 PM PDT 24
Peak memory 200296 kb
Host smart-252f7e98-7140-4ac4-b1f7-f7eace9160e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877468300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3877468300
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3008491046
Short name T44
Test name
Test status
Simulation time 249500197 ps
CPU time 1.62 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:42 PM PDT 24
Peak memory 200488 kb
Host smart-5372d104-1fe6-4c22-88aa-abacd8e62a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008491046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3008491046
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3828799355
Short name T385
Test name
Test status
Simulation time 3228636333 ps
CPU time 13.71 seconds
Started Aug 06 07:47:45 PM PDT 24
Finished Aug 06 07:47:59 PM PDT 24
Peak memory 200588 kb
Host smart-c0dc405a-63fc-4adb-9d5d-5114faa4baad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828799355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3828799355
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.3602746569
Short name T141
Test name
Test status
Simulation time 508334735 ps
CPU time 2.66 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:42 PM PDT 24
Peak memory 200212 kb
Host smart-f020fc97-ce16-4fbd-bad6-c595a56c1889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602746569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3602746569
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1256684729
Short name T494
Test name
Test status
Simulation time 101540974 ps
CPU time 0.94 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:41 PM PDT 24
Peak memory 200296 kb
Host smart-5d9646ad-c55a-47d2-90af-5910741370e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256684729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1256684729
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.526789975
Short name T80
Test name
Test status
Simulation time 68447199 ps
CPU time 0.75 seconds
Started Aug 06 07:47:38 PM PDT 24
Finished Aug 06 07:47:39 PM PDT 24
Peak memory 200136 kb
Host smart-bbf3df34-0267-46d3-b639-f358a463a84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526789975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.526789975
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.4133758503
Short name T498
Test name
Test status
Simulation time 2361040213 ps
CPU time 7.87 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:48 PM PDT 24
Peak memory 217752 kb
Host smart-72b6f982-ec4b-4882-a091-160eaee9c55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133758503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.4133758503
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.448590926
Short name T444
Test name
Test status
Simulation time 246618438 ps
CPU time 1.04 seconds
Started Aug 06 07:47:41 PM PDT 24
Finished Aug 06 07:47:42 PM PDT 24
Peak memory 217488 kb
Host smart-b858f108-2251-4921-bf81-950facb589e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448590926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.448590926
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.688015110
Short name T489
Test name
Test status
Simulation time 140234597 ps
CPU time 0.84 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200132 kb
Host smart-42d1a655-4003-4e4c-b02d-515b9a3586ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688015110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.688015110
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.19813504
Short name T536
Test name
Test status
Simulation time 1558408770 ps
CPU time 6.47 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:47 PM PDT 24
Peak memory 200432 kb
Host smart-2468e489-15be-4ff7-b5a3-1a2a91e6068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19813504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.19813504
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.692700796
Short name T176
Test name
Test status
Simulation time 161829848 ps
CPU time 1.17 seconds
Started Aug 06 07:47:41 PM PDT 24
Finished Aug 06 07:47:42 PM PDT 24
Peak memory 200236 kb
Host smart-6a8f4ebb-dd42-4ce9-8bb6-5e6f366db164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692700796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.692700796
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2770013591
Short name T297
Test name
Test status
Simulation time 196527019 ps
CPU time 1.36 seconds
Started Aug 06 07:47:45 PM PDT 24
Finished Aug 06 07:47:47 PM PDT 24
Peak memory 200508 kb
Host smart-764e522f-90a1-412b-a340-d799326ca02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770013591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2770013591
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.738881968
Short name T331
Test name
Test status
Simulation time 14017717202 ps
CPU time 49.04 seconds
Started Aug 06 07:47:44 PM PDT 24
Finished Aug 06 07:48:33 PM PDT 24
Peak memory 200568 kb
Host smart-07de6f87-88de-4460-9818-2963a986800d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738881968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.738881968
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3881919791
Short name T448
Test name
Test status
Simulation time 491320119 ps
CPU time 2.47 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:42 PM PDT 24
Peak memory 200176 kb
Host smart-50075845-005a-47f5-93ae-15f1d3057945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881919791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3881919791
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1890243814
Short name T311
Test name
Test status
Simulation time 172528191 ps
CPU time 1.27 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:42 PM PDT 24
Peak memory 200364 kb
Host smart-95a740cc-c33f-48f3-a455-c3b4ec065eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890243814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1890243814
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2625177149
Short name T218
Test name
Test status
Simulation time 75201322 ps
CPU time 0.8 seconds
Started Aug 06 07:47:49 PM PDT 24
Finished Aug 06 07:47:50 PM PDT 24
Peak memory 200156 kb
Host smart-8e7379d3-e854-4a70-b5b2-2d29618582a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625177149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2625177149
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3906699270
Short name T396
Test name
Test status
Simulation time 1224908527 ps
CPU time 5.81 seconds
Started Aug 06 07:47:46 PM PDT 24
Finished Aug 06 07:47:52 PM PDT 24
Peak memory 216836 kb
Host smart-acfc3610-4f0c-4b41-ace3-beda552dccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906699270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3906699270
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2222619391
Short name T309
Test name
Test status
Simulation time 244865313 ps
CPU time 1.01 seconds
Started Aug 06 07:47:51 PM PDT 24
Finished Aug 06 07:47:52 PM PDT 24
Peak memory 217440 kb
Host smart-f3b1f744-d2d7-4789-a408-9491d4092d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222619391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2222619391
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3888111130
Short name T21
Test name
Test status
Simulation time 156232360 ps
CPU time 0.81 seconds
Started Aug 06 07:47:40 PM PDT 24
Finished Aug 06 07:47:40 PM PDT 24
Peak memory 200144 kb
Host smart-67956044-0cb0-405f-9a86-689ac427ce0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888111130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3888111130
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2007151325
Short name T383
Test name
Test status
Simulation time 794405117 ps
CPU time 3.79 seconds
Started Aug 06 07:47:47 PM PDT 24
Finished Aug 06 07:47:51 PM PDT 24
Peak memory 200604 kb
Host smart-9134cb85-e003-4941-a2c2-c7a8d462eea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007151325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2007151325
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.4095711761
Short name T324
Test name
Test status
Simulation time 143820814 ps
CPU time 1.11 seconds
Started Aug 06 07:47:48 PM PDT 24
Finished Aug 06 07:47:49 PM PDT 24
Peak memory 200364 kb
Host smart-a2a4a16b-09b6-46ba-b7de-ba4b9f2e7a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095711761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.4095711761
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.961358105
Short name T252
Test name
Test status
Simulation time 234166275 ps
CPU time 1.53 seconds
Started Aug 06 07:47:39 PM PDT 24
Finished Aug 06 07:47:41 PM PDT 24
Peak memory 200512 kb
Host smart-dc920ac0-d793-46b8-950f-31eef1b0fe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961358105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.961358105
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3136850876
Short name T12
Test name
Test status
Simulation time 137538304 ps
CPU time 1.11 seconds
Started Aug 06 07:47:47 PM PDT 24
Finished Aug 06 07:47:49 PM PDT 24
Peak memory 200340 kb
Host smart-96ab269d-9d8a-47de-8814-371b5a248272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136850876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3136850876
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.485523034
Short name T361
Test name
Test status
Simulation time 326481877 ps
CPU time 1.99 seconds
Started Aug 06 07:47:47 PM PDT 24
Finished Aug 06 07:47:49 PM PDT 24
Peak memory 200240 kb
Host smart-a04667a5-1619-485f-b493-d5b4e09845ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485523034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.485523034
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2976362131
Short name T256
Test name
Test status
Simulation time 218785689 ps
CPU time 1.29 seconds
Started Aug 06 07:47:48 PM PDT 24
Finished Aug 06 07:47:49 PM PDT 24
Peak memory 200288 kb
Host smart-d8134d88-60a2-48f8-9dc8-71dd31917e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976362131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2976362131
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3951345228
Short name T513
Test name
Test status
Simulation time 81945457 ps
CPU time 0.78 seconds
Started Aug 06 07:47:48 PM PDT 24
Finished Aug 06 07:47:49 PM PDT 24
Peak memory 200112 kb
Host smart-82772f0d-defe-4585-a15e-5cf04b7c8b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951345228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3951345228
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.828181112
Short name T51
Test name
Test status
Simulation time 1214783538 ps
CPU time 5.37 seconds
Started Aug 06 07:47:45 PM PDT 24
Finished Aug 06 07:47:50 PM PDT 24
Peak memory 221748 kb
Host smart-eb28a656-fa59-4d6b-a1ef-4ccfd68ff48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828181112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.828181112
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.155355126
Short name T466
Test name
Test status
Simulation time 243992503 ps
CPU time 1.07 seconds
Started Aug 06 07:47:49 PM PDT 24
Finished Aug 06 07:47:50 PM PDT 24
Peak memory 217444 kb
Host smart-fb9153c9-a663-4247-80b2-bfecda9488c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155355126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.155355126
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2974097232
Short name T490
Test name
Test status
Simulation time 144038824 ps
CPU time 0.82 seconds
Started Aug 06 07:47:47 PM PDT 24
Finished Aug 06 07:47:48 PM PDT 24
Peak memory 200104 kb
Host smart-1e5a6a3e-edff-46a6-b3c7-477e3c0ba487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974097232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2974097232
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.996356586
Short name T298
Test name
Test status
Simulation time 1252917736 ps
CPU time 5.6 seconds
Started Aug 06 07:47:49 PM PDT 24
Finished Aug 06 07:47:55 PM PDT 24
Peak memory 200592 kb
Host smart-a489d546-afed-4e42-b079-507fe479117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996356586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.996356586
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1961379720
Short name T135
Test name
Test status
Simulation time 170148285 ps
CPU time 1.23 seconds
Started Aug 06 07:47:52 PM PDT 24
Finished Aug 06 07:47:53 PM PDT 24
Peak memory 200348 kb
Host smart-beb2b2c5-f8d0-4cb9-b364-c4b0f4e68776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961379720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1961379720
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.252585592
Short name T457
Test name
Test status
Simulation time 228486917 ps
CPU time 1.42 seconds
Started Aug 06 07:47:50 PM PDT 24
Finished Aug 06 07:47:51 PM PDT 24
Peak memory 200440 kb
Host smart-4a1a472b-e3ca-4a1a-ae23-6fd6bc477e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252585592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.252585592
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.533691795
Short name T323
Test name
Test status
Simulation time 3816104028 ps
CPU time 16.71 seconds
Started Aug 06 07:47:52 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 200660 kb
Host smart-6990fdf1-7110-4d14-88dd-7aa184abe9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533691795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.533691795
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3390151818
Short name T484
Test name
Test status
Simulation time 421793300 ps
CPU time 2.51 seconds
Started Aug 06 07:47:49 PM PDT 24
Finished Aug 06 07:47:52 PM PDT 24
Peak memory 208472 kb
Host smart-b358d35f-c170-4169-ae90-1d36ca503568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390151818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3390151818
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.3611561228
Short name T221
Test name
Test status
Simulation time 205359532 ps
CPU time 1.28 seconds
Started Aug 06 07:47:50 PM PDT 24
Finished Aug 06 07:47:51 PM PDT 24
Peak memory 200340 kb
Host smart-dbc4caa0-c47b-4fa0-9a4a-ef16fdb11946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611561228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3611561228
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.674476067
Short name T4
Test name
Test status
Simulation time 57118804 ps
CPU time 0.75 seconds
Started Aug 06 07:46:41 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 200096 kb
Host smart-fe4b714c-4d08-4c86-819a-cf0bca0d2317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674476067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.674476067
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3570674301
Short name T451
Test name
Test status
Simulation time 1223542127 ps
CPU time 5.48 seconds
Started Aug 06 07:46:45 PM PDT 24
Finished Aug 06 07:46:51 PM PDT 24
Peak memory 217752 kb
Host smart-6b8ea08d-9d2f-43e6-b9ac-d56ab7ed062f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570674301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3570674301
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1911281125
Short name T249
Test name
Test status
Simulation time 244542385 ps
CPU time 1.1 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:45 PM PDT 24
Peak memory 217684 kb
Host smart-6c3db9b2-ef7e-4476-a0cd-720a526783fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911281125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1911281125
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.306955838
Short name T370
Test name
Test status
Simulation time 141157117 ps
CPU time 0.81 seconds
Started Aug 06 07:46:39 PM PDT 24
Finished Aug 06 07:46:40 PM PDT 24
Peak memory 200148 kb
Host smart-8f0e2cf5-bc6c-4df5-9d32-91c78e1b35e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306955838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.306955838
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.567634009
Short name T99
Test name
Test status
Simulation time 1008202244 ps
CPU time 5.45 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:45 PM PDT 24
Peak memory 200512 kb
Host smart-489b3394-2974-45bc-a257-fd0f1516124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567634009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.567634009
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1872024079
Short name T77
Test name
Test status
Simulation time 8315224654 ps
CPU time 13.17 seconds
Started Aug 06 07:46:41 PM PDT 24
Finished Aug 06 07:46:55 PM PDT 24
Peak memory 217356 kb
Host smart-202affb7-52c3-4a2a-a0a5-1d29fdb97ab7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872024079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1872024079
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2573744819
Short name T418
Test name
Test status
Simulation time 98154889 ps
CPU time 1 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:44 PM PDT 24
Peak memory 200300 kb
Host smart-b70077d2-46cd-4acf-a097-b9a8bd81c6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573744819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2573744819
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3838045349
Short name T88
Test name
Test status
Simulation time 195539107 ps
CPU time 1.48 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:42 PM PDT 24
Peak memory 200380 kb
Host smart-8522d8e8-c728-41c4-8948-9921fabb8d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838045349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3838045349
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2730922544
Short name T531
Test name
Test status
Simulation time 1244875709 ps
CPU time 6.03 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:50 PM PDT 24
Peak memory 200468 kb
Host smart-b63200b3-6065-4d8b-bd6f-26d05e71ab1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730922544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2730922544
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.2704408448
Short name T446
Test name
Test status
Simulation time 361655114 ps
CPU time 2.3 seconds
Started Aug 06 07:46:41 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200224 kb
Host smart-fd4d222e-e0f7-4955-a4f2-f448498785aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704408448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2704408448
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2526311319
Short name T290
Test name
Test status
Simulation time 86869840 ps
CPU time 0.86 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200132 kb
Host smart-0e7cfc7d-20f1-45e3-ab68-2d9b5d7eeeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526311319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2526311319
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.623150880
Short name T28
Test name
Test status
Simulation time 1885680277 ps
CPU time 7.77 seconds
Started Aug 06 07:47:49 PM PDT 24
Finished Aug 06 07:47:57 PM PDT 24
Peak memory 217776 kb
Host smart-4e17a6b9-8fe9-405d-838c-d5be76bca4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623150880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.623150880
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2649798541
Short name T262
Test name
Test status
Simulation time 244524828 ps
CPU time 1.19 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 217596 kb
Host smart-ff7d35a7-a660-492d-9ba3-505e2e1e39e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649798541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2649798541
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.861552584
Short name T18
Test name
Test status
Simulation time 129825654 ps
CPU time 0.82 seconds
Started Aug 06 07:47:47 PM PDT 24
Finished Aug 06 07:47:48 PM PDT 24
Peak memory 200104 kb
Host smart-a7b5646d-b238-48b2-b6c4-cb73eb033c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861552584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.861552584
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1600422939
Short name T522
Test name
Test status
Simulation time 655087538 ps
CPU time 3.59 seconds
Started Aug 06 07:47:47 PM PDT 24
Finished Aug 06 07:47:50 PM PDT 24
Peak memory 200544 kb
Host smart-82c6fe19-c68b-4f1f-a9b0-bc7537b7a2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600422939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1600422939
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.4086579756
Short name T156
Test name
Test status
Simulation time 153248060 ps
CPU time 1.12 seconds
Started Aug 06 07:47:48 PM PDT 24
Finished Aug 06 07:47:49 PM PDT 24
Peak memory 200280 kb
Host smart-fe262a01-6d15-4ca5-ab3c-a0a06d6e2bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086579756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.4086579756
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1109107379
Short name T150
Test name
Test status
Simulation time 190483737 ps
CPU time 1.34 seconds
Started Aug 06 07:47:49 PM PDT 24
Finished Aug 06 07:47:50 PM PDT 24
Peak memory 200428 kb
Host smart-537b2ffb-3d85-40b1-bfc1-9e417f58abdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109107379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1109107379
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2198006680
Short name T89
Test name
Test status
Simulation time 4240274610 ps
CPU time 18.37 seconds
Started Aug 06 07:48:06 PM PDT 24
Finished Aug 06 07:48:24 PM PDT 24
Peak memory 200604 kb
Host smart-a90ead7b-7103-4434-9ef4-7a8ff672bc13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198006680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2198006680
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3619122806
Short name T45
Test name
Test status
Simulation time 334532274 ps
CPU time 1.99 seconds
Started Aug 06 07:47:48 PM PDT 24
Finished Aug 06 07:47:50 PM PDT 24
Peak memory 200240 kb
Host smart-1e0e6064-9661-48b3-94e7-2c3d6e019b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619122806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3619122806
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.382189966
Short name T371
Test name
Test status
Simulation time 104481270 ps
CPU time 0.94 seconds
Started Aug 06 07:47:47 PM PDT 24
Finished Aug 06 07:47:48 PM PDT 24
Peak memory 200296 kb
Host smart-0500a2b4-88c9-4891-a10e-57cd019e1071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382189966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.382189966
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3867380432
Short name T345
Test name
Test status
Simulation time 66358711 ps
CPU time 0.75 seconds
Started Aug 06 07:48:05 PM PDT 24
Finished Aug 06 07:48:06 PM PDT 24
Peak memory 200112 kb
Host smart-92f17cea-8b41-4507-9a70-eea7eb5ab9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867380432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3867380432
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3229091112
Short name T240
Test name
Test status
Simulation time 2361767324 ps
CPU time 8.98 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:19 PM PDT 24
Peak memory 217812 kb
Host smart-885fe8fa-5e13-4dc3-bf48-ac56ea6aac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229091112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3229091112
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2715613215
Short name T358
Test name
Test status
Simulation time 245039790 ps
CPU time 1.06 seconds
Started Aug 06 07:48:06 PM PDT 24
Finished Aug 06 07:48:07 PM PDT 24
Peak memory 217544 kb
Host smart-49c3db33-d312-4848-9c0f-2e9cd55b8989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715613215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2715613215
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3936169347
Short name T279
Test name
Test status
Simulation time 118399981 ps
CPU time 0.81 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 200132 kb
Host smart-1e58fc05-5375-4bcb-9ff1-420cf15860b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936169347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3936169347
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2556684012
Short name T129
Test name
Test status
Simulation time 2025513839 ps
CPU time 6.95 seconds
Started Aug 06 07:48:04 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 200528 kb
Host smart-e729276c-9407-451c-8f1e-73a5021cfa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556684012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2556684012
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.791404089
Short name T52
Test name
Test status
Simulation time 179439189 ps
CPU time 1.28 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 200304 kb
Host smart-190e60f5-c24b-412f-b826-9cca51fa7838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791404089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.791404089
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1412814684
Short name T456
Test name
Test status
Simulation time 124819189 ps
CPU time 1.15 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:08 PM PDT 24
Peak memory 200484 kb
Host smart-0f0efc61-ac6e-41d6-bf7b-2fa9a57a7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412814684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1412814684
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4000679269
Short name T496
Test name
Test status
Simulation time 6497997800 ps
CPU time 23.25 seconds
Started Aug 06 07:48:06 PM PDT 24
Finished Aug 06 07:48:30 PM PDT 24
Peak memory 200592 kb
Host smart-c931d4b4-b198-4612-b2cf-12a0b774172f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000679269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4000679269
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1135482708
Short name T251
Test name
Test status
Simulation time 385913957 ps
CPU time 2.19 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200272 kb
Host smart-235aee91-4359-480f-8655-cc95f45a5f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135482708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1135482708
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3901704497
Short name T487
Test name
Test status
Simulation time 102735806 ps
CPU time 0.94 seconds
Started Aug 06 07:48:06 PM PDT 24
Finished Aug 06 07:48:07 PM PDT 24
Peak memory 200340 kb
Host smart-5270a1e8-becc-48e6-9d7e-4cf0db8b3855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901704497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3901704497
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3282817223
Short name T170
Test name
Test status
Simulation time 90953468 ps
CPU time 0.83 seconds
Started Aug 06 07:48:06 PM PDT 24
Finished Aug 06 07:48:07 PM PDT 24
Peak memory 200156 kb
Host smart-7fd513d0-d0e6-4ddc-8bb4-4e9443cceeb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282817223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3282817223
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2446649952
Short name T60
Test name
Test status
Simulation time 1876621263 ps
CPU time 7.13 seconds
Started Aug 06 07:48:06 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 217664 kb
Host smart-fca92cb5-6b77-46b1-bb37-12d4ece8ed8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446649952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2446649952
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2611220308
Short name T2
Test name
Test status
Simulation time 245647980 ps
CPU time 1.05 seconds
Started Aug 06 07:48:05 PM PDT 24
Finished Aug 06 07:48:07 PM PDT 24
Peak memory 217540 kb
Host smart-d145bfad-09ee-466d-9e8b-d66d4c2e430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611220308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2611220308
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1004080249
Short name T19
Test name
Test status
Simulation time 180037443 ps
CPU time 0.92 seconds
Started Aug 06 07:48:06 PM PDT 24
Finished Aug 06 07:48:07 PM PDT 24
Peak memory 200144 kb
Host smart-a4222fc6-7443-4eaa-b3ac-00ac443963b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004080249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1004080249
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1923355142
Short name T189
Test name
Test status
Simulation time 1427960360 ps
CPU time 6.54 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 200648 kb
Host smart-5915bdd2-54a3-4c8e-9161-fd5c6d30d72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923355142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1923355142
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.64290377
Short name T247
Test name
Test status
Simulation time 174577210 ps
CPU time 1.13 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 200332 kb
Host smart-bfcc37f4-c6d4-48d5-9c2d-db87bf91456b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64290377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.64290377
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1763253238
Short name T450
Test name
Test status
Simulation time 235077266 ps
CPU time 1.44 seconds
Started Aug 06 07:48:05 PM PDT 24
Finished Aug 06 07:48:07 PM PDT 24
Peak memory 200408 kb
Host smart-d7ca2358-3df1-40a8-8e0d-c055c86c7a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763253238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1763253238
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2179583463
Short name T363
Test name
Test status
Simulation time 7372093650 ps
CPU time 24.04 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:36 PM PDT 24
Peak memory 208788 kb
Host smart-15baeee0-204e-44d1-94e5-45caddbd61d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179583463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2179583463
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.807018736
Short name T11
Test name
Test status
Simulation time 456747117 ps
CPU time 2.45 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 208404 kb
Host smart-4dbdc188-98bc-45b3-b0f2-a17c207c9f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807018736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.807018736
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3457285357
Short name T336
Test name
Test status
Simulation time 304941819 ps
CPU time 1.61 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 200468 kb
Host smart-23a9022b-69ce-42e8-af5d-f357fa3385a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457285357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3457285357
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2187503143
Short name T476
Test name
Test status
Simulation time 84536847 ps
CPU time 0.81 seconds
Started Aug 06 07:48:06 PM PDT 24
Finished Aug 06 07:48:07 PM PDT 24
Peak memory 200112 kb
Host smart-afb25891-13dc-4811-a545-39b275f820e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187503143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2187503143
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.62177691
Short name T245
Test name
Test status
Simulation time 1898540489 ps
CPU time 7.14 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:16 PM PDT 24
Peak memory 217796 kb
Host smart-ccc5ee9e-4254-4206-b227-10019b54054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62177691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.62177691
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2779602735
Short name T411
Test name
Test status
Simulation time 243871493 ps
CPU time 1.05 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 217592 kb
Host smart-ea29812f-d225-4479-8003-67f59156a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779602735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2779602735
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1885087416
Short name T24
Test name
Test status
Simulation time 129773000 ps
CPU time 0.82 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 200104 kb
Host smart-348c8d98-79d0-4c2c-9afa-944396644f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885087416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1885087416
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.4277669649
Short name T348
Test name
Test status
Simulation time 1346948509 ps
CPU time 5.12 seconds
Started Aug 06 07:48:04 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 200584 kb
Host smart-56549b96-8d08-42d6-a1ef-9b387e6f16ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277669649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4277669649
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1417195350
Short name T152
Test name
Test status
Simulation time 191152110 ps
CPU time 1.23 seconds
Started Aug 06 07:48:05 PM PDT 24
Finished Aug 06 07:48:06 PM PDT 24
Peak memory 200368 kb
Host smart-1f88e9e6-3d62-42c6-b843-da13ba307895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417195350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1417195350
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.785008314
Short name T468
Test name
Test status
Simulation time 112449178 ps
CPU time 1.15 seconds
Started Aug 06 07:48:05 PM PDT 24
Finished Aug 06 07:48:06 PM PDT 24
Peak memory 200484 kb
Host smart-695c685c-7be6-4abb-91d1-0ffa7fec4d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785008314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.785008314
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3475009884
Short name T131
Test name
Test status
Simulation time 5887203291 ps
CPU time 19.98 seconds
Started Aug 06 07:48:05 PM PDT 24
Finished Aug 06 07:48:25 PM PDT 24
Peak memory 200612 kb
Host smart-42b8af10-b1a4-4180-a77c-c013c59c8767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475009884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3475009884
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1593332299
Short name T453
Test name
Test status
Simulation time 140866509 ps
CPU time 1.69 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 200280 kb
Host smart-4648fd2c-e56d-4912-9233-56dcd4fa7d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593332299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1593332299
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.491293740
Short name T333
Test name
Test status
Simulation time 127123433 ps
CPU time 1.02 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:08 PM PDT 24
Peak memory 200364 kb
Host smart-c1b69b2d-ba73-4483-882c-238ebd8dbb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491293740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.491293740
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3110184954
Short name T227
Test name
Test status
Simulation time 71190093 ps
CPU time 0.78 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:08 PM PDT 24
Peak memory 200112 kb
Host smart-7e6c1694-6ad1-4785-b436-082b5de025e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110184954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3110184954
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3356977029
Short name T35
Test name
Test status
Simulation time 1903512133 ps
CPU time 6.9 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:16 PM PDT 24
Peak memory 217428 kb
Host smart-d8a7fdd1-7ebc-4378-aa18-e1a920c09c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356977029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3356977029
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.749909891
Short name T481
Test name
Test status
Simulation time 243572862 ps
CPU time 1.1 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 217592 kb
Host smart-791f332e-a7ee-4ab6-ae7e-24d5cff6468d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749909891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.749909891
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2956220290
Short name T308
Test name
Test status
Simulation time 171361663 ps
CPU time 0.85 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:08 PM PDT 24
Peak memory 200144 kb
Host smart-85bdccb1-1c38-4464-b682-3fd83d7fc37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956220290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2956220290
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3002186435
Short name T397
Test name
Test status
Simulation time 1879461150 ps
CPU time 6.78 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 200536 kb
Host smart-ce907aa9-38ab-42b5-8eee-c5e5c58c1d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002186435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3002186435
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2509972501
Short name T377
Test name
Test status
Simulation time 180899305 ps
CPU time 1.28 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 200296 kb
Host smart-b045e110-4b59-41c0-9b39-9949ead52a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509972501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2509972501
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3238696874
Short name T203
Test name
Test status
Simulation time 196191805 ps
CPU time 1.43 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200456 kb
Host smart-1f9d2ff7-6f6a-45f9-b6e0-92e4d823e590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238696874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3238696874
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3120426018
Short name T330
Test name
Test status
Simulation time 9822145981 ps
CPU time 35.55 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:43 PM PDT 24
Peak memory 209872 kb
Host smart-c4133b8e-8133-4047-8b9d-c13305fba5c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120426018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3120426018
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3072387461
Short name T178
Test name
Test status
Simulation time 391290972 ps
CPU time 2.53 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200240 kb
Host smart-fe6a92d6-acbb-48a9-b28a-ecee74f2dbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072387461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3072387461
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2495780491
Short name T16
Test name
Test status
Simulation time 162915037 ps
CPU time 1.31 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 200480 kb
Host smart-464049b7-aece-4967-ba18-93f4f04cf4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495780491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2495780491
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.219007560
Short name T436
Test name
Test status
Simulation time 58165638 ps
CPU time 0.71 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:08 PM PDT 24
Peak memory 200140 kb
Host smart-a8ea7f4b-a966-4ffc-b323-d1495acd3e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219007560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.219007560
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.2350061740
Short name T410
Test name
Test status
Simulation time 1896912014 ps
CPU time 7.87 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 216816 kb
Host smart-aa2dc3c0-66ac-4077-a511-f85eddcc14ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350061740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2350061740
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.889700721
Short name T359
Test name
Test status
Simulation time 244286069 ps
CPU time 1.03 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 217560 kb
Host smart-40d777f2-94d1-4d7f-b2bf-0dac949d739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889700721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.889700721
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2832132308
Short name T195
Test name
Test status
Simulation time 149580490 ps
CPU time 0.93 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 200104 kb
Host smart-04b8d205-0dcf-4205-b631-04b1db71b3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832132308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2832132308
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.97471315
Short name T213
Test name
Test status
Simulation time 685701070 ps
CPU time 3.79 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 200584 kb
Host smart-1148d6a3-46e8-4925-9598-a3b98722f539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97471315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.97471315
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3837771837
Short name T452
Test name
Test status
Simulation time 100190683 ps
CPU time 0.99 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 200328 kb
Host smart-4dde22d2-a134-4eab-b48d-abd8d561dfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837771837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3837771837
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3797795521
Short name T224
Test name
Test status
Simulation time 114327958 ps
CPU time 1.19 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 200464 kb
Host smart-25fd0ece-7952-481d-bf18-f574475689ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797795521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3797795521
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.890444940
Short name T539
Test name
Test status
Simulation time 7467349451 ps
CPU time 26.23 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:35 PM PDT 24
Peak memory 208872 kb
Host smart-555889bb-49e0-456d-b5bc-697981113a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890444940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.890444940
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3968067897
Short name T302
Test name
Test status
Simulation time 316367351 ps
CPU time 2.06 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 208508 kb
Host smart-da965868-4e70-4d91-8666-c1ffa17d53b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968067897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3968067897
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.760032217
Short name T268
Test name
Test status
Simulation time 65540277 ps
CPU time 0.8 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:09 PM PDT 24
Peak memory 200332 kb
Host smart-8a59abe5-6b31-4edd-b9b7-2f9e363be782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760032217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.760032217
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1799280163
Short name T208
Test name
Test status
Simulation time 73610204 ps
CPU time 0.78 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 200048 kb
Host smart-2353745e-c94a-47ba-9ca4-b89e1d307e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799280163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1799280163
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.621290390
Short name T428
Test name
Test status
Simulation time 2351921699 ps
CPU time 9.37 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:19 PM PDT 24
Peak memory 217856 kb
Host smart-e0fe2c49-1c51-4a52-a350-be5ced9c87db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621290390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.621290390
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3807669901
Short name T229
Test name
Test status
Simulation time 244949046 ps
CPU time 1.09 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 217564 kb
Host smart-902f19fc-da00-4bea-a88d-4b53d1198f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807669901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3807669901
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.179960586
Short name T280
Test name
Test status
Simulation time 182440271 ps
CPU time 0.9 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 200140 kb
Host smart-74018c2e-af9c-41c5-9771-6a733e0d9c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179960586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.179960586
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1595670440
Short name T529
Test name
Test status
Simulation time 1364498115 ps
CPU time 5.18 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 200496 kb
Host smart-f8c4099c-792c-4e97-8364-b85393135a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595670440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1595670440
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.4056982332
Short name T284
Test name
Test status
Simulation time 152576035 ps
CPU time 1.15 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 200280 kb
Host smart-5da98dce-6d65-46cc-be56-ff2bac13bc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056982332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.4056982332
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2204438979
Short name T234
Test name
Test status
Simulation time 193442588 ps
CPU time 1.36 seconds
Started Aug 06 07:48:08 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 200544 kb
Host smart-31ac7510-cc4b-4cd7-b06f-0165ff93bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204438979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2204438979
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4034717650
Short name T459
Test name
Test status
Simulation time 5176569889 ps
CPU time 17.19 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:27 PM PDT 24
Peak memory 200608 kb
Host smart-f791d6b1-5c7a-48e7-8396-587c0ad574e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034717650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4034717650
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3418582533
Short name T87
Test name
Test status
Simulation time 132165968 ps
CPU time 1.7 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 199928 kb
Host smart-2f8b0832-916b-4f2c-8089-29f7e76616f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418582533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3418582533
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2696923336
Short name T271
Test name
Test status
Simulation time 134987892 ps
CPU time 1.12 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 199900 kb
Host smart-f820e87a-341b-4acc-b1d4-bd5d4639b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696923336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2696923336
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.4289662959
Short name T162
Test name
Test status
Simulation time 73534448 ps
CPU time 0.83 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 200136 kb
Host smart-8ef16a58-52cf-47c8-b546-2f0209d95f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289662959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4289662959
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.407412870
Short name T380
Test name
Test status
Simulation time 2384347532 ps
CPU time 8.27 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:19 PM PDT 24
Peak memory 217808 kb
Host smart-f7699706-bbb4-4104-8867-4eac458408fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407412870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.407412870
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1581268214
Short name T285
Test name
Test status
Simulation time 244318871 ps
CPU time 1.18 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 217520 kb
Host smart-1d864c39-32d0-4d6b-9961-414093a89b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581268214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1581268214
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.983793725
Short name T276
Test name
Test status
Simulation time 113864456 ps
CPU time 0.78 seconds
Started Aug 06 07:48:07 PM PDT 24
Finished Aug 06 07:48:08 PM PDT 24
Peak memory 200100 kb
Host smart-f9f77274-4ac4-4c21-8e7f-ba4d867a5e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983793725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.983793725
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1321870728
Short name T515
Test name
Test status
Simulation time 1338795930 ps
CPU time 5.15 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 200556 kb
Host smart-0fbebc26-eba6-47ca-9b60-51b6793ec92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321870728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1321870728
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.414762389
Short name T327
Test name
Test status
Simulation time 105733824 ps
CPU time 1.01 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:10 PM PDT 24
Peak memory 200364 kb
Host smart-12d90d34-ecad-4868-bf2c-edc2467bd87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414762389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.414762389
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2010746410
Short name T137
Test name
Test status
Simulation time 198161581 ps
CPU time 1.29 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200460 kb
Host smart-071595c9-0e7b-4c49-bb62-478a146b3fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010746410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2010746410
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2502578963
Short name T244
Test name
Test status
Simulation time 7261794168 ps
CPU time 31.4 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:44 PM PDT 24
Peak memory 200588 kb
Host smart-4e474de3-b861-4b97-955f-6facce68b6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502578963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2502578963
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.4234644412
Short name T524
Test name
Test status
Simulation time 460452665 ps
CPU time 2.81 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:14 PM PDT 24
Peak memory 200268 kb
Host smart-f8c5164a-8421-45a5-a0f2-63f79d47fe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234644412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4234644412
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.762842020
Short name T295
Test name
Test status
Simulation time 119826135 ps
CPU time 1.01 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 200364 kb
Host smart-0f766673-6f99-4d90-a731-44970e485758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762842020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.762842020
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.451384747
Short name T319
Test name
Test status
Simulation time 66662042 ps
CPU time 0.76 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 200348 kb
Host smart-9757f734-a520-43a1-91c9-5dae1e5359ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451384747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.451384747
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.129581881
Short name T471
Test name
Test status
Simulation time 244322939 ps
CPU time 1.02 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 217468 kb
Host smart-b1be04db-52bf-49d3-a12a-acf71d7dc7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129581881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.129581881
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.154132044
Short name T318
Test name
Test status
Simulation time 159156809 ps
CPU time 0.88 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 200160 kb
Host smart-d4d6495b-f7f4-4971-8afd-91cce8479e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154132044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.154132044
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.400527575
Short name T130
Test name
Test status
Simulation time 1708762221 ps
CPU time 6.45 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:18 PM PDT 24
Peak memory 200564 kb
Host smart-4a8730ff-6b30-469e-b5a1-f7eb249f8c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400527575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.400527575
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3391711727
Short name T301
Test name
Test status
Simulation time 104583168 ps
CPU time 1 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 200340 kb
Host smart-28f40528-5602-48e3-b5ba-d218f1a96c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391711727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3391711727
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1227081449
Short name T492
Test name
Test status
Simulation time 238401785 ps
CPU time 1.41 seconds
Started Aug 06 07:48:11 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200472 kb
Host smart-53b869cc-f1b6-431c-98e6-5c0c42b1deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227081449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1227081449
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2140275945
Short name T434
Test name
Test status
Simulation time 4678450487 ps
CPU time 16.56 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:28 PM PDT 24
Peak memory 208748 kb
Host smart-8deb586e-4c26-4339-833d-f681c44205b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140275945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2140275945
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2575659472
Short name T463
Test name
Test status
Simulation time 147246301 ps
CPU time 1.78 seconds
Started Aug 06 07:48:02 PM PDT 24
Finished Aug 06 07:48:04 PM PDT 24
Peak memory 200192 kb
Host smart-02e6e419-1f3b-4f2f-98a0-0364ee203a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575659472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2575659472
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3220443762
Short name T321
Test name
Test status
Simulation time 147068744 ps
CPU time 1.16 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200288 kb
Host smart-ead91fb2-a84b-4c7c-8759-9af75800c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220443762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3220443762
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3873491764
Short name T304
Test name
Test status
Simulation time 59363293 ps
CPU time 0.75 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:11 PM PDT 24
Peak memory 200124 kb
Host smart-38251550-c918-446c-9360-1c0107262749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873491764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3873491764
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.9869872
Short name T322
Test name
Test status
Simulation time 1227244907 ps
CPU time 5.49 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:19 PM PDT 24
Peak memory 217284 kb
Host smart-7830f44b-91e5-4447-b033-ec8520ded983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9869872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.9869872
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.276250604
Short name T426
Test name
Test status
Simulation time 244620701 ps
CPU time 1.12 seconds
Started Aug 06 07:48:10 PM PDT 24
Finished Aug 06 07:48:12 PM PDT 24
Peak memory 217484 kb
Host smart-368acaa5-c818-40d0-bf9d-2d2b7d0fd507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276250604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.276250604
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2856579325
Short name T22
Test name
Test status
Simulation time 164288310 ps
CPU time 0.85 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200132 kb
Host smart-49902125-252e-487e-bc6d-6083ec1e2957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856579325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2856579325
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2770980348
Short name T179
Test name
Test status
Simulation time 1090626850 ps
CPU time 5.5 seconds
Started Aug 06 07:48:09 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 200532 kb
Host smart-c7ec5f3a-dd71-4585-b847-49dc3a35f774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770980348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2770980348
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2704096594
Short name T405
Test name
Test status
Simulation time 173234571 ps
CPU time 1.17 seconds
Started Aug 06 07:48:12 PM PDT 24
Finished Aug 06 07:48:13 PM PDT 24
Peak memory 200324 kb
Host smart-61cb5310-6b62-48e8-8cca-5c5ba994cf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704096594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2704096594
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2165708946
Short name T390
Test name
Test status
Simulation time 196700312 ps
CPU time 1.31 seconds
Started Aug 06 07:48:13 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 200428 kb
Host smart-6bc30a42-8c22-493a-96b9-34cb8977253f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165708946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2165708946
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3373602031
Short name T479
Test name
Test status
Simulation time 118075348 ps
CPU time 1.39 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 200488 kb
Host smart-cba47422-f296-4929-9eb7-e5c7a51d58b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373602031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3373602031
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1194443306
Short name T477
Test name
Test status
Simulation time 106317976 ps
CPU time 0.97 seconds
Started Aug 06 07:48:14 PM PDT 24
Finished Aug 06 07:48:15 PM PDT 24
Peak memory 200536 kb
Host smart-f762ddd9-e26a-4c4a-8603-dcc8a72e72a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194443306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1194443306
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2415694428
Short name T519
Test name
Test status
Simulation time 67450427 ps
CPU time 0.73 seconds
Started Aug 06 07:46:41 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 200152 kb
Host smart-05962aa4-6e9b-45a7-b815-a2de75ba6ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415694428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2415694428
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4035411033
Short name T516
Test name
Test status
Simulation time 2356304023 ps
CPU time 8.05 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:51 PM PDT 24
Peak memory 217756 kb
Host smart-721f126b-69dc-468e-98ae-57a59e05b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035411033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4035411033
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1050174361
Short name T217
Test name
Test status
Simulation time 244459133 ps
CPU time 1.03 seconds
Started Aug 06 07:46:46 PM PDT 24
Finished Aug 06 07:46:47 PM PDT 24
Peak memory 217508 kb
Host smart-13275c3d-4e86-4115-8092-525d97743248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050174361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1050174361
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1283356938
Short name T374
Test name
Test status
Simulation time 144161920 ps
CPU time 0.92 seconds
Started Aug 06 07:46:42 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200052 kb
Host smart-d2eb3471-3b79-4dc9-a1f7-3169969493e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283356938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1283356938
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3423441911
Short name T306
Test name
Test status
Simulation time 1613384790 ps
CPU time 6.31 seconds
Started Aug 06 07:46:47 PM PDT 24
Finished Aug 06 07:46:53 PM PDT 24
Peak memory 200576 kb
Host smart-38971160-0947-40ae-92ca-ba22749d080c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423441911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3423441911
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2694601629
Short name T239
Test name
Test status
Simulation time 140288001 ps
CPU time 1.06 seconds
Started Aug 06 07:46:44 PM PDT 24
Finished Aug 06 07:46:45 PM PDT 24
Peak memory 200308 kb
Host smart-152ff121-e146-44c1-8197-e4d30410cf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694601629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2694601629
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2934740933
Short name T200
Test name
Test status
Simulation time 196957384 ps
CPU time 1.37 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 200440 kb
Host smart-ff39826e-4e66-4abd-b887-69a119967d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934740933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2934740933
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.2062305515
Short name T1
Test name
Test status
Simulation time 1463997950 ps
CPU time 5.96 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:46 PM PDT 24
Peak memory 200536 kb
Host smart-3a907599-931e-437e-865e-ce1c1e0be0c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062305515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2062305515
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2004405984
Short name T161
Test name
Test status
Simulation time 132407297 ps
CPU time 1.61 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:42 PM PDT 24
Peak memory 200276 kb
Host smart-c142889c-6048-4fcd-a3f2-50d86424b674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004405984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2004405984
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2267740730
Short name T183
Test name
Test status
Simulation time 111899447 ps
CPU time 0.92 seconds
Started Aug 06 07:46:41 PM PDT 24
Finished Aug 06 07:46:42 PM PDT 24
Peak memory 200284 kb
Host smart-2a0a45d6-0e72-41a9-a93f-c1990445223d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267740730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2267740730
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3645401119
Short name T534
Test name
Test status
Simulation time 69700154 ps
CPU time 0.8 seconds
Started Aug 06 07:46:44 PM PDT 24
Finished Aug 06 07:46:45 PM PDT 24
Peak memory 200120 kb
Host smart-e3a690e2-1cfc-4ef0-915d-6f160c470479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645401119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3645401119
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.613257124
Short name T43
Test name
Test status
Simulation time 2161047518 ps
CPU time 9.04 seconds
Started Aug 06 07:46:42 PM PDT 24
Finished Aug 06 07:46:51 PM PDT 24
Peak memory 217628 kb
Host smart-bb9e522d-86c6-4ec4-b5c7-2e959b81b298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613257124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.613257124
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3865557878
Short name T286
Test name
Test status
Simulation time 244529777 ps
CPU time 1.09 seconds
Started Aug 06 07:46:46 PM PDT 24
Finished Aug 06 07:46:47 PM PDT 24
Peak memory 217568 kb
Host smart-396b03f8-4b1b-499c-8173-3fe564927331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865557878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3865557878
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.424446105
Short name T384
Test name
Test status
Simulation time 201700628 ps
CPU time 0.87 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 200136 kb
Host smart-03627b6d-57e3-48fb-b335-7214879fb021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424446105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.424446105
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3963071273
Short name T378
Test name
Test status
Simulation time 1833262598 ps
CPU time 6.55 seconds
Started Aug 06 07:46:44 PM PDT 24
Finished Aug 06 07:46:51 PM PDT 24
Peak memory 200500 kb
Host smart-f9099457-e04e-4a18-bc42-a0e9d46d1ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963071273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3963071273
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1441830251
Short name T85
Test name
Test status
Simulation time 102451406 ps
CPU time 0.99 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:44 PM PDT 24
Peak memory 200540 kb
Host smart-2ab0807b-cc22-4064-b2b2-5d4284e32fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441830251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1441830251
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1957403334
Short name T341
Test name
Test status
Simulation time 193621280 ps
CPU time 1.36 seconds
Started Aug 06 07:46:42 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200432 kb
Host smart-1f3bd03d-9367-489b-865f-9780e51b5262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957403334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1957403334
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.4128291688
Short name T497
Test name
Test status
Simulation time 1803298116 ps
CPU time 8.5 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:52 PM PDT 24
Peak memory 200740 kb
Host smart-8c8b0564-1584-4087-aff0-d8aecbee2b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128291688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.4128291688
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.294829300
Short name T525
Test name
Test status
Simulation time 345486293 ps
CPU time 2.27 seconds
Started Aug 06 07:46:41 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200288 kb
Host smart-99c96589-8be4-4538-a957-7d14bc45e37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294829300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.294829300
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.430330739
Short name T365
Test name
Test status
Simulation time 199995323 ps
CPU time 1.21 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:42 PM PDT 24
Peak memory 200324 kb
Host smart-56b91bd7-2cbb-432c-8e0f-2b05a63fda5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430330739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.430330739
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3712374852
Short name T173
Test name
Test status
Simulation time 82862486 ps
CPU time 0.82 seconds
Started Aug 06 07:46:47 PM PDT 24
Finished Aug 06 07:46:48 PM PDT 24
Peak memory 200148 kb
Host smart-53ccd307-938b-4f5e-9b8d-3d2851239220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712374852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3712374852
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1537588190
Short name T54
Test name
Test status
Simulation time 1899799442 ps
CPU time 6.56 seconds
Started Aug 06 07:46:44 PM PDT 24
Finished Aug 06 07:46:51 PM PDT 24
Peak memory 217688 kb
Host smart-361bb6c3-c9ed-4762-997c-ed826e4ee30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537588190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1537588190
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.797876281
Short name T344
Test name
Test status
Simulation time 245028920 ps
CPU time 1.04 seconds
Started Aug 06 07:46:45 PM PDT 24
Finished Aug 06 07:46:46 PM PDT 24
Peak memory 217556 kb
Host smart-53877d15-9204-409f-9d65-22d9796f6057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797876281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.797876281
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2896483994
Short name T273
Test name
Test status
Simulation time 135161461 ps
CPU time 0.84 seconds
Started Aug 06 07:46:42 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200156 kb
Host smart-bbe2eff9-af38-4fcc-a8c3-c42bca8e816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896483994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2896483994
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3431094728
Short name T431
Test name
Test status
Simulation time 1418789137 ps
CPU time 5.31 seconds
Started Aug 06 07:46:41 PM PDT 24
Finished Aug 06 07:46:46 PM PDT 24
Peak memory 200504 kb
Host smart-eb100b56-5fc5-4b74-9c19-8dd54aa849d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431094728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3431094728
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.256291121
Short name T109
Test name
Test status
Simulation time 182031252 ps
CPU time 1.23 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:44 PM PDT 24
Peak memory 200348 kb
Host smart-cfae75b0-df5c-4d24-9cb3-5c4ac4e9535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256291121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.256291121
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3941727566
Short name T508
Test name
Test status
Simulation time 189287787 ps
CPU time 1.41 seconds
Started Aug 06 07:46:41 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200548 kb
Host smart-e65fb8a9-42ee-4172-8a7c-6f01f99be9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941727566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3941727566
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3927232701
Short name T303
Test name
Test status
Simulation time 3085145853 ps
CPU time 14.6 seconds
Started Aug 06 07:46:46 PM PDT 24
Finished Aug 06 07:47:01 PM PDT 24
Peak memory 208816 kb
Host smart-8a3f8b84-06ed-4110-8efc-2139eb2c92dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927232701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3927232701
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3626047036
Short name T188
Test name
Test status
Simulation time 111908786 ps
CPU time 1.41 seconds
Started Aug 06 07:46:45 PM PDT 24
Finished Aug 06 07:46:47 PM PDT 24
Peak memory 200300 kb
Host smart-a2abf499-b887-4a65-8d88-6a39bb8e37cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626047036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3626047036
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.4030505022
Short name T27
Test name
Test status
Simulation time 205657331 ps
CPU time 1.47 seconds
Started Aug 06 07:46:40 PM PDT 24
Finished Aug 06 07:46:41 PM PDT 24
Peak memory 200232 kb
Host smart-31677daa-1a6d-4177-9ecb-c4721a4f8a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030505022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.4030505022
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1086210802
Short name T532
Test name
Test status
Simulation time 77107682 ps
CPU time 0.84 seconds
Started Aug 06 07:46:42 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200104 kb
Host smart-9c333212-de89-4615-84f9-d31e3a3fdf0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086210802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1086210802
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3340841916
Short name T535
Test name
Test status
Simulation time 1901929537 ps
CPU time 7 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:50 PM PDT 24
Peak memory 221628 kb
Host smart-c5273451-d8bd-4faf-a2f7-b3455dbc8aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340841916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3340841916
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1080705411
Short name T259
Test name
Test status
Simulation time 243539741 ps
CPU time 1.19 seconds
Started Aug 06 07:46:43 PM PDT 24
Finished Aug 06 07:46:44 PM PDT 24
Peak memory 217468 kb
Host smart-254e4673-6e8c-4094-95c1-7dfc0812564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080705411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1080705411
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2341099515
Short name T437
Test name
Test status
Simulation time 131734289 ps
CPU time 0.78 seconds
Started Aug 06 07:46:42 PM PDT 24
Finished Aug 06 07:46:43 PM PDT 24
Peak memory 200148 kb
Host smart-258c86b0-b7e2-4fe2-bef1-8f629fb05064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341099515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2341099515
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3470309418
Short name T132
Test name
Test status
Simulation time 1909511802 ps
CPU time 6.55 seconds
Started Aug 06 07:46:45 PM PDT 24
Finished Aug 06 07:46:52 PM PDT 24
Peak memory 200620 kb
Host smart-4f9e4c8d-f0ac-46ac-921d-d37412fc821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470309418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3470309418
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1815919373
Short name T504
Test name
Test status
Simulation time 183195363 ps
CPU time 1.18 seconds
Started Aug 06 07:46:46 PM PDT 24
Finished Aug 06 07:46:47 PM PDT 24
Peak memory 200356 kb
Host smart-a0e1fea2-ae0d-49a4-9659-6ec88b26100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815919373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1815919373
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2226970202
Short name T518
Test name
Test status
Simulation time 233525217 ps
CPU time 1.44 seconds
Started Aug 06 07:46:46 PM PDT 24
Finished Aug 06 07:46:48 PM PDT 24
Peak memory 200492 kb
Host smart-8008c04c-0eb9-43fc-99b6-00b9cf8723ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226970202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2226970202
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2828918204
Short name T84
Test name
Test status
Simulation time 458746487 ps
CPU time 2.5 seconds
Started Aug 06 07:46:46 PM PDT 24
Finished Aug 06 07:46:49 PM PDT 24
Peak memory 208456 kb
Host smart-d1633f38-2a24-4ba7-a3e6-a883f2645db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828918204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2828918204
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1625211656
Short name T368
Test name
Test status
Simulation time 111536702 ps
CPU time 0.98 seconds
Started Aug 06 07:46:44 PM PDT 24
Finished Aug 06 07:46:45 PM PDT 24
Peak memory 200296 kb
Host smart-7c1ff109-eb22-42b7-8896-f40c913860cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625211656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1625211656
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1481129069
Short name T174
Test name
Test status
Simulation time 65951342 ps
CPU time 0.75 seconds
Started Aug 06 07:47:04 PM PDT 24
Finished Aug 06 07:47:05 PM PDT 24
Peak memory 200112 kb
Host smart-5324b260-9a4b-4a96-aa0e-72c17fd877eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481129069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1481129069
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2537691453
Short name T58
Test name
Test status
Simulation time 2365092739 ps
CPU time 7.99 seconds
Started Aug 06 07:47:04 PM PDT 24
Finished Aug 06 07:47:12 PM PDT 24
Peak memory 217948 kb
Host smart-a1e65691-20f4-47b4-9988-eb6c7adfb759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537691453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2537691453
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1082941506
Short name T267
Test name
Test status
Simulation time 243818171 ps
CPU time 1.19 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 217448 kb
Host smart-7566513e-99ca-49ed-89a8-89fe67e68fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082941506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1082941506
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2515330798
Short name T423
Test name
Test status
Simulation time 126816847 ps
CPU time 0.82 seconds
Started Aug 06 07:46:44 PM PDT 24
Finished Aug 06 07:46:45 PM PDT 24
Peak memory 200108 kb
Host smart-371cdf4f-6924-4016-9181-fff768064439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515330798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2515330798
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1021187354
Short name T473
Test name
Test status
Simulation time 1668627877 ps
CPU time 6.21 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:14 PM PDT 24
Peak memory 200616 kb
Host smart-a035b803-2b88-4d05-89e3-d57d69350763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021187354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1021187354
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2021065386
Short name T48
Test name
Test status
Simulation time 148415249 ps
CPU time 1.09 seconds
Started Aug 06 07:47:04 PM PDT 24
Finished Aug 06 07:47:05 PM PDT 24
Peak memory 200364 kb
Host smart-2f85bdb9-2c5c-4065-affe-09742445c645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021065386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2021065386
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1440588776
Short name T197
Test name
Test status
Simulation time 204949251 ps
CPU time 1.36 seconds
Started Aug 06 07:46:45 PM PDT 24
Finished Aug 06 07:46:46 PM PDT 24
Peak memory 200520 kb
Host smart-5e59e7f2-185d-4aca-8e87-5732fdebb1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440588776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1440588776
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3889327918
Short name T110
Test name
Test status
Simulation time 1775745082 ps
CPU time 6.56 seconds
Started Aug 06 07:47:06 PM PDT 24
Finished Aug 06 07:47:13 PM PDT 24
Peak memory 208680 kb
Host smart-a81af394-6982-4485-a41d-c2aa84af73fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889327918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3889327918
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1235786779
Short name T394
Test name
Test status
Simulation time 122439841 ps
CPU time 1.62 seconds
Started Aug 06 07:47:07 PM PDT 24
Finished Aug 06 07:47:09 PM PDT 24
Peak memory 200344 kb
Host smart-c4c0182f-20c4-43a9-87a0-6a1d50da7d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235786779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1235786779
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3349394516
Short name T237
Test name
Test status
Simulation time 85494575 ps
CPU time 0.92 seconds
Started Aug 06 07:47:03 PM PDT 24
Finished Aug 06 07:47:04 PM PDT 24
Peak memory 200300 kb
Host smart-134bb3c6-f6d3-4f72-9d86-80ee84921d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349394516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3349394516
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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