Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8468

1

T1

15

T4

14

T8

34

auto[1]

11320

1

T1

1

T4

87

T7

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5993	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6785	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2979	1			T4	18		T7	1		T8	11
reset_info_cp[4]	4064	1			T4	19		T7	1		T8	17
reset_info_cp[8]	117	1			T1	1		T13	1		T14	1
reset_info_cp[16]	112	1			T14	1		T27	1		T28	1
reset_info_cp[32]	122	1			T13	1		T14	3		T27	1
reset_info_cp[64]	111	1			T1	1		T28	1		T42	1
reset_info_cp[128]	125	1			T1	1		T8	1		T25	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3264	1			T4	14		T8	8		T14	9
reset_info_cp[1]	auto[1]	2901	1			T4	12		T7	1		T8	15
reset_info_cp[2]	auto[0]	951	1			T8	5		T14	3		T51	4
reset_info_cp[2]	auto[1]	2028	1			T4	18		T7	1		T8	6
reset_info_cp[4]	auto[0]	1445	1			T8	9		T14	3		T27	5
reset_info_cp[4]	auto[1]	2619	1			T4	19		T7	1		T8	8
reset_info_cp[8]	auto[0]	47	1			T1	1		T13	1		T14	1
reset_info_cp[8]	auto[1]	70	1			T31	3		T45	1		T138	1
reset_info_cp[16]	auto[0]	38	1			T88	1		T100	1		T139	1
reset_info_cp[16]	auto[1]	74	1			T14	1		T27	1		T28	1
reset_info_cp[32]	auto[0]	51	1			T13	1		T14	2		T62	1
reset_info_cp[32]	auto[1]	71	1			T14	1		T27	1		T59	3
reset_info_cp[64]	auto[0]	45	1			T1	1		T42	1		T132	2
reset_info_cp[64]	auto[1]	66	1			T28	1		T34	3		T88	3
reset_info_cp[128]	auto[0]	45	1			T1	1		T8	1		T25	1
reset_info_cp[128]	auto[1]	80	1			T27	1		T28	1		T45	2