Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
index_cp	8	0	8	100.00	100	1	1	0

Summary for Variable index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	42800	1			T4	150		T7	14		T8	182
valid[1]	34964	1			T4	150		T7	14		T8	152
valid[2]	34964	1			T4	150		T7	14		T8	152
valid[3]	34964	1			T4	150		T7	14		T8	152
valid[4]	34964	1			T4	150		T7	14		T8	152
valid[5]	34964	1			T4	150		T7	14		T8	152
valid[6]	34964	1			T4	150		T7	14		T8	152
valid[7]	34964	1			T4	150		T7	14		T8	152