Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/14.rstmgr_alert_test.2748611502 Aug 07 06:23:09 PM PDT 24 Aug 07 06:23:10 PM PDT 24 78029855 ps
T539 /workspace/coverage/default/30.rstmgr_stress_all.1631494225 Aug 07 06:23:37 PM PDT 24 Aug 07 06:24:07 PM PDT 24 7025343392 ps
T540 /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2698906724 Aug 07 06:23:36 PM PDT 24 Aug 07 06:23:37 PM PDT 24 244161069 ps
T541 /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3516854331 Aug 07 06:23:40 PM PDT 24 Aug 07 06:23:41 PM PDT 24 96774237 ps
T542 /workspace/coverage/default/26.rstmgr_por_stretcher.348974374 Aug 07 06:23:26 PM PDT 24 Aug 07 06:23:27 PM PDT 24 169574459 ps
T66 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2819859804 Aug 07 05:01:49 PM PDT 24 Aug 07 05:01:51 PM PDT 24 285818582 ps
T70 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2801081366 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:47 PM PDT 24 353032589 ps
T71 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.940074863 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:46 PM PDT 24 281191716 ps
T72 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.271524091 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:48 PM PDT 24 505749554 ps
T67 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.838900835 Aug 07 05:01:50 PM PDT 24 Aug 07 05:01:51 PM PDT 24 94480208 ps
T95 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3130196563 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:47 PM PDT 24 143526179 ps
T68 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1379782906 Aug 07 05:01:50 PM PDT 24 Aug 07 05:01:51 PM PDT 24 154284459 ps
T96 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1800626789 Aug 07 05:01:30 PM PDT 24 Aug 07 05:01:33 PM PDT 24 483705974 ps
T69 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1869811824 Aug 07 05:01:49 PM PDT 24 Aug 07 05:01:51 PM PDT 24 424246063 ps
T107 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4020760632 Aug 07 05:01:51 PM PDT 24 Aug 07 05:01:52 PM PDT 24 129487367 ps
T99 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1174767984 Aug 07 05:01:36 PM PDT 24 Aug 07 05:01:39 PM PDT 24 460276274 ps
T97 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4240473078 Aug 07 05:01:46 PM PDT 24 Aug 07 05:01:49 PM PDT 24 885380217 ps
T108 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1147941134 Aug 07 05:01:55 PM PDT 24 Aug 07 05:01:57 PM PDT 24 237410078 ps
T109 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2615757669 Aug 07 05:01:50 PM PDT 24 Aug 07 05:01:51 PM PDT 24 64241859 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1759056183 Aug 07 05:01:35 PM PDT 24 Aug 07 05:01:36 PM PDT 24 117533372 ps
T110 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.935856465 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:38 PM PDT 24 60979882 ps
T98 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1353345345 Aug 07 05:02:25 PM PDT 24 Aug 07 05:02:27 PM PDT 24 282070510 ps
T111 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4111126735 Aug 07 05:02:22 PM PDT 24 Aug 07 05:02:23 PM PDT 24 54438253 ps
T137 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2299373307 Aug 07 05:01:38 PM PDT 24 Aug 07 05:01:44 PM PDT 24 492038775 ps
T544 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.149783349 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:39 PM PDT 24 254324622 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2785400010 Aug 07 05:01:35 PM PDT 24 Aug 07 05:01:36 PM PDT 24 113856859 ps
T126 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3813341734 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:45 PM PDT 24 195832556 ps
T112 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4071856283 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:44 PM PDT 24 60870246 ps
T546 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.717719908 Aug 07 05:01:35 PM PDT 24 Aug 07 05:01:41 PM PDT 24 479946009 ps
T547 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2785580747 Aug 07 05:01:35 PM PDT 24 Aug 07 05:01:36 PM PDT 24 131082156 ps
T548 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2946040827 Aug 07 05:02:01 PM PDT 24 Aug 07 05:02:02 PM PDT 24 77904965 ps
T113 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1038147360 Aug 07 05:01:39 PM PDT 24 Aug 07 05:01:40 PM PDT 24 58688006 ps
T125 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3361711215 Aug 07 05:02:13 PM PDT 24 Aug 07 05:02:16 PM PDT 24 190449229 ps
T127 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3243074382 Aug 07 05:01:42 PM PDT 24 Aug 07 05:01:44 PM PDT 24 236440070 ps
T103 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2130835304 Aug 07 05:01:31 PM PDT 24 Aug 07 05:01:33 PM PDT 24 83148573 ps
T114 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3809341416 Aug 07 05:01:56 PM PDT 24 Aug 07 05:01:57 PM PDT 24 80865862 ps
T549 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.109230438 Aug 07 05:01:41 PM PDT 24 Aug 07 05:01:42 PM PDT 24 119704099 ps
T128 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4043827229 Aug 07 05:01:33 PM PDT 24 Aug 07 05:01:35 PM PDT 24 198905020 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3101042922 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:40 PM PDT 24 470450056 ps
T115 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.247029791 Aug 07 05:01:41 PM PDT 24 Aug 07 05:01:43 PM PDT 24 139693189 ps
T122 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2016836675 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:41 PM PDT 24 896367279 ps
T551 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.487404352 Aug 07 05:01:50 PM PDT 24 Aug 07 05:01:51 PM PDT 24 73022537 ps
T552 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2573752557 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:43 PM PDT 24 490906179 ps
T553 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1204985333 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:38 PM PDT 24 66078635 ps
T554 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3263836613 Aug 07 05:01:49 PM PDT 24 Aug 07 05:01:51 PM PDT 24 503404335 ps
T555 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1125775376 Aug 07 05:01:34 PM PDT 24 Aug 07 05:01:37 PM PDT 24 383029391 ps
T556 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3311396537 Aug 07 05:01:48 PM PDT 24 Aug 07 05:01:49 PM PDT 24 88150350 ps
T557 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.684033957 Aug 07 05:01:45 PM PDT 24 Aug 07 05:01:46 PM PDT 24 75030752 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.68375472 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:38 PM PDT 24 136526435 ps
T559 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.282635520 Aug 07 05:01:42 PM PDT 24 Aug 07 05:01:45 PM PDT 24 541165568 ps
T560 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1614418213 Aug 07 05:01:49 PM PDT 24 Aug 07 05:01:50 PM PDT 24 126486410 ps
T561 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.621967862 Aug 07 05:01:50 PM PDT 24 Aug 07 05:01:51 PM PDT 24 127738340 ps
T119 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.427832147 Aug 07 05:01:55 PM PDT 24 Aug 07 05:01:57 PM PDT 24 504287814 ps
T562 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3418699772 Aug 07 05:01:50 PM PDT 24 Aug 07 05:01:53 PM PDT 24 358205963 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.194053034 Aug 07 05:01:38 PM PDT 24 Aug 07 05:01:41 PM PDT 24 368750246 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1867075816 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:40 PM PDT 24 347076256 ps
T565 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.199073362 Aug 07 05:01:39 PM PDT 24 Aug 07 05:01:40 PM PDT 24 148373252 ps
T566 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3560672787 Aug 07 05:01:38 PM PDT 24 Aug 07 05:01:39 PM PDT 24 141036763 ps
T567 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.178460813 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:44 PM PDT 24 131833192 ps
T120 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.22957801 Aug 07 05:01:51 PM PDT 24 Aug 07 05:01:54 PM PDT 24 822250346 ps
T568 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2293520510 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:47 PM PDT 24 187113134 ps
T116 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.189718471 Aug 07 05:01:48 PM PDT 24 Aug 07 05:01:51 PM PDT 24 779002279 ps
T569 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1038174013 Aug 07 05:01:47 PM PDT 24 Aug 07 05:01:48 PM PDT 24 73070588 ps
T123 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4126430138 Aug 07 05:01:50 PM PDT 24 Aug 07 05:01:53 PM PDT 24 495499864 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1815397620 Aug 07 05:01:36 PM PDT 24 Aug 07 05:01:37 PM PDT 24 115708047 ps
T571 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1766622858 Aug 07 05:01:51 PM PDT 24 Aug 07 05:01:54 PM PDT 24 463582894 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1763409580 Aug 07 05:01:53 PM PDT 24 Aug 07 05:01:55 PM PDT 24 131905606 ps
T573 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.450711232 Aug 07 05:01:38 PM PDT 24 Aug 07 05:01:40 PM PDT 24 268661725 ps
T574 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.356464823 Aug 07 05:01:52 PM PDT 24 Aug 07 05:01:54 PM PDT 24 131704616 ps
T575 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.321991401 Aug 07 05:01:42 PM PDT 24 Aug 07 05:01:44 PM PDT 24 200700661 ps
T576 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3876415076 Aug 07 05:01:39 PM PDT 24 Aug 07 05:01:40 PM PDT 24 132451525 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.842109478 Aug 07 05:01:36 PM PDT 24 Aug 07 05:01:38 PM PDT 24 134666610 ps
T121 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1939855649 Aug 07 05:01:42 PM PDT 24 Aug 07 05:01:46 PM PDT 24 890130867 ps
T578 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4172368586 Aug 07 05:01:42 PM PDT 24 Aug 07 05:01:43 PM PDT 24 92115181 ps
T579 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1471040250 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:45 PM PDT 24 130649733 ps
T580 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1441158722 Aug 07 05:01:36 PM PDT 24 Aug 07 05:01:37 PM PDT 24 73605155 ps
T581 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1674188060 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:47 PM PDT 24 835002641 ps
T582 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.22322750 Aug 07 05:01:57 PM PDT 24 Aug 07 05:01:59 PM PDT 24 157624459 ps
T583 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.389348543 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:43 PM PDT 24 488322380 ps
T584 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.731493423 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:45 PM PDT 24 78776749 ps
T585 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1308650027 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:45 PM PDT 24 192779599 ps
T586 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.948744145 Aug 07 05:01:42 PM PDT 24 Aug 07 05:01:43 PM PDT 24 90154012 ps
T587 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.312708232 Aug 07 05:01:36 PM PDT 24 Aug 07 05:01:39 PM PDT 24 139789561 ps
T588 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2345443689 Aug 07 05:01:48 PM PDT 24 Aug 07 05:01:50 PM PDT 24 120442539 ps
T589 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1728361528 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:45 PM PDT 24 122281052 ps
T590 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.169064103 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:45 PM PDT 24 209538906 ps
T591 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2729014638 Aug 07 05:01:57 PM PDT 24 Aug 07 05:01:58 PM PDT 24 139943597 ps
T136 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3792024879 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:46 PM PDT 24 800031495 ps
T592 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3123798418 Aug 07 05:02:25 PM PDT 24 Aug 07 05:02:29 PM PDT 24 656792592 ps
T593 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1298594643 Aug 07 05:01:36 PM PDT 24 Aug 07 05:01:38 PM PDT 24 107771812 ps
T594 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3077180363 Aug 07 05:01:58 PM PDT 24 Aug 07 05:02:00 PM PDT 24 214941680 ps
T595 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3010449806 Aug 07 05:01:48 PM PDT 24 Aug 07 05:01:50 PM PDT 24 183665310 ps
T596 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1487293698 Aug 07 05:01:56 PM PDT 24 Aug 07 05:01:57 PM PDT 24 110665646 ps
T597 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3562314618 Aug 07 05:01:29 PM PDT 24 Aug 07 05:01:30 PM PDT 24 102205869 ps
T117 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3142280502 Aug 07 05:01:30 PM PDT 24 Aug 07 05:01:33 PM PDT 24 850877703 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3324619333 Aug 07 05:01:30 PM PDT 24 Aug 07 05:01:31 PM PDT 24 84023354 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1629714650 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:46 PM PDT 24 208452591 ps
T600 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3876789068 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:44 PM PDT 24 119532074 ps
T601 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2164154601 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:45 PM PDT 24 189155027 ps
T602 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2553163104 Aug 07 05:01:37 PM PDT 24 Aug 07 05:01:38 PM PDT 24 109199080 ps
T603 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1244239642 Aug 07 05:01:31 PM PDT 24 Aug 07 05:01:34 PM PDT 24 180622942 ps
T118 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3896913592 Aug 07 05:01:47 PM PDT 24 Aug 07 05:01:51 PM PDT 24 944832258 ps
T604 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.452260870 Aug 07 05:02:25 PM PDT 24 Aug 07 05:02:28 PM PDT 24 939964252 ps
T605 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4256725543 Aug 07 05:01:57 PM PDT 24 Aug 07 05:01:58 PM PDT 24 135874401 ps
T606 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1374685957 Aug 07 05:01:49 PM PDT 24 Aug 07 05:01:51 PM PDT 24 128498890 ps
T607 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3807716655 Aug 07 05:01:36 PM PDT 24 Aug 07 05:01:42 PM PDT 24 476950552 ps
T608 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1986980332 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:45 PM PDT 24 105453275 ps
T609 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2040882389 Aug 07 05:01:32 PM PDT 24 Aug 07 05:01:33 PM PDT 24 63704996 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2355207933 Aug 07 05:01:39 PM PDT 24 Aug 07 05:01:40 PM PDT 24 128656082 ps
T611 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2163094987 Aug 07 05:01:34 PM PDT 24 Aug 07 05:01:34 PM PDT 24 60446078 ps
T612 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.662411812 Aug 07 05:01:35 PM PDT 24 Aug 07 05:01:36 PM PDT 24 158064433 ps
T613 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1301839582 Aug 07 05:01:49 PM PDT 24 Aug 07 05:01:50 PM PDT 24 182236698 ps
T124 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3477962341 Aug 07 05:01:43 PM PDT 24 Aug 07 05:01:46 PM PDT 24 784709724 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1316322062 Aug 07 05:01:51 PM PDT 24 Aug 07 05:01:52 PM PDT 24 136956693 ps
T615 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.929330998 Aug 07 05:01:45 PM PDT 24 Aug 07 05:01:47 PM PDT 24 498653098 ps
T616 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3125627827 Aug 07 05:01:48 PM PDT 24 Aug 07 05:01:49 PM PDT 24 77567901 ps
T617 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3543098517 Aug 07 05:01:48 PM PDT 24 Aug 07 05:01:49 PM PDT 24 73285074 ps
T618 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2420840915 Aug 07 05:01:53 PM PDT 24 Aug 07 05:01:55 PM PDT 24 467496144 ps
T619 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3246227892 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:46 PM PDT 24 422153834 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3976804202 Aug 07 05:01:44 PM PDT 24 Aug 07 05:01:47 PM PDT 24 397690825 ps

Test location /workspace/coverage/default/9.rstmgr_stress_all.2756857831
Short name T8
Test name
Test status
Simulation time 3604846225 ps
CPU time 14.03 seconds
Started Aug 07 06:22:57 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 208912 kb
Host smart-366dbaf9-438f-4fa4-974b-5d56d8036f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756857831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2756857831
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4091746729
Short name T7
Test name
Test status
Simulation time 120731237 ps
CPU time 1.27 seconds
Started Aug 07 06:24:03 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 200728 kb
Host smart-4ba1ebfc-99bd-4562-a373-d12c36b47b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091746729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4091746729
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1379782906
Short name T68
Test name
Test status
Simulation time 154284459 ps
CPU time 1.39 seconds
Started Aug 07 05:01:50 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 208364 kb
Host smart-764b53dc-e02e-4bef-a6c4-270eae2445fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379782906 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.1379782906
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1599552334
Short name T75
Test name
Test status
Simulation time 16757036670 ps
CPU time 24.82 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:23:05 PM PDT 24
Peak memory 218344 kb
Host smart-2f5a32de-3fd7-4e3c-aa31-9e4e3fc9da40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599552334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1599552334
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3907467452
Short name T34
Test name
Test status
Simulation time 2349048458 ps
CPU time 9.19 seconds
Started Aug 07 06:23:59 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 217892 kb
Host smart-51505433-6c25-4c4e-9800-89ca6e3746fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907467452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3907467452
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3775809460
Short name T145
Test name
Test status
Simulation time 119109449 ps
CPU time 1.54 seconds
Started Aug 07 06:22:41 PM PDT 24
Finished Aug 07 06:22:43 PM PDT 24
Peak memory 200284 kb
Host smart-c237de14-7871-4d93-9270-60303febdf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775809460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3775809460
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2223777821
Short name T14
Test name
Test status
Simulation time 1531342087 ps
CPU time 6.7 seconds
Started Aug 07 06:22:59 PM PDT 24
Finished Aug 07 06:23:05 PM PDT 24
Peak memory 200556 kb
Host smart-24f469fa-d8d2-477c-a0df-8839c794cc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223777821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2223777821
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4240473078
Short name T97
Test name
Test status
Simulation time 885380217 ps
CPU time 3.19 seconds
Started Aug 07 05:01:46 PM PDT 24
Finished Aug 07 05:01:49 PM PDT 24
Peak memory 200148 kb
Host smart-63ca69cb-d97f-4b59-a8b7-24723b860f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240473078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4240473078
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.714528782
Short name T32
Test name
Test status
Simulation time 79118704 ps
CPU time 0.8 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200168 kb
Host smart-80effa93-4976-484c-bf72-017a9af7eff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714528782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.714528782
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3407414978
Short name T54
Test name
Test status
Simulation time 175899040 ps
CPU time 1.18 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 200324 kb
Host smart-112f063a-424d-417c-9117-5856851326ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407414978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3407414978
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2331281464
Short name T78
Test name
Test status
Simulation time 1296785101 ps
CPU time 6.56 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:06 PM PDT 24
Peak memory 200560 kb
Host smart-3a830fe5-594c-445d-9fd2-1ea396b90865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331281464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2331281464
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2801081366
Short name T70
Test name
Test status
Simulation time 353032589 ps
CPU time 2.77 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:47 PM PDT 24
Peak memory 211824 kb
Host smart-f6a61fa6-590d-4d11-8a2e-9b550a451b54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801081366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2801081366
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3477962341
Short name T124
Test name
Test status
Simulation time 784709724 ps
CPU time 2.9 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:46 PM PDT 24
Peak memory 200024 kb
Host smart-a4dd0eb6-f1ed-46b5-a113-853882c68bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477962341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3477962341
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3290785124
Short name T36
Test name
Test status
Simulation time 2349581943 ps
CPU time 8.19 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 221780 kb
Host smart-4018a5c0-d505-4718-a080-4068c892b4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290785124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3290785124
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.848934134
Short name T139
Test name
Test status
Simulation time 123152468 ps
CPU time 1.11 seconds
Started Aug 07 06:23:04 PM PDT 24
Finished Aug 07 06:23:05 PM PDT 24
Peak memory 200380 kb
Host smart-67bffec7-6f3e-4385-83b6-5077652b795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848934134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.848934134
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2293520510
Short name T568
Test name
Test status
Simulation time 187113134 ps
CPU time 2.77 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:47 PM PDT 24
Peak memory 208364 kb
Host smart-5d531ccc-a0b3-4d1b-8dc7-74ff479bb630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293520510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2293520510
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3805456940
Short name T38
Test name
Test status
Simulation time 1220373395 ps
CPU time 5.76 seconds
Started Aug 07 06:23:09 PM PDT 24
Finished Aug 07 06:23:15 PM PDT 24
Peak memory 217744 kb
Host smart-b512fab7-6c7f-4d6e-8362-611a5816fafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805456940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3805456940
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.22957801
Short name T120
Test name
Test status
Simulation time 822250346 ps
CPU time 2.76 seconds
Started Aug 07 05:01:51 PM PDT 24
Finished Aug 07 05:01:54 PM PDT 24
Peak memory 200204 kb
Host smart-d97aad84-4065-40f6-84e4-97750884f6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22957801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.22957801
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2615757669
Short name T109
Test name
Test status
Simulation time 64241859 ps
CPU time 0.8 seconds
Started Aug 07 05:01:50 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200020 kb
Host smart-8b1a05c4-b42b-4d74-ace5-0b8625e0a715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615757669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2615757669
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.270102673
Short name T18
Test name
Test status
Simulation time 223613725 ps
CPU time 0.88 seconds
Started Aug 07 06:22:37 PM PDT 24
Finished Aug 07 06:22:38 PM PDT 24
Peak memory 200160 kb
Host smart-1b10ab1a-8d21-4586-9446-eb9139755ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270102673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.270102673
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3426454680
Short name T172
Test name
Test status
Simulation time 1886463575 ps
CPU time 7.32 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 217812 kb
Host smart-b08b1175-d1fc-4b0c-bedd-c8b2815a1b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426454680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3426454680
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3142280502
Short name T117
Test name
Test status
Simulation time 850877703 ps
CPU time 2.83 seconds
Started Aug 07 05:01:30 PM PDT 24
Finished Aug 07 05:01:33 PM PDT 24
Peak memory 200176 kb
Host smart-ba9e6e04-ecd4-4fd2-9e4b-c6f8e72189b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142280502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3142280502
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.194053034
Short name T563
Test name
Test status
Simulation time 368750246 ps
CPU time 2.58 seconds
Started Aug 07 05:01:38 PM PDT 24
Finished Aug 07 05:01:41 PM PDT 24
Peak memory 200128 kb
Host smart-af94205a-035d-4b75-a44c-ca51ef5313b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194053034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.194053034
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.389348543
Short name T583
Test name
Test status
Simulation time 488322380 ps
CPU time 5.84 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:43 PM PDT 24
Peak memory 200160 kb
Host smart-94f0c34b-6015-4ea8-bf27-9c468f253030
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389348543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.389348543
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3562314618
Short name T597
Test name
Test status
Simulation time 102205869 ps
CPU time 0.84 seconds
Started Aug 07 05:01:29 PM PDT 24
Finished Aug 07 05:01:30 PM PDT 24
Peak memory 200016 kb
Host smart-986aae45-f1ca-45a5-8525-6f08ed2d7e8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562314618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
562314618
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4043827229
Short name T128
Test name
Test status
Simulation time 198905020 ps
CPU time 1.79 seconds
Started Aug 07 05:01:33 PM PDT 24
Finished Aug 07 05:01:35 PM PDT 24
Peak memory 208528 kb
Host smart-0dde4843-9470-4740-abba-8a26673368fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043827229 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.4043827229
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2130835304
Short name T103
Test name
Test status
Simulation time 83148573 ps
CPU time 0.87 seconds
Started Aug 07 05:01:31 PM PDT 24
Finished Aug 07 05:01:33 PM PDT 24
Peak memory 199964 kb
Host smart-ce642431-eaf2-466a-a6b0-3e8d81d17f91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130835304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2130835304
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3324619333
Short name T598
Test name
Test status
Simulation time 84023354 ps
CPU time 1 seconds
Started Aug 07 05:01:30 PM PDT 24
Finished Aug 07 05:01:31 PM PDT 24
Peak memory 200064 kb
Host smart-ad509373-6617-43c2-ad27-2c848f773328
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324619333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3324619333
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1353345345
Short name T98
Test name
Test status
Simulation time 282070510 ps
CPU time 2.12 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 208180 kb
Host smart-1b0e9726-d0b2-4563-882b-13c7b5eb55d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353345345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1353345345
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2016836675
Short name T122
Test name
Test status
Simulation time 896367279 ps
CPU time 3.1 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:41 PM PDT 24
Peak memory 200192 kb
Host smart-33716d95-e8cd-4c12-a5c7-0362fcc4e62b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016836675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2016836675
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3976804202
Short name T620
Test name
Test status
Simulation time 397690825 ps
CPU time 2.59 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:47 PM PDT 24
Peak memory 200144 kb
Host smart-09d5eced-3e6c-48cc-949b-19046bfc376b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976804202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
976804202
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2299373307
Short name T137
Test name
Test status
Simulation time 492038775 ps
CPU time 5.77 seconds
Started Aug 07 05:01:38 PM PDT 24
Finished Aug 07 05:01:44 PM PDT 24
Peak memory 200100 kb
Host smart-3faa5e42-0460-4abc-9d70-9b46d1a410d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299373307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
299373307
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1759056183
Short name T543
Test name
Test status
Simulation time 117533372 ps
CPU time 0.9 seconds
Started Aug 07 05:01:35 PM PDT 24
Finished Aug 07 05:01:36 PM PDT 24
Peak memory 199920 kb
Host smart-9af97be8-5410-440e-b9e7-68b433c13314
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759056183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
759056183
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3560672787
Short name T566
Test name
Test status
Simulation time 141036763 ps
CPU time 1.15 seconds
Started Aug 07 05:01:38 PM PDT 24
Finished Aug 07 05:01:39 PM PDT 24
Peak memory 208264 kb
Host smart-5d3036d4-39d1-46ac-a782-da9927baddfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560672787 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3560672787
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2163094987
Short name T611
Test name
Test status
Simulation time 60446078 ps
CPU time 0.72 seconds
Started Aug 07 05:01:34 PM PDT 24
Finished Aug 07 05:01:34 PM PDT 24
Peak memory 200072 kb
Host smart-784e229f-53fe-41c1-8e6f-82df941e3f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163094987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2163094987
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1629714650
Short name T599
Test name
Test status
Simulation time 208452591 ps
CPU time 1.58 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:46 PM PDT 24
Peak memory 200192 kb
Host smart-e5e28e1d-ea7d-4018-bb28-f102889e9cf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629714650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1629714650
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1244239642
Short name T603
Test name
Test status
Simulation time 180622942 ps
CPU time 2.53 seconds
Started Aug 07 05:01:31 PM PDT 24
Finished Aug 07 05:01:34 PM PDT 24
Peak memory 208352 kb
Host smart-37b98e11-55bb-4eca-95df-cfecce5df07f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244239642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1244239642
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.321991401
Short name T575
Test name
Test status
Simulation time 200700661 ps
CPU time 1.35 seconds
Started Aug 07 05:01:42 PM PDT 24
Finished Aug 07 05:01:44 PM PDT 24
Peak memory 208352 kb
Host smart-f7ea5829-7c31-447a-adb0-351d44f32698
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321991401 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.321991401
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1038174013
Short name T569
Test name
Test status
Simulation time 73070588 ps
CPU time 0.77 seconds
Started Aug 07 05:01:47 PM PDT 24
Finished Aug 07 05:01:48 PM PDT 24
Peak memory 200020 kb
Host smart-642c71ff-d2b9-467c-9e52-e64a8f12c670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038174013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1038174013
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.169064103
Short name T590
Test name
Test status
Simulation time 209538906 ps
CPU time 1.44 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 200148 kb
Host smart-a5b19a5f-c62c-4b61-bcc8-beab7e56306b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169064103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.169064103
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.929330998
Short name T615
Test name
Test status
Simulation time 498653098 ps
CPU time 1.97 seconds
Started Aug 07 05:01:45 PM PDT 24
Finished Aug 07 05:01:47 PM PDT 24
Peak memory 200144 kb
Host smart-71940463-ae3d-48c6-8015-c2f56bda9242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929330998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.929330998
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.109230438
Short name T549
Test name
Test status
Simulation time 119704099 ps
CPU time 0.95 seconds
Started Aug 07 05:01:41 PM PDT 24
Finished Aug 07 05:01:42 PM PDT 24
Peak memory 200124 kb
Host smart-0590a612-7347-4d88-b834-848a0992dd32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109230438 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.109230438
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.684033957
Short name T557
Test name
Test status
Simulation time 75030752 ps
CPU time 0.79 seconds
Started Aug 07 05:01:45 PM PDT 24
Finished Aug 07 05:01:46 PM PDT 24
Peak memory 200020 kb
Host smart-c3a11683-a96a-4fb1-93da-41514757a2a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684033957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.684033957
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1728361528
Short name T589
Test name
Test status
Simulation time 122281052 ps
CPU time 1.08 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 200060 kb
Host smart-a480c9b1-7514-41a8-a627-9d7d315fb9d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728361528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1728361528
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1614418213
Short name T560
Test name
Test status
Simulation time 126486410 ps
CPU time 0.95 seconds
Started Aug 07 05:01:49 PM PDT 24
Finished Aug 07 05:01:50 PM PDT 24
Peak memory 200036 kb
Host smart-6a01655b-87bf-484a-915d-bf4349fc0342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614418213 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1614418213
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.948744145
Short name T586
Test name
Test status
Simulation time 90154012 ps
CPU time 0.87 seconds
Started Aug 07 05:01:42 PM PDT 24
Finished Aug 07 05:01:43 PM PDT 24
Peak memory 199928 kb
Host smart-7a4277e5-a8b2-4b6a-b825-a5bd6bceeeaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948744145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.948744145
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1471040250
Short name T579
Test name
Test status
Simulation time 130649733 ps
CPU time 1.3 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 200072 kb
Host smart-7e0690b3-cad4-4927-8a07-cf19f2dfb640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471040250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1471040250
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.271524091
Short name T72
Test name
Test status
Simulation time 505749554 ps
CPU time 3.72 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:48 PM PDT 24
Peak memory 211740 kb
Host smart-236e4c32-135d-4ff0-989b-92d06248bdb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271524091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.271524091
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3311396537
Short name T556
Test name
Test status
Simulation time 88150350 ps
CPU time 0.86 seconds
Started Aug 07 05:01:48 PM PDT 24
Finished Aug 07 05:01:49 PM PDT 24
Peak memory 199900 kb
Host smart-9f042f17-02a5-42b1-8ac1-91ca2e674d07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311396537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3311396537
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.621967862
Short name T561
Test name
Test status
Simulation time 127738340 ps
CPU time 1.1 seconds
Started Aug 07 05:01:50 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200104 kb
Host smart-e11c365f-1eb6-4701-a230-cbcdde04f22b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621967862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.621967862
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3361711215
Short name T125
Test name
Test status
Simulation time 190449229 ps
CPU time 2.64 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 211924 kb
Host smart-24eb713b-0337-4f43-9cfd-3c9f50c0bbe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361711215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3361711215
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4126430138
Short name T123
Test name
Test status
Simulation time 495499864 ps
CPU time 2.07 seconds
Started Aug 07 05:01:50 PM PDT 24
Finished Aug 07 05:01:53 PM PDT 24
Peak memory 200168 kb
Host smart-153cef3e-8555-44d3-bbf0-b87e1dba65c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126430138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.4126430138
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1374685957
Short name T606
Test name
Test status
Simulation time 128498890 ps
CPU time 1.39 seconds
Started Aug 07 05:01:49 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 208332 kb
Host smart-ff6deb24-8da7-40f4-be48-f1465d890e0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374685957 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1374685957
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.487404352
Short name T551
Test name
Test status
Simulation time 73022537 ps
CPU time 0.77 seconds
Started Aug 07 05:01:50 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200000 kb
Host smart-8472b80e-536c-412b-8e77-1f1c6ca02c6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487404352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.487404352
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1301839582
Short name T613
Test name
Test status
Simulation time 182236698 ps
CPU time 1.45 seconds
Started Aug 07 05:01:49 PM PDT 24
Finished Aug 07 05:01:50 PM PDT 24
Peak memory 200136 kb
Host smart-c614dcf0-01fd-401c-8ce6-3047ec5ccb53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301839582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1301839582
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.356464823
Short name T574
Test name
Test status
Simulation time 131704616 ps
CPU time 1.92 seconds
Started Aug 07 05:01:52 PM PDT 24
Finished Aug 07 05:01:54 PM PDT 24
Peak memory 210148 kb
Host smart-93ab8341-3436-4f18-9fa6-d48bd5269e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356464823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.356464823
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.189718471
Short name T116
Test name
Test status
Simulation time 779002279 ps
CPU time 3.18 seconds
Started Aug 07 05:01:48 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200248 kb
Host smart-8ee22c0c-c10d-45f3-b4f5-685c34ab25d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189718471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.189718471
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2345443689
Short name T588
Test name
Test status
Simulation time 120442539 ps
CPU time 1.28 seconds
Started Aug 07 05:01:48 PM PDT 24
Finished Aug 07 05:01:50 PM PDT 24
Peak memory 208492 kb
Host smart-b20c05ba-1d84-4ee0-925a-33550d01bd83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345443689 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2345443689
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4020760632
Short name T107
Test name
Test status
Simulation time 129487367 ps
CPU time 1.08 seconds
Started Aug 07 05:01:51 PM PDT 24
Finished Aug 07 05:01:52 PM PDT 24
Peak memory 200020 kb
Host smart-c40b8bf9-349e-4dcf-9f92-b29d13360a24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020760632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4020760632
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3418699772
Short name T562
Test name
Test status
Simulation time 358205963 ps
CPU time 2.36 seconds
Started Aug 07 05:01:50 PM PDT 24
Finished Aug 07 05:01:53 PM PDT 24
Peak memory 216368 kb
Host smart-f9c502cc-ef40-4f04-8da6-f34808ce9e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418699772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3418699772
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.838900835
Short name T67
Test name
Test status
Simulation time 94480208 ps
CPU time 0.95 seconds
Started Aug 07 05:01:50 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200152 kb
Host smart-dbaf21c2-9262-49f9-90c4-0990367b76ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838900835 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.838900835
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3543098517
Short name T617
Test name
Test status
Simulation time 73285074 ps
CPU time 0.81 seconds
Started Aug 07 05:01:48 PM PDT 24
Finished Aug 07 05:01:49 PM PDT 24
Peak memory 199952 kb
Host smart-5516905f-64e8-40a7-b87a-98667c91d05a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543098517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3543098517
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1316322062
Short name T614
Test name
Test status
Simulation time 136956693 ps
CPU time 1.07 seconds
Started Aug 07 05:01:51 PM PDT 24
Finished Aug 07 05:01:52 PM PDT 24
Peak memory 200016 kb
Host smart-838888cb-a797-41e3-b0d9-201de2316379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316322062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1316322062
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.1766622858
Short name T571
Test name
Test status
Simulation time 463582894 ps
CPU time 3.22 seconds
Started Aug 07 05:01:51 PM PDT 24
Finished Aug 07 05:01:54 PM PDT 24
Peak memory 208288 kb
Host smart-e2df9732-0d0e-4aa5-a2a7-57ff3cde457a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766622858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1766622858
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1869811824
Short name T69
Test name
Test status
Simulation time 424246063 ps
CPU time 1.85 seconds
Started Aug 07 05:01:49 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200224 kb
Host smart-bd194d2a-9442-4338-84d9-07048a441da4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869811824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1869811824
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2729014638
Short name T591
Test name
Test status
Simulation time 139943597 ps
CPU time 1.07 seconds
Started Aug 07 05:01:57 PM PDT 24
Finished Aug 07 05:01:58 PM PDT 24
Peak memory 200124 kb
Host smart-1cc4c999-a679-450f-a221-06672cfdd5d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729014638 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2729014638
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3125627827
Short name T616
Test name
Test status
Simulation time 77567901 ps
CPU time 0.78 seconds
Started Aug 07 05:01:48 PM PDT 24
Finished Aug 07 05:01:49 PM PDT 24
Peak memory 199968 kb
Host smart-17b78e80-d4ac-4ed9-bfb7-45ff0e0c348b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125627827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3125627827
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2819859804
Short name T66
Test name
Test status
Simulation time 285818582 ps
CPU time 1.75 seconds
Started Aug 07 05:01:49 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200148 kb
Host smart-5bf29834-7a76-4582-9095-5ddf0f7dd7cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819859804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2819859804
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3010449806
Short name T595
Test name
Test status
Simulation time 183665310 ps
CPU time 2.63 seconds
Started Aug 07 05:01:48 PM PDT 24
Finished Aug 07 05:01:50 PM PDT 24
Peak memory 216276 kb
Host smart-cf315f1b-dc31-4edb-a483-151479fcbb5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010449806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3010449806
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3263836613
Short name T554
Test name
Test status
Simulation time 503404335 ps
CPU time 2.03 seconds
Started Aug 07 05:01:49 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200136 kb
Host smart-fb06d25a-2209-4fc3-be65-92a341424a08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263836613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3263836613
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1763409580
Short name T572
Test name
Test status
Simulation time 131905606 ps
CPU time 1.47 seconds
Started Aug 07 05:01:53 PM PDT 24
Finished Aug 07 05:01:55 PM PDT 24
Peak memory 208348 kb
Host smart-af1d1fb9-e7bc-4e4e-9928-45afd6aa1ae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763409580 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1763409580
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3809341416
Short name T114
Test name
Test status
Simulation time 80865862 ps
CPU time 0.86 seconds
Started Aug 07 05:01:56 PM PDT 24
Finished Aug 07 05:01:57 PM PDT 24
Peak memory 199964 kb
Host smart-8a3d0a25-3f84-4d97-9688-02a607672b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809341416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3809341416
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1147941134
Short name T108
Test name
Test status
Simulation time 237410078 ps
CPU time 1.52 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:01:57 PM PDT 24
Peak memory 200208 kb
Host smart-71705715-2bc4-46b1-931a-6f35d4a2b20d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147941134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1147941134
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.22322750
Short name T582
Test name
Test status
Simulation time 157624459 ps
CPU time 2.24 seconds
Started Aug 07 05:01:57 PM PDT 24
Finished Aug 07 05:01:59 PM PDT 24
Peak memory 216292 kb
Host smart-2dd23816-4e1a-490d-9b32-8773ca42e673
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.22322750
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2420840915
Short name T618
Test name
Test status
Simulation time 467496144 ps
CPU time 1.95 seconds
Started Aug 07 05:01:53 PM PDT 24
Finished Aug 07 05:01:55 PM PDT 24
Peak memory 200120 kb
Host smart-08cfda6f-bc2e-4f57-9e8e-18303dbef33b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420840915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2420840915
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1487293698
Short name T596
Test name
Test status
Simulation time 110665646 ps
CPU time 0.98 seconds
Started Aug 07 05:01:56 PM PDT 24
Finished Aug 07 05:01:57 PM PDT 24
Peak memory 200144 kb
Host smart-049fc66e-733b-43f5-a9b8-1f08e4ca31b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487293698 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1487293698
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2946040827
Short name T548
Test name
Test status
Simulation time 77904965 ps
CPU time 0.78 seconds
Started Aug 07 05:02:01 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 199988 kb
Host smart-0cc4a580-12fa-407f-bc25-c0b8e472d914
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946040827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2946040827
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4256725543
Short name T605
Test name
Test status
Simulation time 135874401 ps
CPU time 1.39 seconds
Started Aug 07 05:01:57 PM PDT 24
Finished Aug 07 05:01:58 PM PDT 24
Peak memory 200160 kb
Host smart-ee82535b-b63b-4b2e-a9d1-3a99026eafbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256725543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4256725543
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3077180363
Short name T594
Test name
Test status
Simulation time 214941680 ps
CPU time 1.55 seconds
Started Aug 07 05:01:58 PM PDT 24
Finished Aug 07 05:02:00 PM PDT 24
Peak memory 208220 kb
Host smart-b36e604e-bf1b-4fdb-b731-61f2b1fd5506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077180363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3077180363
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.427832147
Short name T119
Test name
Test status
Simulation time 504287814 ps
CPU time 1.98 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:01:57 PM PDT 24
Peak memory 200200 kb
Host smart-5b714530-42d3-4d58-bfa2-8802bc6a503c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427832147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.427832147
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1867075816
Short name T564
Test name
Test status
Simulation time 347076256 ps
CPU time 2.52 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:40 PM PDT 24
Peak memory 208292 kb
Host smart-4f791021-5ff9-4ec8-9dd2-74b457e7e66f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867075816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
867075816
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.717719908
Short name T546
Test name
Test status
Simulation time 479946009 ps
CPU time 5.57 seconds
Started Aug 07 05:01:35 PM PDT 24
Finished Aug 07 05:01:41 PM PDT 24
Peak memory 200124 kb
Host smart-8ca3687b-0e4b-4447-877c-0b037d7cddaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717719908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.717719908
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.68375472
Short name T558
Test name
Test status
Simulation time 136526435 ps
CPU time 0.91 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:38 PM PDT 24
Peak memory 200032 kb
Host smart-58c2ec20-7310-4a0d-bd17-529f91027ab6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68375472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.68375472
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1815397620
Short name T570
Test name
Test status
Simulation time 115708047 ps
CPU time 1 seconds
Started Aug 07 05:01:36 PM PDT 24
Finished Aug 07 05:01:37 PM PDT 24
Peak memory 200120 kb
Host smart-c44afa64-22f1-4287-86bd-7f50de124ca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815397620 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1815397620
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2040882389
Short name T609
Test name
Test status
Simulation time 63704996 ps
CPU time 0.83 seconds
Started Aug 07 05:01:32 PM PDT 24
Finished Aug 07 05:01:33 PM PDT 24
Peak memory 200040 kb
Host smart-59fb674e-88ed-4d82-8797-87abfb3d805f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040882389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2040882389
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1298594643
Short name T593
Test name
Test status
Simulation time 107771812 ps
CPU time 1.29 seconds
Started Aug 07 05:01:36 PM PDT 24
Finished Aug 07 05:01:38 PM PDT 24
Peak memory 200156 kb
Host smart-dfe1b849-f851-4f21-a2d6-ca0c6a7851a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298594643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1298594643
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1800626789
Short name T96
Test name
Test status
Simulation time 483705974 ps
CPU time 3.27 seconds
Started Aug 07 05:01:30 PM PDT 24
Finished Aug 07 05:01:33 PM PDT 24
Peak memory 216172 kb
Host smart-b1c2aa6a-8ecc-421a-8754-0537d7e31a26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800626789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1800626789
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3246227892
Short name T619
Test name
Test status
Simulation time 422153834 ps
CPU time 1.87 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:46 PM PDT 24
Peak memory 200208 kb
Host smart-43cefdf1-abc8-4f4b-9280-f5b419e32ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246227892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3246227892
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.450711232
Short name T573
Test name
Test status
Simulation time 268661725 ps
CPU time 1.69 seconds
Started Aug 07 05:01:38 PM PDT 24
Finished Aug 07 05:01:40 PM PDT 24
Peak memory 200104 kb
Host smart-2d414062-a432-4ab1-8b7f-d34fb453fee8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450711232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.450711232
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2573752557
Short name T552
Test name
Test status
Simulation time 490906179 ps
CPU time 5.82 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:43 PM PDT 24
Peak memory 199972 kb
Host smart-b1fa0b46-0d38-4f51-a060-8f60a137e266
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573752557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
573752557
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.199073362
Short name T565
Test name
Test status
Simulation time 148373252 ps
CPU time 0.93 seconds
Started Aug 07 05:01:39 PM PDT 24
Finished Aug 07 05:01:40 PM PDT 24
Peak memory 200044 kb
Host smart-baa2c597-3bc4-4650-a3fc-7f47f10fb8fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199073362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.199073362
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2785580747
Short name T547
Test name
Test status
Simulation time 131082156 ps
CPU time 1.12 seconds
Started Aug 07 05:01:35 PM PDT 24
Finished Aug 07 05:01:36 PM PDT 24
Peak memory 208196 kb
Host smart-397d9670-1d31-4b18-91b3-70d2807aaf19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785580747 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2785580747
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.935856465
Short name T110
Test name
Test status
Simulation time 60979882 ps
CPU time 0.74 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:38 PM PDT 24
Peak memory 199980 kb
Host smart-3805d3aa-457d-4462-8da2-bf818ca0f830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935856465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.935856465
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2355207933
Short name T610
Test name
Test status
Simulation time 128656082 ps
CPU time 1.26 seconds
Started Aug 07 05:01:39 PM PDT 24
Finished Aug 07 05:01:40 PM PDT 24
Peak memory 200140 kb
Host smart-2d12b2b5-cf2f-4bfa-8872-488849655b9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355207933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.2355207933
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.940074863
Short name T71
Test name
Test status
Simulation time 281191716 ps
CPU time 2.34 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:46 PM PDT 24
Peak memory 208352 kb
Host smart-8b60d4ea-8c82-408a-9fcf-8d5b93945756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940074863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.940074863
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1939855649
Short name T121
Test name
Test status
Simulation time 890130867 ps
CPU time 3.19 seconds
Started Aug 07 05:01:42 PM PDT 24
Finished Aug 07 05:01:46 PM PDT 24
Peak memory 200192 kb
Host smart-b3809216-7b82-4919-978f-e9c96220951e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939855649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1939855649
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.149783349
Short name T544
Test name
Test status
Simulation time 254324622 ps
CPU time 1.6 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:39 PM PDT 24
Peak memory 200004 kb
Host smart-0cba6dc7-acb5-4359-b100-267b432d52de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149783349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.149783349
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3807716655
Short name T607
Test name
Test status
Simulation time 476950552 ps
CPU time 5.65 seconds
Started Aug 07 05:01:36 PM PDT 24
Finished Aug 07 05:01:42 PM PDT 24
Peak memory 200112 kb
Host smart-e942cf8d-db10-4b70-b682-5ed45c5e69dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807716655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
807716655
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2785400010
Short name T545
Test name
Test status
Simulation time 113856859 ps
CPU time 0.85 seconds
Started Aug 07 05:01:35 PM PDT 24
Finished Aug 07 05:01:36 PM PDT 24
Peak memory 199980 kb
Host smart-6fdbb483-e437-4d87-a894-15b610390f50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785400010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
785400010
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.842109478
Short name T577
Test name
Test status
Simulation time 134666610 ps
CPU time 1.06 seconds
Started Aug 07 05:01:36 PM PDT 24
Finished Aug 07 05:01:38 PM PDT 24
Peak memory 208288 kb
Host smart-772d9c98-da60-4145-b66c-8a0282d6c451
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842109478 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.842109478
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1441158722
Short name T580
Test name
Test status
Simulation time 73605155 ps
CPU time 0.76 seconds
Started Aug 07 05:01:36 PM PDT 24
Finished Aug 07 05:01:37 PM PDT 24
Peak memory 199996 kb
Host smart-db0915cd-0be3-464b-ab84-6237cf0c8a1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441158722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1441158722
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3876415076
Short name T576
Test name
Test status
Simulation time 132451525 ps
CPU time 1.35 seconds
Started Aug 07 05:01:39 PM PDT 24
Finished Aug 07 05:01:40 PM PDT 24
Peak memory 200144 kb
Host smart-ddf8dd5c-8d6c-4fa0-8a4c-89c920ba2a45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876415076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3876415076
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3123798418
Short name T592
Test name
Test status
Simulation time 656792592 ps
CPU time 3.91 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 208092 kb
Host smart-90a5fa26-5548-4015-a89c-91610f02c371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123798418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3123798418
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3101042922
Short name T550
Test name
Test status
Simulation time 470450056 ps
CPU time 2.15 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:40 PM PDT 24
Peak memory 200124 kb
Host smart-7847db8d-d4e6-42b0-a55e-45a67409191b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101042922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.3101042922
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2553163104
Short name T602
Test name
Test status
Simulation time 109199080 ps
CPU time 1.06 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:38 PM PDT 24
Peak memory 208320 kb
Host smart-81c38155-dee5-467d-8eb4-3c10f971cf69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553163104 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2553163104
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1204985333
Short name T553
Test name
Test status
Simulation time 66078635 ps
CPU time 0.77 seconds
Started Aug 07 05:01:37 PM PDT 24
Finished Aug 07 05:01:38 PM PDT 24
Peak memory 199944 kb
Host smart-d24122b3-ddef-424e-8f6a-ec954a73a70c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204985333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1204985333
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.662411812
Short name T612
Test name
Test status
Simulation time 158064433 ps
CPU time 1.18 seconds
Started Aug 07 05:01:35 PM PDT 24
Finished Aug 07 05:01:36 PM PDT 24
Peak memory 200068 kb
Host smart-99c7c4be-66c1-4582-a309-56ce42d84c89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662411812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.662411812
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1125775376
Short name T555
Test name
Test status
Simulation time 383029391 ps
CPU time 2.97 seconds
Started Aug 07 05:01:34 PM PDT 24
Finished Aug 07 05:01:37 PM PDT 24
Peak memory 212652 kb
Host smart-4ae76900-aaa6-420d-86d4-3f112538471b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125775376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1125775376
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1174767984
Short name T99
Test name
Test status
Simulation time 460276274 ps
CPU time 1.86 seconds
Started Aug 07 05:01:36 PM PDT 24
Finished Aug 07 05:01:39 PM PDT 24
Peak memory 200152 kb
Host smart-29a1474d-f4e1-4efc-b5f9-f82eabc935e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174767984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1174767984
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1308650027
Short name T585
Test name
Test status
Simulation time 192779599 ps
CPU time 1.28 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 208320 kb
Host smart-8a07ac17-310f-46f5-8ca9-f0d2437b1a87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308650027 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1308650027
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1038147360
Short name T113
Test name
Test status
Simulation time 58688006 ps
CPU time 0.74 seconds
Started Aug 07 05:01:39 PM PDT 24
Finished Aug 07 05:01:40 PM PDT 24
Peak memory 200044 kb
Host smart-2444cd98-ded7-4881-8341-f5c46625d7e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038147360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1038147360
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3876789068
Short name T600
Test name
Test status
Simulation time 119532074 ps
CPU time 1.1 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:44 PM PDT 24
Peak memory 199796 kb
Host smart-2c9ba5d3-c9c9-428f-b448-d48cdc1d7f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876789068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3876789068
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.312708232
Short name T587
Test name
Test status
Simulation time 139789561 ps
CPU time 2.18 seconds
Started Aug 07 05:01:36 PM PDT 24
Finished Aug 07 05:01:39 PM PDT 24
Peak memory 216336 kb
Host smart-e564b1c8-f1bb-40bf-a5d9-e258890d4c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312708232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.312708232
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3792024879
Short name T136
Test name
Test status
Simulation time 800031495 ps
CPU time 2.85 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:46 PM PDT 24
Peak memory 199776 kb
Host smart-b4d94508-5723-458b-86e7-4dbfc49f7b70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792024879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3792024879
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1986980332
Short name T608
Test name
Test status
Simulation time 105453275 ps
CPU time 1.12 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 208380 kb
Host smart-4f4196fa-f9fa-4589-b4fe-ec7e900b11ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986980332 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1986980332
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.4172368586
Short name T578
Test name
Test status
Simulation time 92115181 ps
CPU time 0.9 seconds
Started Aug 07 05:01:42 PM PDT 24
Finished Aug 07 05:01:43 PM PDT 24
Peak memory 199940 kb
Host smart-c9af3a87-99cb-481f-8a45-3699b4b2c384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172368586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.4172368586
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.178460813
Short name T567
Test name
Test status
Simulation time 131833192 ps
CPU time 1.04 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:44 PM PDT 24
Peak memory 199944 kb
Host smart-2cf3fdbc-6fb8-4a7c-9a78-d0693b54cede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178460813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sam
e_csr_outstanding.178460813
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3130196563
Short name T95
Test name
Test status
Simulation time 143526179 ps
CPU time 2.13 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:47 PM PDT 24
Peak memory 216496 kb
Host smart-feec78e1-094b-4053-beb5-3aab8d3a77fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130196563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3130196563
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.452260870
Short name T604
Test name
Test status
Simulation time 939964252 ps
CPU time 3.21 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:28 PM PDT 24
Peak memory 200124 kb
Host smart-82529dca-60ef-4389-b9eb-6d1b18a4ddaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452260870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
452260870
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3813341734
Short name T126
Test name
Test status
Simulation time 195832556 ps
CPU time 1.95 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 208480 kb
Host smart-8a0f92b2-a1a2-4c21-b918-576daa247a9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813341734 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3813341734
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4111126735
Short name T111
Test name
Test status
Simulation time 54438253 ps
CPU time 0.75 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 199940 kb
Host smart-57d536d4-59cc-46d0-a4d5-3e79d6d09eb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111126735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4111126735
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.731493423
Short name T584
Test name
Test status
Simulation time 78776749 ps
CPU time 1.01 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 200072 kb
Host smart-94b68e3b-55a8-4bbb-88a5-2d195c9121ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731493423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.731493423
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.282635520
Short name T559
Test name
Test status
Simulation time 541165568 ps
CPU time 3.32 seconds
Started Aug 07 05:01:42 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 208308 kb
Host smart-0c805add-8b89-48b6-a78e-ae055d7bf104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282635520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.282635520
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3896913592
Short name T118
Test name
Test status
Simulation time 944832258 ps
CPU time 3.58 seconds
Started Aug 07 05:01:47 PM PDT 24
Finished Aug 07 05:01:51 PM PDT 24
Peak memory 200240 kb
Host smart-70929b11-6413-44ef-b841-ceb5274d6210
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896913592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3896913592
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2164154601
Short name T601
Test name
Test status
Simulation time 189155027 ps
CPU time 1.27 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:45 PM PDT 24
Peak memory 208296 kb
Host smart-66fc9169-7902-4c58-8b0f-b8e8836b5199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164154601 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2164154601
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.4071856283
Short name T112
Test name
Test status
Simulation time 60870246 ps
CPU time 0.82 seconds
Started Aug 07 05:01:43 PM PDT 24
Finished Aug 07 05:01:44 PM PDT 24
Peak memory 199872 kb
Host smart-ab47da7b-6f59-42e4-b106-de0568f695d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071856283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.4071856283
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.247029791
Short name T115
Test name
Test status
Simulation time 139693189 ps
CPU time 1.34 seconds
Started Aug 07 05:01:41 PM PDT 24
Finished Aug 07 05:01:43 PM PDT 24
Peak memory 200104 kb
Host smart-a0537b7c-0093-4c82-b76b-badec4f061a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247029791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.247029791
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3243074382
Short name T127
Test name
Test status
Simulation time 236440070 ps
CPU time 1.72 seconds
Started Aug 07 05:01:42 PM PDT 24
Finished Aug 07 05:01:44 PM PDT 24
Peak memory 208256 kb
Host smart-fab646a7-2321-4fb8-b97b-bbca2369d24b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243074382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3243074382
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1674188060
Short name T581
Test name
Test status
Simulation time 835002641 ps
CPU time 2.87 seconds
Started Aug 07 05:01:44 PM PDT 24
Finished Aug 07 05:01:47 PM PDT 24
Peak memory 200200 kb
Host smart-4c2cc8a1-e887-4863-8c86-8df16e22a0a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674188060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1674188060
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2307142444
Short name T386
Test name
Test status
Simulation time 71695629 ps
CPU time 0.74 seconds
Started Aug 07 06:22:37 PM PDT 24
Finished Aug 07 06:22:38 PM PDT 24
Peak memory 200144 kb
Host smart-601bd8b3-75a8-4ab2-8745-ac5e159bdcb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307142444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2307142444
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1166571977
Short name T364
Test name
Test status
Simulation time 1220539983 ps
CPU time 6.11 seconds
Started Aug 07 06:22:39 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 217772 kb
Host smart-27a261a1-5605-4a44-a6a1-9cdcd8667854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166571977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1166571977
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3594081386
Short name T5
Test name
Test status
Simulation time 244524395 ps
CPU time 1.15 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 217568 kb
Host smart-d1c14e56-cbf2-4a95-9b98-a5f0640f08ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594081386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3594081386
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3733707201
Short name T51
Test name
Test status
Simulation time 1466961671 ps
CPU time 6.01 seconds
Started Aug 07 06:22:39 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 200528 kb
Host smart-7f332fab-8e72-4d41-8af6-5ae35c591141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733707201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3733707201
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.274100838
Short name T156
Test name
Test status
Simulation time 161287544 ps
CPU time 1.13 seconds
Started Aug 07 06:22:44 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 200360 kb
Host smart-799df06c-8773-4280-a2de-ef0db7060a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274100838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.274100838
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2619542153
Short name T294
Test name
Test status
Simulation time 195452061 ps
CPU time 1.45 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:43 PM PDT 24
Peak memory 200540 kb
Host smart-6f6d2275-56a3-4f5e-b83e-4983d6d66fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619542153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2619542153
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1101946547
Short name T129
Test name
Test status
Simulation time 5482075399 ps
CPU time 18.24 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:23:00 PM PDT 24
Peak memory 200632 kb
Host smart-11a72451-12e2-40ea-ab96-66fd693ad778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101946547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1101946547
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.41650417
Short name T388
Test name
Test status
Simulation time 303917985 ps
CPU time 1.93 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:44 PM PDT 24
Peak memory 208492 kb
Host smart-b508007a-5b76-4941-b803-e6419c06b57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41650417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.41650417
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.75481904
Short name T62
Test name
Test status
Simulation time 91027739 ps
CPU time 0.84 seconds
Started Aug 07 06:22:38 PM PDT 24
Finished Aug 07 06:22:39 PM PDT 24
Peak memory 200352 kb
Host smart-e5f505e8-bfec-4f54-b786-26a709ea2953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75481904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.75481904
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1603968246
Short name T53
Test name
Test status
Simulation time 58331605 ps
CPU time 0.71 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:42 PM PDT 24
Peak memory 200168 kb
Host smart-bdf46a5a-060a-42b7-b171-5e2dfaf6c5a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603968246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1603968246
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1536574883
Short name T377
Test name
Test status
Simulation time 245035614 ps
CPU time 1.13 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:43 PM PDT 24
Peak memory 217748 kb
Host smart-245fe47b-5572-438d-b90f-c7b04d206c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536574883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1536574883
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2373477716
Short name T24
Test name
Test status
Simulation time 199402089 ps
CPU time 0.97 seconds
Started Aug 07 06:22:41 PM PDT 24
Finished Aug 07 06:22:42 PM PDT 24
Peak memory 200144 kb
Host smart-527af08b-9ca6-4bcc-b16c-515f602e0c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373477716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2373477716
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2767653277
Short name T289
Test name
Test status
Simulation time 1729493027 ps
CPU time 6.7 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:49 PM PDT 24
Peak memory 200548 kb
Host smart-b1ae7989-e4d4-4ea1-b72c-c08c574c2e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767653277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2767653277
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1397137913
Short name T73
Test name
Test status
Simulation time 16526579605 ps
CPU time 32.99 seconds
Started Aug 07 06:22:41 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 217292 kb
Host smart-7496b8d5-d1d7-40fe-adbd-c263756063a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397137913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1397137913
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3920553944
Short name T528
Test name
Test status
Simulation time 162826868 ps
CPU time 1.2 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 200356 kb
Host smart-2d3cb3af-4b1c-4a89-aaa9-13668f9c96c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920553944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3920553944
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3210194532
Short name T415
Test name
Test status
Simulation time 123248314 ps
CPU time 1.16 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:22:41 PM PDT 24
Peak memory 200496 kb
Host smart-15feefe4-6f94-4b35-8e92-444f83d8a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210194532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3210194532
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2977226992
Short name T308
Test name
Test status
Simulation time 4835950039 ps
CPU time 23.41 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 200584 kb
Host smart-d4b3f9cc-48bf-4ce0-9df0-1b80d345b93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977226992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2977226992
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.496848611
Short name T244
Test name
Test status
Simulation time 196942094 ps
CPU time 1.31 seconds
Started Aug 07 06:22:40 PM PDT 24
Finished Aug 07 06:22:42 PM PDT 24
Peak memory 200388 kb
Host smart-e13de26a-510a-474c-b519-4062453bec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496848611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.496848611
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1540240853
Short name T334
Test name
Test status
Simulation time 75398839 ps
CPU time 0.82 seconds
Started Aug 07 06:23:04 PM PDT 24
Finished Aug 07 06:23:05 PM PDT 24
Peak memory 200164 kb
Host smart-9b34e33d-ad88-4e1c-8233-e36740fd15dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540240853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1540240853
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.2546399969
Short name T39
Test name
Test status
Simulation time 1227716305 ps
CPU time 5.45 seconds
Started Aug 07 06:23:02 PM PDT 24
Finished Aug 07 06:23:07 PM PDT 24
Peak memory 221732 kb
Host smart-9525f85e-22c2-4b03-8e01-e0aa0f5a162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546399969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2546399969
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1460155349
Short name T504
Test name
Test status
Simulation time 244119272 ps
CPU time 1.16 seconds
Started Aug 07 06:23:03 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 217496 kb
Host smart-6c45d7ee-5a29-459d-bf64-300cfcbc23d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460155349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1460155349
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1232094379
Short name T393
Test name
Test status
Simulation time 148363081 ps
CPU time 0.82 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:56 PM PDT 24
Peak memory 200160 kb
Host smart-f82cb321-2aa9-441f-93ea-b74a011a1445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232094379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1232094379
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3131250931
Short name T301
Test name
Test status
Simulation time 1138949902 ps
CPU time 6.01 seconds
Started Aug 07 06:23:02 PM PDT 24
Finished Aug 07 06:23:08 PM PDT 24
Peak memory 200556 kb
Host smart-7b0dc8ab-4aab-4dab-9612-3baa7dfeaa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131250931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3131250931
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2457467055
Short name T435
Test name
Test status
Simulation time 143065543 ps
CPU time 1.19 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:02 PM PDT 24
Peak memory 200348 kb
Host smart-d6c0ce34-d712-4fc1-a148-16bb95e179ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457467055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2457467055
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.1853929020
Short name T94
Test name
Test status
Simulation time 192947194 ps
CPU time 1.36 seconds
Started Aug 07 06:22:57 PM PDT 24
Finished Aug 07 06:22:59 PM PDT 24
Peak memory 200476 kb
Host smart-27327ea5-a0ff-484f-8b93-29092b02ae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853929020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1853929020
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.787799800
Short name T370
Test name
Test status
Simulation time 7701584307 ps
CPU time 33.48 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:34 PM PDT 24
Peak memory 200612 kb
Host smart-e3da1687-c5bd-4805-b4df-0e490c156dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787799800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.787799800
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2601965082
Short name T235
Test name
Test status
Simulation time 492539573 ps
CPU time 2.64 seconds
Started Aug 07 06:23:00 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 200296 kb
Host smart-2bf0b448-8f1c-48c2-a2c2-92d915585682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601965082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2601965082
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.694812088
Short name T441
Test name
Test status
Simulation time 72907885 ps
CPU time 0.78 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:02 PM PDT 24
Peak memory 200168 kb
Host smart-533f3a3d-c72c-4b07-b8d3-a1a261395f01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694812088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.694812088
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.1683755353
Short name T55
Test name
Test status
Simulation time 2177832034 ps
CPU time 8.06 seconds
Started Aug 07 06:22:59 PM PDT 24
Finished Aug 07 06:23:07 PM PDT 24
Peak memory 221816 kb
Host smart-36610e3d-b5c9-467e-8c46-031df5384fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683755353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1683755353
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2538335132
Short name T526
Test name
Test status
Simulation time 244448306 ps
CPU time 1.04 seconds
Started Aug 07 06:22:59 PM PDT 24
Finished Aug 07 06:23:00 PM PDT 24
Peak memory 217528 kb
Host smart-152ab572-a09e-4d20-aafb-de95a0037fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538335132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2538335132
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2586619343
Short name T15
Test name
Test status
Simulation time 98413745 ps
CPU time 0.77 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:02 PM PDT 24
Peak memory 200168 kb
Host smart-b387d565-f5d0-46dd-8467-0b79e6964bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586619343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2586619343
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1733551880
Short name T430
Test name
Test status
Simulation time 234164529 ps
CPU time 1.62 seconds
Started Aug 07 06:23:00 PM PDT 24
Finished Aug 07 06:23:02 PM PDT 24
Peak memory 200544 kb
Host smart-ccc11037-d85b-4d1e-9450-06042a679c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733551880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1733551880
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.818980244
Short name T321
Test name
Test status
Simulation time 2116760246 ps
CPU time 10.2 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 200588 kb
Host smart-acbb9b84-5b9b-4b2f-bad6-31bbf48b5a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818980244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.818980244
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1921983406
Short name T232
Test name
Test status
Simulation time 347445637 ps
CPU time 2.33 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 200340 kb
Host smart-18f49e45-8952-48a5-9925-acf46fb58ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921983406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1921983406
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1099526823
Short name T25
Test name
Test status
Simulation time 188361695 ps
CPU time 1.3 seconds
Started Aug 07 06:22:59 PM PDT 24
Finished Aug 07 06:23:00 PM PDT 24
Peak memory 200376 kb
Host smart-8989d20b-c1c0-47ce-8c77-2435765fdcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099526823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1099526823
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.923192159
Short name T347
Test name
Test status
Simulation time 76449250 ps
CPU time 0.79 seconds
Started Aug 07 06:23:05 PM PDT 24
Finished Aug 07 06:23:06 PM PDT 24
Peak memory 200156 kb
Host smart-6231fb45-d9b9-4bfd-b32d-9cd700d789cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923192159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.923192159
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2438454756
Short name T290
Test name
Test status
Simulation time 1894664305 ps
CPU time 7.28 seconds
Started Aug 07 06:23:08 PM PDT 24
Finished Aug 07 06:23:15 PM PDT 24
Peak memory 217804 kb
Host smart-7381d6f7-e64f-4fef-a781-accadc0a4fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438454756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2438454756
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2608798349
Short name T150
Test name
Test status
Simulation time 244618515 ps
CPU time 1.08 seconds
Started Aug 07 06:23:05 PM PDT 24
Finished Aug 07 06:23:06 PM PDT 24
Peak memory 217512 kb
Host smart-40e597b3-22f0-492d-8737-9bb4c9e20c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608798349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2608798349
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2289275658
Short name T480
Test name
Test status
Simulation time 125199932 ps
CPU time 0.85 seconds
Started Aug 07 06:23:03 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 200188 kb
Host smart-1e1eeb7f-9ae5-4e5d-8b56-3a9ecddf696d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289275658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2289275658
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2088062302
Short name T479
Test name
Test status
Simulation time 831615038 ps
CPU time 4.08 seconds
Started Aug 07 06:22:58 PM PDT 24
Finished Aug 07 06:23:02 PM PDT 24
Peak memory 200556 kb
Host smart-c48395f6-7c02-4d13-9415-b928ee5b8f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088062302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2088062302
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2779165105
Short name T166
Test name
Test status
Simulation time 103991470 ps
CPU time 1.03 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:02 PM PDT 24
Peak memory 200364 kb
Host smart-d399c88c-c7cc-42ea-9e15-84d8e6165c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779165105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2779165105
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3738157126
Short name T178
Test name
Test status
Simulation time 247607909 ps
CPU time 1.64 seconds
Started Aug 07 06:23:02 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 200436 kb
Host smart-93242918-24c5-4f8f-ab29-1d9c4652bb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738157126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3738157126
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.127642980
Short name T536
Test name
Test status
Simulation time 3672264363 ps
CPU time 17.78 seconds
Started Aug 07 06:23:07 PM PDT 24
Finished Aug 07 06:23:25 PM PDT 24
Peak memory 208820 kb
Host smart-b266882e-bc02-4ed2-a63b-b82198fcb6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127642980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.127642980
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3380315256
Short name T366
Test name
Test status
Simulation time 294076102 ps
CPU time 2.06 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 208472 kb
Host smart-ce0db80a-d1a2-470a-84a6-be246894e00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380315256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3380315256
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.673376540
Short name T13
Test name
Test status
Simulation time 192940593 ps
CPU time 1.41 seconds
Started Aug 07 06:23:01 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 200236 kb
Host smart-a3c086cd-b623-46f1-867a-451c7df2ec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673376540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.673376540
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3421873427
Short name T529
Test name
Test status
Simulation time 69858080 ps
CPU time 0.75 seconds
Started Aug 07 06:23:06 PM PDT 24
Finished Aug 07 06:23:07 PM PDT 24
Peak memory 200132 kb
Host smart-a90b7b21-8778-404f-8440-152c5211bcbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421873427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3421873427
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3481558080
Short name T380
Test name
Test status
Simulation time 243990541 ps
CPU time 1.07 seconds
Started Aug 07 06:23:07 PM PDT 24
Finished Aug 07 06:23:08 PM PDT 24
Peak memory 217576 kb
Host smart-65c633b2-b0e2-4dd9-a706-d9e348141ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481558080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3481558080
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.464154772
Short name T216
Test name
Test status
Simulation time 102498098 ps
CPU time 0.77 seconds
Started Aug 07 06:23:06 PM PDT 24
Finished Aug 07 06:23:07 PM PDT 24
Peak memory 200132 kb
Host smart-706ac11d-c3d8-4bf7-b650-69cd1156ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464154772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.464154772
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2222586884
Short name T131
Test name
Test status
Simulation time 1480669964 ps
CPU time 5.51 seconds
Started Aug 07 06:23:05 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 200568 kb
Host smart-6afc0e6e-76fe-4469-9b2c-6e48d2370cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222586884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2222586884
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3696213380
Short name T144
Test name
Test status
Simulation time 189025311 ps
CPU time 1.22 seconds
Started Aug 07 06:23:10 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 200392 kb
Host smart-6d5e81ac-bfb1-471b-abca-7f3d8ea02514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696213380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3696213380
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3021757339
Short name T133
Test name
Test status
Simulation time 221073368 ps
CPU time 1.42 seconds
Started Aug 07 06:23:06 PM PDT 24
Finished Aug 07 06:23:07 PM PDT 24
Peak memory 200528 kb
Host smart-783922b2-62cb-4349-bea8-256b4f368b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021757339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3021757339
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2598723729
Short name T291
Test name
Test status
Simulation time 7585388014 ps
CPU time 25.91 seconds
Started Aug 07 06:23:10 PM PDT 24
Finished Aug 07 06:23:36 PM PDT 24
Peak memory 200612 kb
Host smart-86f2ba51-e7da-4ba3-bbe3-d59f24aa8a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598723729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2598723729
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.452179956
Short name T474
Test name
Test status
Simulation time 321399019 ps
CPU time 2.17 seconds
Started Aug 07 06:23:07 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 200284 kb
Host smart-8f9c1283-821a-40af-a66c-17f28a957d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452179956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.452179956
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1889055922
Short name T342
Test name
Test status
Simulation time 260784066 ps
CPU time 1.4 seconds
Started Aug 07 06:23:07 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 200364 kb
Host smart-4ff8aab3-af70-465d-9dcf-d71a79892120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889055922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1889055922
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2748611502
Short name T538
Test name
Test status
Simulation time 78029855 ps
CPU time 0.85 seconds
Started Aug 07 06:23:09 PM PDT 24
Finished Aug 07 06:23:10 PM PDT 24
Peak memory 200120 kb
Host smart-b5dd7b45-907d-407a-8c43-969bdc97db00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748611502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2748611502
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1337781049
Short name T64
Test name
Test status
Simulation time 2383375367 ps
CPU time 9.16 seconds
Started Aug 07 06:23:08 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 217928 kb
Host smart-c07ca49a-c9c1-4a6e-9f6b-09c2d82c702d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337781049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1337781049
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.4069842730
Short name T372
Test name
Test status
Simulation time 243917000 ps
CPU time 1.15 seconds
Started Aug 07 06:23:05 PM PDT 24
Finished Aug 07 06:23:07 PM PDT 24
Peak memory 217516 kb
Host smart-48a9ce83-00c2-43a5-ba79-db890e474b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069842730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.4069842730
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1529869565
Short name T458
Test name
Test status
Simulation time 91822193 ps
CPU time 0.73 seconds
Started Aug 07 06:23:05 PM PDT 24
Finished Aug 07 06:23:06 PM PDT 24
Peak memory 200188 kb
Host smart-56749ecc-0d00-4e17-a7a4-4611dfcdbbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529869565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1529869565
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.807784400
Short name T84
Test name
Test status
Simulation time 1517714830 ps
CPU time 6.14 seconds
Started Aug 07 06:23:06 PM PDT 24
Finished Aug 07 06:23:12 PM PDT 24
Peak memory 200548 kb
Host smart-5b215835-bbcf-42f3-a2fd-aee22da75afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807784400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.807784400
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.738035831
Short name T138
Test name
Test status
Simulation time 100690732 ps
CPU time 0.96 seconds
Started Aug 07 06:23:10 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 200388 kb
Host smart-54faceaf-fba9-4b30-887f-173425575fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738035831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.738035831
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3030802319
Short name T12
Test name
Test status
Simulation time 113358340 ps
CPU time 1.22 seconds
Started Aug 07 06:23:08 PM PDT 24
Finished Aug 07 06:23:10 PM PDT 24
Peak memory 200492 kb
Host smart-03bf969c-fca4-4268-9346-926f8a004019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030802319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3030802319
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3847148225
Short name T181
Test name
Test status
Simulation time 234072083 ps
CPU time 1.51 seconds
Started Aug 07 06:23:05 PM PDT 24
Finished Aug 07 06:23:07 PM PDT 24
Peak memory 200484 kb
Host smart-4dfcf116-c864-4165-8170-d5bf383bfed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847148225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3847148225
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1387644697
Short name T154
Test name
Test status
Simulation time 355406247 ps
CPU time 2.34 seconds
Started Aug 07 06:23:08 PM PDT 24
Finished Aug 07 06:23:10 PM PDT 24
Peak memory 200300 kb
Host smart-52c154a7-11b2-4ac2-be18-4d3f6e835456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387644697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1387644697
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.131010928
Short name T304
Test name
Test status
Simulation time 122156820 ps
CPU time 1.02 seconds
Started Aug 07 06:23:09 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 200344 kb
Host smart-f3bd28d1-95a8-4844-a780-65f13872845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131010928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.131010928
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.438254840
Short name T481
Test name
Test status
Simulation time 61231738 ps
CPU time 0.72 seconds
Started Aug 07 06:23:15 PM PDT 24
Finished Aug 07 06:23:15 PM PDT 24
Peak memory 200132 kb
Host smart-00756165-11d6-4b58-b4de-f36f818aff3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438254840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.438254840
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3018541797
Short name T365
Test name
Test status
Simulation time 1898499127 ps
CPU time 6.91 seconds
Started Aug 07 06:23:08 PM PDT 24
Finished Aug 07 06:23:15 PM PDT 24
Peak memory 217568 kb
Host smart-99c82a63-504f-4941-b7ea-44ad033a5a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018541797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3018541797
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.9038459
Short name T190
Test name
Test status
Simulation time 244082677 ps
CPU time 1.1 seconds
Started Aug 07 06:23:08 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 217444 kb
Host smart-db475047-98cb-46f0-8837-9ec582515930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9038459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.9038459
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.427471535
Short name T438
Test name
Test status
Simulation time 235818620 ps
CPU time 0.93 seconds
Started Aug 07 06:23:09 PM PDT 24
Finished Aug 07 06:23:10 PM PDT 24
Peak memory 200156 kb
Host smart-3184cae9-e6ff-48f2-b94d-3b1adee0b6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427471535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.427471535
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2638743720
Short name T319
Test name
Test status
Simulation time 1880246626 ps
CPU time 6.68 seconds
Started Aug 07 06:23:10 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 200612 kb
Host smart-c18e60d5-b938-4454-82f9-6405820a5626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638743720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2638743720
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2201560409
Short name T333
Test name
Test status
Simulation time 99782449 ps
CPU time 1.01 seconds
Started Aug 07 06:23:10 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 200392 kb
Host smart-1314a48f-b50b-4a9f-8dab-26882b577618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201560409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2201560409
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4220695649
Short name T489
Test name
Test status
Simulation time 196164914 ps
CPU time 1.41 seconds
Started Aug 07 06:23:07 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 200580 kb
Host smart-83780a22-7fb5-4e48-a424-38219356455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220695649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4220695649
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.4185228127
Short name T286
Test name
Test status
Simulation time 4849863871 ps
CPU time 17.58 seconds
Started Aug 07 06:23:07 PM PDT 24
Finished Aug 07 06:23:24 PM PDT 24
Peak memory 200620 kb
Host smart-26eafa45-2cc6-4354-9be3-e8bf9b1d8181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185228127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4185228127
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.4032172370
Short name T90
Test name
Test status
Simulation time 121943575 ps
CPU time 1.46 seconds
Started Aug 07 06:23:07 PM PDT 24
Finished Aug 07 06:23:09 PM PDT 24
Peak memory 200260 kb
Host smart-aa6a4b21-3e4d-448c-9b29-4b6d7ae756a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032172370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.4032172370
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2244240709
Short name T132
Test name
Test status
Simulation time 230739204 ps
CPU time 1.38 seconds
Started Aug 07 06:23:10 PM PDT 24
Finished Aug 07 06:23:11 PM PDT 24
Peak memory 200308 kb
Host smart-d5ac0cb6-72bc-46c5-b1bd-307882bddfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244240709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2244240709
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.404050234
Short name T257
Test name
Test status
Simulation time 67371472 ps
CPU time 0.78 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:13 PM PDT 24
Peak memory 200172 kb
Host smart-46720ef4-04b5-42af-8e21-5441f8b513f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404050234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.404050234
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.777307293
Short name T471
Test name
Test status
Simulation time 2175414532 ps
CPU time 7.87 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:20 PM PDT 24
Peak memory 221796 kb
Host smart-f34e8a07-9fe1-4692-81eb-50591a09660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777307293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.777307293
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2192409845
Short name T30
Test name
Test status
Simulation time 244356838 ps
CPU time 1.16 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 217536 kb
Host smart-db982a4e-3ed4-4120-ab85-0ed8453b8629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192409845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2192409845
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1755042610
Short name T462
Test name
Test status
Simulation time 193857840 ps
CPU time 0.91 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 200056 kb
Host smart-807f4585-f8a0-40cb-8ea9-3faa7f4f3efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755042610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1755042610
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1961414180
Short name T450
Test name
Test status
Simulation time 1076905303 ps
CPU time 5.13 seconds
Started Aug 07 06:23:11 PM PDT 24
Finished Aug 07 06:23:16 PM PDT 24
Peak memory 200564 kb
Host smart-7189ca7f-63d4-4bcd-aa4e-fba6ab1ad626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961414180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1961414180
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2249885545
Short name T384
Test name
Test status
Simulation time 141243763 ps
CPU time 1.13 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:13 PM PDT 24
Peak memory 200352 kb
Host smart-9c86dcfb-7805-44e2-97c8-e54c35a4a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249885545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2249885545
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1987065530
Short name T152
Test name
Test status
Simulation time 186195775 ps
CPU time 1.38 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 200528 kb
Host smart-61f1421d-c366-4dc6-958c-4666ccfd9609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987065530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1987065530
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2688091733
Short name T213
Test name
Test status
Simulation time 11658830406 ps
CPU time 42.57 seconds
Started Aug 07 06:23:09 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 209860 kb
Host smart-5af5dc8e-b0fd-4805-a72c-e59f33b4b55d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688091733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2688091733
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1924548296
Short name T26
Test name
Test status
Simulation time 115409517 ps
CPU time 1.5 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:15 PM PDT 24
Peak memory 200348 kb
Host smart-70dd5314-0bf2-4745-835c-e0fa3988c4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924548296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1924548296
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3000903270
Short name T513
Test name
Test status
Simulation time 91869808 ps
CPU time 0.79 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:13 PM PDT 24
Peak memory 200336 kb
Host smart-4e460113-20be-4fd5-919c-11180c7992f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000903270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3000903270
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.66944589
Short name T343
Test name
Test status
Simulation time 85283135 ps
CPU time 0.88 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 200172 kb
Host smart-6fc8000e-d4f1-47db-be9b-3beacbaf161a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66944589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.66944589
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.4063678049
Short name T31
Test name
Test status
Simulation time 2357516312 ps
CPU time 9.26 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:22 PM PDT 24
Peak memory 217960 kb
Host smart-f354bb09-da09-459b-a2df-53e2a75132c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063678049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.4063678049
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3449816698
Short name T306
Test name
Test status
Simulation time 243246647 ps
CPU time 1.07 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 217508 kb
Host smart-d8e81940-90b0-498f-b138-5e34500e19d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449816698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3449816698
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1616865593
Short name T353
Test name
Test status
Simulation time 113438398 ps
CPU time 0.79 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:13 PM PDT 24
Peak memory 200176 kb
Host smart-61fe18be-ef59-467e-876e-995ae9a5bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616865593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1616865593
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3633361394
Short name T265
Test name
Test status
Simulation time 982502929 ps
CPU time 4.89 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 200544 kb
Host smart-c99a0376-0e22-420a-a3d4-e8157124b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633361394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3633361394
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1234529956
Short name T256
Test name
Test status
Simulation time 175856175 ps
CPU time 1.27 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 200328 kb
Host smart-b08579db-823a-415a-b046-2cd672737841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234529956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1234529956
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3402232390
Short name T483
Test name
Test status
Simulation time 111522620 ps
CPU time 1.18 seconds
Started Aug 07 06:23:10 PM PDT 24
Finished Aug 07 06:23:12 PM PDT 24
Peak memory 200488 kb
Host smart-8c23998b-3665-45c1-957e-8d76cfd0774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402232390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3402232390
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.2416168779
Short name T283
Test name
Test status
Simulation time 4785735365 ps
CPU time 23.43 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:35 PM PDT 24
Peak memory 208836 kb
Host smart-d9c5551e-1260-499b-9d14-467a7f1e3c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416168779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2416168779
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2070090521
Short name T87
Test name
Test status
Simulation time 338361220 ps
CPU time 2.26 seconds
Started Aug 07 06:23:15 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 200340 kb
Host smart-19521670-8830-4196-888a-2981a7e97f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070090521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2070090521
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3071869207
Short name T488
Test name
Test status
Simulation time 153235638 ps
CPU time 1.37 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 200488 kb
Host smart-23b886f9-4d4a-44d2-a9c5-ee4e105c37a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071869207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3071869207
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4161164536
Short name T158
Test name
Test status
Simulation time 78648847 ps
CPU time 0.83 seconds
Started Aug 07 06:23:18 PM PDT 24
Finished Aug 07 06:23:19 PM PDT 24
Peak memory 200140 kb
Host smart-b015a45b-9c2e-4ac3-ac06-c477d8dc9929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161164536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4161164536
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3413836968
Short name T394
Test name
Test status
Simulation time 1224373416 ps
CPU time 5.61 seconds
Started Aug 07 06:23:38 PM PDT 24
Finished Aug 07 06:23:44 PM PDT 24
Peak memory 221692 kb
Host smart-5c1a7a70-6e14-4792-81d5-ec4eb8c02c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413836968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3413836968
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1042658729
Short name T142
Test name
Test status
Simulation time 244568267 ps
CPU time 1.03 seconds
Started Aug 07 06:23:19 PM PDT 24
Finished Aug 07 06:23:20 PM PDT 24
Peak memory 217552 kb
Host smart-eaf52344-b009-451e-806e-7b8f39b29514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042658729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1042658729
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3608754811
Short name T492
Test name
Test status
Simulation time 195867732 ps
CPU time 0.95 seconds
Started Aug 07 06:23:11 PM PDT 24
Finished Aug 07 06:23:12 PM PDT 24
Peak memory 200016 kb
Host smart-c124779f-0920-4e49-b9c7-22925c33b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608754811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3608754811
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2689353199
Short name T442
Test name
Test status
Simulation time 1067615568 ps
CPU time 5.03 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200612 kb
Host smart-9ea8b854-85ed-42b9-9a9d-dbd8a3c4c0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689353199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2689353199
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3924928942
Short name T288
Test name
Test status
Simulation time 103110737 ps
CPU time 1.04 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:14 PM PDT 24
Peak memory 200356 kb
Host smart-33841d3e-29c0-439a-a694-d6402987ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924928942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3924928942
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1333834601
Short name T29
Test name
Test status
Simulation time 191451680 ps
CPU time 1.34 seconds
Started Aug 07 06:23:12 PM PDT 24
Finished Aug 07 06:23:13 PM PDT 24
Peak memory 200492 kb
Host smart-01d1c148-dace-4d3a-94c9-3d4942c026c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333834601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1333834601
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.268025485
Short name T383
Test name
Test status
Simulation time 8566519867 ps
CPU time 32.36 seconds
Started Aug 07 06:23:17 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 200608 kb
Host smart-71e1c843-5d50-437a-8f1a-2f7d0e95470b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268025485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.268025485
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1422415439
Short name T490
Test name
Test status
Simulation time 374662334 ps
CPU time 2.44 seconds
Started Aug 07 06:23:13 PM PDT 24
Finished Aug 07 06:23:16 PM PDT 24
Peak memory 200248 kb
Host smart-71626419-af16-4838-8a22-3510dccc479a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422415439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1422415439
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.490011308
Short name T1
Test name
Test status
Simulation time 241360805 ps
CPU time 1.4 seconds
Started Aug 07 06:23:15 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 200312 kb
Host smart-db684a0a-db66-4a25-a303-0f67546c5a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490011308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.490011308
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3226236307
Short name T151
Test name
Test status
Simulation time 64405354 ps
CPU time 0.74 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200172 kb
Host smart-6ced6c6a-c76e-4655-ab99-db247bfca35f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226236307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3226236307
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2425954321
Short name T322
Test name
Test status
Simulation time 1231337945 ps
CPU time 5.4 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:36 PM PDT 24
Peak memory 217780 kb
Host smart-7f477278-52ff-495c-8a68-169ab38b8a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425954321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2425954321
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4283052395
Short name T33
Test name
Test status
Simulation time 245000596 ps
CPU time 1.06 seconds
Started Aug 07 06:23:20 PM PDT 24
Finished Aug 07 06:23:21 PM PDT 24
Peak memory 217524 kb
Host smart-cec61d06-0b5f-4314-a2d1-0c877ade56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283052395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4283052395
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2365348216
Short name T315
Test name
Test status
Simulation time 85859691 ps
CPU time 0.77 seconds
Started Aug 07 06:23:17 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200160 kb
Host smart-d90495c9-2d89-4594-8d44-9f81de10d277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365348216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2365348216
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2562194168
Short name T344
Test name
Test status
Simulation time 1573299478 ps
CPU time 6.61 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:23 PM PDT 24
Peak memory 200568 kb
Host smart-bd4742bd-c74a-43ae-8410-41df06b3ff00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562194168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2562194168
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2285414406
Short name T313
Test name
Test status
Simulation time 101911231 ps
CPU time 0.98 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200360 kb
Host smart-046aa284-a691-4bde-9378-8b212aa0f1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285414406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2285414406
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3547521726
Short name T439
Test name
Test status
Simulation time 256042004 ps
CPU time 1.47 seconds
Started Aug 07 06:23:17 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200688 kb
Host smart-1063cad9-5307-4794-8027-e0b26b5bd845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547521726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3547521726
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3935628377
Short name T486
Test name
Test status
Simulation time 3366807399 ps
CPU time 14.52 seconds
Started Aug 07 06:23:17 PM PDT 24
Finished Aug 07 06:23:32 PM PDT 24
Peak memory 208852 kb
Host smart-6a8b4aa0-f4a1-4eae-a120-a7ea5788ba6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935628377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3935628377
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3975027629
Short name T249
Test name
Test status
Simulation time 354619538 ps
CPU time 2.04 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:19 PM PDT 24
Peak memory 200296 kb
Host smart-9d4276ca-32de-4ad6-b2cd-dc9e652f7d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975027629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3975027629
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.937018521
Short name T455
Test name
Test status
Simulation time 135701873 ps
CPU time 1.12 seconds
Started Aug 07 06:23:20 PM PDT 24
Finished Aug 07 06:23:21 PM PDT 24
Peak memory 200376 kb
Host smart-25372ba7-129e-4f6e-bd38-7d2998896a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937018521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.937018521
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.705088019
Short name T143
Test name
Test status
Simulation time 70274839 ps
CPU time 0.78 seconds
Started Aug 07 06:22:45 PM PDT 24
Finished Aug 07 06:22:46 PM PDT 24
Peak memory 200140 kb
Host smart-5f93af34-83eb-42f0-84c1-3bb769f902dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705088019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.705088019
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3186747929
Short name T37
Test name
Test status
Simulation time 1231376825 ps
CPU time 5.33 seconds
Started Aug 07 06:22:44 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 221360 kb
Host smart-8670cb02-605e-4b79-a9c4-92a4527b2714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186747929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3186747929
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3894142170
Short name T350
Test name
Test status
Simulation time 244786630 ps
CPU time 1.07 seconds
Started Aug 07 06:22:45 PM PDT 24
Finished Aug 07 06:22:46 PM PDT 24
Peak memory 217552 kb
Host smart-17dc6b83-2a46-40ea-b62f-f5ccf6c07b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894142170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3894142170
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.808793910
Short name T369
Test name
Test status
Simulation time 191155113 ps
CPU time 0.89 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:43 PM PDT 24
Peak memory 200060 kb
Host smart-4b7a2664-fa5f-47d2-83e4-7afa05aac28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808793910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.808793910
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3270985016
Short name T196
Test name
Test status
Simulation time 1256117513 ps
CPU time 5.51 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 200560 kb
Host smart-88c12dbe-5916-42a0-9757-228cb7a56ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270985016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3270985016
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1396549194
Short name T74
Test name
Test status
Simulation time 16782378350 ps
CPU time 25.32 seconds
Started Aug 07 06:22:45 PM PDT 24
Finished Aug 07 06:23:10 PM PDT 24
Peak memory 218356 kb
Host smart-e86bfca3-c8e3-45c0-9869-b84b009c3750
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396549194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1396549194
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2189115485
Short name T258
Test name
Test status
Simulation time 139189538 ps
CPU time 1.15 seconds
Started Aug 07 06:22:45 PM PDT 24
Finished Aug 07 06:22:46 PM PDT 24
Peak memory 200388 kb
Host smart-cb6b5721-cfbb-4f48-9774-7322e2315642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189115485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2189115485
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3608551003
Short name T341
Test name
Test status
Simulation time 251701411 ps
CPU time 1.51 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:44 PM PDT 24
Peak memory 200488 kb
Host smart-aa510e12-dd06-4513-bf49-c907077be627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608551003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3608551003
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1012441344
Short name T478
Test name
Test status
Simulation time 8406062607 ps
CPU time 30.07 seconds
Started Aug 07 06:22:45 PM PDT 24
Finished Aug 07 06:23:15 PM PDT 24
Peak memory 200644 kb
Host smart-08ac7b32-de00-4d35-a7f6-c384b814d41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012441344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1012441344
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2337850760
Short name T466
Test name
Test status
Simulation time 333775254 ps
CPU time 2.24 seconds
Started Aug 07 06:22:43 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 200352 kb
Host smart-06659445-7480-4b8c-9eb0-f8b09e696629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337850760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2337850760
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1613099409
Short name T493
Test name
Test status
Simulation time 170328374 ps
CPU time 1.15 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:44 PM PDT 24
Peak memory 200248 kb
Host smart-79f49f75-f48d-4fb0-b655-ae7e66cfe023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613099409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1613099409
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2529165688
Short name T375
Test name
Test status
Simulation time 59527722 ps
CPU time 0.74 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 200168 kb
Host smart-d728c52e-2aff-45b1-a3be-296983230b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529165688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2529165688
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2739859827
Short name T527
Test name
Test status
Simulation time 1902247741 ps
CPU time 7.08 seconds
Started Aug 07 06:23:19 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 217768 kb
Host smart-7ff96f1c-a0c1-4385-a10e-64e324264ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739859827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2739859827
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.2289505368
Short name T245
Test name
Test status
Simulation time 244451449 ps
CPU time 1.18 seconds
Started Aug 07 06:23:20 PM PDT 24
Finished Aug 07 06:23:21 PM PDT 24
Peak memory 217532 kb
Host smart-803fac18-f7ac-436e-ad04-5e6173010550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289505368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.2289505368
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3166645114
Short name T456
Test name
Test status
Simulation time 189873170 ps
CPU time 0.94 seconds
Started Aug 07 06:23:18 PM PDT 24
Finished Aug 07 06:23:19 PM PDT 24
Peak memory 200188 kb
Host smart-63c452d9-6775-4860-84fe-7fe6c50dbc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166645114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3166645114
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2123405245
Short name T460
Test name
Test status
Simulation time 1739262666 ps
CPU time 6.98 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:23 PM PDT 24
Peak memory 200460 kb
Host smart-857700bb-8b97-45e7-9705-17f319183277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123405245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2123405245
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.826056534
Short name T153
Test name
Test status
Simulation time 156862143 ps
CPU time 1.16 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200360 kb
Host smart-8d15c001-0d0c-4173-a815-376f555544a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826056534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.826056534
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2274092547
Short name T86
Test name
Test status
Simulation time 250077913 ps
CPU time 1.47 seconds
Started Aug 07 06:23:18 PM PDT 24
Finished Aug 07 06:23:19 PM PDT 24
Peak memory 200540 kb
Host smart-1acf302f-9479-4f43-a7c0-8f88cbe9125f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274092547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2274092547
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.830229697
Short name T194
Test name
Test status
Simulation time 3851223085 ps
CPU time 18.13 seconds
Started Aug 07 06:23:17 PM PDT 24
Finished Aug 07 06:23:35 PM PDT 24
Peak memory 208824 kb
Host smart-dd0a7582-12cb-4818-a69f-075dcc8c90c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830229697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.830229697
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.593513280
Short name T134
Test name
Test status
Simulation time 487252877 ps
CPU time 2.71 seconds
Started Aug 07 06:23:18 PM PDT 24
Finished Aug 07 06:23:21 PM PDT 24
Peak memory 200308 kb
Host smart-28938b1d-b62d-4fa1-9ffb-4cddc5dfeec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593513280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.593513280
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1628948509
Short name T273
Test name
Test status
Simulation time 158737278 ps
CPU time 1.23 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200540 kb
Host smart-3002309f-90f6-4e52-bae0-7c3885ebd7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628948509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1628948509
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.774102596
Short name T316
Test name
Test status
Simulation time 73499541 ps
CPU time 0.78 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200172 kb
Host smart-0a7df47f-00fb-49ee-b87a-792af0e22c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774102596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.774102596
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2043333073
Short name T41
Test name
Test status
Simulation time 1225632263 ps
CPU time 5.75 seconds
Started Aug 07 06:23:20 PM PDT 24
Finished Aug 07 06:23:25 PM PDT 24
Peak memory 217740 kb
Host smart-b741c64b-ebc9-4597-ae1a-158052299428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043333073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2043333073
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4126497762
Short name T357
Test name
Test status
Simulation time 243653723 ps
CPU time 1.07 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 217540 kb
Host smart-79be2ca1-b7ec-4b04-97d2-dcdde7a94b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126497762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4126497762
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1617683210
Short name T521
Test name
Test status
Simulation time 163281636 ps
CPU time 0.83 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 200152 kb
Host smart-f689303a-a04f-4109-b379-41ee912a1e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617683210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1617683210
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1923503537
Short name T497
Test name
Test status
Simulation time 900662484 ps
CPU time 4.58 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:21 PM PDT 24
Peak memory 200536 kb
Host smart-efd380c4-10ae-44ae-83b0-acec3aeaf852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923503537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1923503537
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3119304832
Short name T426
Test name
Test status
Simulation time 108160113 ps
CPU time 0.98 seconds
Started Aug 07 06:23:17 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200276 kb
Host smart-6ad3cce8-b871-4bba-afb5-9b6e38d05a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119304832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3119304832
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3763527717
Short name T475
Test name
Test status
Simulation time 255735601 ps
CPU time 1.54 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200484 kb
Host smart-89bc51fe-971c-43f8-b0be-b1ee4f876271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763527717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3763527717
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1743946436
Short name T443
Test name
Test status
Simulation time 9519114661 ps
CPU time 39.82 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:24:09 PM PDT 24
Peak memory 208836 kb
Host smart-8208fb67-aa7c-4396-8caf-142f9f1a5424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743946436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1743946436
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1551806144
Short name T354
Test name
Test status
Simulation time 261208676 ps
CPU time 1.88 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200280 kb
Host smart-c54b9d05-a100-4245-bcb9-e2966240e24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551806144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1551806144
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2444019286
Short name T11
Test name
Test status
Simulation time 69438402 ps
CPU time 0.74 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200360 kb
Host smart-5eda47d4-c0b7-4c90-8415-e48d84f44add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444019286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2444019286
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2255827340
Short name T428
Test name
Test status
Simulation time 69498681 ps
CPU time 0.78 seconds
Started Aug 07 06:23:24 PM PDT 24
Finished Aug 07 06:23:24 PM PDT 24
Peak memory 200168 kb
Host smart-24473b8f-e1bb-41f8-b79c-66ecb735173b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255827340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2255827340
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3221039854
Short name T508
Test name
Test status
Simulation time 1885044032 ps
CPU time 7.05 seconds
Started Aug 07 06:23:24 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 217752 kb
Host smart-fd93721e-85d7-42e8-851c-66ffffa39e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221039854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3221039854
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1427879649
Short name T307
Test name
Test status
Simulation time 244491173 ps
CPU time 1.27 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:26 PM PDT 24
Peak memory 217528 kb
Host smart-547f1be9-2ee5-4332-bf11-63c37b026c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427879649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1427879649
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1836319641
Short name T448
Test name
Test status
Simulation time 105865917 ps
CPU time 0.8 seconds
Started Aug 07 06:23:17 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200196 kb
Host smart-60d01c21-76de-419b-b311-0331f047026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836319641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1836319641
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.1167292044
Short name T373
Test name
Test status
Simulation time 1347827718 ps
CPU time 5.7 seconds
Started Aug 07 06:23:16 PM PDT 24
Finished Aug 07 06:23:22 PM PDT 24
Peak memory 200540 kb
Host smart-d74f0acf-30ba-4393-be96-598d5ae41fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167292044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1167292044
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.399453355
Short name T197
Test name
Test status
Simulation time 160328948 ps
CPU time 1.2 seconds
Started Aug 07 06:23:24 PM PDT 24
Finished Aug 07 06:23:26 PM PDT 24
Peak memory 200348 kb
Host smart-b6413748-a210-4315-b23a-24db759061ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399453355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.399453355
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2163554360
Short name T91
Test name
Test status
Simulation time 125321434 ps
CPU time 1.18 seconds
Started Aug 07 06:23:17 PM PDT 24
Finished Aug 07 06:23:18 PM PDT 24
Peak memory 200496 kb
Host smart-652f19a7-ecc1-4e86-98b1-fd57f2c91594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163554360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2163554360
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2770047307
Short name T464
Test name
Test status
Simulation time 232084052 ps
CPU time 1.41 seconds
Started Aug 07 06:23:23 PM PDT 24
Finished Aug 07 06:23:24 PM PDT 24
Peak memory 200140 kb
Host smart-32c09cde-9721-4d63-96c0-63708207c353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770047307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2770047307
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2599017348
Short name T211
Test name
Test status
Simulation time 111022023 ps
CPU time 1.48 seconds
Started Aug 07 06:23:23 PM PDT 24
Finished Aug 07 06:23:24 PM PDT 24
Peak memory 200324 kb
Host smart-6a812849-841b-4b3b-b419-252d0d331ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599017348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2599017348
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3160867212
Short name T167
Test name
Test status
Simulation time 87396536 ps
CPU time 0.9 seconds
Started Aug 07 06:23:24 PM PDT 24
Finished Aug 07 06:23:25 PM PDT 24
Peak memory 200368 kb
Host smart-6fc0d57b-6abb-4efb-89d1-808c884f5ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160867212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3160867212
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2655889136
Short name T336
Test name
Test status
Simulation time 69369548 ps
CPU time 0.78 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200172 kb
Host smart-5d93ec91-d8dc-4294-84dd-ffd4ae194218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655889136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2655889136
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1292921562
Short name T434
Test name
Test status
Simulation time 1896673240 ps
CPU time 8.57 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:34 PM PDT 24
Peak memory 217772 kb
Host smart-b3d30440-ed33-420b-86b6-0d8437c78411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292921562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1292921562
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2084632752
Short name T421
Test name
Test status
Simulation time 244325625 ps
CPU time 1.18 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:29 PM PDT 24
Peak memory 217536 kb
Host smart-4228f86b-be68-4645-a9a3-694ef9933eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084632752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2084632752
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3254729308
Short name T23
Test name
Test status
Simulation time 104159064 ps
CPU time 0.78 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200080 kb
Host smart-84a6dfd0-9381-458c-90eb-08dbdb7ddfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254729308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3254729308
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.456938424
Short name T201
Test name
Test status
Simulation time 669499583 ps
CPU time 3.5 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:40 PM PDT 24
Peak memory 200548 kb
Host smart-cac1853f-e5e2-4c95-91c5-a15cdc19cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456938424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.456938424
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.799646678
Short name T271
Test name
Test status
Simulation time 145272955 ps
CPU time 1.15 seconds
Started Aug 07 06:23:24 PM PDT 24
Finished Aug 07 06:23:26 PM PDT 24
Peak memory 200372 kb
Host smart-6ab4a9ee-321f-4d30-9757-26f3a723fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799646678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.799646678
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1082805092
Short name T44
Test name
Test status
Simulation time 204327528 ps
CPU time 1.34 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200548 kb
Host smart-b87cd53c-12be-4ccf-8621-766f076b361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082805092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1082805092
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.575051307
Short name T516
Test name
Test status
Simulation time 6976246710 ps
CPU time 28.2 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:58 PM PDT 24
Peak memory 208860 kb
Host smart-7cc2d920-d0d6-4e1e-9731-0bd62024bf99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575051307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.575051307
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2511194622
Short name T191
Test name
Test status
Simulation time 131665269 ps
CPU time 1.68 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200348 kb
Host smart-ef83feb4-164a-4b18-89f6-1d546166354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511194622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2511194622
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4006461007
Short name T236
Test name
Test status
Simulation time 153703886 ps
CPU time 1.13 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200356 kb
Host smart-bf7f1366-4a88-44b4-9331-3b75235658a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006461007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4006461007
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.201714376
Short name T522
Test name
Test status
Simulation time 76279819 ps
CPU time 0.8 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200124 kb
Host smart-d59e788f-81e2-464e-81fe-a0459a9b8338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201714376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.201714376
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3163076192
Short name T515
Test name
Test status
Simulation time 1887930022 ps
CPU time 7.92 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:33 PM PDT 24
Peak memory 217660 kb
Host smart-c8efe2fe-0f45-4bb4-b0c9-e0ddea357619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163076192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3163076192
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3571762832
Short name T503
Test name
Test status
Simulation time 243989396 ps
CPU time 1.07 seconds
Started Aug 07 06:23:24 PM PDT 24
Finished Aug 07 06:23:26 PM PDT 24
Peak memory 217588 kb
Host smart-f33c62e2-8792-47c7-adad-e7c0d08fc8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571762832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3571762832
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.423031857
Short name T206
Test name
Test status
Simulation time 154152904 ps
CPU time 0.84 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 200124 kb
Host smart-90ed8aae-e543-4224-816d-40edc4cd7575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423031857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.423031857
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1503081807
Short name T410
Test name
Test status
Simulation time 810461750 ps
CPU time 3.96 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200556 kb
Host smart-a9aaaa45-2f1e-4306-8aa8-468476afcc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503081807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1503081807
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2335471512
Short name T282
Test name
Test status
Simulation time 165656025 ps
CPU time 1.14 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:32 PM PDT 24
Peak memory 200364 kb
Host smart-da56c4ec-09f6-428a-a93f-844349736e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335471512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2335471512
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2743243658
Short name T285
Test name
Test status
Simulation time 202910446 ps
CPU time 1.4 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200684 kb
Host smart-d9762841-4bac-4fd5-bd8d-a9a59567663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743243658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2743243658
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2727696619
Short name T264
Test name
Test status
Simulation time 955240860 ps
CPU time 4.43 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:34 PM PDT 24
Peak memory 200576 kb
Host smart-db8695c0-c5e2-448b-b46b-fb5a497dedb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727696619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2727696619
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.31697381
Short name T506
Test name
Test status
Simulation time 331857176 ps
CPU time 2.09 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200500 kb
Host smart-3d356d39-93ff-482b-b97f-5d576db531e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31697381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.31697381
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2141127852
Short name T233
Test name
Test status
Simulation time 164192192 ps
CPU time 1.12 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200328 kb
Host smart-44f75bfd-b789-446a-a4e7-3f390c6a3711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141127852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2141127852
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2409501260
Short name T229
Test name
Test status
Simulation time 66397923 ps
CPU time 0.81 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:25 PM PDT 24
Peak memory 200156 kb
Host smart-f4d10452-fda7-410a-bd68-9c9f77a74ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409501260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2409501260
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.66454714
Short name T417
Test name
Test status
Simulation time 1890346457 ps
CPU time 7.34 seconds
Started Aug 07 06:23:24 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 217276 kb
Host smart-85ddc31f-006a-44e4-923a-37f22409c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66454714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.66454714
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2889527565
Short name T180
Test name
Test status
Simulation time 244196206 ps
CPU time 1.2 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:26 PM PDT 24
Peak memory 217596 kb
Host smart-8ec568be-7458-4175-8e0f-c015f868b878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889527565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2889527565
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2765268655
Short name T429
Test name
Test status
Simulation time 156749022 ps
CPU time 0.87 seconds
Started Aug 07 06:23:27 PM PDT 24
Finished Aug 07 06:23:28 PM PDT 24
Peak memory 200188 kb
Host smart-a2e84826-7fcc-41f0-bd92-1157a857028d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765268655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2765268655
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.352276248
Short name T130
Test name
Test status
Simulation time 1353453431 ps
CPU time 5.58 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200528 kb
Host smart-badbb898-6740-410b-8fbd-19a2a70416f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352276248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.352276248
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3828309649
Short name T161
Test name
Test status
Simulation time 167534626 ps
CPU time 1.22 seconds
Started Aug 07 06:23:27 PM PDT 24
Finished Aug 07 06:23:28 PM PDT 24
Peak memory 200356 kb
Host smart-e3d78cad-cb41-45bf-a3bb-6e7bc8a2aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828309649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3828309649
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3272971625
Short name T278
Test name
Test status
Simulation time 194742098 ps
CPU time 1.44 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200524 kb
Host smart-333c3e34-354a-4032-825c-9873e881cf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272971625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3272971625
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1737360005
Short name T261
Test name
Test status
Simulation time 1356757566 ps
CPU time 5.83 seconds
Started Aug 07 06:23:23 PM PDT 24
Finished Aug 07 06:23:29 PM PDT 24
Peak memory 200608 kb
Host smart-e2dd80ce-270d-4ce3-99ad-1f34ad262cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737360005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1737360005
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3029030508
Short name T310
Test name
Test status
Simulation time 270655929 ps
CPU time 1.78 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200340 kb
Host smart-77079a0e-05d0-462a-b5d7-0b25092b0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029030508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3029030508
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1018013273
Short name T491
Test name
Test status
Simulation time 97656616 ps
CPU time 0.91 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:26 PM PDT 24
Peak memory 200328 kb
Host smart-f2bd8ac6-6de1-4c72-8c3b-d0ebfc73cfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018013273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1018013273
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1462515834
Short name T225
Test name
Test status
Simulation time 66361612 ps
CPU time 0.81 seconds
Started Aug 07 06:23:31 PM PDT 24
Finished Aug 07 06:23:32 PM PDT 24
Peak memory 200132 kb
Host smart-2737b991-96ac-4c17-ad1b-2d544bd849f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462515834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1462515834
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2208640403
Short name T45
Test name
Test status
Simulation time 1907130581 ps
CPU time 7.25 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:35 PM PDT 24
Peak memory 217484 kb
Host smart-b25d21ec-4f63-4d45-8820-8f065b6f888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208640403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2208640403
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.845470185
Short name T425
Test name
Test status
Simulation time 244442669 ps
CPU time 1.12 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:29 PM PDT 24
Peak memory 217512 kb
Host smart-504cd2f0-f01f-4646-9e2f-6ee450437430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845470185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.845470185
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.348974374
Short name T542
Test name
Test status
Simulation time 169574459 ps
CPU time 0.93 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200156 kb
Host smart-f324a340-50cb-4e26-aa6d-ad1ca0d4a9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348974374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.348974374
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.4163633187
Short name T241
Test name
Test status
Simulation time 907750252 ps
CPU time 4.66 seconds
Started Aug 07 06:23:24 PM PDT 24
Finished Aug 07 06:23:29 PM PDT 24
Peak memory 200608 kb
Host smart-8488ef8e-28e0-4459-bd07-204f94212b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163633187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4163633187
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1317268558
Short name T148
Test name
Test status
Simulation time 178485578 ps
CPU time 1.17 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200352 kb
Host smart-020877fa-d262-4d11-adf1-b8ef18827123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317268558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1317268558
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1674891061
Short name T230
Test name
Test status
Simulation time 245250418 ps
CPU time 1.44 seconds
Started Aug 07 06:23:26 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200500 kb
Host smart-9e511d3a-4317-40d0-900d-73b3b4266626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674891061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1674891061
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3465319434
Short name T199
Test name
Test status
Simulation time 3397177334 ps
CPU time 11.99 seconds
Started Aug 07 06:23:31 PM PDT 24
Finished Aug 07 06:23:43 PM PDT 24
Peak memory 208832 kb
Host smart-9cf393a6-40a5-4a0d-9b33-1da450ab0c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465319434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3465319434
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.863325123
Short name T255
Test name
Test status
Simulation time 127661204 ps
CPU time 1.61 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 208480 kb
Host smart-7675a80d-e1b2-4f63-b5df-46881de94e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863325123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.863325123
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.4183793169
Short name T327
Test name
Test status
Simulation time 220833620 ps
CPU time 1.58 seconds
Started Aug 07 06:23:25 PM PDT 24
Finished Aug 07 06:23:27 PM PDT 24
Peak memory 200376 kb
Host smart-14304307-7acd-4a3f-b553-42d503548f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183793169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.4183793169
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3259870626
Short name T401
Test name
Test status
Simulation time 61412810 ps
CPU time 0.76 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:29 PM PDT 24
Peak memory 200164 kb
Host smart-62ca3439-5367-492b-9ba6-1ec59804b9d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259870626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3259870626
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4205717530
Short name T162
Test name
Test status
Simulation time 244499319 ps
CPU time 1.12 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 217568 kb
Host smart-4f60dffd-740a-4892-a940-c1c61f237489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205717530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4205717530
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2593678487
Short name T21
Test name
Test status
Simulation time 124246105 ps
CPU time 0.82 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200196 kb
Host smart-3cf77dd3-6735-4c80-8af6-6e50a2fa2927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593678487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2593678487
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.726872593
Short name T352
Test name
Test status
Simulation time 1922961726 ps
CPU time 7.46 seconds
Started Aug 07 06:23:31 PM PDT 24
Finished Aug 07 06:23:39 PM PDT 24
Peak memory 200556 kb
Host smart-66c467a1-91ba-4408-bb27-14619547d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726872593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.726872593
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1891886617
Short name T141
Test name
Test status
Simulation time 105993410 ps
CPU time 1.02 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200364 kb
Host smart-f1c480e4-3e40-403e-947f-9cb07cd9cb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891886617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1891886617
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.63568145
Short name T305
Test name
Test status
Simulation time 192909406 ps
CPU time 1.37 seconds
Started Aug 07 06:23:31 PM PDT 24
Finished Aug 07 06:23:32 PM PDT 24
Peak memory 200516 kb
Host smart-cd624437-beca-4555-8d46-12ddc786f66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63568145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.63568145
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3957587324
Short name T243
Test name
Test status
Simulation time 4702530502 ps
CPU time 19.95 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 208832 kb
Host smart-ef049a8b-1104-408c-8d1f-61fb3ac18b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957587324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3957587324
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2092799750
Short name T215
Test name
Test status
Simulation time 305038810 ps
CPU time 2.04 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200284 kb
Host smart-3ab235b6-befa-4f24-b4bb-a934de7fa450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092799750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2092799750
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2804596224
Short name T42
Test name
Test status
Simulation time 167031925 ps
CPU time 1.27 seconds
Started Aug 07 06:23:31 PM PDT 24
Finished Aug 07 06:23:33 PM PDT 24
Peak memory 200364 kb
Host smart-11300fd8-33ed-4953-8c42-409bd12aa8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804596224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2804596224
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2373323970
Short name T40
Test name
Test status
Simulation time 1899537225 ps
CPU time 7.17 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:36 PM PDT 24
Peak memory 221756 kb
Host smart-bc097db8-f8e5-4224-9f52-3637071b12ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373323970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2373323970
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2698906724
Short name T540
Test name
Test status
Simulation time 244161069 ps
CPU time 1.08 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 217508 kb
Host smart-554435d2-3af8-4212-a746-e99d700746c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698906724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2698906724
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2242516478
Short name T17
Test name
Test status
Simulation time 173537571 ps
CPU time 0.89 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200112 kb
Host smart-297e9679-76e8-4b62-9bd4-79e6ec9885fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242516478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2242516478
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1471284624
Short name T101
Test name
Test status
Simulation time 2180178659 ps
CPU time 7.49 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 200620 kb
Host smart-af39674e-1e91-4ee9-8416-c7e0c1279ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471284624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1471284624
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.483783952
Short name T298
Test name
Test status
Simulation time 189617903 ps
CPU time 1.23 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200356 kb
Host smart-1883ca49-8a6c-49e3-8c97-1b1fb326a2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483783952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.483783952
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3583203867
Short name T79
Test name
Test status
Simulation time 186029742 ps
CPU time 1.29 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200500 kb
Host smart-fd749282-cbf8-4878-b58e-f92d86e107f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583203867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3583203867
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.584118418
Short name T287
Test name
Test status
Simulation time 14629688340 ps
CPU time 52.34 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 208804 kb
Host smart-7cf292fb-0ddd-48cb-92af-2e131216a4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584118418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.584118418
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3590121231
Short name T330
Test name
Test status
Simulation time 452913147 ps
CPU time 2.82 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200296 kb
Host smart-a3e59914-e7a7-47a9-bcca-d999f8934cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590121231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3590121231
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.4168679365
Short name T470
Test name
Test status
Simulation time 111111602 ps
CPU time 1.01 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200368 kb
Host smart-c2c564dd-23fb-476f-87b4-6593362248e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168679365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.4168679365
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1518240036
Short name T140
Test name
Test status
Simulation time 76445048 ps
CPU time 0.76 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:29 PM PDT 24
Peak memory 200172 kb
Host smart-bf4359db-3ab7-475b-9ec5-d84f75e16258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518240036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1518240036
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1212299951
Short name T35
Test name
Test status
Simulation time 2161722432 ps
CPU time 8.13 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 221804 kb
Host smart-4ac32ca5-87bf-4749-ae39-af39a289b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212299951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1212299951
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3000572317
Short name T392
Test name
Test status
Simulation time 244577318 ps
CPU time 1.13 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 217592 kb
Host smart-e291bfdf-31f7-4891-9539-20b0679d2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000572317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3000572317
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2677380655
Short name T192
Test name
Test status
Simulation time 161276382 ps
CPU time 0.84 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:31 PM PDT 24
Peak memory 200188 kb
Host smart-176c086d-1263-403b-9be0-bf189ac1955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677380655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2677380655
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3338780426
Short name T100
Test name
Test status
Simulation time 913070406 ps
CPU time 4.01 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:40 PM PDT 24
Peak memory 200528 kb
Host smart-51b506ab-4bb1-4b79-b5f0-4e31793aecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338780426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3338780426
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3803778611
Short name T324
Test name
Test status
Simulation time 171411306 ps
CPU time 1.27 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200368 kb
Host smart-ed931d68-6673-49fe-8f50-d6cc736c0725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803778611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3803778611
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3791774241
Short name T217
Test name
Test status
Simulation time 236820479 ps
CPU time 1.46 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:29 PM PDT 24
Peak memory 200476 kb
Host smart-1b634ef0-e2d9-46af-89ac-70916c3812f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791774241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3791774241
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2183094528
Short name T237
Test name
Test status
Simulation time 1749248210 ps
CPU time 6.24 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:43 PM PDT 24
Peak memory 200544 kb
Host smart-314fbee9-66a2-40cb-8203-ae22cd2d555c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183094528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2183094528
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2514626109
Short name T65
Test name
Test status
Simulation time 467533786 ps
CPU time 2.34 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:32 PM PDT 24
Peak memory 200228 kb
Host smart-89ff4e92-7d6a-43b9-adca-4589a9ad45ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514626109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2514626109
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2688239304
Short name T248
Test name
Test status
Simulation time 169939173 ps
CPU time 1.19 seconds
Started Aug 07 06:23:31 PM PDT 24
Finished Aug 07 06:23:33 PM PDT 24
Peak memory 200316 kb
Host smart-f4327523-0012-4cee-8898-4cdeee6400e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688239304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2688239304
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.815226955
Short name T176
Test name
Test status
Simulation time 76779892 ps
CPU time 0.81 seconds
Started Aug 07 06:22:45 PM PDT 24
Finished Aug 07 06:22:46 PM PDT 24
Peak memory 200208 kb
Host smart-fa4e90a7-d05e-4677-b6bd-a9f3c496b453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815226955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.815226955
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2905809209
Short name T59
Test name
Test status
Simulation time 1230283379 ps
CPU time 5.64 seconds
Started Aug 07 06:22:44 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 217420 kb
Host smart-f0c26924-3ecf-406c-9387-3130c6f8d144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905809209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2905809209
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3536054744
Short name T382
Test name
Test status
Simulation time 248957338 ps
CPU time 1.06 seconds
Started Aug 07 06:22:45 PM PDT 24
Finished Aug 07 06:22:46 PM PDT 24
Peak memory 217492 kb
Host smart-ff59a775-dbfd-476c-9a48-ce4e3db8acfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536054744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3536054744
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2261761542
Short name T389
Test name
Test status
Simulation time 161859275 ps
CPU time 0.84 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 200132 kb
Host smart-49be3d48-c204-4977-a5bf-435b63887986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261761542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2261761542
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.299616792
Short name T220
Test name
Test status
Simulation time 2207048036 ps
CPU time 8.09 seconds
Started Aug 07 06:22:44 PM PDT 24
Finished Aug 07 06:22:52 PM PDT 24
Peak memory 200544 kb
Host smart-df7d9baa-fd47-4c3e-ae1c-fd4d9fe3a586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299616792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.299616792
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.380829466
Short name T77
Test name
Test status
Simulation time 16502238437 ps
CPU time 29.48 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:23:17 PM PDT 24
Peak memory 217272 kb
Host smart-36e820f2-b3e0-4f26-8c5f-36b10b0edd2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380829466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.380829466
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1494395313
Short name T81
Test name
Test status
Simulation time 107944264 ps
CPU time 1.06 seconds
Started Aug 07 06:22:43 PM PDT 24
Finished Aug 07 06:22:44 PM PDT 24
Peak memory 200388 kb
Host smart-9c2260ac-604d-4a25-9cac-981c21141ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494395313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1494395313
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1697207245
Short name T405
Test name
Test status
Simulation time 192784133 ps
CPU time 1.31 seconds
Started Aug 07 06:22:45 PM PDT 24
Finished Aug 07 06:22:46 PM PDT 24
Peak memory 200516 kb
Host smart-abe4da7c-59e6-48c5-bb0b-34eaf712aa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697207245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1697207245
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3688217046
Short name T361
Test name
Test status
Simulation time 1771592292 ps
CPU time 6.32 seconds
Started Aug 07 06:22:41 PM PDT 24
Finished Aug 07 06:22:47 PM PDT 24
Peak memory 200560 kb
Host smart-a6fd5d92-231d-4ffd-9c55-b515943660e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688217046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3688217046
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3576035706
Short name T363
Test name
Test status
Simulation time 500418901 ps
CPU time 2.82 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 200272 kb
Host smart-f2a764b9-4559-46f1-8fbd-7d79c3778d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576035706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3576035706
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3298829570
Short name T427
Test name
Test status
Simulation time 90480157 ps
CPU time 0.85 seconds
Started Aug 07 06:22:44 PM PDT 24
Finished Aug 07 06:22:45 PM PDT 24
Peak memory 200380 kb
Host smart-a38786e7-a7e0-41fb-a790-fddeb45e6a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298829570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3298829570
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.627866068
Short name T284
Test name
Test status
Simulation time 77650640 ps
CPU time 0.81 seconds
Started Aug 07 06:23:34 PM PDT 24
Finished Aug 07 06:23:35 PM PDT 24
Peak memory 200132 kb
Host smart-e1097ddc-ecf4-4289-9988-fbc30672b8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627866068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.627866068
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1371361585
Short name T50
Test name
Test status
Simulation time 1226840023 ps
CPU time 5.35 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:41 PM PDT 24
Peak memory 221680 kb
Host smart-b10fb144-d5f6-4496-abe6-8d52271f06a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371361585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1371361585
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.219501405
Short name T345
Test name
Test status
Simulation time 244284104 ps
CPU time 1.06 seconds
Started Aug 07 06:23:35 PM PDT 24
Finished Aug 07 06:23:36 PM PDT 24
Peak memory 217536 kb
Host smart-a7f63e93-af6f-4fa8-905e-3d5bbb46293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219501405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.219501405
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3718900344
Short name T452
Test name
Test status
Simulation time 171403482 ps
CPU time 0.84 seconds
Started Aug 07 06:23:29 PM PDT 24
Finished Aug 07 06:23:30 PM PDT 24
Peak memory 200184 kb
Host smart-e9255d61-fac2-450d-b315-f42d13431332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718900344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3718900344
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.712893170
Short name T338
Test name
Test status
Simulation time 766540167 ps
CPU time 4.02 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:34 PM PDT 24
Peak memory 200556 kb
Host smart-07e2b893-97a4-4df5-9a56-21aaa6194c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712893170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.712893170
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2604062603
Short name T155
Test name
Test status
Simulation time 96499785 ps
CPU time 0.95 seconds
Started Aug 07 06:23:28 PM PDT 24
Finished Aug 07 06:23:29 PM PDT 24
Peak memory 200308 kb
Host smart-cbdd38ec-8e09-4f3f-b900-95f8617d5e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604062603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2604062603
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3856668095
Short name T254
Test name
Test status
Simulation time 192782887 ps
CPU time 1.36 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 200460 kb
Host smart-16f5281d-d9a6-4a3d-806d-e509714fc6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856668095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3856668095
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1631494225
Short name T539
Test name
Test status
Simulation time 7025343392 ps
CPU time 30.63 seconds
Started Aug 07 06:23:37 PM PDT 24
Finished Aug 07 06:24:07 PM PDT 24
Peak memory 208848 kb
Host smart-f979510e-14fd-4565-b166-78202384c719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631494225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1631494225
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.374331242
Short name T204
Test name
Test status
Simulation time 134480834 ps
CPU time 1.75 seconds
Started Aug 07 06:23:30 PM PDT 24
Finished Aug 07 06:23:32 PM PDT 24
Peak memory 200300 kb
Host smart-a069600c-851b-409b-95d5-5ae365ecc580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374331242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.374331242
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3930706236
Short name T374
Test name
Test status
Simulation time 293206706 ps
CPU time 1.83 seconds
Started Aug 07 06:23:31 PM PDT 24
Finished Aug 07 06:23:33 PM PDT 24
Peak memory 200528 kb
Host smart-1047a20a-c8bc-4107-9ba7-61ec47e34bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930706236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3930706236
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2581772576
Short name T328
Test name
Test status
Simulation time 67400964 ps
CPU time 0.74 seconds
Started Aug 07 06:23:43 PM PDT 24
Finished Aug 07 06:23:43 PM PDT 24
Peak memory 200164 kb
Host smart-0b17fed0-fc78-4c3d-ab57-050840fc1e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581772576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2581772576
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1107289414
Short name T47
Test name
Test status
Simulation time 1890722045 ps
CPU time 7.59 seconds
Started Aug 07 06:23:35 PM PDT 24
Finished Aug 07 06:23:42 PM PDT 24
Peak memory 217764 kb
Host smart-438db091-8fc3-444d-8561-6a4de4aeae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107289414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1107289414
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.734394313
Short name T412
Test name
Test status
Simulation time 244154213 ps
CPU time 1 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 217528 kb
Host smart-7b143eaa-96a4-40a0-b8d1-be2238ad4bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734394313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.734394313
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1861863142
Short name T19
Test name
Test status
Simulation time 114155125 ps
CPU time 0.86 seconds
Started Aug 07 06:23:37 PM PDT 24
Finished Aug 07 06:23:38 PM PDT 24
Peak memory 200148 kb
Host smart-21721bb2-faa9-4a24-ae0a-fdbd17a01bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861863142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1861863142
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3883394235
Short name T437
Test name
Test status
Simulation time 942905792 ps
CPU time 4.31 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:41 PM PDT 24
Peak memory 200556 kb
Host smart-b0470c98-322d-46ed-9e24-ef336b1c87fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883394235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3883394235
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3759437931
Short name T295
Test name
Test status
Simulation time 158708600 ps
CPU time 1.16 seconds
Started Aug 07 06:23:37 PM PDT 24
Finished Aug 07 06:23:38 PM PDT 24
Peak memory 200332 kb
Host smart-9085c9f5-923f-4e9e-bef2-443027206e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759437931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3759437931
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.844996675
Short name T252
Test name
Test status
Simulation time 195998472 ps
CPU time 1.5 seconds
Started Aug 07 06:23:37 PM PDT 24
Finished Aug 07 06:23:38 PM PDT 24
Peak memory 200500 kb
Host smart-988816d6-6a2a-4067-9c5a-5ab20a3b21a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844996675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.844996675
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2395610064
Short name T218
Test name
Test status
Simulation time 8997052015 ps
CPU time 31.08 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:24:12 PM PDT 24
Peak memory 200616 kb
Host smart-28146577-d609-48c8-884c-6ab23bb09f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395610064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2395610064
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.152245953
Short name T200
Test name
Test status
Simulation time 121442897 ps
CPU time 1.52 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:42 PM PDT 24
Peak memory 199700 kb
Host smart-9df2d6e6-71e1-4a46-8336-bb1347acebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152245953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.152245953
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1640165700
Short name T234
Test name
Test status
Simulation time 228155215 ps
CPU time 1.42 seconds
Started Aug 07 06:23:37 PM PDT 24
Finished Aug 07 06:23:38 PM PDT 24
Peak memory 200384 kb
Host smart-c42cd0e9-c4cc-4ed3-a098-f203a86a6bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640165700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1640165700
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2681757206
Short name T523
Test name
Test status
Simulation time 68618905 ps
CPU time 0.78 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:41 PM PDT 24
Peak memory 199536 kb
Host smart-eba5ce1d-21bc-48dd-893a-8fc73560b193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681757206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2681757206
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2381229655
Short name T530
Test name
Test status
Simulation time 2365295259 ps
CPU time 8.05 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 217696 kb
Host smart-71be81d4-6025-445b-b0ad-62097bf87fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381229655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2381229655
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2911463555
Short name T276
Test name
Test status
Simulation time 243956878 ps
CPU time 1.09 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 217520 kb
Host smart-f5acf1b3-604a-4ce4-bedb-20c6b8e7cf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911463555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2911463555
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4195831855
Short name T16
Test name
Test status
Simulation time 214620802 ps
CPU time 0.92 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:23:43 PM PDT 24
Peak memory 200152 kb
Host smart-10efb013-8683-4c4d-9a3d-207daee229af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195831855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4195831855
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.3013844863
Short name T266
Test name
Test status
Simulation time 773323848 ps
CPU time 4.38 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:44 PM PDT 24
Peak memory 200556 kb
Host smart-10a44c54-bac4-4166-964d-c972f9375d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013844863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3013844863
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3516854331
Short name T541
Test name
Test status
Simulation time 96774237 ps
CPU time 0.95 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:41 PM PDT 24
Peak memory 200380 kb
Host smart-9f363bd6-768b-4303-8465-d7bd499b0e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516854331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3516854331
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.271052207
Short name T391
Test name
Test status
Simulation time 188151015 ps
CPU time 1.35 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:38 PM PDT 24
Peak memory 200516 kb
Host smart-fdd0c4fe-4f6a-4c8e-8c45-d46540be35a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271052207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.271052207
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1295008845
Short name T231
Test name
Test status
Simulation time 163082234 ps
CPU time 1.18 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:23:42 PM PDT 24
Peak memory 200392 kb
Host smart-b192d19f-95d4-4b0b-9189-d56ebc9d93de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295008845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1295008845
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2419876153
Short name T525
Test name
Test status
Simulation time 111369899 ps
CPU time 1.43 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:42 PM PDT 24
Peak memory 200336 kb
Host smart-e7488c92-3c17-40bf-9cb3-fcbbfd07cb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419876153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2419876153
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2167704793
Short name T520
Test name
Test status
Simulation time 69038896 ps
CPU time 0.82 seconds
Started Aug 07 06:23:42 PM PDT 24
Finished Aug 07 06:23:43 PM PDT 24
Peak memory 200328 kb
Host smart-0babd8c2-bd70-44b7-9ccf-5403406e67d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167704793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2167704793
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1269633255
Short name T157
Test name
Test status
Simulation time 60731322 ps
CPU time 0.71 seconds
Started Aug 07 06:23:38 PM PDT 24
Finished Aug 07 06:23:39 PM PDT 24
Peak memory 200172 kb
Host smart-3d15ee7e-ca31-40d0-ba39-7cd1fd4278f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269633255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1269633255
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2268399771
Short name T501
Test name
Test status
Simulation time 2368180409 ps
CPU time 8.74 seconds
Started Aug 07 06:23:45 PM PDT 24
Finished Aug 07 06:23:54 PM PDT 24
Peak memory 221656 kb
Host smart-cecc6d8b-a2ef-43b9-a60a-24ed636a7892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268399771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2268399771
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1216996636
Short name T164
Test name
Test status
Simulation time 243414253 ps
CPU time 1.09 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:23:42 PM PDT 24
Peak memory 217532 kb
Host smart-03672469-299f-46b0-bcdb-93500e2ee133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216996636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1216996636
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1699546041
Short name T259
Test name
Test status
Simulation time 218745837 ps
CPU time 0.92 seconds
Started Aug 07 06:23:36 PM PDT 24
Finished Aug 07 06:23:37 PM PDT 24
Peak memory 200180 kb
Host smart-a7e95f7a-8ea6-4c26-8c43-75d607c18f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699546041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1699546041
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3805071681
Short name T104
Test name
Test status
Simulation time 1801715603 ps
CPU time 6.75 seconds
Started Aug 07 06:23:39 PM PDT 24
Finished Aug 07 06:23:46 PM PDT 24
Peak memory 200592 kb
Host smart-43d78399-05d2-4468-bc13-d8c441c0d66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805071681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3805071681
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1722463719
Short name T505
Test name
Test status
Simulation time 108083086 ps
CPU time 1.1 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:41 PM PDT 24
Peak memory 200384 kb
Host smart-aabbe0c5-f27e-4355-8a8c-248eeefd2bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722463719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1722463719
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3464247444
Short name T387
Test name
Test status
Simulation time 201373296 ps
CPU time 1.38 seconds
Started Aug 07 06:23:42 PM PDT 24
Finished Aug 07 06:23:44 PM PDT 24
Peak memory 200460 kb
Host smart-de899eef-7b16-4d92-8498-4fabaf3e6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464247444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3464247444
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1090747776
Short name T267
Test name
Test status
Simulation time 6685965891 ps
CPU time 24.44 seconds
Started Aug 07 06:23:44 PM PDT 24
Finished Aug 07 06:24:09 PM PDT 24
Peak memory 200596 kb
Host smart-eac2db97-87d8-4328-89b9-157cecc7cad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090747776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1090747776
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3133601163
Short name T459
Test name
Test status
Simulation time 253578049 ps
CPU time 1.68 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200212 kb
Host smart-9f376c8d-cb41-4930-ba19-12ec37db01c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133601163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3133601163
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2398369399
Short name T379
Test name
Test status
Simulation time 216572842 ps
CPU time 1.38 seconds
Started Aug 07 06:23:38 PM PDT 24
Finished Aug 07 06:23:39 PM PDT 24
Peak memory 200328 kb
Host smart-d71f4d59-7c31-4587-817a-bb42d9bde5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398369399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2398369399
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2400626797
Short name T404
Test name
Test status
Simulation time 75066189 ps
CPU time 0.83 seconds
Started Aug 07 06:23:47 PM PDT 24
Finished Aug 07 06:23:48 PM PDT 24
Peak memory 200216 kb
Host smart-f910b6be-3dc2-4db3-bf03-46533a1015a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400626797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2400626797
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.222099812
Short name T4
Test name
Test status
Simulation time 1216832896 ps
CPU time 5.37 seconds
Started Aug 07 06:23:43 PM PDT 24
Finished Aug 07 06:23:48 PM PDT 24
Peak memory 217508 kb
Host smart-5a4d0a58-2bd7-4fdc-9861-f0627719d01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222099812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.222099812
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3227426458
Short name T3
Test name
Test status
Simulation time 244082498 ps
CPU time 1.1 seconds
Started Aug 07 06:23:45 PM PDT 24
Finished Aug 07 06:23:46 PM PDT 24
Peak memory 217492 kb
Host smart-b1a67e36-2287-4ab3-98ae-642454ca2e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227426458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3227426458
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.698117685
Short name T323
Test name
Test status
Simulation time 114605463 ps
CPU time 0.79 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:23:42 PM PDT 24
Peak memory 200156 kb
Host smart-f66da22d-7959-4483-926a-9c98da5b0287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698117685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.698117685
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.840003309
Short name T510
Test name
Test status
Simulation time 898872498 ps
CPU time 4.6 seconds
Started Aug 07 06:23:46 PM PDT 24
Finished Aug 07 06:23:51 PM PDT 24
Peak memory 200604 kb
Host smart-cb2c4401-ac3b-4596-9e96-9335e1979b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840003309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.840003309
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1076320189
Short name T80
Test name
Test status
Simulation time 176862971 ps
CPU time 1.24 seconds
Started Aug 07 06:23:57 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 200308 kb
Host smart-22591932-d092-4367-8be2-3f98ac9e319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076320189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1076320189
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2395966535
Short name T331
Test name
Test status
Simulation time 248072592 ps
CPU time 1.52 seconds
Started Aug 07 06:23:47 PM PDT 24
Finished Aug 07 06:23:48 PM PDT 24
Peak memory 200492 kb
Host smart-9dbd958e-4220-4abd-824a-614ac5df6fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395966535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2395966535
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1470612800
Short name T58
Test name
Test status
Simulation time 324617457 ps
CPU time 1.85 seconds
Started Aug 07 06:23:45 PM PDT 24
Finished Aug 07 06:23:47 PM PDT 24
Peak memory 200532 kb
Host smart-b8e5018c-4b94-4f28-84c5-8e41d662b70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470612800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1470612800
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1002121334
Short name T402
Test name
Test status
Simulation time 147373868 ps
CPU time 1.81 seconds
Started Aug 07 06:23:49 PM PDT 24
Finished Aug 07 06:23:51 PM PDT 24
Peak memory 200296 kb
Host smart-645aa9dd-bd4e-4d3a-915a-ee96c32a28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002121334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1002121334
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1715325722
Short name T399
Test name
Test status
Simulation time 107955828 ps
CPU time 1.06 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:42 PM PDT 24
Peak memory 200396 kb
Host smart-fc847c8c-ca35-4d00-b319-168aa59a451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715325722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1715325722
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3450318715
Short name T6
Test name
Test status
Simulation time 75319336 ps
CPU time 0.82 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:23:59 PM PDT 24
Peak memory 200084 kb
Host smart-2de79111-11bf-48cb-a8e8-3489dbc323bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450318715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3450318715
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2970042595
Short name T485
Test name
Test status
Simulation time 1887997380 ps
CPU time 6.77 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:23:48 PM PDT 24
Peak memory 221724 kb
Host smart-c79fd3ef-e6bc-45aa-ba4e-f7187b8505db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970042595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2970042595
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.677627609
Short name T496
Test name
Test status
Simulation time 244125460 ps
CPU time 1.15 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:53 PM PDT 24
Peak memory 217544 kb
Host smart-cc2c58be-2ea5-4918-9bfa-5027dd0e0bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677627609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.677627609
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3572580102
Short name T332
Test name
Test status
Simulation time 129772824 ps
CPU time 0.83 seconds
Started Aug 07 06:23:45 PM PDT 24
Finished Aug 07 06:23:46 PM PDT 24
Peak memory 200176 kb
Host smart-ad96b764-fe74-4036-a5b1-b5025008f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572580102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3572580102
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2486776734
Short name T250
Test name
Test status
Simulation time 1204197485 ps
CPU time 4.87 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:23:46 PM PDT 24
Peak memory 200560 kb
Host smart-a3fa3573-db8d-4fed-9764-0e240acea7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486776734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2486776734
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.127774898
Short name T239
Test name
Test status
Simulation time 151706286 ps
CPU time 1.2 seconds
Started Aug 07 06:23:49 PM PDT 24
Finished Aug 07 06:23:51 PM PDT 24
Peak memory 200356 kb
Host smart-f10440dd-b531-4bf8-8554-04ce0fc20608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127774898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.127774898
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1177703883
Short name T414
Test name
Test status
Simulation time 194321984 ps
CPU time 1.47 seconds
Started Aug 07 06:23:43 PM PDT 24
Finished Aug 07 06:23:45 PM PDT 24
Peak memory 200520 kb
Host smart-e3d9c390-3526-4c76-9339-9d3fb18821e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177703883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1177703883
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1243195063
Short name T105
Test name
Test status
Simulation time 11148663569 ps
CPU time 37.43 seconds
Started Aug 07 06:23:42 PM PDT 24
Finished Aug 07 06:24:20 PM PDT 24
Peak memory 200656 kb
Host smart-cbadfd13-f5b2-46a6-b44e-09110a581ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243195063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1243195063
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1258002592
Short name T184
Test name
Test status
Simulation time 418984874 ps
CPU time 2.53 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:53 PM PDT 24
Peak memory 208500 kb
Host smart-f0e21ce0-d76b-413a-a0a6-0ae1cf96c9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258002592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1258002592
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3352261432
Short name T311
Test name
Test status
Simulation time 175197009 ps
CPU time 1.24 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:41 PM PDT 24
Peak memory 200524 kb
Host smart-db86ebb0-5c21-48db-bf04-ba1c0cf47333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352261432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3352261432
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3173506098
Short name T299
Test name
Test status
Simulation time 76040845 ps
CPU time 0.81 seconds
Started Aug 07 06:23:54 PM PDT 24
Finished Aug 07 06:23:55 PM PDT 24
Peak memory 200088 kb
Host smart-8072c464-1632-4df1-aaf8-da4ac876d5aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173506098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3173506098
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2874843125
Short name T367
Test name
Test status
Simulation time 1225034993 ps
CPU time 5.87 seconds
Started Aug 07 06:23:46 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 229876 kb
Host smart-4c96a0a7-b574-4ef3-aa54-7f35585a956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874843125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2874843125
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1769388217
Short name T360
Test name
Test status
Simulation time 243450877 ps
CPU time 1.14 seconds
Started Aug 07 06:23:43 PM PDT 24
Finished Aug 07 06:23:44 PM PDT 24
Peak memory 217536 kb
Host smart-7d1e8b02-0857-496c-93d3-b543bfbeb5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769388217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1769388217
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.1048779539
Short name T396
Test name
Test status
Simulation time 211666967 ps
CPU time 0.93 seconds
Started Aug 07 06:23:43 PM PDT 24
Finished Aug 07 06:23:44 PM PDT 24
Peak memory 200168 kb
Host smart-6f5d3828-08d2-46d7-bdfd-0c2456d112d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048779539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1048779539
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1759924605
Short name T325
Test name
Test status
Simulation time 2301596084 ps
CPU time 9.19 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 200588 kb
Host smart-880ba670-e52c-45ee-9ac2-e7553a6f6882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759924605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1759924605
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2066307739
Short name T203
Test name
Test status
Simulation time 184565438 ps
CPU time 1.18 seconds
Started Aug 07 06:23:40 PM PDT 24
Finished Aug 07 06:23:42 PM PDT 24
Peak memory 200356 kb
Host smart-9485dcde-c1c0-4fbe-979b-9dd733867568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066307739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2066307739
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2832305063
Short name T92
Test name
Test status
Simulation time 247315370 ps
CPU time 1.63 seconds
Started Aug 07 06:23:46 PM PDT 24
Finished Aug 07 06:23:48 PM PDT 24
Peak memory 200536 kb
Host smart-43bede00-c0b3-4168-9988-57caa34b4f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832305063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2832305063
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2915779089
Short name T85
Test name
Test status
Simulation time 3242022946 ps
CPU time 15.26 seconds
Started Aug 07 06:23:45 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 200616 kb
Host smart-f6a311c4-247f-49d7-8bb0-734519ed16ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915779089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2915779089
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4084977183
Short name T422
Test name
Test status
Simulation time 466576869 ps
CPU time 2.58 seconds
Started Aug 07 06:23:46 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 200224 kb
Host smart-d4602447-cfce-49a3-bbc9-78054a298369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084977183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4084977183
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2273019404
Short name T208
Test name
Test status
Simulation time 204623844 ps
CPU time 1.4 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:53 PM PDT 24
Peak memory 200340 kb
Host smart-4317c22e-f48b-4ee5-be43-8a6b3d7b0f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273019404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2273019404
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3226713890
Short name T195
Test name
Test status
Simulation time 64236841 ps
CPU time 0.77 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 200168 kb
Host smart-22122eca-a220-450d-9063-8f3c99066013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226713890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3226713890
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3660739339
Short name T61
Test name
Test status
Simulation time 2166926090 ps
CPU time 7.75 seconds
Started Aug 07 06:23:57 PM PDT 24
Finished Aug 07 06:24:05 PM PDT 24
Peak memory 221780 kb
Host smart-477f39bb-4a7a-469b-92a8-80f2a54255c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660739339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3660739339
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1505179718
Short name T188
Test name
Test status
Simulation time 244235070 ps
CPU time 1.09 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 217600 kb
Host smart-2d8785df-f1e4-4aab-986e-be659231a43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505179718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1505179718
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.4179878668
Short name T502
Test name
Test status
Simulation time 162067422 ps
CPU time 0.9 seconds
Started Aug 07 06:23:53 PM PDT 24
Finished Aug 07 06:23:54 PM PDT 24
Peak memory 200140 kb
Host smart-d8e759a4-ac89-4cbb-845d-b80d2fc513a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179878668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4179878668
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.939472213
Short name T453
Test name
Test status
Simulation time 997537049 ps
CPU time 4.71 seconds
Started Aug 07 06:23:44 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 200560 kb
Host smart-dedfe556-eb6a-4b7a-a22a-a1123c3ea658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939472213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.939472213
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2182486128
Short name T484
Test name
Test status
Simulation time 98826439 ps
CPU time 0.98 seconds
Started Aug 07 06:23:43 PM PDT 24
Finished Aug 07 06:23:44 PM PDT 24
Peak memory 200348 kb
Host smart-a66a1141-3757-409b-8b16-eb1cd5459c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182486128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2182486128
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.4240865214
Short name T170
Test name
Test status
Simulation time 223612518 ps
CPU time 1.43 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200544 kb
Host smart-b235c46c-d96c-4eb8-b760-85c87e5986fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240865214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4240865214
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2336834520
Short name T473
Test name
Test status
Simulation time 7873796492 ps
CPU time 33.28 seconds
Started Aug 07 06:23:47 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 208824 kb
Host smart-966059f8-6211-4ebd-beeb-c540887f2e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336834520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2336834520
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2098000029
Short name T358
Test name
Test status
Simulation time 144416163 ps
CPU time 1.72 seconds
Started Aug 07 06:23:41 PM PDT 24
Finished Aug 07 06:23:43 PM PDT 24
Peak memory 200216 kb
Host smart-6f4898d0-7a25-46a7-8251-b086bab28613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098000029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2098000029
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1481978496
Short name T416
Test name
Test status
Simulation time 103861531 ps
CPU time 1.05 seconds
Started Aug 07 06:23:46 PM PDT 24
Finished Aug 07 06:23:47 PM PDT 24
Peak memory 200264 kb
Host smart-a4d97ce3-9f8e-42b0-bac2-073819b3c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481978496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1481978496
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2209641286
Short name T160
Test name
Test status
Simulation time 101902231 ps
CPU time 0.88 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200172 kb
Host smart-9cd3f4d5-028e-4999-b0ee-e0451e9e35ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209641286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2209641286
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.437268801
Short name T46
Test name
Test status
Simulation time 2355920575 ps
CPU time 8.31 seconds
Started Aug 07 06:23:47 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 217276 kb
Host smart-95b98f93-3da2-4a0d-a718-28403a49af99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437268801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.437268801
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2806785709
Short name T378
Test name
Test status
Simulation time 244694057 ps
CPU time 1.06 seconds
Started Aug 07 06:23:47 PM PDT 24
Finished Aug 07 06:23:48 PM PDT 24
Peak memory 217576 kb
Host smart-287d3685-672b-4673-b8b3-d991ce227840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806785709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2806785709
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.902587329
Short name T424
Test name
Test status
Simulation time 224736336 ps
CPU time 1 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:51 PM PDT 24
Peak memory 200156 kb
Host smart-1893f5f8-1c6c-4574-83f0-f9f067c89e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902587329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.902587329
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2495096259
Short name T500
Test name
Test status
Simulation time 1039323530 ps
CPU time 5.15 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 200568 kb
Host smart-27f3be3a-4a1b-450e-b462-69a6e504e525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495096259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2495096259
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3037472606
Short name T457
Test name
Test status
Simulation time 142537707 ps
CPU time 1.1 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200392 kb
Host smart-95f3366c-bfbe-4111-a235-96b2a620d9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037472606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3037472606
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1222339220
Short name T314
Test name
Test status
Simulation time 202747302 ps
CPU time 1.51 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200500 kb
Host smart-ea47fb8d-e596-4213-90af-56920234b7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222339220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1222339220
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3965755176
Short name T346
Test name
Test status
Simulation time 4753317297 ps
CPU time 16.53 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 200608 kb
Host smart-9dc272aa-79fb-45ca-ae07-647acced4681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965755176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3965755176
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.798074237
Short name T277
Test name
Test status
Simulation time 288737551 ps
CPU time 2.17 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:53 PM PDT 24
Peak memory 208492 kb
Host smart-e2512f5e-bb92-4841-9fe1-faf731862630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798074237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.798074237
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.188661917
Short name T10
Test name
Test status
Simulation time 73321585 ps
CPU time 0.8 seconds
Started Aug 07 06:23:55 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 200344 kb
Host smart-9bec556a-be98-427d-806f-516db00d3204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188661917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.188661917
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3905374222
Short name T179
Test name
Test status
Simulation time 56700990 ps
CPU time 0.73 seconds
Started Aug 07 06:23:53 PM PDT 24
Finished Aug 07 06:23:54 PM PDT 24
Peak memory 200024 kb
Host smart-ac032b95-d747-49f3-8c2b-a71698efb0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905374222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3905374222
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2658703172
Short name T49
Test name
Test status
Simulation time 2369169812 ps
CPU time 8.56 seconds
Started Aug 07 06:23:59 PM PDT 24
Finished Aug 07 06:24:07 PM PDT 24
Peak memory 221788 kb
Host smart-62fcf26b-0ddf-46b6-b7a6-54be9541ce78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658703172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2658703172
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3451073235
Short name T183
Test name
Test status
Simulation time 245197151 ps
CPU time 1.05 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 217552 kb
Host smart-61deef35-8b02-40a8-9165-6c595557c9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451073235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3451073235
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3283660512
Short name T302
Test name
Test status
Simulation time 93707852 ps
CPU time 0.78 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 200120 kb
Host smart-b93ce9db-c8e0-491d-a9af-00c3a2aa4658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283660512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3283660512
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3304750172
Short name T57
Test name
Test status
Simulation time 1727379810 ps
CPU time 6.69 seconds
Started Aug 07 06:23:49 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 200604 kb
Host smart-8fd88084-ddfa-4a7b-9bd9-87118291ff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304750172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3304750172
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3461460670
Short name T202
Test name
Test status
Simulation time 181657478 ps
CPU time 1.27 seconds
Started Aug 07 06:23:49 PM PDT 24
Finished Aug 07 06:23:50 PM PDT 24
Peak memory 200376 kb
Host smart-2636f193-820e-45bf-82d8-5e40ba61a6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461460670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3461460670
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3700753457
Short name T418
Test name
Test status
Simulation time 105582798 ps
CPU time 1.22 seconds
Started Aug 07 06:23:49 PM PDT 24
Finished Aug 07 06:23:50 PM PDT 24
Peak memory 200480 kb
Host smart-ccc2a1e5-6d59-4f9c-b068-c5ef7bbda6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700753457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3700753457
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3788709436
Short name T499
Test name
Test status
Simulation time 8816010815 ps
CPU time 32.97 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:24:23 PM PDT 24
Peak memory 200620 kb
Host smart-9b92490f-518a-4018-b48e-69adfefc130a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788709436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3788709436
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3801212453
Short name T518
Test name
Test status
Simulation time 317790074 ps
CPU time 2.13 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:23:59 PM PDT 24
Peak memory 200348 kb
Host smart-96a311f5-6123-4ded-8688-4eb30be489ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801212453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3801212453
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2664998012
Short name T468
Test name
Test status
Simulation time 115818598 ps
CPU time 1.01 seconds
Started Aug 07 06:23:49 PM PDT 24
Finished Aug 07 06:23:50 PM PDT 24
Peak memory 200368 kb
Host smart-0edf0a6f-4b05-476d-b2af-7474e908f52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664998012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2664998012
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4188463572
Short name T444
Test name
Test status
Simulation time 91653771 ps
CPU time 0.83 seconds
Started Aug 07 06:22:53 PM PDT 24
Finished Aug 07 06:22:54 PM PDT 24
Peak memory 200092 kb
Host smart-5979b0f3-aebf-4a0a-9b48-42653e83a697
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188463572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4188463572
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3972016103
Short name T340
Test name
Test status
Simulation time 1222655692 ps
CPU time 5.94 seconds
Started Aug 07 06:22:53 PM PDT 24
Finished Aug 07 06:22:59 PM PDT 24
Peak memory 221640 kb
Host smart-c2f88256-8d10-4d4e-8bf4-79a17ecc2dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972016103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3972016103
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3351290177
Short name T169
Test name
Test status
Simulation time 243745244 ps
CPU time 1.05 seconds
Started Aug 07 06:22:49 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 217504 kb
Host smart-2b9c7540-7b9a-458b-84f6-eddce358f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351290177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3351290177
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.4025324005
Short name T445
Test name
Test status
Simulation time 144776880 ps
CPU time 0.8 seconds
Started Aug 07 06:22:42 PM PDT 24
Finished Aug 07 06:22:43 PM PDT 24
Peak memory 200156 kb
Host smart-7a2f063d-b307-4c3c-90ab-5f025745742f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025324005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.4025324005
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3739410822
Short name T535
Test name
Test status
Simulation time 1022581853 ps
CPU time 5.59 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:22:53 PM PDT 24
Peak memory 200584 kb
Host smart-1cd29bb0-6504-4a0b-aafa-c5ca60967021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739410822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3739410822
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.746706871
Short name T76
Test name
Test status
Simulation time 8373588086 ps
CPU time 12.8 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:23:01 PM PDT 24
Peak memory 217328 kb
Host smart-7b366142-285e-4543-b4c0-6491caa68f83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746706871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.746706871
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3884330697
Short name T207
Test name
Test status
Simulation time 104607997 ps
CPU time 1.04 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:49 PM PDT 24
Peak memory 200328 kb
Host smart-e452696d-c8bb-4002-ae2c-f3264dd2d97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884330697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3884330697
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2111892319
Short name T408
Test name
Test status
Simulation time 111457344 ps
CPU time 1.22 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 200464 kb
Host smart-950dced3-99b1-4af2-b366-0908ab2e5710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111892319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2111892319
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2995228762
Short name T351
Test name
Test status
Simulation time 7765883303 ps
CPU time 35.42 seconds
Started Aug 07 06:22:50 PM PDT 24
Finished Aug 07 06:23:26 PM PDT 24
Peak memory 208716 kb
Host smart-f16492f1-fa82-4223-8881-3b17854a31fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995228762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2995228762
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1073771302
Short name T175
Test name
Test status
Simulation time 374457257 ps
CPU time 2.38 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:22:50 PM PDT 24
Peak memory 208400 kb
Host smart-a0c7740a-030d-4b91-81e5-ab69b06750f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073771302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1073771302
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4205204065
Short name T246
Test name
Test status
Simulation time 153369484 ps
CPU time 1.13 seconds
Started Aug 07 06:22:50 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 200360 kb
Host smart-535f6957-81d9-4212-bedc-126779d8f6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205204065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4205204065
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4103097963
Short name T83
Test name
Test status
Simulation time 92193143 ps
CPU time 0.88 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:23:57 PM PDT 24
Peak memory 200160 kb
Host smart-7acfaff4-da80-466e-975b-56d07c2f92d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103097963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4103097963
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3509453522
Short name T395
Test name
Test status
Simulation time 1884042710 ps
CPU time 7.29 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:59 PM PDT 24
Peak memory 217728 kb
Host smart-d0371772-8092-4cf5-bda0-f94f1f0d42aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509453522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3509453522
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1177177631
Short name T274
Test name
Test status
Simulation time 244401415 ps
CPU time 1.09 seconds
Started Aug 07 06:23:55 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 217516 kb
Host smart-c9a4b17a-b9f9-4729-b09c-f6ae13f4d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177177631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1177177631
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1374043371
Short name T210
Test name
Test status
Simulation time 212280704 ps
CPU time 0.91 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200160 kb
Host smart-223d615e-6b20-47d9-b60c-fe1717789471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374043371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1374043371
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2692757569
Short name T222
Test name
Test status
Simulation time 1327338037 ps
CPU time 5.04 seconds
Started Aug 07 06:23:49 PM PDT 24
Finished Aug 07 06:23:54 PM PDT 24
Peak memory 200464 kb
Host smart-cb3c7707-54f3-41e9-b7b3-c94fbb6e84da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692757569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2692757569
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.506578642
Short name T303
Test name
Test status
Simulation time 184452914 ps
CPU time 1.21 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200336 kb
Host smart-606f3ea7-d21a-40af-86c3-6c585acd4663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506578642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.506578642
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.339551813
Short name T454
Test name
Test status
Simulation time 199531192 ps
CPU time 1.37 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200480 kb
Host smart-9da368e9-a894-4424-9fb5-deddeea6ef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339551813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.339551813
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.808345778
Short name T260
Test name
Test status
Simulation time 3534311929 ps
CPU time 16.28 seconds
Started Aug 07 06:23:52 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 200652 kb
Host smart-1608c1e9-ffc1-4b84-adf3-8467cd541f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808345778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.808345778
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.685586637
Short name T359
Test name
Test status
Simulation time 524365372 ps
CPU time 2.94 seconds
Started Aug 07 06:23:53 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 200304 kb
Host smart-c0011c40-056e-43ed-b259-c769358170d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685586637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.685586637
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.4099373262
Short name T397
Test name
Test status
Simulation time 116822079 ps
CPU time 1.02 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200364 kb
Host smart-57e13e4d-0eb3-4fe0-8094-2d2d16fcec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099373262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4099373262
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.232819757
Short name T174
Test name
Test status
Simulation time 59410484 ps
CPU time 0.8 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200160 kb
Host smart-533cfee4-16cf-463f-94c0-a07b5c318c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232819757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.232819757
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2364414896
Short name T326
Test name
Test status
Simulation time 2359374261 ps
CPU time 8.69 seconds
Started Aug 07 06:23:52 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 217180 kb
Host smart-2419968e-7723-4ec1-b022-770e3fec1541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364414896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2364414896
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3588302424
Short name T263
Test name
Test status
Simulation time 244397793 ps
CPU time 1.14 seconds
Started Aug 07 06:23:55 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 217532 kb
Host smart-e706324e-b43b-4e6e-ae61-9713c95d273b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588302424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3588302424
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3400899288
Short name T214
Test name
Test status
Simulation time 211537974 ps
CPU time 0.97 seconds
Started Aug 07 06:23:48 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 200196 kb
Host smart-0a28c958-09df-4896-bfd5-d03978b9b5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400899288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3400899288
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.725094504
Short name T495
Test name
Test status
Simulation time 770545616 ps
CPU time 4.04 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:54 PM PDT 24
Peak memory 200556 kb
Host smart-8b0b8d22-c435-467c-8c7c-eb8abe51e8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725094504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.725094504
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2551416572
Short name T56
Test name
Test status
Simulation time 182953067 ps
CPU time 1.16 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:51 PM PDT 24
Peak memory 200348 kb
Host smart-0401b8d6-75e2-4dbe-87de-e83920998638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551416572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2551416572
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.4017719617
Short name T185
Test name
Test status
Simulation time 192326612 ps
CPU time 1.36 seconds
Started Aug 07 06:23:48 PM PDT 24
Finished Aug 07 06:23:49 PM PDT 24
Peak memory 200488 kb
Host smart-02122e21-1eb8-4524-9707-fc8018eaf0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017719617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4017719617
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.4140264862
Short name T219
Test name
Test status
Simulation time 7056674723 ps
CPU time 31.18 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:24:22 PM PDT 24
Peak memory 200620 kb
Host smart-7d6c3b98-6445-4490-8aa8-750d66008879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140264862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4140264862
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3147457085
Short name T186
Test name
Test status
Simulation time 358113161 ps
CPU time 1.95 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 200296 kb
Host smart-2e23382b-e171-494c-940b-03254865b000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147457085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3147457085
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.984435897
Short name T146
Test name
Test status
Simulation time 253613662 ps
CPU time 1.56 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:52 PM PDT 24
Peak memory 200536 kb
Host smart-0f0ca6ea-14c4-4208-94cb-b2494da48307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984435897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.984435897
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3177402850
Short name T173
Test name
Test status
Simulation time 53022052 ps
CPU time 0.72 seconds
Started Aug 07 06:23:55 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 200164 kb
Host smart-30393ef7-5916-4d2a-9b03-976c8a8c0435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177402850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3177402850
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4198222376
Short name T519
Test name
Test status
Simulation time 1223788662 ps
CPU time 5.52 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 217828 kb
Host smart-2992e37c-dafd-4a8c-9688-592339e24cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198222376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4198222376
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1945164663
Short name T227
Test name
Test status
Simulation time 244613599 ps
CPU time 1.08 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 217508 kb
Host smart-04489674-47a8-4397-852f-9bd8c5fc7665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945164663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1945164663
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2665720189
Short name T440
Test name
Test status
Simulation time 195988822 ps
CPU time 1 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 200152 kb
Host smart-1736383f-10ba-460a-b8c9-d93112556120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665720189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2665720189
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.4271632782
Short name T451
Test name
Test status
Simulation time 861236514 ps
CPU time 4.75 seconds
Started Aug 07 06:23:52 PM PDT 24
Finished Aug 07 06:23:57 PM PDT 24
Peak memory 200548 kb
Host smart-0294c9a3-c529-440b-b43c-6908767ae5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271632782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.4271632782
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.4160176067
Short name T335
Test name
Test status
Simulation time 150660247 ps
CPU time 1.12 seconds
Started Aug 07 06:23:54 PM PDT 24
Finished Aug 07 06:23:55 PM PDT 24
Peak memory 200388 kb
Host smart-344c35dc-ccf6-40d8-b929-e3b71f23999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160176067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.4160176067
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3370114432
Short name T93
Test name
Test status
Simulation time 114624267 ps
CPU time 1.13 seconds
Started Aug 07 06:23:50 PM PDT 24
Finished Aug 07 06:23:51 PM PDT 24
Peak memory 200500 kb
Host smart-216e1eaf-7c9a-4895-987a-cd011a83a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370114432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3370114432
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.18975881
Short name T309
Test name
Test status
Simulation time 4705578001 ps
CPU time 19.3 seconds
Started Aug 07 06:23:55 PM PDT 24
Finished Aug 07 06:24:15 PM PDT 24
Peak memory 200668 kb
Host smart-4de8fe75-559d-4c1e-b233-2e1c9965dfe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18975881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.18975881
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.4120833890
Short name T224
Test name
Test status
Simulation time 334277650 ps
CPU time 2.07 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200268 kb
Host smart-975e57e5-757e-48bf-92c4-321a0517e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120833890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.4120833890
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.413208006
Short name T317
Test name
Test status
Simulation time 173373196 ps
CPU time 1.26 seconds
Started Aug 07 06:23:53 PM PDT 24
Finished Aug 07 06:23:54 PM PDT 24
Peak memory 200360 kb
Host smart-96557122-c50a-4912-a417-e60e3ede17cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413208006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.413208006
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3012203185
Short name T355
Test name
Test status
Simulation time 94740184 ps
CPU time 0.9 seconds
Started Aug 07 06:23:52 PM PDT 24
Finished Aug 07 06:23:53 PM PDT 24
Peak memory 200156 kb
Host smart-5ae5c0d1-ea77-44ec-bce7-4bae7cb34154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012203185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3012203185
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.4232106717
Short name T28
Test name
Test status
Simulation time 1224158958 ps
CPU time 5.93 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 217600 kb
Host smart-3a8cbbe9-7438-4694-af64-6a1a494fd441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232106717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4232106717
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.901467516
Short name T205
Test name
Test status
Simulation time 246362713 ps
CPU time 1.06 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 217524 kb
Host smart-75c66351-029a-4574-afe2-5ea9cc59979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901467516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.901467516
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.595218839
Short name T403
Test name
Test status
Simulation time 237651712 ps
CPU time 1.04 seconds
Started Aug 07 06:23:54 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 200164 kb
Host smart-d4680337-b2a5-4c2b-b7d5-1df234b6e493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595218839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.595218839
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1530478004
Short name T423
Test name
Test status
Simulation time 958287863 ps
CPU time 4.98 seconds
Started Aug 07 06:23:52 PM PDT 24
Finished Aug 07 06:23:57 PM PDT 24
Peak memory 200544 kb
Host smart-44f941fe-0e17-45c3-b9fe-83c0fc0558ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530478004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1530478004
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1961161916
Short name T469
Test name
Test status
Simulation time 108064036 ps
CPU time 0.99 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:23:57 PM PDT 24
Peak memory 200360 kb
Host smart-ec79ef90-d289-4cf3-a80a-df3650bcc430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961161916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1961161916
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3957068139
Short name T165
Test name
Test status
Simulation time 114374489 ps
CPU time 1.16 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 200472 kb
Host smart-dc86c490-260c-471b-a25b-843a0afb0595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957068139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3957068139
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3305442130
Short name T106
Test name
Test status
Simulation time 1636260009 ps
CPU time 5.95 seconds
Started Aug 07 06:23:57 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 200568 kb
Host smart-81a7eaf9-fbd6-46d0-8f4a-aa823680b7bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305442130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3305442130
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2493405841
Short name T381
Test name
Test status
Simulation time 383908761 ps
CPU time 2.36 seconds
Started Aug 07 06:24:19 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 200280 kb
Host smart-0ee0ebd4-25ff-43e9-93e2-51b2ebec8e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493405841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2493405841
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3099708229
Short name T537
Test name
Test status
Simulation time 181652878 ps
CPU time 1.29 seconds
Started Aug 07 06:23:51 PM PDT 24
Finished Aug 07 06:23:53 PM PDT 24
Peak memory 200344 kb
Host smart-15746095-de39-4249-8199-2ff4f0e35b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099708229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3099708229
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.495991886
Short name T411
Test name
Test status
Simulation time 76662692 ps
CPU time 0.88 seconds
Started Aug 07 06:23:54 PM PDT 24
Finished Aug 07 06:23:55 PM PDT 24
Peak memory 200160 kb
Host smart-e74a216b-8b1e-4eeb-8bee-93355f188e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495991886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.495991886
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2050151840
Short name T48
Test name
Test status
Simulation time 1219414807 ps
CPU time 6.08 seconds
Started Aug 07 06:23:53 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 221700 kb
Host smart-7856602b-72da-46fe-9afc-6e9dc873672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050151840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2050151840
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1750221460
Short name T193
Test name
Test status
Simulation time 243740524 ps
CPU time 1.1 seconds
Started Aug 07 06:23:54 PM PDT 24
Finished Aug 07 06:23:56 PM PDT 24
Peak memory 217528 kb
Host smart-901280cd-e7ad-4f43-babc-6a2a5778c65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750221460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1750221460
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.115820545
Short name T262
Test name
Test status
Simulation time 190360864 ps
CPU time 0.92 seconds
Started Aug 07 06:23:52 PM PDT 24
Finished Aug 07 06:23:53 PM PDT 24
Peak memory 200160 kb
Host smart-dd47f784-c9dd-4b54-a07f-1d3916cbd571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115820545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.115820545
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3120476776
Short name T431
Test name
Test status
Simulation time 996780459 ps
CPU time 4.73 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:07 PM PDT 24
Peak memory 200408 kb
Host smart-346d7b6f-ffc6-4781-8b7f-78abfa357f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120476776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3120476776
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2292693787
Short name T446
Test name
Test status
Simulation time 114531754 ps
CPU time 1.03 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:23:57 PM PDT 24
Peak memory 200384 kb
Host smart-24fccc7f-67c3-46af-bacc-bac6f3458f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292693787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2292693787
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2829363887
Short name T318
Test name
Test status
Simulation time 225541253 ps
CPU time 1.48 seconds
Started Aug 07 06:24:03 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 200500 kb
Host smart-0a89fa65-fd7e-4734-ba0f-ef67ab6b3818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829363887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2829363887
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2239080514
Short name T376
Test name
Test status
Simulation time 11046462151 ps
CPU time 40.16 seconds
Started Aug 07 06:24:04 PM PDT 24
Finished Aug 07 06:24:44 PM PDT 24
Peak memory 200672 kb
Host smart-5bac549a-4a8e-4e4c-b596-f4680bd7b3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239080514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2239080514
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2454045041
Short name T433
Test name
Test status
Simulation time 282483356 ps
CPU time 1.9 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:03 PM PDT 24
Peak memory 200280 kb
Host smart-70f31d62-4437-45be-98d2-46e409a62c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454045041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2454045041
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2982489405
Short name T368
Test name
Test status
Simulation time 113443482 ps
CPU time 1.12 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:23:57 PM PDT 24
Peak memory 200376 kb
Host smart-6012bf00-c686-4f7d-ba5f-63fc9820e741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982489405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2982489405
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2410815938
Short name T159
Test name
Test status
Simulation time 71699408 ps
CPU time 0.79 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 200144 kb
Host smart-948e2378-4202-443a-a693-f2ba3f4b03fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410815938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2410815938
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4090124441
Short name T465
Test name
Test status
Simulation time 1901000998 ps
CPU time 7.3 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:09 PM PDT 24
Peak memory 217772 kb
Host smart-b70dfae8-db4a-4ecd-88bd-b2f5b86815b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090124441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4090124441
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3512391232
Short name T356
Test name
Test status
Simulation time 244237320 ps
CPU time 1.14 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 217520 kb
Host smart-fd56e0a5-5594-4f38-8fd5-b9c1dad5134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512391232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3512391232
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2306108223
Short name T22
Test name
Test status
Simulation time 111565294 ps
CPU time 0.81 seconds
Started Aug 07 06:23:54 PM PDT 24
Finished Aug 07 06:23:55 PM PDT 24
Peak memory 200188 kb
Host smart-7041b7d9-8e5f-4b95-b28b-cc68532adbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306108223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2306108223
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.519596241
Short name T409
Test name
Test status
Simulation time 2003681545 ps
CPU time 7.3 seconds
Started Aug 07 06:23:52 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200532 kb
Host smart-78188019-f4a0-4f66-8838-27135dcdeb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519596241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.519596241
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2453515341
Short name T238
Test name
Test status
Simulation time 153572488 ps
CPU time 1.15 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200356 kb
Host smart-d58d4574-a453-4781-8504-a12f16861389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453515341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2453515341
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1788913826
Short name T447
Test name
Test status
Simulation time 110913679 ps
CPU time 1.19 seconds
Started Aug 07 06:23:59 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200472 kb
Host smart-4c1e9b9a-f7cf-419c-a0b4-df48a89ab534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788913826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1788913826
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.593325742
Short name T251
Test name
Test status
Simulation time 256240053 ps
CPU time 1.83 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 200288 kb
Host smart-14133322-b648-4827-8c7d-5a02bb88c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593325742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.593325742
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1306276242
Short name T296
Test name
Test status
Simulation time 90857931 ps
CPU time 0.87 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 200356 kb
Host smart-75c912ae-765e-45d9-9c32-be220fa6cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306276242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1306276242
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.808565517
Short name T82
Test name
Test status
Simulation time 96535805 ps
CPU time 0.87 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 200132 kb
Host smart-3895a692-cad1-41b4-ad33-1851b6b66570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808565517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.808565517
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.797935562
Short name T279
Test name
Test status
Simulation time 1898126413 ps
CPU time 7.06 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:10 PM PDT 24
Peak memory 221764 kb
Host smart-38a93ff5-21fb-4f04-a268-d1f4593f1613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797935562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.797935562
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.470948704
Short name T242
Test name
Test status
Simulation time 244159661 ps
CPU time 1.06 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:23:59 PM PDT 24
Peak memory 217572 kb
Host smart-55e67965-8d62-42ec-b1ee-4baadbe3955d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470948704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.470948704
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.653541535
Short name T198
Test name
Test status
Simulation time 108080047 ps
CPU time 0.76 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:01 PM PDT 24
Peak memory 200148 kb
Host smart-671156cb-01e7-48d2-bba2-a589bfc70983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653541535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.653541535
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.235486476
Short name T487
Test name
Test status
Simulation time 1643343714 ps
CPU time 6.07 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:06 PM PDT 24
Peak memory 200524 kb
Host smart-baa6a529-aba3-449e-b690-8edadd139874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235486476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.235486476
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.551308443
Short name T531
Test name
Test status
Simulation time 155622222 ps
CPU time 1.15 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:23:58 PM PDT 24
Peak memory 200364 kb
Host smart-fca111f4-f5dd-495f-998e-6114221a38cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551308443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.551308443
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4111035960
Short name T171
Test name
Test status
Simulation time 116284447 ps
CPU time 1.17 seconds
Started Aug 07 06:23:53 PM PDT 24
Finished Aug 07 06:23:54 PM PDT 24
Peak memory 200492 kb
Host smart-c7cc6ca7-14f5-44d4-8ba3-b33965aeff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111035960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4111035960
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.608683297
Short name T52
Test name
Test status
Simulation time 4164265457 ps
CPU time 18.65 seconds
Started Aug 07 06:24:25 PM PDT 24
Finished Aug 07 06:24:43 PM PDT 24
Peak memory 210820 kb
Host smart-727840b1-e4d1-4429-92f2-9fb8ceecd317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608683297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.608683297
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.109322313
Short name T293
Test name
Test status
Simulation time 109901647 ps
CPU time 1.44 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200300 kb
Host smart-53fdf75d-ced3-42e9-a22e-eee69d02abe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109322313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.109322313
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.100106155
Short name T297
Test name
Test status
Simulation time 68321501 ps
CPU time 0.77 seconds
Started Aug 07 06:23:56 PM PDT 24
Finished Aug 07 06:23:57 PM PDT 24
Peak memory 200380 kb
Host smart-d0c6be91-821c-4f98-86fc-dad0ba256817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100106155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.100106155
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.4218037143
Short name T177
Test name
Test status
Simulation time 78533575 ps
CPU time 0.73 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:23:59 PM PDT 24
Peak memory 200148 kb
Host smart-ee0382bd-a104-4158-b3cb-ccc73d147f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218037143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4218037143
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1696082284
Short name T63
Test name
Test status
Simulation time 1227410098 ps
CPU time 5.76 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 217804 kb
Host smart-2d42d13a-e020-451f-b6aa-3c91361ac5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696082284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1696082284
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4183995238
Short name T275
Test name
Test status
Simulation time 244119803 ps
CPU time 1.11 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 217500 kb
Host smart-95d900e5-43b1-41b2-862b-94c1cebac5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183995238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4183995238
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.810024976
Short name T476
Test name
Test status
Simulation time 101029053 ps
CPU time 0.78 seconds
Started Aug 07 06:24:04 PM PDT 24
Finished Aug 07 06:24:05 PM PDT 24
Peak memory 200164 kb
Host smart-91b17fb2-e4d1-44a7-8461-7b61d4d030c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810024976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.810024976
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.766133138
Short name T187
Test name
Test status
Simulation time 1076703929 ps
CPU time 5.01 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:05 PM PDT 24
Peak memory 200568 kb
Host smart-e949da6f-209f-4886-9acf-371ca72714ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766133138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.766133138
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.819652884
Short name T43
Test name
Test status
Simulation time 101577293 ps
CPU time 0.98 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200388 kb
Host smart-a62e9fdc-7e8c-4087-9140-f2f367781d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819652884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.819652884
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.460538011
Short name T88
Test name
Test status
Simulation time 9622898902 ps
CPU time 31.21 seconds
Started Aug 07 06:24:03 PM PDT 24
Finished Aug 07 06:24:35 PM PDT 24
Peak memory 209020 kb
Host smart-5ce9166f-3cc6-46b5-b592-fa20d5c480cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460538011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.460538011
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3813919421
Short name T482
Test name
Test status
Simulation time 337372753 ps
CPU time 2.44 seconds
Started Aug 07 06:24:05 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 200320 kb
Host smart-67cb9d69-2249-4f60-9937-d31d3853d7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813919421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3813919421
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1745681199
Short name T463
Test name
Test status
Simulation time 114650281 ps
CPU time 0.95 seconds
Started Aug 07 06:23:57 PM PDT 24
Finished Aug 07 06:23:58 PM PDT 24
Peak memory 200376 kb
Host smart-cd1c51a9-4636-47ef-9b69-2740fef1ab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745681199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1745681199
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3184970230
Short name T371
Test name
Test status
Simulation time 71613847 ps
CPU time 0.77 seconds
Started Aug 07 06:23:55 PM PDT 24
Finished Aug 07 06:23:55 PM PDT 24
Peak memory 200160 kb
Host smart-08e074a8-508e-415e-9e84-f248ccd931ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184970230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3184970230
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1462058297
Short name T494
Test name
Test status
Simulation time 243989106 ps
CPU time 1.08 seconds
Started Aug 07 06:24:00 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 217532 kb
Host smart-60b2533d-119f-4106-b475-51ffaf59a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462058297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1462058297
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3453937891
Short name T390
Test name
Test status
Simulation time 131362126 ps
CPU time 0.82 seconds
Started Aug 07 06:23:57 PM PDT 24
Finished Aug 07 06:23:58 PM PDT 24
Peak memory 200160 kb
Host smart-f425279e-4dd3-4819-8bb7-72c2ae64e72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453937891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3453937891
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3269568244
Short name T270
Test name
Test status
Simulation time 1499576626 ps
CPU time 5.83 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 200536 kb
Host smart-aa7ca4b2-f515-45c6-adf3-8badd43802ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269568244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3269568244
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4142271322
Short name T472
Test name
Test status
Simulation time 180372902 ps
CPU time 1.19 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 200340 kb
Host smart-aa75b82a-4a5c-44b7-8e0c-4f50427f56d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142271322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4142271322
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2417637562
Short name T147
Test name
Test status
Simulation time 112486675 ps
CPU time 1.14 seconds
Started Aug 07 06:23:59 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200488 kb
Host smart-1a8fe119-e380-47b8-b1fc-b06c6e226fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417637562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2417637562
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.857773189
Short name T413
Test name
Test status
Simulation time 2265760238 ps
CPU time 8.79 seconds
Started Aug 07 06:23:57 PM PDT 24
Finished Aug 07 06:24:06 PM PDT 24
Peak memory 200676 kb
Host smart-ee07a281-721f-47b8-a226-b98e0816cfe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857773189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.857773189
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1899746829
Short name T533
Test name
Test status
Simulation time 120070814 ps
CPU time 1.43 seconds
Started Aug 07 06:23:59 PM PDT 24
Finished Aug 07 06:24:00 PM PDT 24
Peak memory 200304 kb
Host smart-8a82cf20-8733-4493-9a9d-6337072794dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899746829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1899746829
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2272641743
Short name T419
Test name
Test status
Simulation time 141406435 ps
CPU time 1.2 seconds
Started Aug 07 06:23:58 PM PDT 24
Finished Aug 07 06:23:59 PM PDT 24
Peak memory 200388 kb
Host smart-f2991e7c-0cf7-4ca5-9159-d7c43b9709a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272641743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2272641743
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4078970050
Short name T320
Test name
Test status
Simulation time 69578965 ps
CPU time 0.77 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:02 PM PDT 24
Peak memory 200172 kb
Host smart-d2fad11f-4b28-450d-972a-acc4441fb312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078970050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4078970050
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1854516980
Short name T406
Test name
Test status
Simulation time 2368171678 ps
CPU time 8.18 seconds
Started Aug 07 06:24:01 PM PDT 24
Finished Aug 07 06:24:09 PM PDT 24
Peak memory 217860 kb
Host smart-5e4c8d61-d910-4d0d-88f7-5cc59a827960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854516980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1854516980
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1942202529
Short name T337
Test name
Test status
Simulation time 248194841 ps
CPU time 1.02 seconds
Started Aug 07 06:24:07 PM PDT 24
Finished Aug 07 06:24:08 PM PDT 24
Peak memory 217536 kb
Host smart-97c8ef90-b61b-474f-ba93-5ff90ee2830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942202529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1942202529
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.637514920
Short name T247
Test name
Test status
Simulation time 152408514 ps
CPU time 0.88 seconds
Started Aug 07 06:24:17 PM PDT 24
Finished Aug 07 06:24:18 PM PDT 24
Peak memory 200356 kb
Host smart-58224912-1c1d-4abd-957f-ab8c3982ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637514920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.637514920
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3031961330
Short name T223
Test name
Test status
Simulation time 2149589263 ps
CPU time 7.44 seconds
Started Aug 07 06:24:14 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 200664 kb
Host smart-427f5ee9-a919-4963-9b96-7ce1f87ed6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031961330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3031961330
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.280343021
Short name T398
Test name
Test status
Simulation time 138790763 ps
CPU time 1.08 seconds
Started Aug 07 06:24:05 PM PDT 24
Finished Aug 07 06:24:06 PM PDT 24
Peak memory 200352 kb
Host smart-7088b90d-6de4-4a77-a786-fbcbc97e92ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280343021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.280343021
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3053788225
Short name T89
Test name
Test status
Simulation time 258247741 ps
CPU time 1.51 seconds
Started Aug 07 06:24:02 PM PDT 24
Finished Aug 07 06:24:04 PM PDT 24
Peak memory 200468 kb
Host smart-0b5770ad-b10a-4333-b8f7-8e375324078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053788225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3053788225
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2240520309
Short name T281
Test name
Test status
Simulation time 10169404016 ps
CPU time 34.51 seconds
Started Aug 07 06:24:03 PM PDT 24
Finished Aug 07 06:24:38 PM PDT 24
Peak memory 200836 kb
Host smart-07358e9d-a022-49f5-80c6-d8aad8ccf01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240520309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2240520309
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.189603786
Short name T269
Test name
Test status
Simulation time 374405651 ps
CPU time 2.3 seconds
Started Aug 07 06:24:08 PM PDT 24
Finished Aug 07 06:24:10 PM PDT 24
Peak memory 208472 kb
Host smart-c0448c31-e37b-49ef-b5ae-25cb0436ad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189603786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.189603786
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.3392193264
Short name T400
Test name
Test status
Simulation time 122957921 ps
CPU time 1.03 seconds
Started Aug 07 06:24:20 PM PDT 24
Finished Aug 07 06:24:21 PM PDT 24
Peak memory 200356 kb
Host smart-bb494c28-4de5-4df1-b089-ac144f292b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392193264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3392193264
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2927829493
Short name T2
Test name
Test status
Simulation time 65119812 ps
CPU time 0.78 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 200156 kb
Host smart-78332e89-eb84-468d-8cea-dce3346487c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927829493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2927829493
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2868057843
Short name T532
Test name
Test status
Simulation time 1213251282 ps
CPU time 5.74 seconds
Started Aug 07 06:22:49 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 217528 kb
Host smart-5c108568-8cb6-4221-be4c-a5b3da303d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868057843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2868057843
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.661053726
Short name T280
Test name
Test status
Simulation time 244445611 ps
CPU time 1.09 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:22:49 PM PDT 24
Peak memory 217576 kb
Host smart-873adf32-d5d3-43bc-8f60-9ea1536e840d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661053726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.661053726
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.4141099300
Short name T498
Test name
Test status
Simulation time 133902085 ps
CPU time 0.85 seconds
Started Aug 07 06:22:50 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 200164 kb
Host smart-ecb71af8-66ef-4fb9-8682-975d2a7a7f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141099300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4141099300
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.904091689
Short name T467
Test name
Test status
Simulation time 1137572095 ps
CPU time 4.7 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 200584 kb
Host smart-7da9ae01-6101-491a-801f-0480e8cdba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904091689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.904091689
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3902927021
Short name T436
Test name
Test status
Simulation time 179690936 ps
CPU time 1.2 seconds
Started Aug 07 06:22:50 PM PDT 24
Finished Aug 07 06:22:52 PM PDT 24
Peak memory 200388 kb
Host smart-656df713-a290-43de-9833-763609fb991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902927021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3902927021
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.508894878
Short name T300
Test name
Test status
Simulation time 115492853 ps
CPU time 1.23 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 200488 kb
Host smart-25886595-2826-4d53-986c-be41704f03a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508894878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.508894878
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1676401290
Short name T329
Test name
Test status
Simulation time 319998008 ps
CPU time 1.77 seconds
Started Aug 07 06:22:53 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 200396 kb
Host smart-35eace98-d2fc-4982-9c0d-4faa80770893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676401290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1676401290
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1932439551
Short name T407
Test name
Test status
Simulation time 352278114 ps
CPU time 2.24 seconds
Started Aug 07 06:22:49 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 200252 kb
Host smart-4010f4da-25dc-4d7e-9dee-23f0d87b44ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932439551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1932439551
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2843927138
Short name T182
Test name
Test status
Simulation time 262825208 ps
CPU time 1.41 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:22:49 PM PDT 24
Peak memory 200360 kb
Host smart-0c3df631-b640-458b-9f2b-c46611bcd482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843927138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2843927138
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.230558135
Short name T348
Test name
Test status
Simulation time 66413649 ps
CPU time 0.77 seconds
Started Aug 07 06:22:49 PM PDT 24
Finished Aug 07 06:22:49 PM PDT 24
Peak memory 200164 kb
Host smart-7bddbdd2-dae7-4482-ad18-c23183bec3a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230558135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.230558135
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1373236286
Short name T135
Test name
Test status
Simulation time 1900752181 ps
CPU time 7.47 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 217764 kb
Host smart-f16d076a-d8c7-412f-9a14-af4ab7c67178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373236286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1373236286
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1585584166
Short name T477
Test name
Test status
Simulation time 245072991 ps
CPU time 1.08 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 217540 kb
Host smart-e39546e4-e8ac-4a6c-9ff4-0ab220ccb5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585584166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1585584166
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3938537877
Short name T509
Test name
Test status
Simulation time 92741982 ps
CPU time 0.76 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:48 PM PDT 24
Peak memory 200120 kb
Host smart-f39bc48e-452e-4d62-8ce7-edfc6bf3634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938537877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3938537877
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3345730208
Short name T27
Test name
Test status
Simulation time 1476135827 ps
CPU time 5.83 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:22:54 PM PDT 24
Peak memory 200532 kb
Host smart-97f18dd2-7431-42e2-aab7-fbb817091a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345730208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3345730208
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.343856155
Short name T209
Test name
Test status
Simulation time 147611177 ps
CPU time 1.13 seconds
Started Aug 07 06:22:52 PM PDT 24
Finished Aug 07 06:22:54 PM PDT 24
Peak memory 200336 kb
Host smart-9068c89e-7648-4d61-b63e-a2f500f7afd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343856155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.343856155
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2779562653
Short name T534
Test name
Test status
Simulation time 120822943 ps
CPU time 1.23 seconds
Started Aug 07 06:22:47 PM PDT 24
Finished Aug 07 06:22:49 PM PDT 24
Peak memory 200528 kb
Host smart-56b77928-e04d-4e34-892e-98b06e57068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779562653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2779562653
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.399766127
Short name T517
Test name
Test status
Simulation time 1267753484 ps
CPU time 6 seconds
Started Aug 07 06:22:49 PM PDT 24
Finished Aug 07 06:22:56 PM PDT 24
Peak memory 200488 kb
Host smart-00444b0f-bb84-4b38-8097-db30e576b335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399766127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.399766127
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2739083477
Short name T268
Test name
Test status
Simulation time 274651691 ps
CPU time 1.88 seconds
Started Aug 07 06:22:53 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 200272 kb
Host smart-553b5512-0162-42c8-a42d-3ce880bd08f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739083477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2739083477
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3331411836
Short name T212
Test name
Test status
Simulation time 90439600 ps
CPU time 0.86 seconds
Started Aug 07 06:22:50 PM PDT 24
Finished Aug 07 06:22:51 PM PDT 24
Peak memory 200236 kb
Host smart-a33b2df6-1b20-425a-8a03-cf8fa013fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331411836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3331411836
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.1458609498
Short name T362
Test name
Test status
Simulation time 70697278 ps
CPU time 0.77 seconds
Started Aug 07 06:22:55 PM PDT 24
Finished Aug 07 06:22:56 PM PDT 24
Peak memory 200160 kb
Host smart-30fb3586-8641-4295-b320-9c217b7eeedf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458609498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1458609498
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1156025359
Short name T60
Test name
Test status
Simulation time 1224989628 ps
CPU time 5.93 seconds
Started Aug 07 06:22:58 PM PDT 24
Finished Aug 07 06:23:04 PM PDT 24
Peak memory 217288 kb
Host smart-4e073696-f932-4163-80f2-e831d6efbb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156025359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1156025359
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2820977944
Short name T163
Test name
Test status
Simulation time 246109094 ps
CPU time 1.04 seconds
Started Aug 07 06:22:54 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 217500 kb
Host smart-f27b025b-a82d-46ae-b81a-5883f9b70c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820977944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2820977944
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.4151257843
Short name T226
Test name
Test status
Simulation time 222940489 ps
CPU time 0.91 seconds
Started Aug 07 06:22:54 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 200156 kb
Host smart-06826d3e-81c7-48be-854f-98c10667777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151257843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.4151257843
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2225463759
Short name T349
Test name
Test status
Simulation time 867903632 ps
CPU time 4.45 seconds
Started Aug 07 06:22:53 PM PDT 24
Finished Aug 07 06:22:58 PM PDT 24
Peak memory 200548 kb
Host smart-0b13c586-e422-48d4-8188-eafa91358649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225463759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2225463759
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1091960449
Short name T149
Test name
Test status
Simulation time 113356977 ps
CPU time 0.99 seconds
Started Aug 07 06:22:54 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 200340 kb
Host smart-966b1ef0-fa17-491f-92ed-288b1bf9d475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091960449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1091960449
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4167400160
Short name T512
Test name
Test status
Simulation time 242943714 ps
CPU time 1.43 seconds
Started Aug 07 06:22:48 PM PDT 24
Finished Aug 07 06:22:49 PM PDT 24
Peak memory 200520 kb
Host smart-435101e3-82e7-462b-9afd-df86fc4ccb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167400160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4167400160
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1386663104
Short name T511
Test name
Test status
Simulation time 9232935500 ps
CPU time 37.07 seconds
Started Aug 07 06:22:55 PM PDT 24
Finished Aug 07 06:23:32 PM PDT 24
Peak memory 200596 kb
Host smart-109d84d5-4b30-4951-a0d9-7aba06ce3f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386663104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1386663104
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.788245735
Short name T9
Test name
Test status
Simulation time 450496479 ps
CPU time 2.4 seconds
Started Aug 07 06:22:55 PM PDT 24
Finished Aug 07 06:22:57 PM PDT 24
Peak memory 200312 kb
Host smart-6cf6d099-9d38-4ab1-86ff-9ae86a6b409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788245735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.788245735
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3292312442
Short name T339
Test name
Test status
Simulation time 185367845 ps
CPU time 1.21 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:57 PM PDT 24
Peak memory 200352 kb
Host smart-9530c9a8-c539-4990-bb6e-ffa099acae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292312442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3292312442
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1288972647
Short name T312
Test name
Test status
Simulation time 71824378 ps
CPU time 0.81 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:57 PM PDT 24
Peak memory 200196 kb
Host smart-e0c27f84-939b-40cd-839e-2787c2ed9b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288972647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1288972647
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1055323602
Short name T272
Test name
Test status
Simulation time 1900172202 ps
CPU time 7.65 seconds
Started Aug 07 06:22:55 PM PDT 24
Finished Aug 07 06:23:03 PM PDT 24
Peak memory 221700 kb
Host smart-a51e51b6-081c-4b97-a46f-855d82789e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055323602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1055323602
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.646089464
Short name T420
Test name
Test status
Simulation time 244194286 ps
CPU time 1.07 seconds
Started Aug 07 06:22:57 PM PDT 24
Finished Aug 07 06:22:58 PM PDT 24
Peak memory 217576 kb
Host smart-82e601a6-4d5b-477e-be26-9cbb2e38e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646089464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.646089464
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1863983645
Short name T20
Test name
Test status
Simulation time 196205789 ps
CPU time 0.9 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:57 PM PDT 24
Peak memory 200132 kb
Host smart-1cbea855-2533-464d-980f-ac30a43ba205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863983645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1863983645
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3410120667
Short name T514
Test name
Test status
Simulation time 1269326404 ps
CPU time 4.81 seconds
Started Aug 07 06:22:55 PM PDT 24
Finished Aug 07 06:23:00 PM PDT 24
Peak memory 200560 kb
Host smart-04e0a0fc-22fd-426e-87a7-b187c6ff2f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410120667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3410120667
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2460445811
Short name T221
Test name
Test status
Simulation time 161983772 ps
CPU time 1.18 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:57 PM PDT 24
Peak memory 200336 kb
Host smart-df86bb02-09a6-45dd-8a10-bc3b963a7044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460445811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2460445811
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.731241027
Short name T240
Test name
Test status
Simulation time 126401966 ps
CPU time 1.18 seconds
Started Aug 07 06:22:54 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 200416 kb
Host smart-689129f8-280e-4de8-b241-b65ca5305539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731241027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.731241027
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2568192365
Short name T102
Test name
Test status
Simulation time 10596952259 ps
CPU time 35.81 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:23:32 PM PDT 24
Peak memory 216916 kb
Host smart-97371113-0346-4cf8-b459-c078963730da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568192365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2568192365
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2795846254
Short name T507
Test name
Test status
Simulation time 288112159 ps
CPU time 2 seconds
Started Aug 07 06:22:55 PM PDT 24
Finished Aug 07 06:22:57 PM PDT 24
Peak memory 200184 kb
Host smart-d02b7066-407c-45d7-9c4a-4e2176a2501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795846254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2795846254
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2185640771
Short name T168
Test name
Test status
Simulation time 179538110 ps
CPU time 1.16 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:58 PM PDT 24
Peak memory 200360 kb
Host smart-510ca812-56b4-4a4c-ad55-6f0c1ea28175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185640771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2185640771
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.28934868
Short name T524
Test name
Test status
Simulation time 67658162 ps
CPU time 0.83 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:57 PM PDT 24
Peak memory 200200 kb
Host smart-55fbe0b3-3ee1-4006-b14b-1b65a7421cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28934868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.28934868
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3333241560
Short name T432
Test name
Test status
Simulation time 1895291208 ps
CPU time 7.87 seconds
Started Aug 07 06:22:54 PM PDT 24
Finished Aug 07 06:23:02 PM PDT 24
Peak memory 221752 kb
Host smart-64e3fa62-b53f-43c9-ab46-45effbd12401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333241560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3333241560
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1432215272
Short name T449
Test name
Test status
Simulation time 245709411 ps
CPU time 1.13 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:57 PM PDT 24
Peak memory 217524 kb
Host smart-c1580d79-815b-4f0b-a2db-5ab9142bcf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432215272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1432215272
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3806215243
Short name T461
Test name
Test status
Simulation time 206703449 ps
CPU time 0.9 seconds
Started Aug 07 06:22:58 PM PDT 24
Finished Aug 07 06:22:59 PM PDT 24
Peak memory 200156 kb
Host smart-951c1260-b0b0-45fc-ae5d-892f05d79ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806215243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3806215243
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.77965884
Short name T189
Test name
Test status
Simulation time 1433829219 ps
CPU time 6.13 seconds
Started Aug 07 06:22:55 PM PDT 24
Finished Aug 07 06:23:01 PM PDT 24
Peak memory 200576 kb
Host smart-5c22c37b-fc81-4e5b-8fbb-dfd4af4602fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77965884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.77965884
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1980870184
Short name T385
Test name
Test status
Simulation time 176868600 ps
CPU time 1.26 seconds
Started Aug 07 06:22:53 PM PDT 24
Finished Aug 07 06:22:55 PM PDT 24
Peak memory 200388 kb
Host smart-55801603-6c9f-4f31-943c-b87c4c172a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980870184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.1980870184
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.4084197967
Short name T253
Test name
Test status
Simulation time 230818837 ps
CPU time 1.57 seconds
Started Aug 07 06:22:57 PM PDT 24
Finished Aug 07 06:22:59 PM PDT 24
Peak memory 200464 kb
Host smart-644ec80f-7051-40d8-b162-ab66e7830154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084197967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4084197967
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2977934421
Short name T228
Test name
Test status
Simulation time 374158347 ps
CPU time 2.4 seconds
Started Aug 07 06:22:56 PM PDT 24
Finished Aug 07 06:22:58 PM PDT 24
Peak memory 200292 kb
Host smart-19502b8f-56b5-41aa-a5ee-788bbe78d9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977934421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2977934421
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.426812255
Short name T292
Test name
Test status
Simulation time 131695445 ps
CPU time 0.99 seconds
Started Aug 07 06:22:55 PM PDT 24
Finished Aug 07 06:22:56 PM PDT 24
Peak memory 200348 kb
Host smart-c908d4d6-8644-4fa4-a212-64691b583be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426812255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.426812255
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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