Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8614

1

T3

5

T4

81

T11

40

auto[1]

11477

1

T1

4

T3

1

T4

51

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6129	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6862	1			T1	2		T2	1		T3	1
reset_info_cp[2]	3119	1			T1	1		T4	21		T5	1
reset_info_cp[4]	4066	1			T1	1		T4	32		T5	1
reset_info_cp[8]	91	1			T16	2		T28	1		T57	1
reset_info_cp[16]	115	1			T4	1		T16	3		T32	2
reset_info_cp[32]	113	1			T3	1		T32	1		T93	1
reset_info_cp[64]	109	1			T11	1		T16	2		T57	1
reset_info_cp[128]	107	1			T16	2		T93	2		T136	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3298	1			T4	28		T11	15		T16	21
reset_info_cp[1]	auto[1]	2944	1			T1	1		T4	17		T5	1
reset_info_cp[2]	auto[0]	985	1			T4	10		T11	4		T16	8
reset_info_cp[2]	auto[1]	2134	1			T1	1		T4	11		T5	1
reset_info_cp[4]	auto[0]	1477	1			T4	18		T11	9		T16	20
reset_info_cp[4]	auto[1]	2589	1			T1	1		T4	14		T5	1
reset_info_cp[8]	auto[0]	39	1			T16	1		T57	1		T46	1
reset_info_cp[8]	auto[1]	52	1			T16	1		T28	1		T49	1
reset_info_cp[16]	auto[0]	38	1			T4	1		T57	1		T138	1
reset_info_cp[16]	auto[1]	77	1			T16	3		T32	2		T93	1
reset_info_cp[32]	auto[0]	39	1			T3	1		T93	1		T137	1
reset_info_cp[32]	auto[1]	74	1			T32	1		T49	1		T34	1
reset_info_cp[64]	auto[0]	53	1			T16	1		T57	1		T136	2
reset_info_cp[64]	auto[1]	56	1			T11	1		T16	1		T66	1
reset_info_cp[128]	auto[0]	42	1			T93	1		T66	1		T139	1
reset_info_cp[128]	auto[1]	65	1			T16	2		T93	1		T136	1