Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T537 /workspace/coverage/default/2.rstmgr_smoke.628586990 Aug 08 06:04:35 PM PDT 24 Aug 08 06:04:37 PM PDT 24 114288083 ps
T538 /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2203834344 Aug 08 06:05:05 PM PDT 24 Aug 08 06:05:06 PM PDT 24 62457012 ps
T539 /workspace/coverage/default/31.rstmgr_stress_all.2044337092 Aug 08 06:05:10 PM PDT 24 Aug 08 06:05:12 PM PDT 24 240529890 ps
T540 /workspace/coverage/default/9.rstmgr_alert_test.3145347480 Aug 08 06:04:50 PM PDT 24 Aug 08 06:04:52 PM PDT 24 79828975 ps
T541 /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3591950772 Aug 08 06:05:00 PM PDT 24 Aug 08 06:05:01 PM PDT 24 106898994 ps
T69 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.783847967 Aug 08 07:39:05 PM PDT 24 Aug 08 07:39:07 PM PDT 24 428820273 ps
T70 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1562661876 Aug 08 07:39:04 PM PDT 24 Aug 08 07:39:05 PM PDT 24 112816710 ps
T71 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.236152946 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:19 PM PDT 24 69775504 ps
T105 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1982209875 Aug 08 07:39:21 PM PDT 24 Aug 08 07:39:22 PM PDT 24 161207026 ps
T72 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3912951090 Aug 08 07:39:30 PM PDT 24 Aug 08 07:39:33 PM PDT 24 936616563 ps
T73 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.302528574 Aug 08 07:39:21 PM PDT 24 Aug 08 07:39:22 PM PDT 24 143189859 ps
T74 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.862038877 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:20 PM PDT 24 227075986 ps
T106 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1193931316 Aug 08 07:39:28 PM PDT 24 Aug 08 07:39:30 PM PDT 24 275662499 ps
T107 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2924896106 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:19 PM PDT 24 60239381 ps
T75 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.128849726 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:18 PM PDT 24 177481687 ps
T84 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1342319649 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:21 PM PDT 24 137621822 ps
T85 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1730950830 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:20 PM PDT 24 191738857 ps
T108 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3270213302 Aug 08 07:39:28 PM PDT 24 Aug 08 07:39:30 PM PDT 24 204077978 ps
T542 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2759364708 Aug 08 07:39:02 PM PDT 24 Aug 08 07:39:03 PM PDT 24 105787232 ps
T135 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.771426686 Aug 08 07:39:02 PM PDT 24 Aug 08 07:39:08 PM PDT 24 1178790061 ps
T86 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2257600936 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:17 PM PDT 24 187153028 ps
T91 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1477739790 Aug 08 07:39:04 PM PDT 24 Aug 08 07:39:07 PM PDT 24 771338386 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.634092792 Aug 08 07:39:02 PM PDT 24 Aug 08 07:39:03 PM PDT 24 75411416 ps
T87 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3952588864 Aug 08 07:39:29 PM PDT 24 Aug 08 07:39:32 PM PDT 24 792124046 ps
T88 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1783644459 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:21 PM PDT 24 355445042 ps
T89 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1654601504 Aug 08 07:39:14 PM PDT 24 Aug 08 07:39:19 PM PDT 24 709991365 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.487317898 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:04 PM PDT 24 215152999 ps
T92 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1362620908 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:21 PM PDT 24 880828482 ps
T109 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1578198090 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:16 PM PDT 24 91455156 ps
T90 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.822031997 Aug 08 07:39:17 PM PDT 24 Aug 08 07:39:19 PM PDT 24 481159326 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2166184125 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:04 PM PDT 24 98079961 ps
T110 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2641392973 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:21 PM PDT 24 127114435 ps
T113 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1995307307 Aug 08 07:39:17 PM PDT 24 Aug 08 07:39:20 PM PDT 24 420238122 ps
T114 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.163946615 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:18 PM PDT 24 177956301 ps
T546 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.75102081 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:17 PM PDT 24 95953326 ps
T547 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3516447502 Aug 08 07:39:31 PM PDT 24 Aug 08 07:39:32 PM PDT 24 138232866 ps
T111 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1903402622 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:17 PM PDT 24 69815955 ps
T548 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2242490946 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:17 PM PDT 24 426946817 ps
T120 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.465381096 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:22 PM PDT 24 241865994 ps
T112 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.882510839 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:05 PM PDT 24 137650711 ps
T121 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2133996012 Aug 08 07:39:02 PM PDT 24 Aug 08 07:39:06 PM PDT 24 437614977 ps
T549 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2791802116 Aug 08 07:39:17 PM PDT 24 Aug 08 07:39:21 PM PDT 24 395246994 ps
T550 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3862424650 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:19 PM PDT 24 136068081 ps
T551 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.129038780 Aug 08 07:39:21 PM PDT 24 Aug 08 07:39:25 PM PDT 24 442994564 ps
T552 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3544635984 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:17 PM PDT 24 127657189 ps
T553 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2300546575 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:11 PM PDT 24 1552666076 ps
T554 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1555690131 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:21 PM PDT 24 801337943 ps
T555 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.211099967 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:21 PM PDT 24 147832053 ps
T556 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3448516806 Aug 08 07:39:02 PM PDT 24 Aug 08 07:39:04 PM PDT 24 104952594 ps
T557 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4142138110 Aug 08 07:39:29 PM PDT 24 Aug 08 07:39:31 PM PDT 24 126909458 ps
T558 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2440115721 Aug 08 07:39:29 PM PDT 24 Aug 08 07:39:30 PM PDT 24 77653896 ps
T559 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1076887760 Aug 08 07:39:20 PM PDT 24 Aug 08 07:39:21 PM PDT 24 86528736 ps
T560 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1836150655 Aug 08 07:39:17 PM PDT 24 Aug 08 07:39:18 PM PDT 24 145078441 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2839105935 Aug 08 07:39:04 PM PDT 24 Aug 08 07:39:14 PM PDT 24 2297507618 ps
T562 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.234024223 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:21 PM PDT 24 317023769 ps
T563 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2986183339 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:18 PM PDT 24 414951248 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3022332721 Aug 08 07:39:22 PM PDT 24 Aug 08 07:39:23 PM PDT 24 57313534 ps
T565 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1841393128 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:05 PM PDT 24 268581035 ps
T119 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2894330477 Aug 08 07:39:02 PM PDT 24 Aug 08 07:39:06 PM PDT 24 964083223 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.897112912 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:16 PM PDT 24 69204467 ps
T567 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.67261417 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:04 PM PDT 24 172651512 ps
T568 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2469331767 Aug 08 07:39:28 PM PDT 24 Aug 08 07:39:31 PM PDT 24 373077197 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.120900486 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:16 PM PDT 24 112498828 ps
T570 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.159838077 Aug 08 07:39:29 PM PDT 24 Aug 08 07:39:31 PM PDT 24 126285859 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1352494618 Aug 08 07:39:14 PM PDT 24 Aug 08 07:39:15 PM PDT 24 94859628 ps
T572 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.292138564 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:18 PM PDT 24 128622109 ps
T573 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4095153200 Aug 08 07:39:17 PM PDT 24 Aug 08 07:39:18 PM PDT 24 54232140 ps
T574 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4202571204 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:20 PM PDT 24 232458462 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2147312311 Aug 08 07:39:04 PM PDT 24 Aug 08 07:39:06 PM PDT 24 104579235 ps
T576 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3891216929 Aug 08 07:39:30 PM PDT 24 Aug 08 07:39:33 PM PDT 24 137614456 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1416725019 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:16 PM PDT 24 67789160 ps
T578 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3183898965 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:04 PM PDT 24 78855758 ps
T579 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3640615814 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:20 PM PDT 24 492316715 ps
T580 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2756153130 Aug 08 07:39:30 PM PDT 24 Aug 08 07:39:31 PM PDT 24 72065436 ps
T581 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2531417935 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:17 PM PDT 24 108205677 ps
T582 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3860245906 Aug 08 07:39:28 PM PDT 24 Aug 08 07:39:30 PM PDT 24 498289683 ps
T583 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1460335183 Aug 08 07:39:28 PM PDT 24 Aug 08 07:39:29 PM PDT 24 78407554 ps
T584 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4175733362 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:19 PM PDT 24 104939674 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.7337702 Aug 08 07:39:05 PM PDT 24 Aug 08 07:39:06 PM PDT 24 129290906 ps
T586 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1684837565 Aug 08 07:39:22 PM PDT 24 Aug 08 07:39:24 PM PDT 24 236609253 ps
T587 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3542424489 Aug 08 07:39:21 PM PDT 24 Aug 08 07:39:23 PM PDT 24 466739178 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3486887904 Aug 08 07:39:04 PM PDT 24 Aug 08 07:39:08 PM PDT 24 478989956 ps
T117 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.331983956 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:18 PM PDT 24 930288661 ps
T118 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.935067993 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:18 PM PDT 24 823282616 ps
T589 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.283451364 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:17 PM PDT 24 75197186 ps
T590 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2945586489 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:19 PM PDT 24 86119168 ps
T591 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3651074919 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:21 PM PDT 24 215456873 ps
T592 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1948526285 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:20 PM PDT 24 124570563 ps
T593 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3584463372 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:20 PM PDT 24 193365322 ps
T594 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3504469118 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:20 PM PDT 24 152282049 ps
T595 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2350171234 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:04 PM PDT 24 124619951 ps
T134 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3009519924 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:23 PM PDT 24 941579593 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2371433715 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:20 PM PDT 24 212240901 ps
T597 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1746458525 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:17 PM PDT 24 247870052 ps
T96 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2812192452 Aug 08 07:39:04 PM PDT 24 Aug 08 07:39:05 PM PDT 24 81564758 ps
T598 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3989301350 Aug 08 07:39:31 PM PDT 24 Aug 08 07:39:32 PM PDT 24 114980617 ps
T599 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1563644197 Aug 08 07:39:04 PM PDT 24 Aug 08 07:39:06 PM PDT 24 256485937 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3859042932 Aug 08 07:39:17 PM PDT 24 Aug 08 07:39:20 PM PDT 24 264948516 ps
T601 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1567825352 Aug 08 07:39:17 PM PDT 24 Aug 08 07:39:19 PM PDT 24 485584909 ps
T602 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3448001206 Aug 08 07:39:03 PM PDT 24 Aug 08 07:39:06 PM PDT 24 433122741 ps
T603 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4228958132 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:19 PM PDT 24 114452270 ps
T604 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.324673991 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:16 PM PDT 24 278196918 ps
T115 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3112987381 Aug 08 07:39:04 PM PDT 24 Aug 08 07:39:07 PM PDT 24 940002829 ps
T605 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.573161685 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:20 PM PDT 24 94791154 ps
T606 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.386414184 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:19 PM PDT 24 129814374 ps
T116 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.936462202 Aug 08 07:39:15 PM PDT 24 Aug 08 07:39:17 PM PDT 24 425074913 ps
T607 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2915352633 Aug 08 07:39:20 PM PDT 24 Aug 08 07:39:22 PM PDT 24 226612070 ps
T608 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2368303541 Aug 08 07:39:18 PM PDT 24 Aug 08 07:39:19 PM PDT 24 73455977 ps
T609 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.578951444 Aug 08 07:39:29 PM PDT 24 Aug 08 07:39:30 PM PDT 24 116665491 ps
T610 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4273546137 Aug 08 07:39:19 PM PDT 24 Aug 08 07:39:20 PM PDT 24 75248690 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1340971440 Aug 08 07:39:22 PM PDT 24 Aug 08 07:39:24 PM PDT 24 481782681 ps
T612 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2688774862 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:17 PM PDT 24 134188810 ps
T613 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2846874435 Aug 08 07:39:30 PM PDT 24 Aug 08 07:39:34 PM PDT 24 678944009 ps
T614 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.784452985 Aug 08 07:39:05 PM PDT 24 Aug 08 07:39:06 PM PDT 24 107355342 ps
T615 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3884012583 Aug 08 07:39:16 PM PDT 24 Aug 08 07:39:21 PM PDT 24 670501685 ps
T616 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1027782798 Aug 08 07:39:22 PM PDT 24 Aug 08 07:39:24 PM PDT 24 485541897 ps
T617 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.546281757 Aug 08 07:39:17 PM PDT 24 Aug 08 07:39:18 PM PDT 24 75070295 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.840204238 Aug 08 07:39:05 PM PDT 24 Aug 08 07:39:06 PM PDT 24 106530220 ps
T619 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.322454368 Aug 08 07:39:21 PM PDT 24 Aug 08 07:39:22 PM PDT 24 65690199 ps
T620 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2971017128 Aug 08 07:39:31 PM PDT 24 Aug 08 07:39:32 PM PDT 24 120192220 ps

Test location /workspace/coverage/default/34.rstmgr_stress_all.470901258
Short name T4
Test name
Test status
Simulation time 3869218609 ps
CPU time 14.19 seconds
Started Aug 08 06:05:18 PM PDT 24
Finished Aug 08 06:05:32 PM PDT 24
Peak memory 200572 kb
Host smart-8cd996a0-73ae-4782-9a0c-aafe9c7171bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470901258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.470901258
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3461021897
Short name T13
Test name
Test status
Simulation time 125039945 ps
CPU time 1.54 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 208468 kb
Host smart-0a95fa64-9bf8-404d-8ec6-9da679a31df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461021897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3461021897
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.128849726
Short name T75
Test name
Test status
Simulation time 177481687 ps
CPU time 1.74 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 208492 kb
Host smart-99e9aade-9837-4ea5-9b28-ae0f842b70a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128849726 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.128849726
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.4261650036
Short name T8
Test name
Test status
Simulation time 8331507672 ps
CPU time 13.13 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 217184 kb
Host smart-bf49cf05-68f1-465e-b685-4751ffbb2f13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261650036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.4261650036
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.43856841
Short name T16
Test name
Test status
Simulation time 5815371658 ps
CPU time 19.68 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:20 PM PDT 24
Peak memory 208892 kb
Host smart-448375b6-3631-4214-8303-a481097b720b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43856841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.43856841
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.796598384
Short name T32
Test name
Test status
Simulation time 2189165486 ps
CPU time 7.59 seconds
Started Aug 08 06:05:51 PM PDT 24
Finished Aug 08 06:05:59 PM PDT 24
Peak memory 217932 kb
Host smart-974fb9d2-0db4-4780-88d4-cb71f8f7ea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796598384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.796598384
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3912951090
Short name T72
Test name
Test status
Simulation time 936616563 ps
CPU time 3.06 seconds
Started Aug 08 07:39:30 PM PDT 24
Finished Aug 08 07:39:33 PM PDT 24
Peak memory 200220 kb
Host smart-26039857-8a6f-480a-901c-b33f2a328787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912951090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3912951090
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2133996012
Short name T121
Test name
Test status
Simulation time 437614977 ps
CPU time 3.21 seconds
Started Aug 08 07:39:02 PM PDT 24
Finished Aug 08 07:39:06 PM PDT 24
Peak memory 208456 kb
Host smart-432348b9-141b-4761-a5d7-6ed89e87a3f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133996012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2133996012
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3914433095
Short name T63
Test name
Test status
Simulation time 108694848 ps
CPU time 1.02 seconds
Started Aug 08 06:05:02 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200356 kb
Host smart-165c4d94-ac3c-47a4-af37-fa36e179b269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914433095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3914433095
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3266479501
Short name T101
Test name
Test status
Simulation time 8084631612 ps
CPU time 29.29 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:30 PM PDT 24
Peak memory 208776 kb
Host smart-284581b4-977d-4dc4-81c6-30ba41abe6b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266479501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3266479501
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1145313045
Short name T42
Test name
Test status
Simulation time 2351342030 ps
CPU time 8.65 seconds
Started Aug 08 06:05:08 PM PDT 24
Finished Aug 08 06:05:17 PM PDT 24
Peak memory 217896 kb
Host smart-4e3a014a-642f-4c26-9aef-6ef64f0c3da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145313045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1145313045
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1481404053
Short name T163
Test name
Test status
Simulation time 81021550 ps
CPU time 0.89 seconds
Started Aug 08 06:04:22 PM PDT 24
Finished Aug 08 06:04:23 PM PDT 24
Peak memory 200156 kb
Host smart-e3c45b2d-8f0e-4bc7-9174-059dd58d7851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481404053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1481404053
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3193810883
Short name T57
Test name
Test status
Simulation time 171995791 ps
CPU time 1.12 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 200360 kb
Host smart-8fd2479e-df0c-4292-9cc8-7be68382a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193810883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3193810883
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3952588864
Short name T87
Test name
Test status
Simulation time 792124046 ps
CPU time 2.91 seconds
Started Aug 08 07:39:29 PM PDT 24
Finished Aug 08 07:39:32 PM PDT 24
Peak memory 200180 kb
Host smart-bedc06ee-e653-4593-8e99-ba459e51ff84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952588864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3952588864
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.298605174
Short name T41
Test name
Test status
Simulation time 1880418541 ps
CPU time 7.15 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 221640 kb
Host smart-e2c8b4b3-6e8e-4f83-b644-1db3c2b84711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298605174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.298605174
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1562661876
Short name T70
Test name
Test status
Simulation time 112816710 ps
CPU time 1.02 seconds
Started Aug 08 07:39:04 PM PDT 24
Finished Aug 08 07:39:05 PM PDT 24
Peak memory 200168 kb
Host smart-b183e198-f217-4b80-84bf-ed7e9f804a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562661876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1562661876
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1530254848
Short name T24
Test name
Test status
Simulation time 157939509 ps
CPU time 0.86 seconds
Started Aug 08 06:04:27 PM PDT 24
Finished Aug 08 06:04:33 PM PDT 24
Peak memory 200144 kb
Host smart-72a7617d-62df-4d67-bbbc-6d1f95af7502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530254848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1530254848
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.331983956
Short name T117
Test name
Test status
Simulation time 930288661 ps
CPU time 3.18 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 200240 kb
Host smart-2c183e75-bf1d-498a-b5ee-0da901d74fef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331983956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.331983956
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3112987381
Short name T115
Test name
Test status
Simulation time 940002829 ps
CPU time 3.04 seconds
Started Aug 08 07:39:04 PM PDT 24
Finished Aug 08 07:39:07 PM PDT 24
Peak memory 200240 kb
Host smart-650d2096-bcb3-408c-9d83-133839fcb721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112987381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3112987381
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1959547208
Short name T300
Test name
Test status
Simulation time 118577361 ps
CPU time 1.48 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 200244 kb
Host smart-fa6c75e0-25e9-41bf-b384-c86965d1cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959547208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1959547208
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.487317898
Short name T544
Test name
Test status
Simulation time 215152999 ps
CPU time 1.57 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:04 PM PDT 24
Peak memory 200184 kb
Host smart-50cf2831-93e1-4ec5-a200-67d84c2f2f70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487317898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.487317898
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2839105935
Short name T561
Test name
Test status
Simulation time 2297507618 ps
CPU time 9.79 seconds
Started Aug 08 07:39:04 PM PDT 24
Finished Aug 08 07:39:14 PM PDT 24
Peak memory 216544 kb
Host smart-471257b4-50a4-47fc-991c-7e830ea6510b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839105935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
839105935
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.784452985
Short name T614
Test name
Test status
Simulation time 107355342 ps
CPU time 0.92 seconds
Started Aug 08 07:39:05 PM PDT 24
Finished Aug 08 07:39:06 PM PDT 24
Peak memory 200044 kb
Host smart-b5c8ff80-4cea-409f-b7e8-4e6ceb1e10c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784452985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.784452985
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.840204238
Short name T618
Test name
Test status
Simulation time 106530220 ps
CPU time 0.96 seconds
Started Aug 08 07:39:05 PM PDT 24
Finished Aug 08 07:39:06 PM PDT 24
Peak memory 200120 kb
Host smart-37b30e0d-ed03-47bc-a2c3-5e3b4ea5e24a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840204238 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.840204238
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.3183898965
Short name T578
Test name
Test status
Simulation time 78855758 ps
CPU time 0.89 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:04 PM PDT 24
Peak memory 200072 kb
Host smart-7a37fd2e-5fdd-4a67-830b-8407b095a5d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183898965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3183898965
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1563644197
Short name T599
Test name
Test status
Simulation time 256485937 ps
CPU time 1.63 seconds
Started Aug 08 07:39:04 PM PDT 24
Finished Aug 08 07:39:06 PM PDT 24
Peak memory 200188 kb
Host smart-58d1cade-e163-4429-9bcf-f0ed4063b914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563644197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1563644197
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2894330477
Short name T119
Test name
Test status
Simulation time 964083223 ps
CPU time 3.24 seconds
Started Aug 08 07:39:02 PM PDT 24
Finished Aug 08 07:39:06 PM PDT 24
Peak memory 200164 kb
Host smart-6aa2d414-7d40-48e7-b756-0679c7385f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894330477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2894330477
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2147312311
Short name T575
Test name
Test status
Simulation time 104579235 ps
CPU time 1.31 seconds
Started Aug 08 07:39:04 PM PDT 24
Finished Aug 08 07:39:06 PM PDT 24
Peak memory 200116 kb
Host smart-3ec789a5-91db-4730-b314-ea8df28f0e08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147312311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
147312311
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2300546575
Short name T553
Test name
Test status
Simulation time 1552666076 ps
CPU time 8.36 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:11 PM PDT 24
Peak memory 200136 kb
Host smart-7e5f0b0a-777a-4b3a-9a69-ffbf465f7dd1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300546575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
300546575
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2166184125
Short name T545
Test name
Test status
Simulation time 98079961 ps
CPU time 0.85 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:04 PM PDT 24
Peak memory 200096 kb
Host smart-0bfa8136-c479-458a-8873-30693e2b86af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166184125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
166184125
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.7337702
Short name T585
Test name
Test status
Simulation time 129290906 ps
CPU time 1.1 seconds
Started Aug 08 07:39:05 PM PDT 24
Finished Aug 08 07:39:06 PM PDT 24
Peak memory 200192 kb
Host smart-6e4dacb3-feef-4e89-ae60-489db67d39d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7337702 -assert nopostproc +UVM_TESTNAME=rs
tmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.7337702
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.634092792
Short name T543
Test name
Test status
Simulation time 75411416 ps
CPU time 0.86 seconds
Started Aug 08 07:39:02 PM PDT 24
Finished Aug 08 07:39:03 PM PDT 24
Peak memory 200088 kb
Host smart-8e7b3ffe-376b-4809-8502-2e42d86dbda0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634092792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.634092792
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3486887904
Short name T588
Test name
Test status
Simulation time 478989956 ps
CPU time 3.34 seconds
Started Aug 08 07:39:04 PM PDT 24
Finished Aug 08 07:39:08 PM PDT 24
Peak memory 208356 kb
Host smart-c7c3449d-50e5-493c-a29a-659e4be72e42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486887904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3486887904
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.783847967
Short name T69
Test name
Test status
Simulation time 428820273 ps
CPU time 2 seconds
Started Aug 08 07:39:05 PM PDT 24
Finished Aug 08 07:39:07 PM PDT 24
Peak memory 200212 kb
Host smart-136e55de-6edb-49ae-80dc-03ac0dd48674
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783847967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
783847967
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3544635984
Short name T552
Test name
Test status
Simulation time 127657189 ps
CPU time 0.96 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200220 kb
Host smart-1f182af4-6921-4bb1-8b75-5c3248dc498b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544635984 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3544635984
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2945586489
Short name T590
Test name
Test status
Simulation time 86119168 ps
CPU time 0.89 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 200084 kb
Host smart-64aa48ab-01f8-4d77-8afe-040ecfc42642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945586489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2945586489
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1684837565
Short name T586
Test name
Test status
Simulation time 236609253 ps
CPU time 1.64 seconds
Started Aug 08 07:39:22 PM PDT 24
Finished Aug 08 07:39:24 PM PDT 24
Peak memory 200008 kb
Host smart-198c587a-d2d4-455e-8f95-ffd2e4fc978a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684837565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1684837565
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3884012583
Short name T615
Test name
Test status
Simulation time 670501685 ps
CPU time 4.59 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 208396 kb
Host smart-a888abcc-02e2-4ed6-af0b-2e67352b5db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884012583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3884012583
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.936462202
Short name T116
Test name
Test status
Simulation time 425074913 ps
CPU time 1.78 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200268 kb
Host smart-eb610ea3-4e78-4b8a-9f47-e10c0defebb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936462202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.936462202
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3862424650
Short name T550
Test name
Test status
Simulation time 136068081 ps
CPU time 1.05 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 208424 kb
Host smart-b6edc1cc-6889-4671-b314-5d67dd519544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862424650 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3862424650
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2924896106
Short name T107
Test name
Test status
Simulation time 60239381 ps
CPU time 0.83 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 200056 kb
Host smart-bc67fe6c-e390-46b9-9f78-2ea3403c5b9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924896106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2924896106
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.324673991
Short name T604
Test name
Test status
Simulation time 278196918 ps
CPU time 1.57 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:16 PM PDT 24
Peak memory 200240 kb
Host smart-b21acc15-3800-447a-a7c4-1d453ad79cf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324673991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.324673991
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.1995307307
Short name T113
Test name
Test status
Simulation time 420238122 ps
CPU time 3.14 seconds
Started Aug 08 07:39:17 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 216444 kb
Host smart-9030cc6c-e925-45a8-ac71-2b2632fce4dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995307307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1995307307
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1567825352
Short name T601
Test name
Test status
Simulation time 485584909 ps
CPU time 1.94 seconds
Started Aug 08 07:39:17 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 200292 kb
Host smart-172b345b-4c96-4bb5-8933-db6e28d50b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567825352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1567825352
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1836150655
Short name T560
Test name
Test status
Simulation time 145078441 ps
CPU time 1.14 seconds
Started Aug 08 07:39:17 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 208400 kb
Host smart-3081f870-7c3d-48c7-9d4c-92e5a88c6da3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836150655 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1836150655
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1903402622
Short name T111
Test name
Test status
Simulation time 69815955 ps
CPU time 0.82 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200136 kb
Host smart-9f582b61-3974-4c75-87d0-e2e2f87fdf32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903402622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1903402622
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2688774862
Short name T612
Test name
Test status
Simulation time 134188810 ps
CPU time 1.36 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200268 kb
Host smart-69021456-9eac-4cb3-84c7-1a235fba5499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688774862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2688774862
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.129038780
Short name T551
Test name
Test status
Simulation time 442994564 ps
CPU time 3.28 seconds
Started Aug 08 07:39:21 PM PDT 24
Finished Aug 08 07:39:25 PM PDT 24
Peak memory 208328 kb
Host smart-06630341-b8a5-4b3b-999b-60f913393467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129038780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.129038780
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1027782798
Short name T616
Test name
Test status
Simulation time 485541897 ps
CPU time 2.01 seconds
Started Aug 08 07:39:22 PM PDT 24
Finished Aug 08 07:39:24 PM PDT 24
Peak memory 199976 kb
Host smart-baa19d84-465f-4643-8120-d9d0f594c276
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027782798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1027782798
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4228958132
Short name T603
Test name
Test status
Simulation time 114452270 ps
CPU time 0.93 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 200224 kb
Host smart-7f90cb96-d017-4712-aa54-e4928eab336a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228958132 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4228958132
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.546281757
Short name T617
Test name
Test status
Simulation time 75070295 ps
CPU time 0.78 seconds
Started Aug 08 07:39:17 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 200036 kb
Host smart-67bd2571-723d-4ce1-985b-fa4138cac3a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546281757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.546281757
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1948526285
Short name T592
Test name
Test status
Simulation time 124570563 ps
CPU time 1.07 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 200064 kb
Host smart-f490f361-8182-4386-9961-c84598303122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948526285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1948526285
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.465381096
Short name T120
Test name
Test status
Simulation time 241865994 ps
CPU time 3.39 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:22 PM PDT 24
Peak memory 212076 kb
Host smart-cc161922-02a7-4067-95f2-5366026ba626
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465381096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.465381096
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1342319649
Short name T84
Test name
Test status
Simulation time 137621822 ps
CPU time 1.06 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 208340 kb
Host smart-a7d01b3d-77af-4322-b56a-1a0d7224c7ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342319649 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1342319649
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.283451364
Short name T589
Test name
Test status
Simulation time 75197186 ps
CPU time 0.88 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200084 kb
Host smart-719c2139-f59d-4137-b1c5-7fd1e5c56de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283451364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.283451364
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1746458525
Short name T597
Test name
Test status
Simulation time 247870052 ps
CPU time 1.54 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200312 kb
Host smart-3baf148a-371c-4827-af37-3951f8278568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746458525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1746458525
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.163946615
Short name T114
Test name
Test status
Simulation time 177956301 ps
CPU time 2.32 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 216244 kb
Host smart-c7a02d14-dbf7-4bb8-b58d-dd9a6b70156e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163946615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.163946615
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1362620908
Short name T92
Test name
Test status
Simulation time 880828482 ps
CPU time 3.13 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 200192 kb
Host smart-54193689-049f-4e4a-9f2e-eacd4c0d18a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362620908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1362620908
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3584463372
Short name T593
Test name
Test status
Simulation time 193365322 ps
CPU time 1.92 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 208536 kb
Host smart-62a55fc5-32f3-4468-89c7-c8c9d14439a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584463372 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3584463372
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.4095153200
Short name T573
Test name
Test status
Simulation time 54232140 ps
CPU time 0.75 seconds
Started Aug 08 07:39:17 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 200012 kb
Host smart-2f9e8f73-c938-4d44-a849-da32ceef86f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095153200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.4095153200
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2641392973
Short name T110
Test name
Test status
Simulation time 127114435 ps
CPU time 1.16 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 200100 kb
Host smart-f65b5cb2-59f4-4ea2-82b1-ea7dcddc5d05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641392973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2641392973
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.234024223
Short name T562
Test name
Test status
Simulation time 317023769 ps
CPU time 2.47 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 216456 kb
Host smart-e7979ec6-d2f6-4548-bd3b-489cf56a8219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234024223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.234024223
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3009519924
Short name T134
Test name
Test status
Simulation time 941579593 ps
CPU time 3.9 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:23 PM PDT 24
Peak memory 200252 kb
Host smart-57994fbc-805c-4eaf-a226-c10ebc955d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009519924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3009519924
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.578951444
Short name T609
Test name
Test status
Simulation time 116665491 ps
CPU time 0.92 seconds
Started Aug 08 07:39:29 PM PDT 24
Finished Aug 08 07:39:30 PM PDT 24
Peak memory 200212 kb
Host smart-38f53753-697b-4118-a510-43cbb803083a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578951444 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.578951444
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.322454368
Short name T619
Test name
Test status
Simulation time 65690199 ps
CPU time 0.84 seconds
Started Aug 08 07:39:21 PM PDT 24
Finished Aug 08 07:39:22 PM PDT 24
Peak memory 200084 kb
Host smart-85ad33c8-77e1-41b3-a2c6-6353af33a839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322454368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.322454368
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.159838077
Short name T570
Test name
Test status
Simulation time 126285859 ps
CPU time 1.08 seconds
Started Aug 08 07:39:29 PM PDT 24
Finished Aug 08 07:39:31 PM PDT 24
Peak memory 200136 kb
Host smart-bae554f4-2ff9-4005-a0cf-6d0c61668d6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159838077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.159838077
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3651074919
Short name T591
Test name
Test status
Simulation time 215456873 ps
CPU time 1.97 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 210468 kb
Host smart-d7806738-7061-4f1c-888a-7160eb39761b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651074919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3651074919
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3640615814
Short name T579
Test name
Test status
Simulation time 492316715 ps
CPU time 1.96 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 200204 kb
Host smart-68693159-86d6-4d50-8938-f5a7e4bf013b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640615814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3640615814
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3516447502
Short name T547
Test name
Test status
Simulation time 138232866 ps
CPU time 1.09 seconds
Started Aug 08 07:39:31 PM PDT 24
Finished Aug 08 07:39:32 PM PDT 24
Peak memory 208328 kb
Host smart-941e2335-1434-4351-bd7c-5bd9667c7c33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516447502 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3516447502
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2756153130
Short name T580
Test name
Test status
Simulation time 72065436 ps
CPU time 0.8 seconds
Started Aug 08 07:39:30 PM PDT 24
Finished Aug 08 07:39:31 PM PDT 24
Peak memory 199996 kb
Host smart-dc765750-e689-483a-b55c-f332a30f0677
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756153130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2756153130
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3270213302
Short name T108
Test name
Test status
Simulation time 204077978 ps
CPU time 1.35 seconds
Started Aug 08 07:39:28 PM PDT 24
Finished Aug 08 07:39:30 PM PDT 24
Peak memory 200256 kb
Host smart-93544064-1b9f-4066-be6a-30472da72ca2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270213302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3270213302
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2469331767
Short name T568
Test name
Test status
Simulation time 373077197 ps
CPU time 2.76 seconds
Started Aug 08 07:39:28 PM PDT 24
Finished Aug 08 07:39:31 PM PDT 24
Peak memory 208332 kb
Host smart-63ad12f0-f02d-475d-b5b3-394834993a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469331767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2469331767
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3989301350
Short name T598
Test name
Test status
Simulation time 114980617 ps
CPU time 0.98 seconds
Started Aug 08 07:39:31 PM PDT 24
Finished Aug 08 07:39:32 PM PDT 24
Peak memory 200128 kb
Host smart-70d09cfe-e6b8-4419-a680-47a75b6bf101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989301350 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3989301350
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1460335183
Short name T583
Test name
Test status
Simulation time 78407554 ps
CPU time 0.81 seconds
Started Aug 08 07:39:28 PM PDT 24
Finished Aug 08 07:39:29 PM PDT 24
Peak memory 200064 kb
Host smart-c478b91c-c6bf-4edc-96f4-8cba548b1ea5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460335183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1460335183
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1193931316
Short name T106
Test name
Test status
Simulation time 275662499 ps
CPU time 1.58 seconds
Started Aug 08 07:39:28 PM PDT 24
Finished Aug 08 07:39:30 PM PDT 24
Peak memory 200268 kb
Host smart-8cae7c64-56fb-4f54-8b9d-4a430b25ffbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193931316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1193931316
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.2846874435
Short name T613
Test name
Test status
Simulation time 678944009 ps
CPU time 4.17 seconds
Started Aug 08 07:39:30 PM PDT 24
Finished Aug 08 07:39:34 PM PDT 24
Peak memory 208316 kb
Host smart-94addecc-3227-460b-807e-0befe0fd1d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846874435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2846874435
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2971017128
Short name T620
Test name
Test status
Simulation time 120192220 ps
CPU time 1.01 seconds
Started Aug 08 07:39:31 PM PDT 24
Finished Aug 08 07:39:32 PM PDT 24
Peak memory 200208 kb
Host smart-0df13c25-452c-4bdd-af6e-ee29405bdcfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971017128 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2971017128
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2440115721
Short name T558
Test name
Test status
Simulation time 77653896 ps
CPU time 0.77 seconds
Started Aug 08 07:39:29 PM PDT 24
Finished Aug 08 07:39:30 PM PDT 24
Peak memory 200036 kb
Host smart-170b54d6-8dc7-4b1a-b4af-6b192831afaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440115721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2440115721
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4142138110
Short name T557
Test name
Test status
Simulation time 126909458 ps
CPU time 1.07 seconds
Started Aug 08 07:39:29 PM PDT 24
Finished Aug 08 07:39:31 PM PDT 24
Peak memory 200084 kb
Host smart-bb4519d5-c623-4ffe-a210-f4e11be7c3b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142138110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4142138110
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.3891216929
Short name T576
Test name
Test status
Simulation time 137614456 ps
CPU time 1.96 seconds
Started Aug 08 07:39:30 PM PDT 24
Finished Aug 08 07:39:33 PM PDT 24
Peak memory 211204 kb
Host smart-88239a32-1ed8-4a17-9c82-6aad2dabefa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891216929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3891216929
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.3860245906
Short name T582
Test name
Test status
Simulation time 498289683 ps
CPU time 1.87 seconds
Started Aug 08 07:39:28 PM PDT 24
Finished Aug 08 07:39:30 PM PDT 24
Peak memory 200232 kb
Host smart-6ef1aa13-3b77-4a44-8c32-52799aed9ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860245906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.3860245906
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3448516806
Short name T556
Test name
Test status
Simulation time 104952594 ps
CPU time 1.37 seconds
Started Aug 08 07:39:02 PM PDT 24
Finished Aug 08 07:39:04 PM PDT 24
Peak memory 200200 kb
Host smart-c1d3dc74-cdd2-4c83-805f-c272f5025e23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448516806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
448516806
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.771426686
Short name T135
Test name
Test status
Simulation time 1178790061 ps
CPU time 5.53 seconds
Started Aug 08 07:39:02 PM PDT 24
Finished Aug 08 07:39:08 PM PDT 24
Peak memory 200184 kb
Host smart-118b317c-01c0-4bba-87de-da4fcc802e50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771426686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.771426686
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2350171234
Short name T595
Test name
Test status
Simulation time 124619951 ps
CPU time 0.87 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:04 PM PDT 24
Peak memory 199900 kb
Host smart-778eff5f-4bce-4142-91ff-48fca0f2e018
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350171234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
350171234
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.67261417
Short name T567
Test name
Test status
Simulation time 172651512 ps
CPU time 1.29 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:04 PM PDT 24
Peak memory 209792 kb
Host smart-566fa90b-e1f0-4150-a997-4f260fcdc32a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67261417 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.67261417
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2812192452
Short name T96
Test name
Test status
Simulation time 81564758 ps
CPU time 0.9 seconds
Started Aug 08 07:39:04 PM PDT 24
Finished Aug 08 07:39:05 PM PDT 24
Peak memory 200068 kb
Host smart-5c5b3737-0c68-473a-b429-9addf00c09aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812192452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2812192452
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.882510839
Short name T112
Test name
Test status
Simulation time 137650711 ps
CPU time 1.27 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:05 PM PDT 24
Peak memory 200232 kb
Host smart-797ac75a-cc37-47a2-be01-de210f83f3a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882510839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.882510839
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1841393128
Short name T565
Test name
Test status
Simulation time 268581035 ps
CPU time 2.22 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:05 PM PDT 24
Peak memory 208272 kb
Host smart-51784b9c-ffd5-4d57-ba53-a1f9fe852d69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841393128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1841393128
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1477739790
Short name T91
Test name
Test status
Simulation time 771338386 ps
CPU time 2.69 seconds
Started Aug 08 07:39:04 PM PDT 24
Finished Aug 08 07:39:07 PM PDT 24
Peak memory 200292 kb
Host smart-1c859289-d00f-49f2-aae5-6bce5e6a127d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477739790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1477739790
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2371433715
Short name T596
Test name
Test status
Simulation time 212240901 ps
CPU time 1.59 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 200376 kb
Host smart-05ab93de-1335-409d-9006-935a56826db9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371433715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
371433715
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3859042932
Short name T600
Test name
Test status
Simulation time 264948516 ps
CPU time 3.33 seconds
Started Aug 08 07:39:17 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 200128 kb
Host smart-76edc2b1-745b-47a6-8f59-ce07e18fb617
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859042932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
859042932
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2759364708
Short name T542
Test name
Test status
Simulation time 105787232 ps
CPU time 0.87 seconds
Started Aug 08 07:39:02 PM PDT 24
Finished Aug 08 07:39:03 PM PDT 24
Peak memory 200080 kb
Host smart-bbd51b81-4276-4c53-a108-f04671f128b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759364708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
759364708
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.302528574
Short name T73
Test name
Test status
Simulation time 143189859 ps
CPU time 1.15 seconds
Started Aug 08 07:39:21 PM PDT 24
Finished Aug 08 07:39:22 PM PDT 24
Peak memory 208384 kb
Host smart-f4655444-eeb0-40d4-ae8f-6b483f25de93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302528574 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.302528574
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3022332721
Short name T564
Test name
Test status
Simulation time 57313534 ps
CPU time 0.76 seconds
Started Aug 08 07:39:22 PM PDT 24
Finished Aug 08 07:39:23 PM PDT 24
Peak memory 199928 kb
Host smart-531a021f-1e73-42ad-8919-0a5248b24ef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022332721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3022332721
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1982209875
Short name T105
Test name
Test status
Simulation time 161207026 ps
CPU time 1.2 seconds
Started Aug 08 07:39:21 PM PDT 24
Finished Aug 08 07:39:22 PM PDT 24
Peak memory 200124 kb
Host smart-faaa30a6-4729-485e-ad29-e3df9903724b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982209875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1982209875
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3448001206
Short name T602
Test name
Test status
Simulation time 433122741 ps
CPU time 3.13 seconds
Started Aug 08 07:39:03 PM PDT 24
Finished Aug 08 07:39:06 PM PDT 24
Peak memory 208320 kb
Host smart-f02da9a2-a2ab-4399-b188-021f0fc993e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448001206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3448001206
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.211099967
Short name T555
Test name
Test status
Simulation time 147832053 ps
CPU time 1.92 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 208352 kb
Host smart-484d0d34-586e-4c7d-8d19-d2c90a2a7d7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211099967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.211099967
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1555690131
Short name T554
Test name
Test status
Simulation time 801337943 ps
CPU time 4.54 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 200232 kb
Host smart-1a4cdb2d-8292-4ebf-9293-c2646cc4c5c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555690131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
555690131
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1352494618
Short name T571
Test name
Test status
Simulation time 94859628 ps
CPU time 0.83 seconds
Started Aug 08 07:39:14 PM PDT 24
Finished Aug 08 07:39:15 PM PDT 24
Peak memory 200096 kb
Host smart-99706f40-dff3-454d-a031-1e126bfce000
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352494618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
352494618
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1730950830
Short name T85
Test name
Test status
Simulation time 191738857 ps
CPU time 1.19 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 200136 kb
Host smart-3baae4f0-4be3-467b-b78f-8d9f7d985dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730950830 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1730950830
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1416725019
Short name T577
Test name
Test status
Simulation time 67789160 ps
CPU time 0.79 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:16 PM PDT 24
Peak memory 200064 kb
Host smart-4c0d69d9-42d9-4090-949a-b3ee7710c654
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416725019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1416725019
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.120900486
Short name T569
Test name
Test status
Simulation time 112498828 ps
CPU time 1.03 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:16 PM PDT 24
Peak memory 200160 kb
Host smart-304403f7-3256-4ce0-bc48-00698cebd2ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120900486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.120900486
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.75102081
Short name T546
Test name
Test status
Simulation time 95953326 ps
CPU time 1.37 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200000 kb
Host smart-790a0574-bc8b-40d9-987b-6ba495ad0e03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75102081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.75102081
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2986183339
Short name T563
Test name
Test status
Simulation time 414951248 ps
CPU time 1.71 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 200232 kb
Host smart-813c3604-36f3-4019-b510-b03faecbe4ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986183339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2986183339
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3504469118
Short name T594
Test name
Test status
Simulation time 152282049 ps
CPU time 1.49 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 208660 kb
Host smart-c57a5abb-1046-458b-9ba5-dc222e89b7e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504469118 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3504469118
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.897112912
Short name T566
Test name
Test status
Simulation time 69204467 ps
CPU time 0.81 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:16 PM PDT 24
Peak memory 200064 kb
Host smart-3a851be1-6da9-404a-ac47-82783315e8b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897112912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.897112912
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.236152946
Short name T71
Test name
Test status
Simulation time 69775504 ps
CPU time 0.88 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 200164 kb
Host smart-b21196fc-0a0e-463e-806e-f6abc848d4cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236152946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.236152946
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.862038877
Short name T74
Test name
Test status
Simulation time 227075986 ps
CPU time 1.87 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 216520 kb
Host smart-80289626-d225-44cc-b00e-8a09673cd3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862038877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.862038877
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.935067993
Short name T118
Test name
Test status
Simulation time 823282616 ps
CPU time 2.76 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 200204 kb
Host smart-ba61de60-db24-4764-b4e4-5767f90988bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935067993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.
935067993
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2257600936
Short name T86
Test name
Test status
Simulation time 187153028 ps
CPU time 1.31 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200208 kb
Host smart-431aca70-0151-4b42-b2ec-25184258ca93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257600936 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.2257600936
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4273546137
Short name T610
Test name
Test status
Simulation time 75248690 ps
CPU time 0.8 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 200060 kb
Host smart-be5b3e9f-91f8-4320-85bc-8e8b8c44a5c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273546137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.4273546137
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2915352633
Short name T607
Test name
Test status
Simulation time 226612070 ps
CPU time 1.46 seconds
Started Aug 08 07:39:20 PM PDT 24
Finished Aug 08 07:39:22 PM PDT 24
Peak memory 200208 kb
Host smart-1fc440ef-c927-4a91-8632-21dddbfdee03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915352633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2915352633
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.1654601504
Short name T89
Test name
Test status
Simulation time 709991365 ps
CPU time 4.45 seconds
Started Aug 08 07:39:14 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 208324 kb
Host smart-c3812718-3ec8-4411-a16e-fd0d3eacc0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654601504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.1654601504
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2242490946
Short name T548
Test name
Test status
Simulation time 426946817 ps
CPU time 1.79 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 200284 kb
Host smart-5543632c-bb15-4840-acb9-8b7e50174dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242490946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2242490946
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.573161685
Short name T605
Test name
Test status
Simulation time 94791154 ps
CPU time 0.87 seconds
Started Aug 08 07:39:19 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 200032 kb
Host smart-4c23267c-4b25-4529-83ca-1847d929972e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573161685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.573161685
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1578198090
Short name T109
Test name
Test status
Simulation time 91455156 ps
CPU time 1.15 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:16 PM PDT 24
Peak memory 200336 kb
Host smart-e2f7ee85-43e3-4f1a-810d-fd00dececf2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578198090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1578198090
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1783644459
Short name T88
Test name
Test status
Simulation time 355445042 ps
CPU time 2.51 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 208284 kb
Host smart-e4006333-9433-47c5-bcb4-091b27e63ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783644459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1783644459
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3542424489
Short name T587
Test name
Test status
Simulation time 466739178 ps
CPU time 1.93 seconds
Started Aug 08 07:39:21 PM PDT 24
Finished Aug 08 07:39:23 PM PDT 24
Peak memory 200260 kb
Host smart-150cfac6-c27c-47f7-9aea-8514a38089fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542424489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3542424489
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2531417935
Short name T581
Test name
Test status
Simulation time 108205677 ps
CPU time 1.11 seconds
Started Aug 08 07:39:16 PM PDT 24
Finished Aug 08 07:39:17 PM PDT 24
Peak memory 208292 kb
Host smart-5813d8af-3cff-4992-bac6-c8f2783a4e8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531417935 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2531417935
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2368303541
Short name T608
Test name
Test status
Simulation time 73455977 ps
CPU time 0.83 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 200056 kb
Host smart-3cdb5bee-1e69-45b5-8d2c-b7eb9d163f0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368303541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2368303541
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4175733362
Short name T584
Test name
Test status
Simulation time 104939674 ps
CPU time 1.37 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 200212 kb
Host smart-fdfef861-42db-4761-b97c-32b152dec57c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175733362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4175733362
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2791802116
Short name T549
Test name
Test status
Simulation time 395246994 ps
CPU time 3.27 seconds
Started Aug 08 07:39:17 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 212080 kb
Host smart-04343a18-6d63-4f49-8176-4a72f0789962
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791802116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2791802116
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1340971440
Short name T611
Test name
Test status
Simulation time 481782681 ps
CPU time 2.03 seconds
Started Aug 08 07:39:22 PM PDT 24
Finished Aug 08 07:39:24 PM PDT 24
Peak memory 200124 kb
Host smart-3106e10c-5cfd-4c1b-a542-e3200ffd5e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340971440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1340971440
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.386414184
Short name T606
Test name
Test status
Simulation time 129814374 ps
CPU time 1.25 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 208292 kb
Host smart-fb389dc5-783b-42b9-987f-1d600e556dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386414184 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.386414184
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1076887760
Short name T559
Test name
Test status
Simulation time 86528736 ps
CPU time 0.92 seconds
Started Aug 08 07:39:20 PM PDT 24
Finished Aug 08 07:39:21 PM PDT 24
Peak memory 200064 kb
Host smart-8c231ffd-c2ec-455c-90ea-6e424bdfc90e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076887760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1076887760
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4202571204
Short name T574
Test name
Test status
Simulation time 232458462 ps
CPU time 1.62 seconds
Started Aug 08 07:39:18 PM PDT 24
Finished Aug 08 07:39:20 PM PDT 24
Peak memory 200416 kb
Host smart-3bb2dcf1-5b54-4f9d-934b-c6b984aa18c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202571204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4202571204
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.292138564
Short name T572
Test name
Test status
Simulation time 128622109 ps
CPU time 1.81 seconds
Started Aug 08 07:39:15 PM PDT 24
Finished Aug 08 07:39:18 PM PDT 24
Peak memory 208324 kb
Host smart-5bbfa797-fdab-4a1c-a665-3146450780c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292138564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.292138564
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.822031997
Short name T90
Test name
Test status
Simulation time 481159326 ps
CPU time 1.79 seconds
Started Aug 08 07:39:17 PM PDT 24
Finished Aug 08 07:39:19 PM PDT 24
Peak memory 200288 kb
Host smart-40e78ca9-42e2-40e7-825c-3558a3d20afc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822031997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
822031997
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1712629578
Short name T61
Test name
Test status
Simulation time 1221710732 ps
CPU time 5.65 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 221732 kb
Host smart-7ea37f08-8f50-40bd-9576-c99f52297a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712629578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1712629578
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.681350725
Short name T166
Test name
Test status
Simulation time 245203815 ps
CPU time 1.12 seconds
Started Aug 08 06:04:28 PM PDT 24
Finished Aug 08 06:04:29 PM PDT 24
Peak memory 217528 kb
Host smart-199fcb20-f77b-43b0-aee1-ed0fe04d2bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681350725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.681350725
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1773912621
Short name T158
Test name
Test status
Simulation time 1384948593 ps
CPU time 5.4 seconds
Started Aug 08 06:04:28 PM PDT 24
Finished Aug 08 06:04:34 PM PDT 24
Peak memory 200484 kb
Host smart-d355a975-ab6a-45c6-92ad-74e2a2ea8bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773912621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1773912621
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2816267093
Short name T76
Test name
Test status
Simulation time 18330344928 ps
CPU time 26.77 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:05:09 PM PDT 24
Peak memory 218192 kb
Host smart-b7a6fce4-2a06-4390-ab66-be96a8f1ecd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816267093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2816267093
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2743681233
Short name T153
Test name
Test status
Simulation time 105372948 ps
CPU time 1.01 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 200232 kb
Host smart-0befaf0d-2c51-4cb5-8ef6-650af5f0e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743681233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2743681233
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.543084885
Short name T178
Test name
Test status
Simulation time 245483754 ps
CPU time 1.58 seconds
Started Aug 08 06:04:50 PM PDT 24
Finished Aug 08 06:04:51 PM PDT 24
Peak memory 200476 kb
Host smart-0f18e956-b5a8-42e5-9954-b8623085865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543084885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.543084885
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3540779273
Short name T165
Test name
Test status
Simulation time 5544244112 ps
CPU time 20.54 seconds
Started Aug 08 06:04:36 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 200652 kb
Host smart-509797ad-b8ae-4d5e-a8bf-9b239f298348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540779273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3540779273
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3686461367
Short name T489
Test name
Test status
Simulation time 271493613 ps
CPU time 1.43 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:43 PM PDT 24
Peak memory 200340 kb
Host smart-00fd0104-33ea-4e39-9565-a345514ef9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686461367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3686461367
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2769431117
Short name T262
Test name
Test status
Simulation time 54194607 ps
CPU time 0.74 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 200112 kb
Host smart-0d88614c-720b-493f-b9b9-5e67e9be75c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769431117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2769431117
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.748993213
Short name T308
Test name
Test status
Simulation time 2359392166 ps
CPU time 8.45 seconds
Started Aug 08 06:04:24 PM PDT 24
Finished Aug 08 06:04:32 PM PDT 24
Peak memory 221568 kb
Host smart-c4c30448-fd2a-4003-9176-08da4a096174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748993213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.748993213
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2834290943
Short name T371
Test name
Test status
Simulation time 244067932 ps
CPU time 1.07 seconds
Started Aug 08 06:04:41 PM PDT 24
Finished Aug 08 06:04:42 PM PDT 24
Peak memory 217392 kb
Host smart-21180edc-06b0-4655-b793-2d3534ab4e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834290943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2834290943
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.404713299
Short name T152
Test name
Test status
Simulation time 84189513 ps
CPU time 0.75 seconds
Started Aug 08 06:04:28 PM PDT 24
Finished Aug 08 06:04:29 PM PDT 24
Peak memory 200084 kb
Host smart-1f06172d-3a01-4b58-8aed-8a5ac2ca3383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404713299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.404713299
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.144890926
Short name T47
Test name
Test status
Simulation time 959071396 ps
CPU time 4.98 seconds
Started Aug 08 06:04:37 PM PDT 24
Finished Aug 08 06:04:43 PM PDT 24
Peak memory 200576 kb
Host smart-edab473d-7d75-4ec9-a630-3026c98e572d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144890926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.144890926
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1218481368
Short name T78
Test name
Test status
Simulation time 16520170239 ps
CPU time 25.96 seconds
Started Aug 08 06:04:26 PM PDT 24
Finished Aug 08 06:04:52 PM PDT 24
Peak memory 217380 kb
Host smart-21b3a418-a2c0-4b72-97dc-4ec795ee5f15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218481368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1218481368
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1423479666
Short name T271
Test name
Test status
Simulation time 167202719 ps
CPU time 1.15 seconds
Started Aug 08 06:04:41 PM PDT 24
Finished Aug 08 06:04:42 PM PDT 24
Peak memory 200340 kb
Host smart-39070733-1510-4995-afef-6c23a9124e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423479666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1423479666
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.537113382
Short name T131
Test name
Test status
Simulation time 231249956 ps
CPU time 1.42 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:43 PM PDT 24
Peak memory 200424 kb
Host smart-9c8bcdc9-55b0-4502-8294-777d046c89fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537113382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.537113382
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.665230448
Short name T455
Test name
Test status
Simulation time 3582518890 ps
CPU time 14.52 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 208852 kb
Host smart-b80e59f5-9134-45ab-b4bc-d467c2682cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665230448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.665230448
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2992609209
Short name T31
Test name
Test status
Simulation time 131322618 ps
CPU time 1.53 seconds
Started Aug 08 06:04:46 PM PDT 24
Finished Aug 08 06:04:47 PM PDT 24
Peak memory 200248 kb
Host smart-66b5a4b4-95a4-4a21-bdd2-345105c85faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992609209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2992609209
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1824997226
Short name T139
Test name
Test status
Simulation time 159622146 ps
CPU time 1.31 seconds
Started Aug 08 06:04:27 PM PDT 24
Finished Aug 08 06:04:28 PM PDT 24
Peak memory 200508 kb
Host smart-22637548-708b-490d-9b83-10cf30aef2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824997226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1824997226
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1118355661
Short name T58
Test name
Test status
Simulation time 105943450 ps
CPU time 0.91 seconds
Started Aug 08 06:04:49 PM PDT 24
Finished Aug 08 06:04:50 PM PDT 24
Peak memory 200156 kb
Host smart-428251f3-5b9b-481b-8349-a4036a7a1c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118355661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1118355661
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3471041038
Short name T345
Test name
Test status
Simulation time 1227214391 ps
CPU time 5.7 seconds
Started Aug 08 06:04:41 PM PDT 24
Finished Aug 08 06:04:47 PM PDT 24
Peak memory 217540 kb
Host smart-21f98316-8c87-40c0-8d91-ab8bef2eb0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471041038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3471041038
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.159140801
Short name T56
Test name
Test status
Simulation time 243786676 ps
CPU time 1.07 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 217448 kb
Host smart-e9d5cde9-c6f3-404d-a26c-c3b2ae0bf746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159140801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.159140801
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2160319825
Short name T216
Test name
Test status
Simulation time 163613731 ps
CPU time 0.88 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:04:54 PM PDT 24
Peak memory 200096 kb
Host smart-3234ca3d-0716-4e21-9c13-ceb7e3d2c79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160319825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2160319825
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.931080262
Short name T94
Test name
Test status
Simulation time 1523385255 ps
CPU time 5.82 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:49 PM PDT 24
Peak memory 200580 kb
Host smart-7f655c19-2f97-448b-a13f-d4bfdcf3077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931080262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.931080262
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4096665560
Short name T201
Test name
Test status
Simulation time 159448420 ps
CPU time 1.1 seconds
Started Aug 08 06:04:46 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 200340 kb
Host smart-b42ec5c2-6b52-410d-903a-f52cc2978581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096665560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4096665560
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2338871952
Short name T82
Test name
Test status
Simulation time 123620137 ps
CPU time 1.18 seconds
Started Aug 08 06:04:46 PM PDT 24
Finished Aug 08 06:04:47 PM PDT 24
Peak memory 200528 kb
Host smart-ca5ad8ee-4bda-421c-8d0d-a0eca010b455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338871952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2338871952
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2588618439
Short name T374
Test name
Test status
Simulation time 7861059106 ps
CPU time 29 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:05:26 PM PDT 24
Peak memory 208808 kb
Host smart-50fd41a1-e4e3-4a93-badc-8689818e2739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588618439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2588618439
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3282549820
Short name T128
Test name
Test status
Simulation time 504575994 ps
CPU time 2.88 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 200344 kb
Host smart-04e875ba-f620-488e-8c79-ea7d1e5c1bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282549820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3282549820
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3468423713
Short name T330
Test name
Test status
Simulation time 199206358 ps
CPU time 1.15 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 200300 kb
Host smart-09c5c222-69c5-4836-b9d8-df4f1ffa856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468423713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3468423713
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1343022760
Short name T506
Test name
Test status
Simulation time 62147284 ps
CPU time 0.71 seconds
Started Aug 08 06:05:02 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200160 kb
Host smart-9be14efd-239f-46bc-b549-e4c92a6a6527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343022760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1343022760
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.727275712
Short name T36
Test name
Test status
Simulation time 1224914019 ps
CPU time 5.48 seconds
Started Aug 08 06:04:58 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 217672 kb
Host smart-18c13921-7de7-49ce-8e45-be439a376a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727275712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.727275712
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.221197956
Short name T361
Test name
Test status
Simulation time 244737531 ps
CPU time 1.1 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 217208 kb
Host smart-71504ab7-6e5e-4c57-9b14-8c65bbc15f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221197956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.221197956
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.718497242
Short name T413
Test name
Test status
Simulation time 83067282 ps
CPU time 0.75 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 200120 kb
Host smart-90fedad2-3c83-419c-b055-b269a9817cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718497242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.718497242
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1336975004
Short name T483
Test name
Test status
Simulation time 1078747278 ps
CPU time 4.84 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:50 PM PDT 24
Peak memory 200516 kb
Host smart-8f434435-3c9f-4baa-a0b6-2324c68d63ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336975004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1336975004
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2342834162
Short name T161
Test name
Test status
Simulation time 105902478 ps
CPU time 1.02 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 200348 kb
Host smart-4c7fda9d-cdb6-4594-8392-de6f1baafea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342834162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2342834162
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1049662309
Short name T81
Test name
Test status
Simulation time 112325503 ps
CPU time 1.15 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 200512 kb
Host smart-3b53735c-b488-4c05-a6a8-01afa2c5b242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049662309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1049662309
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2562958936
Short name T418
Test name
Test status
Simulation time 1723796135 ps
CPU time 7.4 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200452 kb
Host smart-dfed3925-7622-42d8-af00-d1325b5d5c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562958936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2562958936
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2620552735
Short name T259
Test name
Test status
Simulation time 447320210 ps
CPU time 2.24 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 208496 kb
Host smart-35514db5-c7b2-4eae-8a41-3f7017ce2d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620552735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2620552735
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1549499827
Short name T277
Test name
Test status
Simulation time 206075673 ps
CPU time 1.31 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:04:54 PM PDT 24
Peak memory 200384 kb
Host smart-2a8f9869-86b8-46ae-9945-d6409b663393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549499827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1549499827
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3763302436
Short name T283
Test name
Test status
Simulation time 75617746 ps
CPU time 0.8 seconds
Started Aug 08 06:04:52 PM PDT 24
Finished Aug 08 06:04:53 PM PDT 24
Peak memory 200084 kb
Host smart-1bd8981a-d716-42e7-b7e6-7ef196672e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763302436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3763302436
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1909341879
Short name T351
Test name
Test status
Simulation time 1882914452 ps
CPU time 6.61 seconds
Started Aug 08 06:04:50 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 217788 kb
Host smart-5357cf6a-5f3a-4b57-ab3d-eb9d116a8275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909341879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1909341879
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.349102785
Short name T459
Test name
Test status
Simulation time 244611128 ps
CPU time 1.03 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 217476 kb
Host smart-c0dde04a-7705-467d-8afc-d90ec0bfe6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349102785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.349102785
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3942475943
Short name T234
Test name
Test status
Simulation time 135369447 ps
CPU time 0.81 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 200092 kb
Host smart-cb53c72f-7c6b-4fcc-a525-547090df6f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942475943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3942475943
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1662172154
Short name T457
Test name
Test status
Simulation time 1335381508 ps
CPU time 5.44 seconds
Started Aug 08 06:04:51 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 200580 kb
Host smart-9439e6a0-b7e6-4d02-b1d7-de29df2ca4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662172154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1662172154
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1433653292
Short name T247
Test name
Test status
Simulation time 195982260 ps
CPU time 1.35 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200408 kb
Host smart-f1c4cb81-14e3-4bac-9e8e-1c4e093e8446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433653292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1433653292
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2201507824
Short name T521
Test name
Test status
Simulation time 7203457805 ps
CPU time 32.31 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:05:25 PM PDT 24
Peak memory 209816 kb
Host smart-3035aa7b-4f93-4f60-94fd-d4fc635e3442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201507824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2201507824
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3076680840
Short name T469
Test name
Test status
Simulation time 110952666 ps
CPU time 1.45 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 200268 kb
Host smart-44e010bd-a4e5-436c-91d9-5a5af6a5ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076680840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3076680840
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1186263748
Short name T496
Test name
Test status
Simulation time 108031895 ps
CPU time 0.94 seconds
Started Aug 08 06:04:52 PM PDT 24
Finished Aug 08 06:04:53 PM PDT 24
Peak memory 200368 kb
Host smart-515d763d-864e-4aeb-b9ee-f7a7e83aa7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186263748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1186263748
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.329875930
Short name T211
Test name
Test status
Simulation time 78110503 ps
CPU time 0.8 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200064 kb
Host smart-8ca60b85-5d83-4066-8cb1-5942a06a34f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329875930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.329875930
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3581691334
Short name T274
Test name
Test status
Simulation time 2341879953 ps
CPU time 7.98 seconds
Started Aug 08 06:04:51 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 217168 kb
Host smart-aab10729-8384-4ed0-b99e-aa63a41a5f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581691334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3581691334
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.912443661
Short name T407
Test name
Test status
Simulation time 244000983 ps
CPU time 1.13 seconds
Started Aug 08 06:04:54 PM PDT 24
Finished Aug 08 06:04:55 PM PDT 24
Peak memory 217528 kb
Host smart-86a90a5d-5267-4e93-b285-37a814d51438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912443661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.912443661
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3111355538
Short name T230
Test name
Test status
Simulation time 190285264 ps
CPU time 0.91 seconds
Started Aug 08 06:05:19 PM PDT 24
Finished Aug 08 06:05:20 PM PDT 24
Peak memory 200176 kb
Host smart-0a84c1b4-7a5b-40e6-8429-1198b191d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111355538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3111355538
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3472153054
Short name T320
Test name
Test status
Simulation time 1514915877 ps
CPU time 6 seconds
Started Aug 08 06:04:54 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 200524 kb
Host smart-e673e779-673b-4eba-b355-3a651da9ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472153054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3472153054
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4255120917
Short name T482
Test name
Test status
Simulation time 95374595 ps
CPU time 1.01 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:04:54 PM PDT 24
Peak memory 200564 kb
Host smart-25910035-5f3e-4454-96e5-1cd51e248cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255120917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4255120917
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2099038976
Short name T386
Test name
Test status
Simulation time 121662451 ps
CPU time 1.17 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 200488 kb
Host smart-db11ece4-b03a-47f1-951f-b08270567582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099038976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2099038976
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.447726704
Short name T299
Test name
Test status
Simulation time 2190472102 ps
CPU time 8.07 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 200616 kb
Host smart-5baeed90-5e02-4445-8e25-a194b5e5b11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447726704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.447726704
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.901618510
Short name T432
Test name
Test status
Simulation time 110697396 ps
CPU time 1.39 seconds
Started Aug 08 06:04:54 PM PDT 24
Finished Aug 08 06:04:55 PM PDT 24
Peak memory 200308 kb
Host smart-8c377be6-4a08-484e-9351-76e1078bf393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901618510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.901618510
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3958827406
Short name T191
Test name
Test status
Simulation time 145774255 ps
CPU time 1.04 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 200264 kb
Host smart-5bfe663f-67a8-4b89-9f5f-ef7c9f5f45fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958827406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3958827406
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.200230930
Short name T144
Test name
Test status
Simulation time 67243935 ps
CPU time 0.78 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200156 kb
Host smart-5444bb31-5dd0-48fc-804d-a09d841ef634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200230930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.200230930
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2853696793
Short name T355
Test name
Test status
Simulation time 1208577579 ps
CPU time 5.52 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 217672 kb
Host smart-9cd2f2d8-2b8d-4279-b170-3340f33f0050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853696793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2853696793
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.324899248
Short name T162
Test name
Test status
Simulation time 244358037 ps
CPU time 1.06 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 217508 kb
Host smart-25827fd4-1622-44b3-b919-90a135236cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324899248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.324899248
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.4082369179
Short name T219
Test name
Test status
Simulation time 150621506 ps
CPU time 0.8 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 200076 kb
Host smart-52ff1333-7747-4f8f-8425-ecb33093e848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082369179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4082369179
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3517980720
Short name T267
Test name
Test status
Simulation time 812088440 ps
CPU time 3.93 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 200584 kb
Host smart-44fa5832-0ef3-455a-897f-212a98325025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517980720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3517980720
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3433126167
Short name T67
Test name
Test status
Simulation time 106244404 ps
CPU time 0.99 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:04:54 PM PDT 24
Peak memory 200564 kb
Host smart-d8f12e19-4a6a-47c5-96cf-b0ae68e912fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433126167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3433126167
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3057794936
Short name T129
Test name
Test status
Simulation time 244953431 ps
CPU time 1.45 seconds
Started Aug 08 06:04:52 PM PDT 24
Finished Aug 08 06:04:54 PM PDT 24
Peak memory 200444 kb
Host smart-00c5278d-1ab8-4e49-86a6-57df97d4a67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057794936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3057794936
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.4078507187
Short name T523
Test name
Test status
Simulation time 10333904615 ps
CPU time 32.76 seconds
Started Aug 08 06:04:59 PM PDT 24
Finished Aug 08 06:05:32 PM PDT 24
Peak memory 200568 kb
Host smart-1475235c-db9a-4aa7-acf8-fb3410b0ae35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078507187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4078507187
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.3800424417
Short name T54
Test name
Test status
Simulation time 384582103 ps
CPU time 2.13 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:04:55 PM PDT 24
Peak memory 200220 kb
Host smart-4185e8f9-9a85-44fa-b485-33bcfaeed41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800424417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3800424417
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1150926642
Short name T256
Test name
Test status
Simulation time 62774637 ps
CPU time 0.82 seconds
Started Aug 08 06:04:58 PM PDT 24
Finished Aug 08 06:04:59 PM PDT 24
Peak memory 200292 kb
Host smart-f228dbff-f4d9-4cbd-8524-634411616d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150926642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1150926642
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2518257378
Short name T515
Test name
Test status
Simulation time 79415188 ps
CPU time 0.83 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 200152 kb
Host smart-5e15b5e2-9e8f-49ca-9df0-09832b7cb74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518257378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2518257378
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1858968108
Short name T51
Test name
Test status
Simulation time 1897203140 ps
CPU time 7.84 seconds
Started Aug 08 06:04:59 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 217700 kb
Host smart-15329e06-64fa-4dd9-8d7c-8d62cd1301e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858968108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1858968108
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.57776977
Short name T409
Test name
Test status
Simulation time 244117977 ps
CPU time 0.99 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 217524 kb
Host smart-4f2b4226-ef0f-40af-9218-1d77db5a2007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57776977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.57776977
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.1817607393
Short name T192
Test name
Test status
Simulation time 136024893 ps
CPU time 0.85 seconds
Started Aug 08 06:05:02 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200152 kb
Host smart-e1b53346-1ff7-418b-a73b-3c05581ba613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817607393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1817607393
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1041491910
Short name T481
Test name
Test status
Simulation time 1260697598 ps
CPU time 4.93 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:11 PM PDT 24
Peak memory 200468 kb
Host smart-fe3323ca-7eb1-4392-a50c-ff59d4c16cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041491910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1041491910
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2434393230
Short name T231
Test name
Test status
Simulation time 98541267 ps
CPU time 0.95 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 200216 kb
Host smart-c3984b55-aab4-4a7f-87b0-2a4d02f7368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434393230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2434393230
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2211501597
Short name T329
Test name
Test status
Simulation time 255693193 ps
CPU time 1.52 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200544 kb
Host smart-608e3622-2ca3-411b-87b5-d09426e3aa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211501597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2211501597
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.497586495
Short name T169
Test name
Test status
Simulation time 5616998728 ps
CPU time 22.5 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:30 PM PDT 24
Peak memory 208652 kb
Host smart-567d9457-2443-45eb-985c-479ae77b7f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497586495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.497586495
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2083869510
Short name T402
Test name
Test status
Simulation time 380703654 ps
CPU time 2.26 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 208516 kb
Host smart-9b1409bd-4b28-4964-833e-593c9aa443fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083869510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2083869510
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.27422245
Short name T313
Test name
Test status
Simulation time 214997944 ps
CPU time 1.24 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 200272 kb
Host smart-dacb8aed-0cfa-4ede-81b1-cf526741c043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27422245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.27422245
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1633579529
Short name T183
Test name
Test status
Simulation time 79247011 ps
CPU time 0.78 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200152 kb
Host smart-ed926bb0-ef95-4d23-ae7a-2782c84da062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633579529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1633579529
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3648916792
Short name T375
Test name
Test status
Simulation time 1216008779 ps
CPU time 5.33 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 221716 kb
Host smart-68e99ecb-acc4-43c9-a2c0-d1555b5bdbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648916792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3648916792
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.243292974
Short name T142
Test name
Test status
Simulation time 244235056 ps
CPU time 1.05 seconds
Started Aug 08 06:05:09 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 217436 kb
Host smart-277b0313-b607-4f30-bbc5-a0558416ac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243292974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.243292974
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.888137873
Short name T250
Test name
Test status
Simulation time 174287439 ps
CPU time 0.85 seconds
Started Aug 08 06:05:16 PM PDT 24
Finished Aug 08 06:05:17 PM PDT 24
Peak memory 200144 kb
Host smart-a59e346d-eb28-4943-b8a6-de8dff08cad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888137873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.888137873
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.213797254
Short name T530
Test name
Test status
Simulation time 1359622321 ps
CPU time 6.05 seconds
Started Aug 08 06:04:54 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 200604 kb
Host smart-c4241bef-63b9-41e5-a1fd-db816a664f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213797254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.213797254
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2156909798
Short name T173
Test name
Test status
Simulation time 105941524 ps
CPU time 0.99 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:04:54 PM PDT 24
Peak memory 200340 kb
Host smart-8403286e-9292-4425-a093-1a1e5aeaf702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156909798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2156909798
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.1780354843
Short name T433
Test name
Test status
Simulation time 206945069 ps
CPU time 1.4 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 200540 kb
Host smart-efe78036-0ea5-46c3-b648-4080b7c1f7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780354843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1780354843
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3909567314
Short name T93
Test name
Test status
Simulation time 750068463 ps
CPU time 4.01 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 200576 kb
Host smart-0429436d-be6a-4743-ac43-9f51d0660efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909567314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3909567314
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.4065659340
Short name T212
Test name
Test status
Simulation time 426624995 ps
CPU time 2.27 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 208480 kb
Host smart-243b40ce-0146-47de-abf0-ce506bfbc1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065659340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4065659340
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3566212773
Short name T137
Test name
Test status
Simulation time 133023385 ps
CPU time 1.02 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200356 kb
Host smart-2581cd2f-19c5-4771-ae7b-01d29fac6ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566212773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3566212773
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2867309329
Short name T263
Test name
Test status
Simulation time 79202288 ps
CPU time 0.81 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 200164 kb
Host smart-3fc784e5-d8e3-4d55-9c49-54f3224089de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867309329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2867309329
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2972281839
Short name T233
Test name
Test status
Simulation time 244283388 ps
CPU time 1.07 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 217588 kb
Host smart-ec8cd920-a3bd-4537-a820-ddfbcc4c4e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972281839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2972281839
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3788953255
Short name T514
Test name
Test status
Simulation time 245746160 ps
CPU time 1.02 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 200104 kb
Host smart-70d98b48-92b1-4d44-85f6-1a9068ee8761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788953255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3788953255
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.4145942910
Short name T124
Test name
Test status
Simulation time 1717836767 ps
CPU time 6.85 seconds
Started Aug 08 06:04:59 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200556 kb
Host smart-fc5ea767-1998-405b-95ea-10ca25d6d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145942910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.4145942910
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3973539300
Short name T171
Test name
Test status
Simulation time 113528604 ps
CPU time 1 seconds
Started Aug 08 06:05:02 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200356 kb
Host smart-88e6d162-fe18-460f-92b0-e7b2aeb1b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973539300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3973539300
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.870003106
Short name T130
Test name
Test status
Simulation time 259583698 ps
CPU time 1.47 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200500 kb
Host smart-557d19fb-e255-4f1c-b617-dc1d7c568e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870003106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.870003106
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3917549059
Short name T517
Test name
Test status
Simulation time 2990434861 ps
CPU time 12.92 seconds
Started Aug 08 06:05:15 PM PDT 24
Finished Aug 08 06:05:28 PM PDT 24
Peak memory 208784 kb
Host smart-e41de4e5-d2f8-40ce-8123-565bdc10a9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917549059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3917549059
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3456712564
Short name T398
Test name
Test status
Simulation time 520616440 ps
CPU time 2.55 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200184 kb
Host smart-5b0c7ab5-d0ee-46e9-a4cf-eccad7ce7afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456712564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3456712564
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4283240668
Short name T426
Test name
Test status
Simulation time 74356698 ps
CPU time 0.79 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 200344 kb
Host smart-9f8cd1f9-f370-4cd4-b574-dc14962df533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283240668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4283240668
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1824739174
Short name T405
Test name
Test status
Simulation time 65692785 ps
CPU time 0.75 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200092 kb
Host smart-ca655137-f385-4333-a316-4dfbe69de753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824739174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1824739174
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3130384479
Short name T50
Test name
Test status
Simulation time 2359340610 ps
CPU time 8.38 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 221728 kb
Host smart-3196babf-f1fe-4a25-b350-636eb5a0dd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130384479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3130384479
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.393840156
Short name T174
Test name
Test status
Simulation time 245661814 ps
CPU time 1.06 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:11 PM PDT 24
Peak memory 217548 kb
Host smart-c5b45124-a64c-4512-88f0-f1336944a547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393840156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.393840156
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.4291152478
Short name T358
Test name
Test status
Simulation time 174080529 ps
CPU time 0.84 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 199840 kb
Host smart-2b7b8bd6-fbd2-45a9-a252-1d1d8b5e66a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291152478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.4291152478
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.609907693
Short name T100
Test name
Test status
Simulation time 2150919816 ps
CPU time 7.24 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 200532 kb
Host smart-b93362b1-ddbc-41c2-96cb-b59dbb441e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609907693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.609907693
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.123911245
Short name T9
Test name
Test status
Simulation time 102939669 ps
CPU time 0.99 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 200344 kb
Host smart-3c85db61-ea07-47e7-a1f1-2add760eb8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123911245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.123911245
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.895385673
Short name T170
Test name
Test status
Simulation time 205040584 ps
CPU time 1.42 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 200476 kb
Host smart-b25f7e83-b5c1-45c8-8f36-782d68b5626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895385673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.895385673
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3776678779
Short name T465
Test name
Test status
Simulation time 6022951660 ps
CPU time 20.58 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:26 PM PDT 24
Peak memory 209604 kb
Host smart-8738c53b-fe4a-40df-9c5a-9ad9d8231ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776678779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3776678779
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1064179964
Short name T471
Test name
Test status
Simulation time 457831991 ps
CPU time 2.54 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 200240 kb
Host smart-6870836c-7a51-4170-a282-893c00dae3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064179964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1064179964
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2944425710
Short name T305
Test name
Test status
Simulation time 170071604 ps
CPU time 1.16 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200392 kb
Host smart-57f6705c-7d03-4de7-bb84-ddfc3b09bce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944425710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2944425710
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1158308432
Short name T272
Test name
Test status
Simulation time 74028732 ps
CPU time 0.78 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 200152 kb
Host smart-fadd92e7-64e2-4ff6-91cf-66b7a2bf76ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158308432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1158308432
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1612599097
Short name T304
Test name
Test status
Simulation time 2352256140 ps
CPU time 8.13 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 221804 kb
Host smart-a829b052-5415-44de-886b-7b20bdefc8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612599097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1612599097
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3061024775
Short name T237
Test name
Test status
Simulation time 243660002 ps
CPU time 1.08 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 217532 kb
Host smart-40abbeff-c823-4f67-9c09-ced7f757ebd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061024775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3061024775
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1479679359
Short name T210
Test name
Test status
Simulation time 162119427 ps
CPU time 0.82 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 200116 kb
Host smart-dac7e3e8-33b6-4d73-8bb1-bec7aade2723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479679359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1479679359
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1045252042
Short name T224
Test name
Test status
Simulation time 1125452328 ps
CPU time 4.43 seconds
Started Aug 08 06:04:51 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 200620 kb
Host smart-7f55c187-b9e0-4745-a032-b3af5b7aaa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045252042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1045252042
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1007312959
Short name T525
Test name
Test status
Simulation time 157441984 ps
CPU time 1.09 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200360 kb
Host smart-25c08926-1963-443d-afb4-24ac29c5a75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007312959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1007312959
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1033883307
Short name T315
Test name
Test status
Simulation time 118573160 ps
CPU time 1.15 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 200540 kb
Host smart-9ecd331d-ac6f-4f10-b800-cb3bb0aae9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033883307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1033883307
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2076943926
Short name T423
Test name
Test status
Simulation time 11188447546 ps
CPU time 39.77 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:43 PM PDT 24
Peak memory 200680 kb
Host smart-fb7de0fa-41fd-46ee-9df2-b6176cb64df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076943926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2076943926
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1838936620
Short name T209
Test name
Test status
Simulation time 334112509 ps
CPU time 2.1 seconds
Started Aug 08 06:04:54 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 208420 kb
Host smart-fc0b91bd-0370-410a-9032-85d1fb856748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838936620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1838936620
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1208232437
Short name T536
Test name
Test status
Simulation time 100747297 ps
CPU time 0.89 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 200120 kb
Host smart-735051c6-565a-4f7d-ad6a-682b0f4e4fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208232437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1208232437
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3803298965
Short name T49
Test name
Test status
Simulation time 2366837463 ps
CPU time 8.54 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:19 PM PDT 24
Peak memory 217840 kb
Host smart-013c960d-6ac4-46b2-9807-430cd36875f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803298965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3803298965
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3445128751
Short name T502
Test name
Test status
Simulation time 244291741 ps
CPU time 1.15 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 217508 kb
Host smart-b4351390-487c-49db-9ffb-f2094f0329d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445128751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3445128751
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3588685279
Short name T21
Test name
Test status
Simulation time 164903969 ps
CPU time 0.87 seconds
Started Aug 08 06:04:25 PM PDT 24
Finished Aug 08 06:04:26 PM PDT 24
Peak memory 200164 kb
Host smart-624dc191-cab9-4bb2-8a63-9699d18ecec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588685279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3588685279
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.809184332
Short name T104
Test name
Test status
Simulation time 1031707118 ps
CPU time 4.94 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:47 PM PDT 24
Peak memory 200464 kb
Host smart-49ca9f7a-d6cf-4df6-9963-2bcf8e5675a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809184332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.809184332
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3213952516
Short name T77
Test name
Test status
Simulation time 8339814809 ps
CPU time 12.92 seconds
Started Aug 08 06:04:37 PM PDT 24
Finished Aug 08 06:04:51 PM PDT 24
Peak memory 217144 kb
Host smart-2e954d96-739b-49a8-9a95-87fd8d9c43a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213952516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3213952516
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.673252776
Short name T372
Test name
Test status
Simulation time 179246844 ps
CPU time 1.33 seconds
Started Aug 08 06:04:46 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 200252 kb
Host smart-351022c7-95d6-431f-b4c8-c1da6a4f575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673252776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.673252776
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.628586990
Short name T537
Test name
Test status
Simulation time 114288083 ps
CPU time 1.19 seconds
Started Aug 08 06:04:35 PM PDT 24
Finished Aug 08 06:04:37 PM PDT 24
Peak memory 200296 kb
Host smart-46d8944e-19ca-468c-9af7-15c8aa804ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628586990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.628586990
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.228040176
Short name T102
Test name
Test status
Simulation time 17008579077 ps
CPU time 57.31 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:05:39 PM PDT 24
Peak memory 208820 kb
Host smart-4ec1a47b-b12c-47b4-97c4-3ca64c8b040f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228040176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.228040176
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1079402566
Short name T451
Test name
Test status
Simulation time 143204748 ps
CPU time 1.74 seconds
Started Aug 08 06:04:41 PM PDT 24
Finished Aug 08 06:04:43 PM PDT 24
Peak memory 200240 kb
Host smart-d33290e3-7d2d-40e4-9358-484dd4350899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079402566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1079402566
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1370533333
Short name T284
Test name
Test status
Simulation time 91280249 ps
CPU time 0.87 seconds
Started Aug 08 06:04:35 PM PDT 24
Finished Aug 08 06:04:36 PM PDT 24
Peak memory 200136 kb
Host smart-f939446c-df27-4493-a319-dc900f4c85ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370533333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1370533333
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.785943190
Short name T273
Test name
Test status
Simulation time 68785413 ps
CPU time 0.75 seconds
Started Aug 08 06:05:08 PM PDT 24
Finished Aug 08 06:05:09 PM PDT 24
Peak memory 200100 kb
Host smart-38006387-fd2c-4de4-876a-709d80617fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785943190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.785943190
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3752674745
Short name T35
Test name
Test status
Simulation time 1888085896 ps
CPU time 6.67 seconds
Started Aug 08 06:04:58 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 217788 kb
Host smart-f06932a0-f42c-4a2c-9e33-d25b0ee7da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752674745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3752674745
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3101523527
Short name T319
Test name
Test status
Simulation time 244371795 ps
CPU time 1.02 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 217480 kb
Host smart-101fdc16-70aa-45fd-b46b-3c62e985954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101523527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3101523527
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.834030250
Short name T533
Test name
Test status
Simulation time 108824680 ps
CPU time 0.77 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 200152 kb
Host smart-ade52088-3b5a-4f0d-a3c7-e767c1d39863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834030250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.834030250
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3450485727
Short name T66
Test name
Test status
Simulation time 912959351 ps
CPU time 4.84 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200580 kb
Host smart-48612688-827a-4d16-9c71-6ee2333d9e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450485727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3450485727
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3996681088
Short name T487
Test name
Test status
Simulation time 186694665 ps
CPU time 1.17 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200364 kb
Host smart-6f2270c1-5909-48db-b75a-709078013a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996681088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3996681088
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3856579124
Short name T373
Test name
Test status
Simulation time 228863413 ps
CPU time 1.55 seconds
Started Aug 08 06:04:58 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 200444 kb
Host smart-64835722-8ae6-4be3-b1fa-d7045c4b3b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856579124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3856579124
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2790543036
Short name T167
Test name
Test status
Simulation time 368913702 ps
CPU time 2.21 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 200160 kb
Host smart-a2d8fa44-a6c2-40aa-8fe8-e1b49841ff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790543036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2790543036
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3320509990
Short name T126
Test name
Test status
Simulation time 165191713 ps
CPU time 1.02 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 200392 kb
Host smart-cb26a39a-97de-4529-9844-e72c8a51d98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320509990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3320509990
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1864233292
Short name T343
Test name
Test status
Simulation time 75780547 ps
CPU time 0.78 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 200204 kb
Host smart-6549aafc-5503-4da7-a41f-f97d418a11d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864233292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1864233292
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.4287098942
Short name T516
Test name
Test status
Simulation time 1891594025 ps
CPU time 6.61 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 217784 kb
Host smart-515e3c00-0b6f-4ec9-9596-aa9bb7757992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287098942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.4287098942
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3794602762
Short name T436
Test name
Test status
Simulation time 245316159 ps
CPU time 1.02 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 217492 kb
Host smart-737b608e-6f28-4c6b-b43a-ae2ab2150d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794602762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3794602762
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3849693688
Short name T278
Test name
Test status
Simulation time 107275638 ps
CPU time 0.78 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 200212 kb
Host smart-da5d82fb-6965-4ee0-a77b-cadc308b80dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849693688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3849693688
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.4114420792
Short name T347
Test name
Test status
Simulation time 962504380 ps
CPU time 4.8 seconds
Started Aug 08 06:05:02 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 200592 kb
Host smart-76dfc19d-bd32-454a-b3bb-9251e6e86a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114420792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.4114420792
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1316244561
Short name T176
Test name
Test status
Simulation time 182866756 ps
CPU time 1.21 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200360 kb
Host smart-60f39c0b-530e-4cc9-9190-b262d02f6e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316244561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1316244561
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1421263310
Short name T427
Test name
Test status
Simulation time 120822286 ps
CPU time 1.24 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200480 kb
Host smart-fa5c7862-3423-4178-82a4-274ebab1934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421263310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1421263310
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2871662520
Short name T83
Test name
Test status
Simulation time 1128129586 ps
CPU time 6.04 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:09 PM PDT 24
Peak memory 200576 kb
Host smart-967627cc-8adc-4adc-b6a2-f333769a7381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871662520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2871662520
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.3707580361
Short name T238
Test name
Test status
Simulation time 390908183 ps
CPU time 2.47 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200308 kb
Host smart-f3bc9f7f-4dae-44a9-8f45-ecb1b8545698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707580361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3707580361
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1728537401
Short name T383
Test name
Test status
Simulation time 251075692 ps
CPU time 1.33 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 200408 kb
Host smart-0872f3af-795f-438f-9a64-0dad81ffe314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728537401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1728537401
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.4220031168
Short name T404
Test name
Test status
Simulation time 89695801 ps
CPU time 0.83 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200100 kb
Host smart-8f4f31f8-81a9-462b-b3a9-76e89f181c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220031168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4220031168
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3605532141
Short name T363
Test name
Test status
Simulation time 1882127244 ps
CPU time 6.92 seconds
Started Aug 08 06:04:51 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 217844 kb
Host smart-894f6d2c-d41a-481c-aa61-d73f0181f2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605532141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3605532141
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2283524979
Short name T350
Test name
Test status
Simulation time 244615507 ps
CPU time 1.3 seconds
Started Aug 08 06:04:58 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 217448 kb
Host smart-46528aff-06bb-437b-98bb-6ab833a48c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283524979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2283524979
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.730423017
Short name T25
Test name
Test status
Simulation time 92288555 ps
CPU time 0.79 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 199996 kb
Host smart-238360d0-b221-4594-896d-77afac85f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730423017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.730423017
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3841949092
Short name T95
Test name
Test status
Simulation time 884672046 ps
CPU time 4.04 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:14 PM PDT 24
Peak memory 200436 kb
Host smart-dcbcb95b-061b-47ec-bc14-fd95a0136066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841949092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3841949092
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3093186487
Short name T378
Test name
Test status
Simulation time 92370659 ps
CPU time 0.99 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200324 kb
Host smart-ab248648-6e98-45f7-8828-37cb411cabd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093186487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3093186487
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3485388848
Short name T419
Test name
Test status
Simulation time 193609089 ps
CPU time 1.34 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200460 kb
Host smart-74517490-b77b-4b28-9a85-ab09d2b48041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485388848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3485388848
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2924797894
Short name T524
Test name
Test status
Simulation time 1638752135 ps
CPU time 5.92 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:13 PM PDT 24
Peak memory 200492 kb
Host smart-40d332cc-2d93-46a3-8087-f3958540bd5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924797894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2924797894
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.436759567
Short name T127
Test name
Test status
Simulation time 467908860 ps
CPU time 2.65 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:04:59 PM PDT 24
Peak memory 200200 kb
Host smart-d0b640ca-be07-4762-9347-160bbf5e2aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436759567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.436759567
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3700939353
Short name T221
Test name
Test status
Simulation time 269789253 ps
CPU time 1.55 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200492 kb
Host smart-64b77876-6be7-4ef5-b5d2-3033bfb1794c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700939353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3700939353
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.16607694
Short name T159
Test name
Test status
Simulation time 71563349 ps
CPU time 0.82 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200136 kb
Host smart-474eb320-c95b-42ef-b359-adddccf3ce68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.16607694
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1452450519
Short name T332
Test name
Test status
Simulation time 1213531136 ps
CPU time 5.48 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 217696 kb
Host smart-7badaf79-ea17-4fcf-af33-da8799f52ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452450519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1452450519
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2926338712
Short name T140
Test name
Test status
Simulation time 244498365 ps
CPU time 1.17 seconds
Started Aug 08 06:04:59 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 217520 kb
Host smart-98677248-1296-4f98-a463-c3588c44aa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926338712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2926338712
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.4236950468
Short name T335
Test name
Test status
Simulation time 176790660 ps
CPU time 0.87 seconds
Started Aug 08 06:04:58 PM PDT 24
Finished Aug 08 06:04:59 PM PDT 24
Peak memory 200120 kb
Host smart-fdb7a500-b6e2-4b9f-9f5b-d0413f0da574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236950468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.4236950468
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.73703142
Short name T28
Test name
Test status
Simulation time 1279876588 ps
CPU time 5.15 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:16 PM PDT 24
Peak memory 200628 kb
Host smart-46e2e4d3-9a0b-4d08-bcd8-6f215c1a475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73703142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.73703142
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.429486461
Short name T151
Test name
Test status
Simulation time 182442431 ps
CPU time 1.2 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200276 kb
Host smart-3078eaef-b7c9-47dd-91fc-33da87795ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429486461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.429486461
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1337975751
Short name T454
Test name
Test status
Simulation time 191364055 ps
CPU time 1.51 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200504 kb
Host smart-3c0e0d24-2af9-4c58-9f98-98fc55306543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337975751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1337975751
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2990817507
Short name T505
Test name
Test status
Simulation time 6048543789 ps
CPU time 22.69 seconds
Started Aug 08 06:05:08 PM PDT 24
Finished Aug 08 06:05:30 PM PDT 24
Peak memory 208836 kb
Host smart-c55c809b-4a4a-4bcf-b2b4-04f0b2924fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990817507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2990817507
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2831945561
Short name T160
Test name
Test status
Simulation time 371111011 ps
CPU time 2.28 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200260 kb
Host smart-d4f4e5bd-d749-45b1-a67e-8b1a6e86db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831945561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2831945561
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1853206768
Short name T509
Test name
Test status
Simulation time 160789125 ps
CPU time 1.3 seconds
Started Aug 08 06:05:09 PM PDT 24
Finished Aug 08 06:05:11 PM PDT 24
Peak memory 200456 kb
Host smart-e0cf8100-a43b-4782-9f11-e41480cd5fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853206768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1853206768
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1122032135
Short name T258
Test name
Test status
Simulation time 62356475 ps
CPU time 0.75 seconds
Started Aug 08 06:05:08 PM PDT 24
Finished Aug 08 06:05:09 PM PDT 24
Peak memory 200172 kb
Host smart-1e148e37-8198-4dcf-86b5-07bb7af1b0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122032135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1122032135
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.1188469467
Short name T34
Test name
Test status
Simulation time 1229323506 ps
CPU time 5.64 seconds
Started Aug 08 06:05:02 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 217540 kb
Host smart-53c6f928-4fe9-48f3-a0ee-daef80257d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188469467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1188469467
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2015408816
Short name T298
Test name
Test status
Simulation time 247159867 ps
CPU time 1.03 seconds
Started Aug 08 06:05:23 PM PDT 24
Finished Aug 08 06:05:24 PM PDT 24
Peak memory 217536 kb
Host smart-72e662d7-38bb-4710-a8e3-4bb98b437fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015408816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2015408816
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1134078612
Short name T461
Test name
Test status
Simulation time 165483777 ps
CPU time 0.83 seconds
Started Aug 08 06:04:54 PM PDT 24
Finished Aug 08 06:04:55 PM PDT 24
Peak memory 200204 kb
Host smart-3bd83878-952e-4b6c-9149-b850ba2e1536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134078612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1134078612
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.571736791
Short name T291
Test name
Test status
Simulation time 1495412361 ps
CPU time 5.65 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 200448 kb
Host smart-af391d7f-c2db-4718-8f3d-8944cb148045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571736791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.571736791
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.335254053
Short name T491
Test name
Test status
Simulation time 111029785 ps
CPU time 1.04 seconds
Started Aug 08 06:05:31 PM PDT 24
Finished Aug 08 06:05:33 PM PDT 24
Peak memory 200344 kb
Host smart-98e906da-58d5-4c12-93ac-1e1cf5942276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335254053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.335254053
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1327851623
Short name T411
Test name
Test status
Simulation time 201775301 ps
CPU time 1.33 seconds
Started Aug 08 06:04:59 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 200468 kb
Host smart-8737373e-3c48-4397-b28f-e05cd67fef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327851623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1327851623
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3675698496
Short name T98
Test name
Test status
Simulation time 3497510996 ps
CPU time 15.24 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:21 PM PDT 24
Peak memory 208828 kb
Host smart-55f044d7-e40e-4eb6-ad05-531cc1651c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675698496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3675698496
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2296598579
Short name T534
Test name
Test status
Simulation time 116160606 ps
CPU time 1.45 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200280 kb
Host smart-d17b60e0-510f-43be-9642-88514b673602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296598579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2296598579
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2203834344
Short name T538
Test name
Test status
Simulation time 62457012 ps
CPU time 0.79 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200356 kb
Host smart-cce9a3a0-8abe-48e7-809d-fbafa86e47f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203834344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2203834344
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4228944836
Short name T472
Test name
Test status
Simulation time 71782582 ps
CPU time 0.76 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200124 kb
Host smart-c54adcd3-e77e-4ef0-9076-c747fdf8d963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228944836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4228944836
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2443150810
Short name T522
Test name
Test status
Simulation time 1900202868 ps
CPU time 7.06 seconds
Started Aug 08 06:04:58 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 221648 kb
Host smart-df684d9e-7ffb-4fe0-a8b9-f62fdad7222d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443150810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2443150810
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1531781569
Short name T198
Test name
Test status
Simulation time 244705189 ps
CPU time 1.03 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 217488 kb
Host smart-04e8b067-21ba-48f2-b428-b8e01c8ba5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531781569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1531781569
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1001676489
Short name T266
Test name
Test status
Simulation time 171283757 ps
CPU time 0.84 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200128 kb
Host smart-da8a36c8-8524-4223-af81-8221f7866888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001676489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1001676489
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3933115732
Short name T133
Test name
Test status
Simulation time 1267449299 ps
CPU time 4.88 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:09 PM PDT 24
Peak memory 200480 kb
Host smart-328fc026-c93e-4606-ad2f-116818f90e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933115732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3933115732
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3591950772
Short name T541
Test name
Test status
Simulation time 106898994 ps
CPU time 1.02 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 199128 kb
Host smart-8803abcc-1a1d-4ede-a68f-3d7f29a9e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591950772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3591950772
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2970619001
Short name T391
Test name
Test status
Simulation time 192746753 ps
CPU time 1.32 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200448 kb
Host smart-d476df75-38d0-4404-b5ca-0d8b2324dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970619001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2970619001
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.518529582
Short name T99
Test name
Test status
Simulation time 2789678280 ps
CPU time 11.7 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:18 PM PDT 24
Peak memory 200600 kb
Host smart-1b519d64-d3dd-497b-b579-26ea740c8ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518529582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.518529582
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.406830728
Short name T339
Test name
Test status
Simulation time 119081637 ps
CPU time 1.54 seconds
Started Aug 08 06:05:14 PM PDT 24
Finished Aug 08 06:05:15 PM PDT 24
Peak memory 200352 kb
Host smart-84eb6783-9a6a-49b7-87e3-6396622dd78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406830728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.406830728
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.80801971
Short name T473
Test name
Test status
Simulation time 96707236 ps
CPU time 0.9 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:11 PM PDT 24
Peak memory 200380 kb
Host smart-8edf51a3-a0ec-4f96-a7ba-083e701bcbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80801971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.80801971
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3139500687
Short name T531
Test name
Test status
Simulation time 75083042 ps
CPU time 0.79 seconds
Started Aug 08 06:05:12 PM PDT 24
Finished Aug 08 06:05:13 PM PDT 24
Peak memory 200056 kb
Host smart-630921fb-3d11-471a-8968-ec4c43335d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139500687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3139500687
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.340102410
Short name T458
Test name
Test status
Simulation time 1877046640 ps
CPU time 6.99 seconds
Started Aug 08 06:05:12 PM PDT 24
Finished Aug 08 06:05:19 PM PDT 24
Peak memory 229856 kb
Host smart-43470311-ba42-48d5-8bab-84cc138f4181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340102410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.340102410
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2555993261
Short name T535
Test name
Test status
Simulation time 244484690 ps
CPU time 1.06 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 217524 kb
Host smart-e854f474-e08f-411b-9fec-3e4c1c8ca913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555993261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2555993261
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3750391526
Short name T296
Test name
Test status
Simulation time 129108563 ps
CPU time 0.85 seconds
Started Aug 08 06:05:08 PM PDT 24
Finished Aug 08 06:05:09 PM PDT 24
Peak memory 200160 kb
Host smart-5236d946-d30f-4338-8327-3b10262eea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750391526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3750391526
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.144084152
Short name T422
Test name
Test status
Simulation time 993334176 ps
CPU time 4.68 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:15 PM PDT 24
Peak memory 200556 kb
Host smart-f96e3aaa-b555-4324-a252-192a22fd7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144084152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.144084152
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1310941723
Short name T287
Test name
Test status
Simulation time 176157643 ps
CPU time 1.19 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200348 kb
Host smart-92db4de1-6a6b-45f3-ae81-21f6b8b8280e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310941723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1310941723
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1044292053
Short name T44
Test name
Test status
Simulation time 115328396 ps
CPU time 1.15 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200480 kb
Host smart-5ce69539-c396-4e54-a9ef-f7ef4fb53086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044292053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1044292053
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3906575602
Short name T420
Test name
Test status
Simulation time 4344196892 ps
CPU time 15.65 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:16 PM PDT 24
Peak memory 208788 kb
Host smart-2011e118-fed2-44b6-8f6f-441223d8af6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906575602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3906575602
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.120096426
Short name T52
Test name
Test status
Simulation time 148906759 ps
CPU time 1.82 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200136 kb
Host smart-11765516-fe29-4863-942d-15fde683b752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120096426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.120096426
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2237511742
Short name T511
Test name
Test status
Simulation time 201412908 ps
CPU time 1.25 seconds
Started Aug 08 06:05:14 PM PDT 24
Finished Aug 08 06:05:15 PM PDT 24
Peak memory 200272 kb
Host smart-823eff58-ba6c-4acf-a52a-ee7dc7315af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237511742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2237511742
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.1226160814
Short name T528
Test name
Test status
Simulation time 68609876 ps
CPU time 0.75 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200152 kb
Host smart-e89634a8-6823-49b6-adc9-379c0eddef43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226160814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1226160814
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.401480571
Short name T499
Test name
Test status
Simulation time 1877750120 ps
CPU time 6.9 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 217728 kb
Host smart-87559e9a-2951-474d-82a7-ebd8c8a8c4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401480571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.401480571
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1640408609
Short name T229
Test name
Test status
Simulation time 244416280 ps
CPU time 1.13 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 217544 kb
Host smart-f03fb961-f9d5-4e0e-94e2-975cf3f103c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640408609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1640408609
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.241400375
Short name T532
Test name
Test status
Simulation time 200238480 ps
CPU time 1.01 seconds
Started Aug 08 06:05:09 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 200156 kb
Host smart-5b901ec8-d11e-43b8-979f-7fa7a6fc5c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241400375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.241400375
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2755417673
Short name T492
Test name
Test status
Simulation time 1919668377 ps
CPU time 6.5 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 200516 kb
Host smart-eaa43773-84e1-49e3-8805-62cd7e8d359e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755417673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2755417673
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1921289788
Short name T500
Test name
Test status
Simulation time 190537167 ps
CPU time 1.18 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 200320 kb
Host smart-7ed78902-506f-4189-8348-ce4cfde8497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921289788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1921289788
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.935023963
Short name T12
Test name
Test status
Simulation time 122105115 ps
CPU time 1.23 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200380 kb
Host smart-57801dc4-67da-4df9-bfc2-f12650db0245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935023963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.935023963
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3170022125
Short name T341
Test name
Test status
Simulation time 6059796121 ps
CPU time 26.08 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:32 PM PDT 24
Peak memory 200624 kb
Host smart-6487bdad-f4bd-4b37-a5fc-93f9eb1d54ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170022125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3170022125
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2576560149
Short name T194
Test name
Test status
Simulation time 412949205 ps
CPU time 2.13 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 208356 kb
Host smart-ea6d82e5-d5f6-4ed1-820d-24707a83e76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576560149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2576560149
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1877093691
Short name T29
Test name
Test status
Simulation time 74027819 ps
CPU time 0.83 seconds
Started Aug 08 06:05:12 PM PDT 24
Finished Aug 08 06:05:13 PM PDT 24
Peak memory 200300 kb
Host smart-bdb255ae-a941-407b-96fb-e5e19623a034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877093691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1877093691
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.11328174
Short name T264
Test name
Test status
Simulation time 79906246 ps
CPU time 0.78 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200116 kb
Host smart-e203470c-f81f-46ea-8891-4b2073442c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11328174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.11328174
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.4094773799
Short name T379
Test name
Test status
Simulation time 245531471 ps
CPU time 1 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 217540 kb
Host smart-d6fd3ce4-953a-4eb4-bc64-4209258dfd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094773799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.4094773799
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3306076839
Short name T244
Test name
Test status
Simulation time 235992330 ps
CPU time 0.91 seconds
Started Aug 08 06:05:09 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 200180 kb
Host smart-632c15bb-f56e-4062-b60f-dada570987e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306076839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3306076839
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1366281542
Short name T11
Test name
Test status
Simulation time 2043509901 ps
CPU time 7.43 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200560 kb
Host smart-0f37e177-5d2a-4487-a352-811013b10ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366281542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1366281542
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3337324722
Short name T519
Test name
Test status
Simulation time 96990988 ps
CPU time 0.95 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 200356 kb
Host smart-2a7899b1-8b88-4260-bb70-993c5dd2bb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337324722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3337324722
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2117077037
Short name T235
Test name
Test status
Simulation time 120695745 ps
CPU time 1.21 seconds
Started Aug 08 06:05:08 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 200508 kb
Host smart-9b941b92-151b-4f8d-a0e2-50e9fd9dc2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117077037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2117077037
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3863647519
Short name T440
Test name
Test status
Simulation time 4489432230 ps
CPU time 19.88 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:20 PM PDT 24
Peak memory 200584 kb
Host smart-53c00e79-1c50-4899-a361-75e0d988095a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863647519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3863647519
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2465798632
Short name T321
Test name
Test status
Simulation time 473492220 ps
CPU time 2.38 seconds
Started Aug 08 06:05:08 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 200272 kb
Host smart-115a4c19-6001-4b3d-8e60-9fd8ea93acd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465798632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2465798632
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.2038921572
Short name T356
Test name
Test status
Simulation time 146369393 ps
CPU time 1.28 seconds
Started Aug 08 06:05:13 PM PDT 24
Finished Aug 08 06:05:14 PM PDT 24
Peak memory 200344 kb
Host smart-1d61bed3-bf45-4b0d-af37-4ac35f64e2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038921572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2038921572
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1821245253
Short name T154
Test name
Test status
Simulation time 79990985 ps
CPU time 0.79 seconds
Started Aug 08 06:05:01 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200136 kb
Host smart-9d179192-6a26-4da5-90ab-02f375b9004f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821245253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1821245253
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2201545112
Short name T257
Test name
Test status
Simulation time 1219915065 ps
CPU time 5.58 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 229836 kb
Host smart-2680cc95-b2cb-46c3-8c27-95a6a74b5aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201545112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2201545112
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.105472820
Short name T10
Test name
Test status
Simulation time 245366877 ps
CPU time 1.08 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 217528 kb
Host smart-c1d3005e-b655-46ef-85d7-df38ceaee518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105472820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.105472820
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3733958618
Short name T476
Test name
Test status
Simulation time 161440797 ps
CPU time 0.87 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:08 PM PDT 24
Peak memory 199928 kb
Host smart-229a9f5f-e693-4560-bf44-62dd0d8d0a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733958618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3733958618
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2148893840
Short name T444
Test name
Test status
Simulation time 1475468559 ps
CPU time 5.78 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 200596 kb
Host smart-23e8561e-5450-45bb-9081-eb97544e4ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148893840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2148893840
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1143888748
Short name T401
Test name
Test status
Simulation time 140616840 ps
CPU time 1.15 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200360 kb
Host smart-44d775a2-422f-4647-af57-cf7bcf7a6ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143888748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1143888748
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.244768430
Short name T215
Test name
Test status
Simulation time 236444432 ps
CPU time 1.48 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 200548 kb
Host smart-ddcfe164-6d87-4663-9ec4-9954e4cf60b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244768430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.244768430
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1980823356
Short name T439
Test name
Test status
Simulation time 150115691 ps
CPU time 1.81 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 200212 kb
Host smart-0c7abee7-1ebf-41af-af77-0ebf46175f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980823356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1980823356
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1464386170
Short name T223
Test name
Test status
Simulation time 227401747 ps
CPU time 1.24 seconds
Started Aug 08 06:05:03 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 200276 kb
Host smart-1a26a74b-4142-4f82-bde2-3da51bad5175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464386170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1464386170
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3289938581
Short name T53
Test name
Test status
Simulation time 102445724 ps
CPU time 0.86 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:04:54 PM PDT 24
Peak memory 200200 kb
Host smart-d0cc7ac0-dd19-4538-b2ad-5ca4543b5dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289938581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3289938581
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.4150140293
Short name T316
Test name
Test status
Simulation time 1890471871 ps
CPU time 7.43 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 217708 kb
Host smart-23334ef4-1011-4848-b077-eb91e40346a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150140293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.4150140293
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.753945027
Short name T295
Test name
Test status
Simulation time 244541687 ps
CPU time 1.04 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 217532 kb
Host smart-fadc8b49-f85e-465b-9d55-9aa0d5fc2f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753945027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.753945027
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.940611335
Short name T460
Test name
Test status
Simulation time 187443825 ps
CPU time 0.88 seconds
Started Aug 08 06:04:46 PM PDT 24
Finished Aug 08 06:04:47 PM PDT 24
Peak memory 200188 kb
Host smart-cd51aa83-f211-42f3-8790-529e35a5fcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940611335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.940611335
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.452299534
Short name T448
Test name
Test status
Simulation time 1406625960 ps
CPU time 5.9 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 200520 kb
Host smart-eec097c6-2af3-4443-be13-16af40467acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452299534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.452299534
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3799192370
Short name T132
Test name
Test status
Simulation time 172414497 ps
CPU time 1.14 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 200268 kb
Host smart-5e25225a-543d-45cd-a22c-215e7a01ca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799192370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3799192370
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.3540170905
Short name T5
Test name
Test status
Simulation time 200456278 ps
CPU time 1.35 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 200744 kb
Host smart-62797f9a-115b-4bd1-a692-1e13f4fc6ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540170905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3540170905
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.192916025
Short name T309
Test name
Test status
Simulation time 7013470233 ps
CPU time 32.49 seconds
Started Aug 08 06:04:47 PM PDT 24
Finished Aug 08 06:05:20 PM PDT 24
Peak memory 208928 kb
Host smart-48e35ed0-391d-4e05-b906-a0502058a139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192916025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.192916025
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.159483429
Short name T265
Test name
Test status
Simulation time 490002245 ps
CPU time 2.61 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 200236 kb
Host smart-57c60d11-b66c-45e0-ba11-31a3816b92a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159483429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.159483429
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3040971357
Short name T276
Test name
Test status
Simulation time 169609333 ps
CPU time 1.27 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:04:58 PM PDT 24
Peak memory 200464 kb
Host smart-29633478-ef4f-4457-abad-b9cc710d1c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040971357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3040971357
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2411152172
Short name T431
Test name
Test status
Simulation time 74290940 ps
CPU time 0.76 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:22 PM PDT 24
Peak memory 200156 kb
Host smart-8afb6cc8-1428-465b-b100-38b6179e5514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411152172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2411152172
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1206478737
Short name T39
Test name
Test status
Simulation time 1226991958 ps
CPU time 5.14 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:11 PM PDT 24
Peak memory 217744 kb
Host smart-c2932c70-fd19-4896-b8d7-904270faba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206478737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1206478737
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3124658134
Short name T6
Test name
Test status
Simulation time 244815672 ps
CPU time 1.07 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:13 PM PDT 24
Peak memory 217468 kb
Host smart-dad00b20-76f1-464e-a577-4f7cef43e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124658134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3124658134
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.269811166
Short name T261
Test name
Test status
Simulation time 133537828 ps
CPU time 0.8 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200008 kb
Host smart-968f67f1-5730-4112-b858-752755c40c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269811166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.269811166
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2761718761
Short name T416
Test name
Test status
Simulation time 1664881116 ps
CPU time 6.69 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200528 kb
Host smart-be6ef5ce-1c92-4b12-8bd8-59bfae772933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761718761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2761718761
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3411918489
Short name T310
Test name
Test status
Simulation time 112444752 ps
CPU time 1.03 seconds
Started Aug 08 06:05:13 PM PDT 24
Finished Aug 08 06:05:14 PM PDT 24
Peak memory 200344 kb
Host smart-2facb3ce-3821-49f5-9287-0e64199baaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411918489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3411918489
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2225683400
Short name T340
Test name
Test status
Simulation time 255443167 ps
CPU time 1.71 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200560 kb
Host smart-60fac864-6786-437d-8e01-1d515875644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225683400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2225683400
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2850238272
Short name T275
Test name
Test status
Simulation time 6220127490 ps
CPU time 27.93 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:33 PM PDT 24
Peak memory 200624 kb
Host smart-c6204c2f-b0c2-4fd4-a6a0-f926451f49a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850238272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2850238272
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1991105771
Short name T253
Test name
Test status
Simulation time 365407450 ps
CPU time 2.32 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200272 kb
Host smart-7c7a5d43-0686-48a0-b34e-67a5aa1eb23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991105771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1991105771
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.817263826
Short name T485
Test name
Test status
Simulation time 86615141 ps
CPU time 0.89 seconds
Started Aug 08 06:05:02 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 200376 kb
Host smart-6dc060c3-0e2e-41db-bcdc-dfb56cd33e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817263826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.817263826
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2846411041
Short name T189
Test name
Test status
Simulation time 60656215 ps
CPU time 0.74 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200176 kb
Host smart-90ef8768-5a76-4449-9bbb-2bd92d0733ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846411041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2846411041
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.256417388
Short name T425
Test name
Test status
Simulation time 1883797648 ps
CPU time 7.43 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:18 PM PDT 24
Peak memory 221584 kb
Host smart-c908ce74-84a4-429d-b11e-b68dae157b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256417388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.256417388
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3253564615
Short name T508
Test name
Test status
Simulation time 243444671 ps
CPU time 1.06 seconds
Started Aug 08 06:05:07 PM PDT 24
Finished Aug 08 06:05:09 PM PDT 24
Peak memory 217452 kb
Host smart-da492aee-29b9-46e1-8bba-c4b3ea4ef30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253564615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3253564615
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.2083266295
Short name T19
Test name
Test status
Simulation time 198787450 ps
CPU time 0.92 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200020 kb
Host smart-4b86bfc2-69b9-4220-9467-8a5e868e996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083266295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2083266295
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.4033565245
Short name T138
Test name
Test status
Simulation time 1210043903 ps
CPU time 4.79 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:15 PM PDT 24
Peak memory 200548 kb
Host smart-488849ec-50a2-4a8e-8897-e17609d23ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033565245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4033565245
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1531105885
Short name T370
Test name
Test status
Simulation time 174408159 ps
CPU time 1.25 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 200320 kb
Host smart-032eaeed-7b68-4dd1-957a-58a24027d502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531105885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1531105885
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3694904775
Short name T437
Test name
Test status
Simulation time 202785764 ps
CPU time 1.36 seconds
Started Aug 08 06:05:15 PM PDT 24
Finished Aug 08 06:05:17 PM PDT 24
Peak memory 200376 kb
Host smart-47b811e4-2f0c-4db7-8cf7-c59f96718170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694904775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3694904775
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2044337092
Short name T539
Test name
Test status
Simulation time 240529890 ps
CPU time 1.5 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200384 kb
Host smart-3cb6b3d1-9641-4371-a6a1-d424031b5992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044337092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2044337092
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.390721719
Short name T217
Test name
Test status
Simulation time 113832230 ps
CPU time 1.05 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:06 PM PDT 24
Peak memory 200340 kb
Host smart-a73b9ee3-8f97-4a4e-9394-bc44e530b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390721719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.390721719
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3839393955
Short name T527
Test name
Test status
Simulation time 66824655 ps
CPU time 0.78 seconds
Started Aug 08 06:05:23 PM PDT 24
Finished Aug 08 06:05:24 PM PDT 24
Peak memory 200112 kb
Host smart-1ad5f3e3-4c18-4848-8975-bf54134798e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839393955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3839393955
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.36070025
Short name T438
Test name
Test status
Simulation time 1892668024 ps
CPU time 7.71 seconds
Started Aug 08 06:05:06 PM PDT 24
Finished Aug 08 06:05:14 PM PDT 24
Peak memory 229872 kb
Host smart-a8acda19-c25f-4ee5-a75e-3148a4de840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36070025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.36070025
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1048094768
Short name T292
Test name
Test status
Simulation time 243956570 ps
CPU time 1.14 seconds
Started Aug 08 06:05:15 PM PDT 24
Finished Aug 08 06:05:16 PM PDT 24
Peak memory 217532 kb
Host smart-1d23d6bd-447a-447b-a6c5-6b9fdb94635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048094768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1048094768
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4277432952
Short name T286
Test name
Test status
Simulation time 83650215 ps
CPU time 0.73 seconds
Started Aug 08 06:05:04 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200168 kb
Host smart-0c7cfe4c-55f1-43b6-b6db-9e51aec9db4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277432952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4277432952
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.134649307
Short name T342
Test name
Test status
Simulation time 645878363 ps
CPU time 3.69 seconds
Started Aug 08 06:05:09 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200568 kb
Host smart-93e5e108-d62b-4602-a810-1c81bbb5d94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134649307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.134649307
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1495935797
Short name T45
Test name
Test status
Simulation time 96872470 ps
CPU time 0.97 seconds
Started Aug 08 06:05:17 PM PDT 24
Finished Aug 08 06:05:18 PM PDT 24
Peak memory 200304 kb
Host smart-fd40b300-3543-49bc-86ce-98485a082fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495935797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1495935797
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1725683734
Short name T245
Test name
Test status
Simulation time 126612974 ps
CPU time 1.17 seconds
Started Aug 08 06:05:20 PM PDT 24
Finished Aug 08 06:05:22 PM PDT 24
Peak memory 200444 kb
Host smart-e63beb00-e885-43ec-bdd2-39d41cf3f623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725683734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1725683734
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3301397861
Short name T501
Test name
Test status
Simulation time 2376806737 ps
CPU time 7.87 seconds
Started Aug 08 06:05:16 PM PDT 24
Finished Aug 08 06:05:24 PM PDT 24
Peak memory 200640 kb
Host smart-bfe57265-f122-48fc-9bfc-8905551f56bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301397861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3301397861
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.2501984942
Short name T503
Test name
Test status
Simulation time 116957930 ps
CPU time 1.48 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:07 PM PDT 24
Peak memory 200320 kb
Host smart-01090a1f-8b03-4bfe-824a-b4b5be168cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501984942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2501984942
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.737644460
Short name T184
Test name
Test status
Simulation time 110446343 ps
CPU time 0.98 seconds
Started Aug 08 06:05:00 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 200308 kb
Host smart-65625455-a0e2-41eb-95d4-ce5563ae68f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737644460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.737644460
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.2431064920
Short name T143
Test name
Test status
Simulation time 71660584 ps
CPU time 0.77 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200144 kb
Host smart-6cca2d8c-3d23-4b6a-8d86-b6e3179a8c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431064920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2431064920
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.305938936
Short name T484
Test name
Test status
Simulation time 1905216772 ps
CPU time 7.5 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:05:41 PM PDT 24
Peak memory 217720 kb
Host smart-edd0dfea-0f64-49b5-ac8a-2e566c0e3421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305938936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.305938936
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.612578376
Short name T479
Test name
Test status
Simulation time 243785149 ps
CPU time 1.08 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:05:35 PM PDT 24
Peak memory 217516 kb
Host smart-7a5f4df1-af30-4386-ae24-e210c1c01e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612578376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.612578376
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1981230908
Short name T387
Test name
Test status
Simulation time 134244026 ps
CPU time 0.81 seconds
Started Aug 08 06:05:05 PM PDT 24
Finished Aug 08 06:05:05 PM PDT 24
Peak memory 200180 kb
Host smart-6212a5ab-d336-4bd4-aeb1-d68ed85e1ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981230908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1981230908
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.891237326
Short name T125
Test name
Test status
Simulation time 2048000512 ps
CPU time 7.24 seconds
Started Aug 08 06:05:25 PM PDT 24
Finished Aug 08 06:05:32 PM PDT 24
Peak memory 200532 kb
Host smart-0f501eb6-8ee1-4978-ac7d-de7816831f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891237326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.891237326
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3458986995
Short name T463
Test name
Test status
Simulation time 145274657 ps
CPU time 1.12 seconds
Started Aug 08 06:05:09 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 200368 kb
Host smart-7c1a8e04-0650-4fc7-aaed-8b7ae4b5f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458986995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3458986995
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3446015804
Short name T376
Test name
Test status
Simulation time 193321814 ps
CPU time 1.31 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:18 PM PDT 24
Peak memory 200516 kb
Host smart-c88c6ded-0b83-4f32-bc1b-584d48480da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446015804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3446015804
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.226270578
Short name T467
Test name
Test status
Simulation time 16713168290 ps
CPU time 58.36 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:06:32 PM PDT 24
Peak memory 208776 kb
Host smart-12ab506f-0f45-49f0-ba66-673e093a3506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226270578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.226270578
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1493783610
Short name T268
Test name
Test status
Simulation time 134489629 ps
CPU time 1.61 seconds
Started Aug 08 06:05:13 PM PDT 24
Finished Aug 08 06:05:15 PM PDT 24
Peak memory 200304 kb
Host smart-4a75bb3e-8ff9-4f28-95e6-31a2ca80920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493783610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1493783610
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3171546587
Short name T441
Test name
Test status
Simulation time 189657773 ps
CPU time 1.31 seconds
Started Aug 08 06:05:12 PM PDT 24
Finished Aug 08 06:05:13 PM PDT 24
Peak memory 200344 kb
Host smart-8ced0baf-0c5c-4f5e-aa54-5b1d202d690d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171546587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3171546587
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1843515976
Short name T399
Test name
Test status
Simulation time 72651042 ps
CPU time 0.75 seconds
Started Aug 08 06:05:09 PM PDT 24
Finished Aug 08 06:05:09 PM PDT 24
Peak memory 200096 kb
Host smart-be62e4bc-cc26-4b77-9a13-62b7cd1264a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843515976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1843515976
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.2892123093
Short name T464
Test name
Test status
Simulation time 1222588965 ps
CPU time 5.45 seconds
Started Aug 08 06:05:18 PM PDT 24
Finished Aug 08 06:05:24 PM PDT 24
Peak memory 217716 kb
Host smart-efd86594-9d0a-440a-98cc-7cba62140fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892123093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2892123093
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2304548096
Short name T394
Test name
Test status
Simulation time 244041434 ps
CPU time 1.04 seconds
Started Aug 08 06:05:19 PM PDT 24
Finished Aug 08 06:05:20 PM PDT 24
Peak memory 217552 kb
Host smart-5b24a417-e4b0-458b-8c58-4ce4d31faeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304548096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2304548096
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2983223423
Short name T369
Test name
Test status
Simulation time 204788897 ps
CPU time 0.93 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:17 PM PDT 24
Peak memory 200164 kb
Host smart-c8c66cad-4b8e-4d91-946e-95e9637707e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983223423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2983223423
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3619338079
Short name T512
Test name
Test status
Simulation time 1834043529 ps
CPU time 7.14 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:17 PM PDT 24
Peak memory 200524 kb
Host smart-e063e1ae-3690-46a0-b9a2-a1ae121eb712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619338079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3619338079
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3459511276
Short name T232
Test name
Test status
Simulation time 152076557 ps
CPU time 1.18 seconds
Started Aug 08 06:05:15 PM PDT 24
Finished Aug 08 06:05:17 PM PDT 24
Peak memory 200356 kb
Host smart-bde7521b-e0c8-404a-bd90-21c871f63811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459511276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3459511276
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.336646839
Short name T199
Test name
Test status
Simulation time 238689506 ps
CPU time 1.46 seconds
Started Aug 08 06:05:26 PM PDT 24
Finished Aug 08 06:05:27 PM PDT 24
Peak memory 200356 kb
Host smart-ba674685-46c2-415f-8f38-17340c091455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336646839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.336646839
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3499253005
Short name T353
Test name
Test status
Simulation time 120828590 ps
CPU time 1.44 seconds
Started Aug 08 06:05:23 PM PDT 24
Finished Aug 08 06:05:24 PM PDT 24
Peak memory 200208 kb
Host smart-c7bb153d-e508-4da6-8396-17c0f449986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499253005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3499253005
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2830712939
Short name T225
Test name
Test status
Simulation time 174040958 ps
CPU time 1.12 seconds
Started Aug 08 06:05:14 PM PDT 24
Finished Aug 08 06:05:16 PM PDT 24
Peak memory 200264 kb
Host smart-9bf95b41-3d4b-49c7-b3f3-5f5cea86ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830712939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2830712939
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.785797403
Short name T348
Test name
Test status
Simulation time 67784656 ps
CPU time 0.78 seconds
Started Aug 08 06:05:24 PM PDT 24
Finished Aug 08 06:05:25 PM PDT 24
Peak memory 200184 kb
Host smart-7a064ed7-b0bf-44fc-9cb3-027dc3981d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785797403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.785797403
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1701542523
Short name T68
Test name
Test status
Simulation time 1217130342 ps
CPU time 5.73 seconds
Started Aug 08 06:05:19 PM PDT 24
Finished Aug 08 06:05:24 PM PDT 24
Peak memory 217596 kb
Host smart-ed58b5b1-288e-46fe-a93f-0f69916c3f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701542523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1701542523
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2159797321
Short name T415
Test name
Test status
Simulation time 244615060 ps
CPU time 1.03 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 217484 kb
Host smart-8882a8ee-8f97-4fe3-9660-e6616750cd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159797321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2159797321
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1894696256
Short name T302
Test name
Test status
Simulation time 140576847 ps
CPU time 0.78 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:11 PM PDT 24
Peak memory 200112 kb
Host smart-a96c7623-772f-48ba-b78b-2a350a8ae545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894696256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1894696256
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2762706105
Short name T97
Test name
Test status
Simulation time 1769343959 ps
CPU time 6.54 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:18 PM PDT 24
Peak memory 200552 kb
Host smart-0e752b65-8e01-4e68-9a82-e93c3a9bbc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762706105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2762706105
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4048705913
Short name T214
Test name
Test status
Simulation time 158067941 ps
CPU time 1.18 seconds
Started Aug 08 06:05:31 PM PDT 24
Finished Aug 08 06:05:33 PM PDT 24
Peak memory 200380 kb
Host smart-649708bb-d065-4965-a74b-a58f8b1a9b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048705913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4048705913
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2022166476
Short name T498
Test name
Test status
Simulation time 191996599 ps
CPU time 1.33 seconds
Started Aug 08 06:05:30 PM PDT 24
Finished Aug 08 06:05:31 PM PDT 24
Peak memory 200352 kb
Host smart-29051752-e87c-4e05-8c89-9e056d6b2483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022166476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2022166476
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3664230303
Short name T354
Test name
Test status
Simulation time 7325836248 ps
CPU time 25.2 seconds
Started Aug 08 06:05:11 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 208764 kb
Host smart-042218d5-0bd4-4279-b91b-c6227a2892f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664230303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3664230303
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3186149499
Short name T62
Test name
Test status
Simulation time 355240084 ps
CPU time 2.25 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:13 PM PDT 24
Peak memory 200280 kb
Host smart-f06176cf-7300-420f-abcc-2a69bda6901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186149499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3186149499
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3403002129
Short name T200
Test name
Test status
Simulation time 68522595 ps
CPU time 0.8 seconds
Started Aug 08 06:05:31 PM PDT 24
Finished Aug 08 06:05:32 PM PDT 24
Peak memory 200392 kb
Host smart-e3d34106-6a26-40bf-97e1-1697765b1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403002129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3403002129
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3501986354
Short name T168
Test name
Test status
Simulation time 73570837 ps
CPU time 0.82 seconds
Started Aug 08 06:05:33 PM PDT 24
Finished Aug 08 06:05:34 PM PDT 24
Peak memory 200180 kb
Host smart-4c451b32-5701-4caa-8d14-53735269e4a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501986354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3501986354
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2143814133
Short name T336
Test name
Test status
Simulation time 2346958246 ps
CPU time 8.36 seconds
Started Aug 08 06:05:33 PM PDT 24
Finished Aug 08 06:05:41 PM PDT 24
Peak memory 217856 kb
Host smart-4b3e9690-1cce-4834-b6cb-efcedafff640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143814133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2143814133
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3141394294
Short name T7
Test name
Test status
Simulation time 244074823 ps
CPU time 1.09 seconds
Started Aug 08 06:05:40 PM PDT 24
Finished Aug 08 06:05:41 PM PDT 24
Peak memory 217576 kb
Host smart-092a4550-7fb9-4097-b242-3f008cfea908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141394294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3141394294
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3632728989
Short name T17
Test name
Test status
Simulation time 149654329 ps
CPU time 0.86 seconds
Started Aug 08 06:05:27 PM PDT 24
Finished Aug 08 06:05:28 PM PDT 24
Peak memory 200048 kb
Host smart-36b7618a-da30-410e-90f6-2dd48f4368f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632728989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3632728989
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1740821766
Short name T196
Test name
Test status
Simulation time 1634125255 ps
CPU time 6.25 seconds
Started Aug 08 06:05:13 PM PDT 24
Finished Aug 08 06:05:20 PM PDT 24
Peak memory 200540 kb
Host smart-096e10b5-d8c0-4905-b4e9-d77afe2af3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740821766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1740821766
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3669830206
Short name T408
Test name
Test status
Simulation time 101532491 ps
CPU time 1.02 seconds
Started Aug 08 06:05:21 PM PDT 24
Finished Aug 08 06:05:22 PM PDT 24
Peak memory 200312 kb
Host smart-39f39bb6-afb5-446b-97b2-620ffaa7ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669830206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3669830206
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2969047968
Short name T242
Test name
Test status
Simulation time 244538552 ps
CPU time 1.57 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 200480 kb
Host smart-d851f22b-3617-4877-8e8f-e77ad955237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969047968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2969047968
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3947086996
Short name T357
Test name
Test status
Simulation time 5783114097 ps
CPU time 25.34 seconds
Started Aug 08 06:05:29 PM PDT 24
Finished Aug 08 06:05:55 PM PDT 24
Peak memory 200616 kb
Host smart-10bcaf04-3eb6-43eb-acb9-7a7703acd49b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947086996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3947086996
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.758563304
Short name T222
Test name
Test status
Simulation time 382902803 ps
CPU time 2.11 seconds
Started Aug 08 06:05:19 PM PDT 24
Finished Aug 08 06:05:21 PM PDT 24
Peak memory 200272 kb
Host smart-1bc85549-93b0-4f40-9674-3adddf5a1d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758563304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.758563304
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.3098049088
Short name T453
Test name
Test status
Simulation time 138320352 ps
CPU time 1.14 seconds
Started Aug 08 06:05:10 PM PDT 24
Finished Aug 08 06:05:12 PM PDT 24
Peak memory 200312 kb
Host smart-9c828e23-9b19-43b7-9468-a12b46e6e487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098049088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3098049088
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1211379851
Short name T377
Test name
Test status
Simulation time 86482309 ps
CPU time 0.79 seconds
Started Aug 08 06:05:33 PM PDT 24
Finished Aug 08 06:05:34 PM PDT 24
Peak memory 200180 kb
Host smart-26938f15-7a63-4888-8b05-71329d5f0099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211379851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1211379851
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.148900979
Short name T38
Test name
Test status
Simulation time 1229500180 ps
CPU time 5.97 seconds
Started Aug 08 06:05:30 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 217668 kb
Host smart-dd39b51f-ccef-496f-8732-9e971810c224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148900979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.148900979
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3917959947
Short name T285
Test name
Test status
Simulation time 244399474 ps
CPU time 1.08 seconds
Started Aug 08 06:05:32 PM PDT 24
Finished Aug 08 06:05:34 PM PDT 24
Peak memory 217548 kb
Host smart-a331232a-f1e9-425c-8d7a-1b2b3b962437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917959947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3917959947
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1695651740
Short name T478
Test name
Test status
Simulation time 126113379 ps
CPU time 0.82 seconds
Started Aug 08 06:05:30 PM PDT 24
Finished Aug 08 06:05:31 PM PDT 24
Peak memory 200076 kb
Host smart-de902993-57f9-4f22-b410-3823e78a7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695651740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1695651740
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2845592522
Short name T429
Test name
Test status
Simulation time 2163891320 ps
CPU time 8.12 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:05:42 PM PDT 24
Peak memory 200576 kb
Host smart-bfbdd5de-b116-4af4-a114-2b5cda4055af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845592522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2845592522
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3848938710
Short name T462
Test name
Test status
Simulation time 99124426 ps
CPU time 0.99 seconds
Started Aug 08 06:05:23 PM PDT 24
Finished Aug 08 06:05:29 PM PDT 24
Peak memory 200356 kb
Host smart-152f1dc6-3dab-4c3b-8b85-7ebe23959389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848938710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3848938710
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1627949199
Short name T207
Test name
Test status
Simulation time 192829536 ps
CPU time 1.3 seconds
Started Aug 08 06:05:32 PM PDT 24
Finished Aug 08 06:05:33 PM PDT 24
Peak memory 200432 kb
Host smart-82ea0772-7d85-4888-91c5-f673df1000ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627949199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1627949199
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3034453152
Short name T513
Test name
Test status
Simulation time 2880836881 ps
CPU time 9.86 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:46 PM PDT 24
Peak memory 208880 kb
Host smart-1ae3fe50-76ca-4ea7-b5bb-1e0fe2238fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034453152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3034453152
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.956665196
Short name T395
Test name
Test status
Simulation time 126788993 ps
CPU time 1.54 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 200264 kb
Host smart-ff794aac-d314-4719-bed0-ab623253c8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956665196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.956665196
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3543798259
Short name T205
Test name
Test status
Simulation time 172815430 ps
CPU time 1.31 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:39 PM PDT 24
Peak memory 200484 kb
Host smart-bacc317f-2c28-4c95-b647-f79dfa84d78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543798259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3543798259
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.366832859
Short name T146
Test name
Test status
Simulation time 64910523 ps
CPU time 0.75 seconds
Started Aug 08 06:05:19 PM PDT 24
Finished Aug 08 06:05:20 PM PDT 24
Peak memory 200204 kb
Host smart-6e5acc5e-1e8e-4959-ac4d-c3c4107ca810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366832859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.366832859
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2515475273
Short name T293
Test name
Test status
Simulation time 2343136843 ps
CPU time 8.91 seconds
Started Aug 08 06:05:32 PM PDT 24
Finished Aug 08 06:05:41 PM PDT 24
Peak memory 217368 kb
Host smart-2b27870d-bac6-484d-8537-0817e99666ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515475273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2515475273
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1441331955
Short name T195
Test name
Test status
Simulation time 243899579 ps
CPU time 1.12 seconds
Started Aug 08 06:05:30 PM PDT 24
Finished Aug 08 06:05:32 PM PDT 24
Peak memory 217508 kb
Host smart-0e2b1633-b85d-4c09-97c5-6c6c676bf058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441331955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1441331955
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3115832304
Short name T493
Test name
Test status
Simulation time 136124438 ps
CPU time 0.8 seconds
Started Aug 08 06:05:24 PM PDT 24
Finished Aug 08 06:05:25 PM PDT 24
Peak memory 200168 kb
Host smart-bd254d3d-a1eb-41fb-983a-c93f247203fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115832304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3115832304
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.39275128
Short name T55
Test name
Test status
Simulation time 777861782 ps
CPU time 4.01 seconds
Started Aug 08 06:05:33 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 200520 kb
Host smart-e68c888b-b508-467a-846e-d1a5b798dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39275128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.39275128
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.338471989
Short name T204
Test name
Test status
Simulation time 104665902 ps
CPU time 0.94 seconds
Started Aug 08 06:05:18 PM PDT 24
Finished Aug 08 06:05:19 PM PDT 24
Peak memory 200312 kb
Host smart-dc22cbff-d496-4b40-a0c0-41fb94baa7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338471989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.338471989
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2236261273
Short name T226
Test name
Test status
Simulation time 115072338 ps
CPU time 1.25 seconds
Started Aug 08 06:05:27 PM PDT 24
Finished Aug 08 06:05:28 PM PDT 24
Peak memory 200404 kb
Host smart-a63f1ad7-e6e2-4d8c-93ab-e15c1d8b25d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236261273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2236261273
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3601779222
Short name T447
Test name
Test status
Simulation time 15909909947 ps
CPU time 52.9 seconds
Started Aug 08 06:05:25 PM PDT 24
Finished Aug 08 06:06:18 PM PDT 24
Peak memory 216320 kb
Host smart-cf9847de-9b07-45db-a7c2-51abe3563cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601779222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3601779222
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2931555858
Short name T410
Test name
Test status
Simulation time 328866981 ps
CPU time 2.22 seconds
Started Aug 08 06:05:35 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 200208 kb
Host smart-5ba1973f-f15a-4174-a1cb-a3fafa37b1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931555858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2931555858
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1991467780
Short name T323
Test name
Test status
Simulation time 274445470 ps
CPU time 1.47 seconds
Started Aug 08 06:05:27 PM PDT 24
Finished Aug 08 06:05:28 PM PDT 24
Peak memory 200368 kb
Host smart-98257c58-62b3-4d31-a38e-dcdcbe8a70b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991467780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1991467780
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1412831208
Short name T494
Test name
Test status
Simulation time 74155614 ps
CPU time 0.78 seconds
Started Aug 08 06:05:35 PM PDT 24
Finished Aug 08 06:05:36 PM PDT 24
Peak memory 200180 kb
Host smart-3368ed3c-d966-495d-abd5-839810a00f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412831208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1412831208
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2820036419
Short name T48
Test name
Test status
Simulation time 1223294139 ps
CPU time 5.54 seconds
Started Aug 08 06:05:39 PM PDT 24
Finished Aug 08 06:05:44 PM PDT 24
Peak memory 229904 kb
Host smart-8a0f812b-7ca2-4bac-b5c6-511a5220df57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820036419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2820036419
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2905855208
Short name T337
Test name
Test status
Simulation time 244111942 ps
CPU time 1.17 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 217540 kb
Host smart-0b27be31-dcbd-40c3-9c2e-473b8a980278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905855208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2905855208
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.827846674
Short name T443
Test name
Test status
Simulation time 182199710 ps
CPU time 0.83 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 200152 kb
Host smart-d47e3223-65c3-42fd-a68a-444032726196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827846674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.827846674
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.674826194
Short name T301
Test name
Test status
Simulation time 777489180 ps
CPU time 3.74 seconds
Started Aug 08 06:05:40 PM PDT 24
Finished Aug 08 06:05:44 PM PDT 24
Peak memory 200504 kb
Host smart-77283041-e3c1-440f-ad14-52d20fdef2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674826194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.674826194
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3903113781
Short name T147
Test name
Test status
Simulation time 100413388 ps
CPU time 0.99 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 200360 kb
Host smart-a4b71d82-fdc6-47cf-864d-f290eaca09c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903113781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3903113781
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1797576754
Short name T325
Test name
Test status
Simulation time 123815081 ps
CPU time 1.21 seconds
Started Aug 08 06:05:32 PM PDT 24
Finished Aug 08 06:05:33 PM PDT 24
Peak memory 200504 kb
Host smart-c48aa6ca-3eb0-4d72-9493-01c010d20187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797576754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1797576754
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1711526939
Short name T480
Test name
Test status
Simulation time 2051256126 ps
CPU time 9.37 seconds
Started Aug 08 06:05:59 PM PDT 24
Finished Aug 08 06:06:09 PM PDT 24
Peak memory 200512 kb
Host smart-21b586ff-25e0-455a-b54b-25429f5d2daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711526939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1711526939
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1990110256
Short name T385
Test name
Test status
Simulation time 359869154 ps
CPU time 2.03 seconds
Started Aug 08 06:05:35 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 200184 kb
Host smart-2d1a8f5c-6c31-4987-86a9-3cdf93abf834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990110256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1990110256
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2070577085
Short name T486
Test name
Test status
Simulation time 260442654 ps
CPU time 1.43 seconds
Started Aug 08 06:05:40 PM PDT 24
Finished Aug 08 06:05:41 PM PDT 24
Peak memory 200344 kb
Host smart-dab87cf2-e8d0-45db-8f08-aa39ed453c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070577085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2070577085
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2213833300
Short name T239
Test name
Test status
Simulation time 82563745 ps
CPU time 0.82 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 200156 kb
Host smart-50c47308-ddbd-4109-8534-8d12693394cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213833300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2213833300
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3350883834
Short name T37
Test name
Test status
Simulation time 2354095446 ps
CPU time 8.22 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 217208 kb
Host smart-38ec0f11-4229-4ef7-86a1-dd9b89d04a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350883834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3350883834
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3726982388
Short name T141
Test name
Test status
Simulation time 243858305 ps
CPU time 1.07 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 217576 kb
Host smart-f672cae4-8011-4f94-b37f-e6839ad643f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726982388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3726982388
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2373503187
Short name T181
Test name
Test status
Simulation time 133120610 ps
CPU time 0.84 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 200180 kb
Host smart-7bc62492-e834-41e4-ae45-90d89fb21168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373503187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2373503187
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2860277991
Short name T248
Test name
Test status
Simulation time 1536624568 ps
CPU time 5.59 seconds
Started Aug 08 06:04:49 PM PDT 24
Finished Aug 08 06:04:55 PM PDT 24
Peak memory 200464 kb
Host smart-6a9de7bd-7e31-4266-aa13-e12b09315249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860277991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2860277991
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.690507744
Short name T79
Test name
Test status
Simulation time 16548448478 ps
CPU time 25.22 seconds
Started Aug 08 06:04:56 PM PDT 24
Finished Aug 08 06:05:21 PM PDT 24
Peak memory 217312 kb
Host smart-5b7b250f-6e0d-4fa9-ab2a-ef4bba7d2e6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690507744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.690507744
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1323566911
Short name T366
Test name
Test status
Simulation time 98153735 ps
CPU time 0.93 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 200360 kb
Host smart-3b2386ce-a9ab-4859-8ea3-4f1b700765d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323566911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1323566911
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1700118350
Short name T290
Test name
Test status
Simulation time 196915442 ps
CPU time 1.37 seconds
Started Aug 08 06:04:36 PM PDT 24
Finished Aug 08 06:04:37 PM PDT 24
Peak memory 200564 kb
Host smart-4b21ccf8-6d6d-4319-8854-66ae2ee00814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700118350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1700118350
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.123518774
Short name T288
Test name
Test status
Simulation time 1308588385 ps
CPU time 6.2 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:52 PM PDT 24
Peak memory 200608 kb
Host smart-09d80d89-7f3c-4ae2-b67d-c02fb1da5090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123518774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.123518774
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.664040244
Short name T254
Test name
Test status
Simulation time 334109338 ps
CPU time 2.23 seconds
Started Aug 08 06:04:50 PM PDT 24
Finished Aug 08 06:04:53 PM PDT 24
Peak memory 200292 kb
Host smart-f7865c75-a015-42d1-b7f6-b94e80f55df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664040244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.664040244
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1448934854
Short name T474
Test name
Test status
Simulation time 99862564 ps
CPU time 0.89 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 200232 kb
Host smart-6c311143-ca52-4453-a326-bfb0a9aabd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448934854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1448934854
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2623376860
Short name T281
Test name
Test status
Simulation time 66399617 ps
CPU time 0.75 seconds
Started Aug 08 06:05:45 PM PDT 24
Finished Aug 08 06:05:46 PM PDT 24
Peak memory 200080 kb
Host smart-0769890b-d26a-4a28-b59a-eee0869b8ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623376860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2623376860
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.168467003
Short name T252
Test name
Test status
Simulation time 1883423582 ps
CPU time 7.44 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:49 PM PDT 24
Peak memory 217780 kb
Host smart-dd0b8355-b3eb-440a-83e5-09b75483b474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168467003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.168467003
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1457791940
Short name T65
Test name
Test status
Simulation time 245243875 ps
CPU time 1.01 seconds
Started Aug 08 06:05:39 PM PDT 24
Finished Aug 08 06:05:40 PM PDT 24
Peak memory 217476 kb
Host smart-9d2e4b48-54ea-4953-96bd-0392cb9fbf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457791940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1457791940
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3729414325
Short name T26
Test name
Test status
Simulation time 104232711 ps
CPU time 0.8 seconds
Started Aug 08 06:05:45 PM PDT 24
Finished Aug 08 06:05:46 PM PDT 24
Peak memory 200124 kb
Host smart-effb09ef-f344-46bf-91f9-8afb2af809ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729414325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3729414325
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.353740891
Short name T349
Test name
Test status
Simulation time 1853966239 ps
CPU time 6.55 seconds
Started Aug 08 06:05:45 PM PDT 24
Finished Aug 08 06:05:51 PM PDT 24
Peak memory 200508 kb
Host smart-0a0fdf8e-422d-4902-ab8b-26725a432d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353740891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.353740891
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.776854964
Short name T15
Test name
Test status
Simulation time 113736693 ps
CPU time 0.98 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 200372 kb
Host smart-8ae49f47-4ab1-4bd5-b659-1f4869311456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776854964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.776854964
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3018896132
Short name T326
Test name
Test status
Simulation time 123192058 ps
CPU time 1.31 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:42 PM PDT 24
Peak memory 200528 kb
Host smart-b88e502a-d730-48e1-bf8a-454e8b23ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018896132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3018896132
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2575136207
Short name T255
Test name
Test status
Simulation time 1502131884 ps
CPU time 7.65 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:05:42 PM PDT 24
Peak memory 200584 kb
Host smart-0ae4f753-2617-4fdc-98e3-3a7177c68161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575136207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2575136207
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2959388713
Short name T328
Test name
Test status
Simulation time 561277462 ps
CPU time 3.01 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:40 PM PDT 24
Peak memory 200220 kb
Host smart-9e560423-458b-4de0-b1b2-88b1b76b8653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959388713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2959388713
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2379684310
Short name T294
Test name
Test status
Simulation time 119915154 ps
CPU time 0.96 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:05:35 PM PDT 24
Peak memory 200324 kb
Host smart-998f8d75-d372-4b87-bb90-a4d91c58648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379684310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2379684310
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.133501151
Short name T333
Test name
Test status
Simulation time 79566447 ps
CPU time 0.78 seconds
Started Aug 08 06:05:40 PM PDT 24
Finished Aug 08 06:05:41 PM PDT 24
Peak memory 200204 kb
Host smart-f4aaa411-8260-4954-a678-2d5fe8065a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133501151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.133501151
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3511930891
Short name T289
Test name
Test status
Simulation time 1220826047 ps
CPU time 5.45 seconds
Started Aug 08 06:05:40 PM PDT 24
Finished Aug 08 06:05:46 PM PDT 24
Peak memory 221716 kb
Host smart-64390177-28d9-4356-96de-4456047d0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511930891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3511930891
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3565031044
Short name T397
Test name
Test status
Simulation time 244916014 ps
CPU time 1.01 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:43 PM PDT 24
Peak memory 217556 kb
Host smart-fb86146b-e449-4cc9-972e-fd34b60fbf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565031044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3565031044
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1333476328
Short name T243
Test name
Test status
Simulation time 99119455 ps
CPU time 0.74 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 200180 kb
Host smart-6e89b418-6bbd-45e9-a316-6d8e38efdd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333476328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1333476328
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2214753290
Short name T228
Test name
Test status
Simulation time 873069625 ps
CPU time 4.02 seconds
Started Aug 08 06:05:39 PM PDT 24
Finished Aug 08 06:05:43 PM PDT 24
Peak memory 200548 kb
Host smart-f4f37be2-0ed6-4f1a-b0c3-e9b8c576d0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214753290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2214753290
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1459881548
Short name T360
Test name
Test status
Simulation time 152281927 ps
CPU time 1.15 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:05:36 PM PDT 24
Peak memory 200392 kb
Host smart-994b5dee-6e62-4b05-8cf4-d820ae19bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459881548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1459881548
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.823325287
Short name T359
Test name
Test status
Simulation time 119861907 ps
CPU time 1.21 seconds
Started Aug 08 06:05:39 PM PDT 24
Finished Aug 08 06:05:40 PM PDT 24
Peak memory 200488 kb
Host smart-1f0e56b6-10ac-4d13-bf9d-ca77cb832741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823325287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.823325287
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.971867304
Short name T510
Test name
Test status
Simulation time 4564271428 ps
CPU time 19.26 seconds
Started Aug 08 06:05:40 PM PDT 24
Finished Aug 08 06:06:00 PM PDT 24
Peak memory 200628 kb
Host smart-5e1c56a3-7985-43cd-a37b-e6b8cf0060f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971867304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.971867304
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.2949222575
Short name T344
Test name
Test status
Simulation time 142741106 ps
CPU time 1.79 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 200308 kb
Host smart-c016387c-9dd7-4857-8a05-8c6c7eb1cf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949222575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.2949222575
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.341945022
Short name T3
Test name
Test status
Simulation time 93323383 ps
CPU time 0.91 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:42 PM PDT 24
Peak memory 200364 kb
Host smart-890d4986-078b-411c-9c40-a5a504eef758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341945022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.341945022
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.395258369
Short name T227
Test name
Test status
Simulation time 61326063 ps
CPU time 0.76 seconds
Started Aug 08 06:05:32 PM PDT 24
Finished Aug 08 06:05:33 PM PDT 24
Peak memory 200116 kb
Host smart-e5ce4828-f952-4b08-bff7-accbcad16f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395258369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.395258369
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1549082719
Short name T279
Test name
Test status
Simulation time 2357558439 ps
CPU time 7.93 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:49 PM PDT 24
Peak memory 217180 kb
Host smart-9be74868-dd0a-4888-8467-eb5d978388f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549082719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1549082719
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2905353565
Short name T417
Test name
Test status
Simulation time 243702699 ps
CPU time 1.05 seconds
Started Aug 08 06:05:44 PM PDT 24
Finished Aug 08 06:05:45 PM PDT 24
Peak memory 217536 kb
Host smart-7bb6f4f3-aedc-496f-adf0-205f94a3ac84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905353565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2905353565
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.4042752129
Short name T23
Test name
Test status
Simulation time 207868698 ps
CPU time 0.99 seconds
Started Aug 08 06:05:35 PM PDT 24
Finished Aug 08 06:05:36 PM PDT 24
Peak memory 200160 kb
Host smart-b1955679-2198-4d47-bb28-25a7d99885c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042752129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4042752129
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3951246001
Short name T123
Test name
Test status
Simulation time 1953375592 ps
CPU time 6.89 seconds
Started Aug 08 06:05:39 PM PDT 24
Finished Aug 08 06:05:46 PM PDT 24
Peak memory 200584 kb
Host smart-effa8be4-31e5-4284-ae86-fab0dedb0cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951246001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3951246001
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1305633263
Short name T497
Test name
Test status
Simulation time 148955104 ps
CPU time 1.16 seconds
Started Aug 08 06:05:42 PM PDT 24
Finished Aug 08 06:05:43 PM PDT 24
Peak memory 200356 kb
Host smart-24a1f926-0d89-47df-a8f0-bc31e459650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305633263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1305633263
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2744924611
Short name T213
Test name
Test status
Simulation time 122322775 ps
CPU time 1.25 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:05:35 PM PDT 24
Peak memory 200700 kb
Host smart-4989682d-3702-42e8-9f30-c0f08c45db89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744924611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2744924611
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2699844397
Short name T412
Test name
Test status
Simulation time 12269120226 ps
CPU time 39.9 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:06:15 PM PDT 24
Peak memory 200568 kb
Host smart-d873e49f-257e-4ef0-927f-e95cf86855d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699844397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2699844397
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2983067557
Short name T80
Test name
Test status
Simulation time 332524206 ps
CPU time 2.09 seconds
Started Aug 08 06:05:55 PM PDT 24
Finished Aug 08 06:05:57 PM PDT 24
Peak memory 200356 kb
Host smart-8328e08f-ceeb-49ca-98bb-1f5f08a28656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983067557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2983067557
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3596259069
Short name T456
Test name
Test status
Simulation time 150780118 ps
CPU time 1.06 seconds
Started Aug 08 06:05:40 PM PDT 24
Finished Aug 08 06:05:41 PM PDT 24
Peak memory 200356 kb
Host smart-048ca2d9-f669-4087-881c-f38cec59d90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596259069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3596259069
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2047830871
Short name T367
Test name
Test status
Simulation time 68815152 ps
CPU time 0.73 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 200176 kb
Host smart-0fa6ef86-3ce8-4966-a879-4ed752b195f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047830871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2047830871
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1429423214
Short name T246
Test name
Test status
Simulation time 1890293946 ps
CPU time 6.8 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:48 PM PDT 24
Peak memory 221724 kb
Host smart-2ee1aa45-8511-491f-bd54-bfc5968f8b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429423214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1429423214
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2204409839
Short name T380
Test name
Test status
Simulation time 244986600 ps
CPU time 1.08 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 217592 kb
Host smart-56085966-6e51-41b2-8304-964384aff412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204409839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2204409839
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1484494940
Short name T529
Test name
Test status
Simulation time 100479981 ps
CPU time 0.75 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:42 PM PDT 24
Peak memory 200116 kb
Host smart-00e3d818-4625-4573-a925-c0d4bbd0a528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484494940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1484494940
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3405511573
Short name T64
Test name
Test status
Simulation time 1489631228 ps
CPU time 5.73 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:43 PM PDT 24
Peak memory 200584 kb
Host smart-42f9cec4-4c90-4f79-8331-83bee27ab35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405511573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3405511573
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1167397200
Short name T149
Test name
Test status
Simulation time 185659828 ps
CPU time 1.17 seconds
Started Aug 08 06:05:36 PM PDT 24
Finished Aug 08 06:05:37 PM PDT 24
Peak memory 200340 kb
Host smart-8aa8dbb4-f379-4016-b9bf-a97ceda6adcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167397200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1167397200
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2201879047
Short name T445
Test name
Test status
Simulation time 119619189 ps
CPU time 1.15 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:42 PM PDT 24
Peak memory 200512 kb
Host smart-f6e971d4-04c2-45b6-86b4-31cf9db2dddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201879047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2201879047
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.2970040882
Short name T103
Test name
Test status
Simulation time 9559148720 ps
CPU time 34.17 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:06:08 PM PDT 24
Peak memory 209744 kb
Host smart-dab32417-3f53-4ea6-a4fd-e01ea81fac69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970040882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2970040882
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1573303751
Short name T450
Test name
Test status
Simulation time 300159768 ps
CPU time 1.89 seconds
Started Aug 08 06:05:51 PM PDT 24
Finished Aug 08 06:05:53 PM PDT 24
Peak memory 200304 kb
Host smart-545a3cd2-46f8-4820-a663-ce3287693932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573303751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1573303751
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1897986183
Short name T14
Test name
Test status
Simulation time 140622222 ps
CPU time 1.02 seconds
Started Aug 08 06:05:35 PM PDT 24
Finished Aug 08 06:05:36 PM PDT 24
Peak memory 200264 kb
Host smart-a913face-fca9-4b32-87b1-784ac12eb6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897986183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1897986183
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.4039417974
Short name T148
Test name
Test status
Simulation time 60566621 ps
CPU time 0.72 seconds
Started Aug 08 06:05:55 PM PDT 24
Finished Aug 08 06:05:56 PM PDT 24
Peak memory 200112 kb
Host smart-f6b76750-d047-44aa-81d2-5ec73307b2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039417974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4039417974
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2129281892
Short name T327
Test name
Test status
Simulation time 1227958962 ps
CPU time 5.54 seconds
Started Aug 08 06:05:56 PM PDT 24
Finished Aug 08 06:06:02 PM PDT 24
Peak memory 221716 kb
Host smart-5835084b-f67d-4b68-964e-7286426d0b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129281892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2129281892
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3704490279
Short name T495
Test name
Test status
Simulation time 244956349 ps
CPU time 1.05 seconds
Started Aug 08 06:05:35 PM PDT 24
Finished Aug 08 06:05:36 PM PDT 24
Peak memory 217512 kb
Host smart-6d24007b-6f89-45ac-ad3e-b43578d03853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704490279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3704490279
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2307443293
Short name T475
Test name
Test status
Simulation time 201031798 ps
CPU time 0.96 seconds
Started Aug 08 06:05:40 PM PDT 24
Finished Aug 08 06:05:41 PM PDT 24
Peak memory 200180 kb
Host smart-5ac8a52d-2d30-4d40-b065-e6a7b58168fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307443293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2307443293
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3919517644
Short name T520
Test name
Test status
Simulation time 1297494605 ps
CPU time 5.03 seconds
Started Aug 08 06:05:38 PM PDT 24
Finished Aug 08 06:05:43 PM PDT 24
Peak memory 200580 kb
Host smart-357f9397-15d8-4b31-a29b-b524c13781f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919517644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3919517644
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1834106207
Short name T155
Test name
Test status
Simulation time 109078660 ps
CPU time 1.05 seconds
Started Aug 08 06:05:50 PM PDT 24
Finished Aug 08 06:05:51 PM PDT 24
Peak memory 200380 kb
Host smart-efd1cecd-56af-45b5-b5cf-b91519389bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834106207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1834106207
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2408378129
Short name T1
Test name
Test status
Simulation time 192865558 ps
CPU time 1.43 seconds
Started Aug 08 06:05:35 PM PDT 24
Finished Aug 08 06:05:36 PM PDT 24
Peak memory 200552 kb
Host smart-020f94a5-51b1-4782-916f-e92fa1eaa13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408378129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2408378129
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1978225706
Short name T452
Test name
Test status
Simulation time 10483534745 ps
CPU time 34.91 seconds
Started Aug 08 06:05:51 PM PDT 24
Finished Aug 08 06:06:26 PM PDT 24
Peak memory 200604 kb
Host smart-a1c438d7-fc09-46ce-b5e1-380685281e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978225706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1978225706
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1642639766
Short name T324
Test name
Test status
Simulation time 379525741 ps
CPU time 2.28 seconds
Started Aug 08 06:05:55 PM PDT 24
Finished Aug 08 06:05:57 PM PDT 24
Peak memory 200248 kb
Host smart-f160ca2d-7cf8-4f33-a900-68ff5e382fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642639766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1642639766
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.289321038
Short name T504
Test name
Test status
Simulation time 218981463 ps
CPU time 1.31 seconds
Started Aug 08 06:05:48 PM PDT 24
Finished Aug 08 06:05:49 PM PDT 24
Peak memory 200392 kb
Host smart-30fd6df7-43e2-4a68-9ca2-c5c723dd328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289321038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.289321038
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2254067988
Short name T179
Test name
Test status
Simulation time 89201602 ps
CPU time 0.85 seconds
Started Aug 08 06:05:42 PM PDT 24
Finished Aug 08 06:05:43 PM PDT 24
Peak memory 200120 kb
Host smart-8f07bb72-13a9-4c76-a1d8-4ecd80061032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254067988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2254067988
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.100183692
Short name T306
Test name
Test status
Simulation time 243998032 ps
CPU time 1.16 seconds
Started Aug 08 06:05:46 PM PDT 24
Finished Aug 08 06:05:48 PM PDT 24
Peak memory 217548 kb
Host smart-d1eeb356-643c-4b86-8bac-1813314d78e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100183692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.100183692
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3807816939
Short name T22
Test name
Test status
Simulation time 110827191 ps
CPU time 0.83 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 200164 kb
Host smart-575486a9-fcf9-4163-baa0-65243073f88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807816939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3807816939
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3044296504
Short name T381
Test name
Test status
Simulation time 934339585 ps
CPU time 4.36 seconds
Started Aug 08 06:05:49 PM PDT 24
Finished Aug 08 06:05:54 PM PDT 24
Peak memory 200524 kb
Host smart-52b129e2-53bc-41fe-b1b1-ebe44a684fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044296504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3044296504
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2630588316
Short name T393
Test name
Test status
Simulation time 145947995 ps
CPU time 1.05 seconds
Started Aug 08 06:05:50 PM PDT 24
Finished Aug 08 06:05:51 PM PDT 24
Peak memory 200348 kb
Host smart-ef7bc5de-a195-4a22-881c-9cb752551531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630588316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2630588316
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2981374720
Short name T180
Test name
Test status
Simulation time 256691205 ps
CPU time 1.55 seconds
Started Aug 08 06:05:54 PM PDT 24
Finished Aug 08 06:05:56 PM PDT 24
Peak memory 200496 kb
Host smart-60df2e3f-dbcf-4c8d-affa-0073663b23f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981374720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2981374720
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1695480763
Short name T518
Test name
Test status
Simulation time 13669672993 ps
CPU time 53.25 seconds
Started Aug 08 06:05:54 PM PDT 24
Finished Aug 08 06:06:47 PM PDT 24
Peak memory 208840 kb
Host smart-578b68fb-a2c2-4814-aecf-17212cfbd437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695480763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1695480763
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.367925056
Short name T414
Test name
Test status
Simulation time 116230632 ps
CPU time 1.55 seconds
Started Aug 08 06:05:50 PM PDT 24
Finished Aug 08 06:05:52 PM PDT 24
Peak memory 200236 kb
Host smart-cf37a717-5228-42ac-94f3-db9ec99425a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367925056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.367925056
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1243178357
Short name T297
Test name
Test status
Simulation time 199902019 ps
CPU time 1.25 seconds
Started Aug 08 06:05:53 PM PDT 24
Finished Aug 08 06:05:54 PM PDT 24
Peak memory 200324 kb
Host smart-431473ec-eabb-43d5-8371-5302cedc56cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243178357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1243178357
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3675739923
Short name T186
Test name
Test status
Simulation time 77857909 ps
CPU time 0.8 seconds
Started Aug 08 06:05:39 PM PDT 24
Finished Aug 08 06:05:40 PM PDT 24
Peak memory 200160 kb
Host smart-560e29b4-b8db-41f2-8b79-9795d627d01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675739923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3675739923
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1812720497
Short name T40
Test name
Test status
Simulation time 2365673897 ps
CPU time 7.91 seconds
Started Aug 08 06:05:50 PM PDT 24
Finished Aug 08 06:05:58 PM PDT 24
Peak memory 217932 kb
Host smart-255a0623-f109-4855-9acc-61d0878698ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812720497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1812720497
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1401358249
Short name T145
Test name
Test status
Simulation time 243566479 ps
CPU time 1.14 seconds
Started Aug 08 06:05:45 PM PDT 24
Finished Aug 08 06:05:47 PM PDT 24
Peak memory 217580 kb
Host smart-a546cbed-c375-40a2-9f65-712256589c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401358249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1401358249
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2234613827
Short name T365
Test name
Test status
Simulation time 118956244 ps
CPU time 0.78 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:42 PM PDT 24
Peak memory 200180 kb
Host smart-4eb04c21-aea4-4fb2-a823-bd73a8755fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234613827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2234613827
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3480323237
Short name T122
Test name
Test status
Simulation time 1895415001 ps
CPU time 6.88 seconds
Started Aug 08 06:05:56 PM PDT 24
Finished Aug 08 06:06:03 PM PDT 24
Peak memory 200580 kb
Host smart-f83fd8bb-224c-447b-adc8-112e3d334b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480323237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3480323237
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2986348881
Short name T368
Test name
Test status
Simulation time 177914888 ps
CPU time 1.17 seconds
Started Aug 08 06:05:48 PM PDT 24
Finished Aug 08 06:05:50 PM PDT 24
Peak memory 200348 kb
Host smart-aef9b932-694d-4552-ab87-7bf682d156d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986348881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2986348881
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3272226420
Short name T188
Test name
Test status
Simulation time 117120476 ps
CPU time 1.18 seconds
Started Aug 08 06:05:47 PM PDT 24
Finished Aug 08 06:05:48 PM PDT 24
Peak memory 200460 kb
Host smart-ba28a124-efa1-44f2-8737-981ff5c68495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272226420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3272226420
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1524292723
Short name T311
Test name
Test status
Simulation time 2062293352 ps
CPU time 7.25 seconds
Started Aug 08 06:05:55 PM PDT 24
Finished Aug 08 06:06:02 PM PDT 24
Peak memory 200572 kb
Host smart-64a17c4d-1f9e-450a-9eb4-c4046b9a9fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524292723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1524292723
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.239204157
Short name T187
Test name
Test status
Simulation time 422615542 ps
CPU time 2.36 seconds
Started Aug 08 06:05:51 PM PDT 24
Finished Aug 08 06:05:54 PM PDT 24
Peak memory 208532 kb
Host smart-284c773b-f9c7-4c86-859e-003b7ce8a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239204157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.239204157
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.1626486382
Short name T352
Test name
Test status
Simulation time 145780749 ps
CPU time 1.07 seconds
Started Aug 08 06:05:49 PM PDT 24
Finished Aug 08 06:05:50 PM PDT 24
Peak memory 200376 kb
Host smart-86764535-a519-47a1-bec0-5a5a85f55a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626486382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1626486382
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1203334770
Short name T2
Test name
Test status
Simulation time 58778823 ps
CPU time 0.73 seconds
Started Aug 08 06:05:46 PM PDT 24
Finished Aug 08 06:05:47 PM PDT 24
Peak memory 200176 kb
Host smart-90c62bef-bbbe-4666-ae96-a4eb603c766c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203334770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1203334770
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3011456979
Short name T60
Test name
Test status
Simulation time 2175627067 ps
CPU time 7.66 seconds
Started Aug 08 06:05:44 PM PDT 24
Finished Aug 08 06:05:52 PM PDT 24
Peak memory 217804 kb
Host smart-d857adbd-2bd8-4f13-83aa-04d846aed741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011456979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3011456979
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1026341599
Short name T488
Test name
Test status
Simulation time 244528927 ps
CPU time 1.06 seconds
Started Aug 08 06:05:50 PM PDT 24
Finished Aug 08 06:05:51 PM PDT 24
Peak memory 217608 kb
Host smart-18e00486-da21-40b6-828e-049225ee8d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026341599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1026341599
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.1772812835
Short name T20
Test name
Test status
Simulation time 163445246 ps
CPU time 0.85 seconds
Started Aug 08 06:05:50 PM PDT 24
Finished Aug 08 06:05:51 PM PDT 24
Peak memory 200128 kb
Host smart-aeace82f-2842-4e9c-862d-91cf1d1c1076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772812835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1772812835
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.473740300
Short name T390
Test name
Test status
Simulation time 1337035435 ps
CPU time 5.55 seconds
Started Aug 08 06:05:41 PM PDT 24
Finished Aug 08 06:05:47 PM PDT 24
Peak memory 200604 kb
Host smart-419dd1d4-c4ac-44fe-8257-28083d41d704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473740300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.473740300
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1414276270
Short name T314
Test name
Test status
Simulation time 99069158 ps
CPU time 1.01 seconds
Started Aug 08 06:05:45 PM PDT 24
Finished Aug 08 06:05:46 PM PDT 24
Peak memory 200304 kb
Host smart-4e3c5886-d63e-4b42-a428-9c9aeb8c8cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414276270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1414276270
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.553893154
Short name T384
Test name
Test status
Simulation time 124329555 ps
CPU time 1.17 seconds
Started Aug 08 06:05:49 PM PDT 24
Finished Aug 08 06:05:51 PM PDT 24
Peak memory 200488 kb
Host smart-b195d0ab-5857-4e0a-8b60-eb3e55f42c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553893154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.553893154
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.210812237
Short name T424
Test name
Test status
Simulation time 3116262118 ps
CPU time 13.69 seconds
Started Aug 08 06:05:38 PM PDT 24
Finished Aug 08 06:05:52 PM PDT 24
Peak memory 208752 kb
Host smart-2b929782-535e-4e6c-91d5-49e77e9aba9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210812237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.210812237
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.4187244888
Short name T172
Test name
Test status
Simulation time 266250312 ps
CPU time 1.8 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:39 PM PDT 24
Peak memory 200316 kb
Host smart-fb7bae66-2ce5-4bc7-8780-4dbb11bd0ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187244888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4187244888
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3440870907
Short name T403
Test name
Test status
Simulation time 88563873 ps
CPU time 0.83 seconds
Started Aug 08 06:05:50 PM PDT 24
Finished Aug 08 06:05:51 PM PDT 24
Peak memory 200368 kb
Host smart-a98e17f8-f07b-4377-8080-346f989f3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440870907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3440870907
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.451193728
Short name T317
Test name
Test status
Simulation time 72778767 ps
CPU time 0.83 seconds
Started Aug 08 06:05:38 PM PDT 24
Finished Aug 08 06:05:39 PM PDT 24
Peak memory 200368 kb
Host smart-0b266aa3-6557-4349-b53e-8b2693108c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451193728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.451193728
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2906219398
Short name T220
Test name
Test status
Simulation time 1892003775 ps
CPU time 6.96 seconds
Started Aug 08 06:05:51 PM PDT 24
Finished Aug 08 06:05:58 PM PDT 24
Peak memory 217784 kb
Host smart-0ea06dbd-6cd3-415d-b026-88ae3bb2d313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906219398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2906219398
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3861201972
Short name T392
Test name
Test status
Simulation time 244703218 ps
CPU time 1.09 seconds
Started Aug 08 06:05:48 PM PDT 24
Finished Aug 08 06:05:49 PM PDT 24
Peak memory 217460 kb
Host smart-8bd23473-6cb0-4154-987c-62453d44ae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861201972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3861201972
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1048867255
Short name T362
Test name
Test status
Simulation time 164455517 ps
CPU time 0.82 seconds
Started Aug 08 06:05:50 PM PDT 24
Finished Aug 08 06:05:51 PM PDT 24
Peak memory 200120 kb
Host smart-9e63a502-d459-4050-8d39-28e254560bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048867255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1048867255
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.778356511
Short name T280
Test name
Test status
Simulation time 876950991 ps
CPU time 4.08 seconds
Started Aug 08 06:05:54 PM PDT 24
Finished Aug 08 06:05:58 PM PDT 24
Peak memory 200560 kb
Host smart-fee4c829-527a-461e-8ed6-a2154c81d393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778356511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.778356511
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4135665274
Short name T282
Test name
Test status
Simulation time 147784829 ps
CPU time 1.16 seconds
Started Aug 08 06:05:34 PM PDT 24
Finished Aug 08 06:05:35 PM PDT 24
Peak memory 200340 kb
Host smart-f6909ddd-7f71-41de-af89-45ada304a51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135665274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4135665274
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1965361373
Short name T156
Test name
Test status
Simulation time 120069171 ps
CPU time 1.15 seconds
Started Aug 08 06:05:56 PM PDT 24
Finished Aug 08 06:05:57 PM PDT 24
Peak memory 200504 kb
Host smart-e120decd-efca-43f1-83ff-a7a7619a2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965361373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1965361373
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1013589437
Short name T421
Test name
Test status
Simulation time 5995746923 ps
CPU time 19.82 seconds
Started Aug 08 06:05:45 PM PDT 24
Finished Aug 08 06:06:05 PM PDT 24
Peak memory 208844 kb
Host smart-a1c313c0-c0ed-4ac1-a838-5dd6ab5f37fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013589437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1013589437
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2712584159
Short name T27
Test name
Test status
Simulation time 140822148 ps
CPU time 1.82 seconds
Started Aug 08 06:05:37 PM PDT 24
Finished Aug 08 06:05:38 PM PDT 24
Peak memory 200188 kb
Host smart-b99a3200-38ac-4eed-8445-921de8a43659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712584159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2712584159
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1761769215
Short name T197
Test name
Test status
Simulation time 162819668 ps
CPU time 1.24 seconds
Started Aug 08 06:05:46 PM PDT 24
Finished Aug 08 06:05:47 PM PDT 24
Peak memory 200408 kb
Host smart-9a9d1845-b446-4e48-926a-959181add860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761769215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1761769215
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1091475999
Short name T193
Test name
Test status
Simulation time 69527273 ps
CPU time 0.78 seconds
Started Aug 08 06:05:48 PM PDT 24
Finished Aug 08 06:05:48 PM PDT 24
Peak memory 200200 kb
Host smart-6a646e5c-f7fc-4480-a741-a3eb33f8c4e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091475999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1091475999
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1355688017
Short name T406
Test name
Test status
Simulation time 1928634923 ps
CPU time 7.33 seconds
Started Aug 08 06:05:56 PM PDT 24
Finished Aug 08 06:06:03 PM PDT 24
Peak memory 217776 kb
Host smart-dd4afc40-b46b-4b66-9ae4-425d3c7bd1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355688017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1355688017
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.17612408
Short name T164
Test name
Test status
Simulation time 244236566 ps
CPU time 1.12 seconds
Started Aug 08 06:05:38 PM PDT 24
Finished Aug 08 06:05:39 PM PDT 24
Peak memory 217448 kb
Host smart-63ba3db7-7a7b-47fa-99db-b642fb0e776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17612408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.17612408
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1569847438
Short name T446
Test name
Test status
Simulation time 155903832 ps
CPU time 0.86 seconds
Started Aug 08 06:05:35 PM PDT 24
Finished Aug 08 06:05:36 PM PDT 24
Peak memory 200076 kb
Host smart-06011fb6-b089-4de4-90f2-e2b1509df29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569847438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1569847438
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1683741973
Short name T249
Test name
Test status
Simulation time 1538469570 ps
CPU time 6.16 seconds
Started Aug 08 06:05:38 PM PDT 24
Finished Aug 08 06:05:44 PM PDT 24
Peak memory 200496 kb
Host smart-23790573-756a-4ece-850c-37b13cbc163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683741973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1683741973
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3671605153
Short name T430
Test name
Test status
Simulation time 141402110 ps
CPU time 1.08 seconds
Started Aug 08 06:05:51 PM PDT 24
Finished Aug 08 06:05:52 PM PDT 24
Peak memory 200380 kb
Host smart-9bf63417-8b0d-4621-9bd1-68a32d948651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671605153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3671605153
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1953416811
Short name T338
Test name
Test status
Simulation time 196243409 ps
CPU time 1.33 seconds
Started Aug 08 06:06:00 PM PDT 24
Finished Aug 08 06:06:01 PM PDT 24
Peak memory 200452 kb
Host smart-9c65df54-f15c-4894-b403-8692891a8155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953416811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1953416811
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3553432454
Short name T307
Test name
Test status
Simulation time 6740075783 ps
CPU time 21.77 seconds
Started Aug 08 06:05:53 PM PDT 24
Finished Aug 08 06:06:15 PM PDT 24
Peak memory 210168 kb
Host smart-b7cda6f5-a6fc-4560-8a0e-6cba38223c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553432454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3553432454
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3789351925
Short name T331
Test name
Test status
Simulation time 138658475 ps
CPU time 1.76 seconds
Started Aug 08 06:05:44 PM PDT 24
Finished Aug 08 06:05:46 PM PDT 24
Peak memory 208448 kb
Host smart-4ca6d921-d049-4184-a8b0-6bd4a98e5679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789351925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3789351925
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1396702896
Short name T46
Test name
Test status
Simulation time 228872173 ps
CPU time 1.29 seconds
Started Aug 08 06:05:53 PM PDT 24
Finished Aug 08 06:05:54 PM PDT 24
Peak memory 200356 kb
Host smart-6bb7caf4-0ba5-47d7-9ae5-9d2feab0d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396702896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1396702896
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1642592327
Short name T260
Test name
Test status
Simulation time 99572440 ps
CPU time 0.82 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 200152 kb
Host smart-575383cd-6dac-4962-bb56-0300db2850eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642592327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1642592327
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3477285605
Short name T43
Test name
Test status
Simulation time 2373558410 ps
CPU time 8.16 seconds
Started Aug 08 06:04:40 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 217160 kb
Host smart-f20f34d8-9430-4a61-a365-7ff458a01f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477285605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3477285605
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.184970428
Short name T30
Test name
Test status
Simulation time 244569407 ps
CPU time 1.04 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 217548 kb
Host smart-8e392068-336a-4363-b652-71544bc92066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184970428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.184970428
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.357831647
Short name T18
Test name
Test status
Simulation time 212328312 ps
CPU time 0.89 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 200104 kb
Host smart-678d63e9-0c38-45c5-990c-dc4ac5ca4202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357831647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.357831647
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1526413635
Short name T526
Test name
Test status
Simulation time 2116085549 ps
CPU time 7.43 seconds
Started Aug 08 06:04:52 PM PDT 24
Finished Aug 08 06:04:59 PM PDT 24
Peak memory 200604 kb
Host smart-46f14f49-c208-4a67-b9a5-eea5e9a2951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526413635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1526413635
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2898703455
Short name T33
Test name
Test status
Simulation time 149704778 ps
CPU time 1.1 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 200184 kb
Host smart-9c31484e-4422-4602-897f-61834d8dfc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898703455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2898703455
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.4224200527
Short name T206
Test name
Test status
Simulation time 118289407 ps
CPU time 1.18 seconds
Started Aug 08 06:04:48 PM PDT 24
Finished Aug 08 06:04:49 PM PDT 24
Peak memory 200528 kb
Host smart-9b1ab870-dcde-4d59-8a18-46fab4156540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224200527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.4224200527
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.996622810
Short name T312
Test name
Test status
Simulation time 2635131157 ps
CPU time 10.73 seconds
Started Aug 08 06:04:51 PM PDT 24
Finished Aug 08 06:05:02 PM PDT 24
Peak memory 208812 kb
Host smart-d73bfc32-7d6a-4127-98a4-53497aff575b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996622810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.996622810
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1347929404
Short name T466
Test name
Test status
Simulation time 150118720 ps
CPU time 1.87 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 200188 kb
Host smart-f0d64ee1-dc4b-4a65-a74a-e0d625c740ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347929404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1347929404
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.796193436
Short name T241
Test name
Test status
Simulation time 170568694 ps
CPU time 1.25 seconds
Started Aug 08 06:04:46 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 200312 kb
Host smart-e0d694f2-1379-4f8f-b1ad-de89d6c504de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796193436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.796193436
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3227962805
Short name T177
Test name
Test status
Simulation time 89286717 ps
CPU time 0.87 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 200132 kb
Host smart-43f4409b-b8a2-4e1c-9dc1-87c7e50e7d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227962805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3227962805
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1926037979
Short name T322
Test name
Test status
Simulation time 2359098349 ps
CPU time 8.05 seconds
Started Aug 08 06:04:49 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 221744 kb
Host smart-38458e56-58cc-49c1-b590-934dc978fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926037979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1926037979
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3291310027
Short name T334
Test name
Test status
Simulation time 244208656 ps
CPU time 1.02 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 217448 kb
Host smart-b93610a4-ed35-4b66-8c59-28aa7d52a0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291310027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3291310027
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.968314797
Short name T218
Test name
Test status
Simulation time 190316576 ps
CPU time 0.85 seconds
Started Aug 08 06:04:47 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 200092 kb
Host smart-cde92264-77c8-472d-878f-bc392b23bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968314797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.968314797
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2944363507
Short name T382
Test name
Test status
Simulation time 1494075744 ps
CPU time 6.24 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:49 PM PDT 24
Peak memory 200600 kb
Host smart-c0c9c27e-a057-4a95-8337-31a25608e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944363507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2944363507
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2048380038
Short name T190
Test name
Test status
Simulation time 137871007 ps
CPU time 1.1 seconds
Started Aug 08 06:04:48 PM PDT 24
Finished Aug 08 06:04:49 PM PDT 24
Peak memory 200292 kb
Host smart-dc398919-4c50-47ee-9dd3-d4770a030d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048380038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2048380038
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.675393150
Short name T400
Test name
Test status
Simulation time 248873449 ps
CPU time 1.48 seconds
Started Aug 08 06:04:49 PM PDT 24
Finished Aug 08 06:04:51 PM PDT 24
Peak memory 200512 kb
Host smart-47ba12de-d8b7-4461-b05b-ff14818d8c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675393150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.675393150
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1083284595
Short name T396
Test name
Test status
Simulation time 3907108239 ps
CPU time 16.11 seconds
Started Aug 08 06:04:48 PM PDT 24
Finished Aug 08 06:05:04 PM PDT 24
Peak memory 200556 kb
Host smart-38f4b84a-592b-41b9-a39c-3008e8b4f9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083284595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1083284595
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.499614117
Short name T364
Test name
Test status
Simulation time 429078003 ps
CPU time 2.49 seconds
Started Aug 08 06:04:49 PM PDT 24
Finished Aug 08 06:04:52 PM PDT 24
Peak memory 200292 kb
Host smart-00cd634b-f7e6-423c-b226-0579bd17a982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499614117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.499614117
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1163997383
Short name T470
Test name
Test status
Simulation time 148829337 ps
CPU time 1.07 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 200260 kb
Host smart-740e223a-6f54-4665-b559-6485ff0464e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163997383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1163997383
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.585739338
Short name T208
Test name
Test status
Simulation time 69956031 ps
CPU time 0.83 seconds
Started Aug 08 06:04:35 PM PDT 24
Finished Aug 08 06:04:36 PM PDT 24
Peak memory 200152 kb
Host smart-7253274d-21dc-4704-ab6e-72dd00bf32f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585739338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.585739338
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1015148881
Short name T389
Test name
Test status
Simulation time 1891871304 ps
CPU time 7.35 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:51 PM PDT 24
Peak memory 217580 kb
Host smart-308a0d10-8810-4e2e-8473-e24c7c965409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015148881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1015148881
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3715081881
Short name T251
Test name
Test status
Simulation time 244325819 ps
CPU time 1.07 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:44 PM PDT 24
Peak memory 217468 kb
Host smart-25d87351-bb71-44c4-9d6c-79cbf70ba7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715081881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3715081881
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1181930477
Short name T449
Test name
Test status
Simulation time 97731247 ps
CPU time 0.78 seconds
Started Aug 08 06:04:49 PM PDT 24
Finished Aug 08 06:04:50 PM PDT 24
Peak memory 200160 kb
Host smart-c27e7566-eab7-4d19-ac31-dd035a9763a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181930477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1181930477
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3929122389
Short name T303
Test name
Test status
Simulation time 2002458253 ps
CPU time 7.04 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:05:01 PM PDT 24
Peak memory 200580 kb
Host smart-7e0ba9f8-e143-4728-bf26-4ecc6592b68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929122389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3929122389
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2538771567
Short name T185
Test name
Test status
Simulation time 184397741 ps
CPU time 1.16 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:47 PM PDT 24
Peak memory 200260 kb
Host smart-459bf5fc-01a8-4212-a81e-5c8c57489c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538771567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2538771567
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.203809816
Short name T202
Test name
Test status
Simulation time 125083092 ps
CPU time 1.19 seconds
Started Aug 08 06:04:47 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 200496 kb
Host smart-08ed92c6-b9d9-44a2-b646-8e85b25e6c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203809816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.203809816
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3550305746
Short name T507
Test name
Test status
Simulation time 11096533869 ps
CPU time 37.49 seconds
Started Aug 08 06:04:39 PM PDT 24
Finished Aug 08 06:05:16 PM PDT 24
Peak memory 200624 kb
Host smart-7410c212-efa7-4240-8b83-d6d315ddb79d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550305746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3550305746
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3017348045
Short name T157
Test name
Test status
Simulation time 143158489 ps
CPU time 1.71 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 200304 kb
Host smart-a3543ebc-5d7a-4eb3-957b-b265248c3e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017348045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3017348045
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3966375151
Short name T136
Test name
Test status
Simulation time 139609539 ps
CPU time 1.2 seconds
Started Aug 08 06:04:39 PM PDT 24
Finished Aug 08 06:04:41 PM PDT 24
Peak memory 200352 kb
Host smart-88f7869a-0765-4e6e-921f-ca51673f15d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966375151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3966375151
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3120537687
Short name T388
Test name
Test status
Simulation time 61120846 ps
CPU time 0.78 seconds
Started Aug 08 06:04:40 PM PDT 24
Finished Aug 08 06:04:41 PM PDT 24
Peak memory 200188 kb
Host smart-04ad9823-7a85-4bd7-b2b6-68b2a20c9c9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120537687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3120537687
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1923175756
Short name T59
Test name
Test status
Simulation time 1229339836 ps
CPU time 5.54 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:49 PM PDT 24
Peak memory 217664 kb
Host smart-f88b7606-047a-4f82-83cb-b74c468b94ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923175756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1923175756
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2937581917
Short name T435
Test name
Test status
Simulation time 245029507 ps
CPU time 1.08 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:47 PM PDT 24
Peak memory 217592 kb
Host smart-8c912b80-b9dd-4bf0-a436-1e2267df998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937581917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.2937581917
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2608851151
Short name T490
Test name
Test status
Simulation time 118329410 ps
CPU time 0.75 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:04:56 PM PDT 24
Peak memory 200164 kb
Host smart-843b66a1-d478-4f3d-beab-d271fc6d5cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608851151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2608851151
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3060914474
Short name T203
Test name
Test status
Simulation time 1129368107 ps
CPU time 5.06 seconds
Started Aug 08 06:04:45 PM PDT 24
Finished Aug 08 06:04:50 PM PDT 24
Peak memory 200548 kb
Host smart-1707e0c0-b42e-4b6b-9ccd-97b38b7a8b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060914474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3060914474
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1733138371
Short name T318
Test name
Test status
Simulation time 144537055 ps
CPU time 1.14 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:46 PM PDT 24
Peak memory 200340 kb
Host smart-e63165f5-56c7-41e7-8de8-45f491dbf27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733138371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1733138371
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2607224106
Short name T236
Test name
Test status
Simulation time 203580640 ps
CPU time 1.39 seconds
Started Aug 08 06:04:50 PM PDT 24
Finished Aug 08 06:04:51 PM PDT 24
Peak memory 200528 kb
Host smart-1714a3e5-2836-4dd9-bfd0-9e912f81cdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607224106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2607224106
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3390472312
Short name T442
Test name
Test status
Simulation time 6149002282 ps
CPU time 21.07 seconds
Started Aug 08 06:04:49 PM PDT 24
Finished Aug 08 06:05:10 PM PDT 24
Peak memory 217016 kb
Host smart-dc586b10-58b1-420c-8471-bff5bec54a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390472312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3390472312
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3516680715
Short name T270
Test name
Test status
Simulation time 122566548 ps
CPU time 1.6 seconds
Started Aug 08 06:04:48 PM PDT 24
Finished Aug 08 06:04:49 PM PDT 24
Peak memory 208496 kb
Host smart-d606ea73-f3be-484f-9ce1-2b42e8154102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516680715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3516680715
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1974323808
Short name T477
Test name
Test status
Simulation time 70620484 ps
CPU time 0.76 seconds
Started Aug 08 06:04:42 PM PDT 24
Finished Aug 08 06:04:43 PM PDT 24
Peak memory 200360 kb
Host smart-84945912-4ead-4c2c-9ae2-426b7b6f3d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974323808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1974323808
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3145347480
Short name T540
Test name
Test status
Simulation time 79828975 ps
CPU time 0.87 seconds
Started Aug 08 06:04:50 PM PDT 24
Finished Aug 08 06:04:52 PM PDT 24
Peak memory 200112 kb
Host smart-a60c4036-c19b-41d3-a779-4c6ad940dc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145347480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3145347480
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1207247642
Short name T346
Test name
Test status
Simulation time 1221667460 ps
CPU time 5.59 seconds
Started Aug 08 06:04:57 PM PDT 24
Finished Aug 08 06:05:03 PM PDT 24
Peak memory 217764 kb
Host smart-364cd985-b4f0-4314-9a08-c2e5f7b81de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207247642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1207247642
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3023715711
Short name T175
Test name
Test status
Simulation time 243787733 ps
CPU time 1.09 seconds
Started Aug 08 06:04:43 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 217616 kb
Host smart-5bd198ed-46d3-46fa-a1b1-7650860d8fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023715711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3023715711
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.781578154
Short name T434
Test name
Test status
Simulation time 179149646 ps
CPU time 0.97 seconds
Started Aug 08 06:04:47 PM PDT 24
Finished Aug 08 06:04:48 PM PDT 24
Peak memory 200188 kb
Host smart-632e0cb5-a837-4233-8b39-a22638810b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781578154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.781578154
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3957086806
Short name T269
Test name
Test status
Simulation time 914204090 ps
CPU time 4.41 seconds
Started Aug 08 06:04:51 PM PDT 24
Finished Aug 08 06:04:55 PM PDT 24
Peak memory 200480 kb
Host smart-4168f02f-903a-4089-89a4-3b5d70bf1bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957086806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3957086806
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.978395401
Short name T428
Test name
Test status
Simulation time 164864768 ps
CPU time 1.26 seconds
Started Aug 08 06:04:44 PM PDT 24
Finished Aug 08 06:04:45 PM PDT 24
Peak memory 200240 kb
Host smart-65053d72-1313-456a-8e1e-aeebd0642c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978395401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.978395401
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.706935105
Short name T468
Test name
Test status
Simulation time 198621834 ps
CPU time 1.34 seconds
Started Aug 08 06:04:59 PM PDT 24
Finished Aug 08 06:05:00 PM PDT 24
Peak memory 200576 kb
Host smart-e23fcf71-0dab-4ee2-82e9-9f2d1708c598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706935105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.706935105
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3424177613
Short name T150
Test name
Test status
Simulation time 386989776 ps
CPU time 1.75 seconds
Started Aug 08 06:04:53 PM PDT 24
Finished Aug 08 06:04:55 PM PDT 24
Peak memory 200504 kb
Host smart-f5c89961-0117-430f-8547-00e40314cbf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424177613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3424177613
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.621769274
Short name T240
Test name
Test status
Simulation time 371749017 ps
CPU time 2.32 seconds
Started Aug 08 06:04:48 PM PDT 24
Finished Aug 08 06:04:50 PM PDT 24
Peak memory 200304 kb
Host smart-c3ce73ae-e5e5-4db1-b97b-7d1a824acd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621769274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.621769274
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2563174320
Short name T182
Test name
Test status
Simulation time 107532326 ps
CPU time 1.06 seconds
Started Aug 08 06:04:55 PM PDT 24
Finished Aug 08 06:04:57 PM PDT 24
Peak memory 200352 kb
Host smart-ee883773-87fb-4a6e-9577-6ccec7803fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563174320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2563174320
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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