Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8278

1

T3

22

T6

22

T10

18

auto[1]

10949

1

T2

4

T3

79

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6057	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6398	1			T1	1		T2	2		T3	27
reset_info_cp[2]	2936	1			T2	1		T3	14		T4	1
reset_info_cp[4]	3902	1			T2	1		T3	15		T4	1
reset_info_cp[8]	119	1			T6	1		T10	1		T12	1
reset_info_cp[16]	105	1			T3	1		T12	1		T13	2
reset_info_cp[32]	123	1			T2	1		T10	1		T12	4
reset_info_cp[64]	99	1			T3	1		T6	1		T10	1
reset_info_cp[128]	108	1			T3	2		T10	1		T13	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3103	1			T3	22		T6	22		T10	18
reset_info_cp[1]	auto[1]	2675	1			T2	1		T3	4		T4	1
reset_info_cp[2]	auto[0]	937	1			T13	19		T29	3		T51	28
reset_info_cp[2]	auto[1]	1999	1			T2	1		T3	14		T4	1
reset_info_cp[4]	auto[0]	1397	1			T13	35		T29	4		T51	36
reset_info_cp[4]	auto[1]	2505	1			T2	1		T3	15		T4	1
reset_info_cp[8]	auto[0]	52	1			T12	1		T89	1		T41	1
reset_info_cp[8]	auto[1]	67	1			T6	1		T10	1		T51	1
reset_info_cp[16]	auto[0]	37	1			T12	1		T13	1		T51	1
reset_info_cp[16]	auto[1]	68	1			T3	1		T13	1		T51	1
reset_info_cp[32]	auto[0]	58	1			T12	3		T13	1		T89	1
reset_info_cp[32]	auto[1]	65	1			T2	1		T10	1		T12	1
reset_info_cp[64]	auto[0]	47	1			T29	1		T41	2		T74	1
reset_info_cp[64]	auto[1]	52	1			T3	1		T6	1		T10	1
reset_info_cp[128]	auto[0]	30	1			T13	1		T51	1		T74	1
reset_info_cp[128]	auto[1]	78	1			T3	2		T10	1		T51	2