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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.43 99.40 99.24 99.87 99.83 99.46 98.77


Total test records in report: 620
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T537 /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3053342489 Aug 09 07:10:34 PM PDT 24 Aug 09 07:10:35 PM PDT 24 174749947 ps
T538 /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.272741548 Aug 09 07:09:48 PM PDT 24 Aug 09 07:09:49 PM PDT 24 110166605 ps
T539 /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3422500378 Aug 09 07:10:14 PM PDT 24 Aug 09 07:10:15 PM PDT 24 137289047 ps
T540 /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2310070972 Aug 09 07:10:17 PM PDT 24 Aug 09 07:10:18 PM PDT 24 244407053 ps
T541 /workspace/coverage/default/12.rstmgr_reset.1678172930 Aug 09 07:09:42 PM PDT 24 Aug 09 07:09:49 PM PDT 24 1637217420 ps
T57 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2210200627 Aug 09 07:10:48 PM PDT 24 Aug 09 07:10:50 PM PDT 24 355699892 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1789212410 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 108402255 ps
T61 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4230405245 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:57 PM PDT 24 118624505 ps
T62 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1698113526 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 282070686 ps
T59 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2921642086 Aug 09 07:10:56 PM PDT 24 Aug 09 07:10:58 PM PDT 24 514210891 ps
T60 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1015513840 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 126450756 ps
T63 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3273425734 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:57 PM PDT 24 922912131 ps
T76 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2343236930 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:57 PM PDT 24 404542506 ps
T542 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2696184943 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:53 PM PDT 24 76984451 ps
T543 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3775417892 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 123952051 ps
T80 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2720583997 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:57 PM PDT 24 199693228 ps
T78 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2539383154 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:55 PM PDT 24 494654825 ps
T103 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1621167475 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:55 PM PDT 24 124739542 ps
T104 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1834653329 Aug 09 07:10:56 PM PDT 24 Aug 09 07:10:57 PM PDT 24 91287620 ps
T119 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.962980615 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:57 PM PDT 24 492738922 ps
T79 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1843456334 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 177285968 ps
T105 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4053216056 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:56 PM PDT 24 80578448 ps
T93 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3332267431 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 151779867 ps
T87 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4255286514 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:57 PM PDT 24 109707535 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4285645732 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:51 PM PDT 24 87788881 ps
T106 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2853970981 Aug 09 07:10:54 PM PDT 24 Aug 09 07:11:01 PM PDT 24 275867895 ps
T545 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3737644356 Aug 09 07:10:56 PM PDT 24 Aug 09 07:10:56 PM PDT 24 65161004 ps
T77 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1790715572 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 432695322 ps
T546 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2230929975 Aug 09 07:10:56 PM PDT 24 Aug 09 07:11:00 PM PDT 24 270154000 ps
T94 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3495610443 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:57 PM PDT 24 188530701 ps
T88 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.650180507 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:51 PM PDT 24 179117897 ps
T547 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1136136065 Aug 09 07:10:56 PM PDT 24 Aug 09 07:10:57 PM PDT 24 81813479 ps
T548 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4228963743 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:50 PM PDT 24 114954963 ps
T107 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2329581661 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:51 PM PDT 24 228867074 ps
T81 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3107632884 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:58 PM PDT 24 978502094 ps
T549 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2723019885 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 116157338 ps
T108 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2316540459 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:56 PM PDT 24 125120654 ps
T82 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4026298724 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:54 PM PDT 24 879414855 ps
T550 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.676224153 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:51 PM PDT 24 183910297 ps
T551 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.728531803 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:52 PM PDT 24 58823017 ps
T552 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3588001188 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:52 PM PDT 24 200782661 ps
T109 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3288803047 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:56 PM PDT 24 95663160 ps
T553 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3465560313 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:57 PM PDT 24 515736540 ps
T554 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3486834026 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 83706996 ps
T110 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2735800400 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 276318036 ps
T555 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.550675369 Aug 09 07:10:56 PM PDT 24 Aug 09 07:11:03 PM PDT 24 144363387 ps
T84 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.629938774 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 462952324 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2160954103 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:52 PM PDT 24 437166945 ps
T557 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1445195716 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:52 PM PDT 24 159652588 ps
T558 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1454395814 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:55 PM PDT 24 83369703 ps
T111 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3444011519 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:53 PM PDT 24 107440223 ps
T559 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.311133488 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:57 PM PDT 24 435496597 ps
T112 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.589493271 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:50 PM PDT 24 74121346 ps
T560 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1643295952 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:54 PM PDT 24 468164901 ps
T561 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.165550753 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:57 PM PDT 24 114152074 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.29130833 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:50 PM PDT 24 87740113 ps
T85 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2817651266 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:52 PM PDT 24 416918060 ps
T563 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3245583915 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:53 PM PDT 24 121116994 ps
T564 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2220185964 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 206821722 ps
T565 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4127204777 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:55 PM PDT 24 118690263 ps
T566 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1687620268 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 64822746 ps
T567 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1110761609 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:53 PM PDT 24 272082439 ps
T568 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1954739548 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:55 PM PDT 24 106165098 ps
T83 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2314596225 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:58 PM PDT 24 479568819 ps
T569 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3272592879 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:53 PM PDT 24 493775055 ps
T570 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1740080958 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:51 PM PDT 24 103114720 ps
T571 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3843222613 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:57 PM PDT 24 127189589 ps
T572 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2012837877 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:50 PM PDT 24 99816547 ps
T98 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3866307666 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:52 PM PDT 24 84986848 ps
T573 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.588826440 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:53 PM PDT 24 56575849 ps
T574 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1594839726 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 104456904 ps
T575 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2355012545 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:52 PM PDT 24 76863648 ps
T576 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1845996009 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 199367248 ps
T577 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3542723962 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 225741943 ps
T117 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2764604400 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:55 PM PDT 24 792666018 ps
T578 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3462299568 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:56 PM PDT 24 429275237 ps
T579 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.971896873 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:56 PM PDT 24 806244023 ps
T580 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2342436503 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:55 PM PDT 24 60370110 ps
T581 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3603703855 Aug 09 07:10:56 PM PDT 24 Aug 09 07:10:57 PM PDT 24 113607359 ps
T118 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3898100644 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:54 PM PDT 24 950623750 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2337098999 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:50 PM PDT 24 79899273 ps
T583 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2290357290 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:55 PM PDT 24 209357260 ps
T584 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3981588115 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 74570052 ps
T585 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4285858271 Aug 09 07:10:48 PM PDT 24 Aug 09 07:10:54 PM PDT 24 488532355 ps
T586 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3809611442 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:52 PM PDT 24 520787195 ps
T587 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1501795479 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:56 PM PDT 24 133697011 ps
T588 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1551801023 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:55 PM PDT 24 565195969 ps
T589 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3627987108 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:54 PM PDT 24 955907036 ps
T590 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.556902504 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 65446622 ps
T591 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2096970591 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 466365791 ps
T592 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.746367109 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 120995150 ps
T593 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.643077796 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:55 PM PDT 24 436989303 ps
T594 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.313787946 Aug 09 07:10:46 PM PDT 24 Aug 09 07:10:50 PM PDT 24 513249710 ps
T595 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.885320286 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 116747704 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3062720099 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:52 PM PDT 24 142358576 ps
T597 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2979857786 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:55 PM PDT 24 122276308 ps
T86 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1167744111 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:57 PM PDT 24 947453388 ps
T598 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3716065278 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:58 PM PDT 24 372201090 ps
T599 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.287554413 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:55 PM PDT 24 183111405 ps
T600 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2120773639 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 98205949 ps
T601 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2146590478 Aug 09 07:10:56 PM PDT 24 Aug 09 07:11:02 PM PDT 24 74151585 ps
T602 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2814900319 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:52 PM PDT 24 100072810 ps
T603 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.240206918 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 133814896 ps
T604 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1038412725 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 289666067 ps
T605 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4050781883 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:57 PM PDT 24 213997574 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2168781292 Aug 09 07:10:54 PM PDT 24 Aug 09 07:10:56 PM PDT 24 436036105 ps
T607 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3373214093 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:56 PM PDT 24 358168176 ps
T608 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.816365588 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:56 PM PDT 24 133452633 ps
T609 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1841482133 Aug 09 07:10:53 PM PDT 24 Aug 09 07:10:54 PM PDT 24 66440565 ps
T610 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1618170321 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:51 PM PDT 24 187578740 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3420251775 Aug 09 07:10:51 PM PDT 24 Aug 09 07:10:53 PM PDT 24 204577729 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2038290811 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:53 PM PDT 24 73206202 ps
T613 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.502058509 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:50 PM PDT 24 103283074 ps
T614 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2546747924 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 114484082 ps
T615 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.567464425 Aug 09 07:10:55 PM PDT 24 Aug 09 07:10:56 PM PDT 24 58943069 ps
T616 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.180419470 Aug 09 07:10:49 PM PDT 24 Aug 09 07:10:51 PM PDT 24 133574431 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1778561494 Aug 09 07:10:52 PM PDT 24 Aug 09 07:10:54 PM PDT 24 107072737 ps
T618 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.953113548 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:52 PM PDT 24 430285324 ps
T619 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.119337795 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:52 PM PDT 24 156787927 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.513349905 Aug 09 07:10:50 PM PDT 24 Aug 09 07:10:52 PM PDT 24 176870613 ps

Test location /workspace/coverage/default/19.rstmgr_smoke.506973767
Short name T4
Test name
Test status
Simulation time 119499448 ps
CPU time 1.17 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200520 kb
Host smart-4b7a2c5b-1776-4249-bbed-4f5f2da31a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506973767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.506973767
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1242825899
Short name T13
Test name
Test status
Simulation time 5052187732 ps
CPU time 22.65 seconds
Started Aug 09 07:09:44 PM PDT 24
Finished Aug 09 07:10:07 PM PDT 24
Peak memory 208752 kb
Host smart-ae9ff018-94d5-438f-b8cb-09b0ac82e71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242825899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1242825899
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3273425734
Short name T63
Test name
Test status
Simulation time 922912131 ps
CPU time 3.59 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 200192 kb
Host smart-2e63686c-ab9c-458d-a8b1-30b2ca4b4011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273425734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3273425734
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2082513481
Short name T64
Test name
Test status
Simulation time 16513003609 ps
CPU time 28.46 seconds
Started Aug 09 07:09:28 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 218360 kb
Host smart-925a9d5a-920f-4a0b-a26f-e99f640d586f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082513481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2082513481
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.760115790
Short name T56
Test name
Test status
Simulation time 377570074 ps
CPU time 2.1 seconds
Started Aug 09 07:09:39 PM PDT 24
Finished Aug 09 07:09:41 PM PDT 24
Peak memory 208488 kb
Host smart-db958976-c3a6-4316-873d-d8850495b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760115790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.760115790
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1817169266
Short name T10
Test name
Test status
Simulation time 1223368233 ps
CPU time 5.89 seconds
Started Aug 09 07:09:45 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 221584 kb
Host smart-405ed901-e83c-4d41-88e9-cb13c8608cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817169266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1817169266
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2539383154
Short name T78
Test name
Test status
Simulation time 494654825 ps
CPU time 3.9 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 208280 kb
Host smart-dd031053-9262-4275-bc3f-6d2160376638
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539383154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2539383154
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.13632167
Short name T41
Test name
Test status
Simulation time 12005658697 ps
CPU time 43.58 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:10:35 PM PDT 24
Peak memory 208820 kb
Host smart-a7366b75-bd1e-4ce1-bb80-d5ec71ebb99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13632167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.13632167
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3405161803
Short name T1
Test name
Test status
Simulation time 71814718 ps
CPU time 0.8 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200076 kb
Host smart-830c5aee-5579-42cd-acb8-3f932ba1e7a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405161803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3405161803
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2474933884
Short name T150
Test name
Test status
Simulation time 143369159 ps
CPU time 1.07 seconds
Started Aug 09 07:09:20 PM PDT 24
Finished Aug 09 07:09:21 PM PDT 24
Peak memory 200364 kb
Host smart-0ab14a14-c5a4-4510-a8f0-352fb32ca435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474933884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2474933884
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2422786193
Short name T3
Test name
Test status
Simulation time 2364219424 ps
CPU time 9.14 seconds
Started Aug 09 07:09:25 PM PDT 24
Finished Aug 09 07:09:34 PM PDT 24
Peak memory 221768 kb
Host smart-2108ea0a-9543-4a3a-bdd9-461fce42bc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422786193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2422786193
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3107632884
Short name T81
Test name
Test status
Simulation time 978502094 ps
CPU time 3.16 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:58 PM PDT 24
Peak memory 200436 kb
Host smart-23ac05c1-8063-4e76-9335-6fcc605adc49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107632884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3107632884
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.2221881477
Short name T156
Test name
Test status
Simulation time 194362643 ps
CPU time 1.19 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200356 kb
Host smart-8640e5f6-40fe-4957-b7a8-363bab223bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221881477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2221881477
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.521546632
Short name T33
Test name
Test status
Simulation time 1227212353 ps
CPU time 6.23 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 217456 kb
Host smart-456ada70-01b4-4839-bc5e-9168cade7b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521546632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.521546632
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4230405245
Short name T61
Test name
Test status
Simulation time 118624505 ps
CPU time 1.62 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 216672 kb
Host smart-c2a92a3a-f705-40ce-9e2c-b3ad11e3369e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230405245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4230405245
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1621167475
Short name T103
Test name
Test status
Simulation time 124739542 ps
CPU time 1.13 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200120 kb
Host smart-e03588ca-6a3e-4f61-8bab-1501f13791c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621167475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1621167475
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3835450854
Short name T18
Test name
Test status
Simulation time 133483332 ps
CPU time 0.88 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200168 kb
Host smart-aea73035-f891-4d57-a2a3-38a97b297369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835450854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3835450854
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2129960849
Short name T7
Test name
Test status
Simulation time 244699999 ps
CPU time 1.04 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 217456 kb
Host smart-0ed5b6e5-47de-4b92-8621-98adc800a44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129960849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2129960849
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2210200627
Short name T57
Test name
Test status
Simulation time 355699892 ps
CPU time 2.25 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200136 kb
Host smart-96d666c3-93cf-491a-a71e-d7d4b8faa54b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210200627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
210200627
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4285858271
Short name T585
Test name
Test status
Simulation time 488532355 ps
CPU time 5.82 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200208 kb
Host smart-6afc8f3a-6208-4230-933a-d176a36958e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285858271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.4
285858271
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4285645732
Short name T544
Test name
Test status
Simulation time 87788881 ps
CPU time 0.83 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:51 PM PDT 24
Peak memory 200056 kb
Host smart-aa85af42-0050-4194-9f1b-2ba6ea74dc07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285645732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.4
285645732
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4228963743
Short name T548
Test name
Test status
Simulation time 114954963 ps
CPU time 1.07 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200164 kb
Host smart-e24db178-a54e-48a2-b54d-bd22e996233b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228963743 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.4228963743
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2337098999
Short name T582
Test name
Test status
Simulation time 79899273 ps
CPU time 0.81 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200036 kb
Host smart-cb92f557-41ae-46df-a60d-edbc2665a864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337098999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2337098999
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.513349905
Short name T620
Test name
Test status
Simulation time 176870613 ps
CPU time 1.32 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200216 kb
Host smart-b1200dcd-5f1a-4689-b046-ece026144b52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513349905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.513349905
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.313787946
Short name T594
Test name
Test status
Simulation time 513249710 ps
CPU time 3.65 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 208408 kb
Host smart-f94c4d24-59da-43f7-975f-ae955f89860d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313787946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.313787946
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3809611442
Short name T586
Test name
Test status
Simulation time 520787195 ps
CPU time 1.95 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200244 kb
Host smart-f9aa4ccf-4d10-4c32-94d7-0704a1c2c6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809611442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3809611442
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1789212410
Short name T58
Test name
Test status
Simulation time 108402255 ps
CPU time 1.28 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200144 kb
Host smart-d35bb859-f4eb-4f5f-a3d5-1922f31b8838
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789212410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
789212410
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1110761609
Short name T567
Test name
Test status
Simulation time 272082439 ps
CPU time 3.34 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 200184 kb
Host smart-926bef0e-b2ab-484b-8512-87e5322d7459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110761609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
110761609
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.29130833
Short name T562
Test name
Test status
Simulation time 87740113 ps
CPU time 0.9 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200048 kb
Host smart-83958529-daa3-41f9-b89f-6ab7b13396de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.29130833
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.676224153
Short name T550
Test name
Test status
Simulation time 183910297 ps
CPU time 1.64 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:51 PM PDT 24
Peak memory 208484 kb
Host smart-d8cd3e20-6f2d-41bd-91d2-dff5e9d84bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676224153 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.676224153
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2355012545
Short name T575
Test name
Test status
Simulation time 76863648 ps
CPU time 0.8 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 199992 kb
Host smart-83b52453-fc94-4cb9-95e6-ec9243719db0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355012545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2355012545
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1740080958
Short name T570
Test name
Test status
Simulation time 103114720 ps
CPU time 0.91 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:51 PM PDT 24
Peak memory 200068 kb
Host smart-220d4e6e-028e-441f-a376-ec97c5a9692d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740080958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1740080958
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.502058509
Short name T613
Test name
Test status
Simulation time 103283074 ps
CPU time 1.33 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 208344 kb
Host smart-f142e6c9-37c9-4e95-a5a0-41e37ddb93b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502058509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.502058509
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2160954103
Short name T556
Test name
Test status
Simulation time 437166945 ps
CPU time 1.72 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200240 kb
Host smart-2e080691-3e3c-4fd5-9ae9-58b968ade911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160954103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2160954103
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2546747924
Short name T614
Test name
Test status
Simulation time 114484082 ps
CPU time 1.03 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200120 kb
Host smart-c6a79163-93ad-4f06-b2e1-89f605302e16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546747924 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2546747924
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2696184943
Short name T542
Test name
Test status
Simulation time 76984451 ps
CPU time 0.86 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 200040 kb
Host smart-39db02a1-4877-4062-922d-8ae49b31a39b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696184943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2696184943
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3245583915
Short name T563
Test name
Test status
Simulation time 121116994 ps
CPU time 1.06 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 200108 kb
Host smart-45046224-7c6c-4116-a288-beae6b9d0d8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245583915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3245583915
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3373214093
Short name T607
Test name
Test status
Simulation time 358168176 ps
CPU time 2.79 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 208228 kb
Host smart-0b2bc03f-d905-4feb-8447-8c2c4dafbcdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373214093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3373214093
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2764604400
Short name T117
Test name
Test status
Simulation time 792666018 ps
CPU time 2.76 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200236 kb
Host smart-e77e4831-ea6f-4496-8bed-a086b84a27ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764604400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2764604400
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1015513840
Short name T60
Test name
Test status
Simulation time 126450756 ps
CPU time 1.06 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 208320 kb
Host smart-969161ab-df08-423b-8d85-5b5f7be3fbe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015513840 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1015513840
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3981588115
Short name T584
Test name
Test status
Simulation time 74570052 ps
CPU time 0.77 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 199920 kb
Host smart-d6fc518f-888e-4218-bdf5-92b1b4da852e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981588115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3981588115
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.816365588
Short name T608
Test name
Test status
Simulation time 133452633 ps
CPU time 1.11 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200124 kb
Host smart-dd87267b-1ad5-4339-9cb2-0693d681f769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816365588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.816365588
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.885320286
Short name T595
Test name
Test status
Simulation time 116747704 ps
CPU time 1.54 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 208316 kb
Host smart-a304a4d9-ca13-45d4-9f30-7fc0eb593983
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885320286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.885320286
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3898100644
Short name T118
Test name
Test status
Simulation time 950623750 ps
CPU time 3.28 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200188 kb
Host smart-76699349-b12c-4a39-866f-d576d10791eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898100644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3898100644
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1954739548
Short name T568
Test name
Test status
Simulation time 106165098 ps
CPU time 0.98 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200156 kb
Host smart-4c673375-75ec-4ca9-829b-ce04e0b7808d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954739548 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1954739548
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2342436503
Short name T580
Test name
Test status
Simulation time 60370110 ps
CPU time 0.83 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 199988 kb
Host smart-f3c13619-dea2-49d2-b9ff-a1f07ba25258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342436503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2342436503
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.2979857786
Short name T597
Test name
Test status
Simulation time 122276308 ps
CPU time 1.82 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 216480 kb
Host smart-3c3fb26a-2478-48c6-9f1c-10b9b2a88003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979857786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2979857786
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1167744111
Short name T86
Test name
Test status
Simulation time 947453388 ps
CPU time 3.26 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 200168 kb
Host smart-67cb97b1-2b0e-4e8a-966f-63962d69148e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167744111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1167744111
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2723019885
Short name T549
Test name
Test status
Simulation time 116157338 ps
CPU time 0.98 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200136 kb
Host smart-77f91467-07b5-435d-9b53-b427b599e8a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723019885 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2723019885
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1687620268
Short name T566
Test name
Test status
Simulation time 64822746 ps
CPU time 0.83 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200072 kb
Host smart-88d50d2f-262b-4cf9-a876-04a044a0db05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687620268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1687620268
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2735800400
Short name T110
Test name
Test status
Simulation time 276318036 ps
CPU time 1.59 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200120 kb
Host smart-ee63217e-e385-42ef-8eed-7c15a64173a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735800400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2735800400
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3716065278
Short name T598
Test name
Test status
Simulation time 372201090 ps
CPU time 2.89 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:58 PM PDT 24
Peak memory 208548 kb
Host smart-843da9c1-8ca7-4c1f-9340-9017bf64e2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716065278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3716065278
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2817651266
Short name T85
Test name
Test status
Simulation time 416918060 ps
CPU time 1.79 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200200 kb
Host smart-dc46b624-69a3-4c9f-aff4-70acaca1f48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817651266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2817651266
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3843222613
Short name T571
Test name
Test status
Simulation time 127189589 ps
CPU time 1.03 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 209508 kb
Host smart-e866998f-8671-4c57-9f6f-131e93a08e08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843222613 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3843222613
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1841482133
Short name T609
Test name
Test status
Simulation time 66440565 ps
CPU time 0.8 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200072 kb
Host smart-2a58f798-ae03-4dbe-92d3-a1362ba9b21f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841482133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1841482133
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2316540459
Short name T108
Test name
Test status
Simulation time 125120654 ps
CPU time 1.16 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200144 kb
Host smart-c37e982d-75e5-4365-ac43-e019756245ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316540459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2316540459
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2314596225
Short name T83
Test name
Test status
Simulation time 479568819 ps
CPU time 2.08 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:58 PM PDT 24
Peak memory 200348 kb
Host smart-bc703a1e-e0e4-4afe-bf54-b636bc751310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314596225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2314596225
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3495610443
Short name T94
Test name
Test status
Simulation time 188530701 ps
CPU time 1.94 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 208504 kb
Host smart-83763328-a1c9-4414-83f3-c13af60a7b2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495610443 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3495610443
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1136136065
Short name T547
Test name
Test status
Simulation time 81813479 ps
CPU time 0.88 seconds
Started Aug 09 07:10:56 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 200024 kb
Host smart-da34841d-5fd3-459d-acae-252b5bf0ffc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136136065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1136136065
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4053216056
Short name T105
Test name
Test status
Simulation time 80578448 ps
CPU time 0.95 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200128 kb
Host smart-7eb38eeb-86a3-4519-b12c-49c21152ba1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053216056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4053216056
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.4255286514
Short name T87
Test name
Test status
Simulation time 109707535 ps
CPU time 1.39 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 208332 kb
Host smart-9e7cd0db-97a7-4c3b-8e6d-4e08272e8942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255286514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4255286514
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3332267431
Short name T93
Test name
Test status
Simulation time 151779867 ps
CPU time 1.23 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 208408 kb
Host smart-018a02bb-3210-47df-8572-a41eb3a548ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332267431 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3332267431
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2146590478
Short name T601
Test name
Test status
Simulation time 74151585 ps
CPU time 0.91 seconds
Started Aug 09 07:10:56 PM PDT 24
Finished Aug 09 07:11:02 PM PDT 24
Peak memory 200028 kb
Host smart-e87bb117-00ae-4074-930c-94c89d895b88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146590478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2146590478
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1038412725
Short name T604
Test name
Test status
Simulation time 289666067 ps
CPU time 1.74 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200220 kb
Host smart-7ea64c0d-bd4e-47b6-b044-2f80e1fc3dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038412725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.1038412725
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.550675369
Short name T555
Test name
Test status
Simulation time 144363387 ps
CPU time 2.11 seconds
Started Aug 09 07:10:56 PM PDT 24
Finished Aug 09 07:11:03 PM PDT 24
Peak memory 200164 kb
Host smart-ed1edb51-e1a1-478c-af27-8e5a756ea748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550675369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.550675369
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2168781292
Short name T606
Test name
Test status
Simulation time 436036105 ps
CPU time 1.83 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200232 kb
Host smart-54c074e3-8b12-436d-b0ce-d30b1e2b1c47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168781292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2168781292
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.650180507
Short name T88
Test name
Test status
Simulation time 179117897 ps
CPU time 1.67 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:51 PM PDT 24
Peak memory 208524 kb
Host smart-ae18fb22-530d-4bb0-96f9-ae1d4f065838
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650180507 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.650180507
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.556902504
Short name T590
Test name
Test status
Simulation time 65446622 ps
CPU time 0.81 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 199972 kb
Host smart-205e2676-69fa-4128-81a4-ceed1a3d1dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556902504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.556902504
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2814900319
Short name T602
Test name
Test status
Simulation time 100072810 ps
CPU time 1.22 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200208 kb
Host smart-4b40b803-6e15-4dbc-8cbd-76317f13f868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814900319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2814900319
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1643295952
Short name T560
Test name
Test status
Simulation time 468164901 ps
CPU time 3.22 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 208336 kb
Host smart-8ab64633-a644-4a3a-beaf-0bd2fb53541c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643295952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1643295952
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2096970591
Short name T591
Test name
Test status
Simulation time 466365791 ps
CPU time 2.09 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200220 kb
Host smart-460e1864-7902-463a-9a66-421721261768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096970591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2096970591
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.119337795
Short name T619
Test name
Test status
Simulation time 156787927 ps
CPU time 1.23 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 208396 kb
Host smart-4b79e2bd-e77e-4771-b3dc-2d75c0dcd512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119337795 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.119337795
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.728531803
Short name T551
Test name
Test status
Simulation time 58823017 ps
CPU time 0.79 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 199980 kb
Host smart-3d4a4b33-8e61-4906-af4f-e5362127dc72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728531803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.728531803
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2329581661
Short name T107
Test name
Test status
Simulation time 228867074 ps
CPU time 1.41 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:51 PM PDT 24
Peak memory 200260 kb
Host smart-573a4433-c974-41f5-90a3-232c7dec59c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329581661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2329581661
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1445195716
Short name T557
Test name
Test status
Simulation time 159652588 ps
CPU time 2.32 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 208328 kb
Host smart-f95db855-7d24-4d44-9054-632cdad025b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445195716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1445195716
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.953113548
Short name T618
Test name
Test status
Simulation time 430285324 ps
CPU time 2.05 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200292 kb
Host smart-309f8d53-d03e-4969-9fad-9518dfce5bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953113548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.953113548
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1843456334
Short name T79
Test name
Test status
Simulation time 177285968 ps
CPU time 1.6 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 208404 kb
Host smart-3848459c-1d8f-4b78-b2ad-63f628aa3e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843456334 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1843456334
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2038290811
Short name T612
Test name
Test status
Simulation time 73206202 ps
CPU time 0.85 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 199984 kb
Host smart-8359bfac-35af-4efd-8304-42275c6daca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038290811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2038290811
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1845996009
Short name T576
Test name
Test status
Simulation time 199367248 ps
CPU time 1.37 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200192 kb
Host smart-f6b67706-61ba-40f1-8e3f-c5f193d39674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845996009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1845996009
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1698113526
Short name T62
Test name
Test status
Simulation time 282070686 ps
CPU time 2.38 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 208308 kb
Host smart-9a8daa6c-f429-464e-b9f9-9e1ebba1efeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698113526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1698113526
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.629938774
Short name T84
Test name
Test status
Simulation time 462952324 ps
CPU time 1.85 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200284 kb
Host smart-01eb7347-18fc-47f5-86e5-d3ca1c7f5b78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629938774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.629938774
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3542723962
Short name T577
Test name
Test status
Simulation time 225741943 ps
CPU time 1.66 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 208368 kb
Host smart-365f714c-e2b4-43c7-b6bc-dddbae732eaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542723962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
542723962
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.971896873
Short name T579
Test name
Test status
Simulation time 806244023 ps
CPU time 4.46 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200124 kb
Host smart-dd6bbd09-ccf5-42a5-9e7c-88bdcf444867
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971896873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.971896873
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3062720099
Short name T596
Test name
Test status
Simulation time 142358576 ps
CPU time 1.04 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200040 kb
Host smart-e08edf48-974e-41ba-8a20-cac83a7e78c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062720099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
062720099
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2720583997
Short name T80
Test name
Test status
Simulation time 199693228 ps
CPU time 1.34 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 200308 kb
Host smart-76ecefd8-d538-4f51-b1c0-62901de0977f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720583997 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2720583997
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.3866307666
Short name T98
Test name
Test status
Simulation time 84986848 ps
CPU time 0.86 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200000 kb
Host smart-23d82cc8-a402-4e41-816e-67c534c0ec66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866307666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3866307666
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4050781883
Short name T605
Test name
Test status
Simulation time 213997574 ps
CPU time 1.61 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 200256 kb
Host smart-2133538b-5f80-42a0-9385-520be8115b12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050781883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.4050781883
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.3465560313
Short name T553
Test name
Test status
Simulation time 515736540 ps
CPU time 3.46 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 208344 kb
Host smart-7363ed11-eadc-4f21-b5c4-f607f460e493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465560313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3465560313
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1551801023
Short name T588
Test name
Test status
Simulation time 565195969 ps
CPU time 1.96 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200216 kb
Host smart-2150aac7-a0f5-4b93-8ea2-88f68196d370
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551801023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1551801023
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1778561494
Short name T617
Test name
Test status
Simulation time 107072737 ps
CPU time 1.38 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200100 kb
Host smart-108aabe3-091c-428d-9f17-57df2d6fb7ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778561494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
778561494
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.962980615
Short name T119
Test name
Test status
Simulation time 492738922 ps
CPU time 5.75 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 200096 kb
Host smart-03f446fc-3ba0-437b-b6c6-0d53cbc0f0b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962980615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.962980615
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3775417892
Short name T543
Test name
Test status
Simulation time 123952051 ps
CPU time 0.9 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200064 kb
Host smart-82cbaec4-9051-4996-b5a7-c73df4386121
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775417892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
775417892
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.240206918
Short name T603
Test name
Test status
Simulation time 133814896 ps
CPU time 1.08 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 208340 kb
Host smart-8ebe0117-9d18-4258-bca6-4297d69c29a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240206918 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.240206918
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.567464425
Short name T615
Test name
Test status
Simulation time 58943069 ps
CPU time 0.81 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200044 kb
Host smart-294704ef-bd00-48bc-9d27-abc0d0edbb02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567464425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.567464425
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1501795479
Short name T587
Test name
Test status
Simulation time 133697011 ps
CPU time 1.1 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 199932 kb
Host smart-ee89ca9e-c379-4aed-92cc-0b953bc45444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501795479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1501795479
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2120773639
Short name T600
Test name
Test status
Simulation time 98205949 ps
CPU time 1.35 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 216308 kb
Host smart-e9ca2d17-82bb-4942-8392-ed9c7e4a60bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120773639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2120773639
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.643077796
Short name T593
Test name
Test status
Simulation time 436989303 ps
CPU time 1.78 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200228 kb
Host smart-65b7208f-c047-47ee-b775-c4e6ba4ae3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643077796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
643077796
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2290357290
Short name T583
Test name
Test status
Simulation time 209357260 ps
CPU time 1.59 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200108 kb
Host smart-94af89c7-aa6b-4c7a-acb0-c512a428f002
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290357290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
290357290
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2230929975
Short name T546
Test name
Test status
Simulation time 270154000 ps
CPU time 3.26 seconds
Started Aug 09 07:10:56 PM PDT 24
Finished Aug 09 07:11:00 PM PDT 24
Peak memory 200128 kb
Host smart-96dd0a72-539c-4942-94e3-76b0855ec6cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230929975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
230929975
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1594839726
Short name T574
Test name
Test status
Simulation time 104456904 ps
CPU time 0.87 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200008 kb
Host smart-e874c29a-6eac-4131-8a2c-084b52d05041
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594839726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
594839726
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4127204777
Short name T565
Test name
Test status
Simulation time 118690263 ps
CPU time 0.94 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200180 kb
Host smart-7c48a9a1-4152-41d2-9669-b262de33c257
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127204777 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.4127204777
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1454395814
Short name T558
Test name
Test status
Simulation time 83369703 ps
CPU time 0.87 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200076 kb
Host smart-5d143763-a2df-47e5-bfee-99dc443693ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454395814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1454395814
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2853970981
Short name T106
Test name
Test status
Simulation time 275867895 ps
CPU time 1.62 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:11:01 PM PDT 24
Peak memory 200232 kb
Host smart-d41f08a3-3df8-4b85-a624-102797ba6372
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853970981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.2853970981
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2220185964
Short name T564
Test name
Test status
Simulation time 206821722 ps
CPU time 1.65 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 208364 kb
Host smart-a19dc355-1231-469b-a4bb-e0b08828522a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220185964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2220185964
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1790715572
Short name T77
Test name
Test status
Simulation time 432695322 ps
CPU time 1.85 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200244 kb
Host smart-2af233c9-5383-47b9-ba5e-a71852a69e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790715572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1790715572
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.165550753
Short name T561
Test name
Test status
Simulation time 114152074 ps
CPU time 1.3 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 208360 kb
Host smart-3c1c6623-8eab-4ccb-a329-b67482e7690b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165550753 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.165550753
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1834653329
Short name T104
Test name
Test status
Simulation time 91287620 ps
CPU time 0.86 seconds
Started Aug 09 07:10:56 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 200024 kb
Host smart-e4b96555-3a28-44a6-aee0-5e08f89d95b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834653329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1834653329
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.746367109
Short name T592
Test name
Test status
Simulation time 120995150 ps
CPU time 1.07 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200144 kb
Host smart-cc6eeb0d-f479-4ca7-a088-c157349bd9f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746367109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.746367109
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.311133488
Short name T559
Test name
Test status
Simulation time 435496597 ps
CPU time 2.98 seconds
Started Aug 09 07:10:54 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 200180 kb
Host smart-a60a69ac-d4df-4104-a45e-98a209f3253a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311133488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.311133488
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3603703855
Short name T581
Test name
Test status
Simulation time 113607359 ps
CPU time 1.16 seconds
Started Aug 09 07:10:56 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 208120 kb
Host smart-879f8a03-ca22-429e-be9a-cf78393fea6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603703855 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3603703855
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3737644356
Short name T545
Test name
Test status
Simulation time 65161004 ps
CPU time 0.75 seconds
Started Aug 09 07:10:56 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 199620 kb
Host smart-05107384-82c8-4c86-a6a8-67d060836d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737644356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3737644356
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3288803047
Short name T109
Test name
Test status
Simulation time 95663160 ps
CPU time 1.22 seconds
Started Aug 09 07:10:55 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 200224 kb
Host smart-e319dcee-5e68-4fde-912e-a1e72d3db6ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288803047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3288803047
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3462299568
Short name T578
Test name
Test status
Simulation time 429275237 ps
CPU time 3.1 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 208316 kb
Host smart-2558e62d-6fb4-42eb-99ca-4d1f3353940a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462299568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3462299568
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2921642086
Short name T59
Test name
Test status
Simulation time 514210891 ps
CPU time 1.85 seconds
Started Aug 09 07:10:56 PM PDT 24
Finished Aug 09 07:10:58 PM PDT 24
Peak memory 200164 kb
Host smart-cceff3b0-40ec-411e-b8c4-683e8a4ad666
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921642086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2921642086
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3588001188
Short name T552
Test name
Test status
Simulation time 200782661 ps
CPU time 1.33 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 208372 kb
Host smart-3e6ef048-e821-4bc4-bddd-043427363440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588001188 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3588001188
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.3486834026
Short name T554
Test name
Test status
Simulation time 83706996 ps
CPU time 0.85 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 199980 kb
Host smart-465b1d9f-b50f-459a-b4b9-6011d21039b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486834026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.3486834026
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2012837877
Short name T572
Test name
Test status
Simulation time 99816547 ps
CPU time 1.22 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200068 kb
Host smart-4e571d10-a1c8-40a4-8f69-d669b6e2fa61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012837877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2012837877
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3627987108
Short name T589
Test name
Test status
Simulation time 955907036 ps
CPU time 3.07 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200196 kb
Host smart-e191c3c8-5934-4a53-82e2-f3bc78d4680a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627987108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3627987108
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3420251775
Short name T611
Test name
Test status
Simulation time 204577729 ps
CPU time 1.4 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 208332 kb
Host smart-ddb8fbba-ecaf-4074-a4c8-8c78216c03c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420251775 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.3420251775
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.588826440
Short name T573
Test name
Test status
Simulation time 56575849 ps
CPU time 0.74 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 199912 kb
Host smart-28f6b4ee-5211-4d6c-9449-d8cd15ccf287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588826440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.588826440
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1618170321
Short name T610
Test name
Test status
Simulation time 187578740 ps
CPU time 1.42 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:51 PM PDT 24
Peak memory 200192 kb
Host smart-22221e96-9a05-417d-bbe4-5264417e8c83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618170321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1618170321
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.180419470
Short name T616
Test name
Test status
Simulation time 133574431 ps
CPU time 2.15 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:51 PM PDT 24
Peak memory 208176 kb
Host smart-280f8008-f683-4931-9c67-666e7d10313a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180419470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.180419470
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3272592879
Short name T569
Test name
Test status
Simulation time 493775055 ps
CPU time 2.19 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 200200 kb
Host smart-1f72a106-def7-477d-aaa0-148f4359e461
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272592879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.3272592879
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.287554413
Short name T599
Test name
Test status
Simulation time 183111405 ps
CPU time 1.69 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 208452 kb
Host smart-a98d5e15-f215-48fc-80b7-eed1fe25d1e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287554413 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.287554413
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.589493271
Short name T112
Test name
Test status
Simulation time 74121346 ps
CPU time 0.89 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 199972 kb
Host smart-58a3177c-8499-4c4c-98b3-6eb32f00154b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589493271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.589493271
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3444011519
Short name T111
Test name
Test status
Simulation time 107440223 ps
CPU time 1.31 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 200188 kb
Host smart-5c8f9be2-c46c-4bef-900f-d416b0c1dfbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444011519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3444011519
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2343236930
Short name T76
Test name
Test status
Simulation time 404542506 ps
CPU time 2.8 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 208348 kb
Host smart-cd708a15-8496-4fee-9b30-cf265f65265b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343236930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2343236930
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4026298724
Short name T82
Test name
Test status
Simulation time 879414855 ps
CPU time 2.94 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200260 kb
Host smart-38cf1802-44c3-47ce-bf8f-175d29d39c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026298724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.4026298724
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3570976982
Short name T217
Test name
Test status
Simulation time 59495620 ps
CPU time 0.78 seconds
Started Aug 09 07:09:08 PM PDT 24
Finished Aug 09 07:09:09 PM PDT 24
Peak memory 200164 kb
Host smart-1b0a6d84-1cc0-424c-be50-83592e81a2cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570976982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3570976982
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1393874633
Short name T517
Test name
Test status
Simulation time 1222533460 ps
CPU time 5.6 seconds
Started Aug 09 07:09:07 PM PDT 24
Finished Aug 09 07:09:12 PM PDT 24
Peak memory 217352 kb
Host smart-d2bd132a-b360-4611-b4e8-8f3feeee8313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393874633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1393874633
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.238507634
Short name T367
Test name
Test status
Simulation time 243742496 ps
CPU time 1.11 seconds
Started Aug 09 07:09:12 PM PDT 24
Finished Aug 09 07:09:13 PM PDT 24
Peak memory 217480 kb
Host smart-65fe92fa-3ee2-49f3-a010-24c8609373dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238507634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.238507634
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.497799075
Short name T298
Test name
Test status
Simulation time 113107325 ps
CPU time 0.8 seconds
Started Aug 09 07:09:14 PM PDT 24
Finished Aug 09 07:09:15 PM PDT 24
Peak memory 200152 kb
Host smart-b037141d-8e19-4d86-9713-0404230ed1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497799075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.497799075
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1114418972
Short name T390
Test name
Test status
Simulation time 1544174144 ps
CPU time 6.06 seconds
Started Aug 09 07:09:16 PM PDT 24
Finished Aug 09 07:09:22 PM PDT 24
Peak memory 200488 kb
Host smart-b8c28f4c-a8db-4385-bc02-911d62a16ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114418972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1114418972
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3387495683
Short name T70
Test name
Test status
Simulation time 8532604201 ps
CPU time 13.4 seconds
Started Aug 09 07:09:08 PM PDT 24
Finished Aug 09 07:09:22 PM PDT 24
Peak memory 217452 kb
Host smart-7e47217e-5304-43c1-8d04-8534025ed2dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387495683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3387495683
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1218448511
Short name T406
Test name
Test status
Simulation time 108237667 ps
CPU time 1.05 seconds
Started Aug 09 07:09:23 PM PDT 24
Finished Aug 09 07:09:24 PM PDT 24
Peak memory 200276 kb
Host smart-d6286938-5749-494e-8760-c905e3907743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218448511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1218448511
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2029006672
Short name T349
Test name
Test status
Simulation time 122329830 ps
CPU time 1.2 seconds
Started Aug 09 07:09:19 PM PDT 24
Finished Aug 09 07:09:20 PM PDT 24
Peak memory 200444 kb
Host smart-31370b19-c946-4742-affe-dcf344d27d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029006672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2029006672
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4087208300
Short name T509
Test name
Test status
Simulation time 3110848376 ps
CPU time 12.4 seconds
Started Aug 09 07:09:12 PM PDT 24
Finished Aug 09 07:09:25 PM PDT 24
Peak memory 208708 kb
Host smart-eb485d7f-1b6c-4400-a448-3a720f769c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087208300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4087208300
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3028494515
Short name T116
Test name
Test status
Simulation time 546080681 ps
CPU time 2.66 seconds
Started Aug 09 07:09:15 PM PDT 24
Finished Aug 09 07:09:17 PM PDT 24
Peak memory 200296 kb
Host smart-c1e849d7-e5ca-4102-b40c-c816938fef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028494515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3028494515
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1490326628
Short name T258
Test name
Test status
Simulation time 83790727 ps
CPU time 0.85 seconds
Started Aug 09 07:09:05 PM PDT 24
Finished Aug 09 07:09:06 PM PDT 24
Peak memory 200384 kb
Host smart-fddc906d-ff24-421c-ab42-d87c100a75c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490326628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1490326628
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2067644820
Short name T161
Test name
Test status
Simulation time 69157184 ps
CPU time 0.77 seconds
Started Aug 09 07:09:33 PM PDT 24
Finished Aug 09 07:09:34 PM PDT 24
Peak memory 200140 kb
Host smart-d5bd48d0-9ca3-4daf-8565-1f42c81bfa02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067644820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2067644820
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1705664731
Short name T53
Test name
Test status
Simulation time 1234282763 ps
CPU time 5.45 seconds
Started Aug 09 07:09:18 PM PDT 24
Finished Aug 09 07:09:23 PM PDT 24
Peak memory 216416 kb
Host smart-7925e3a6-b16d-42ad-bff0-461d3aea5369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705664731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1705664731
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.921675550
Short name T399
Test name
Test status
Simulation time 246038781 ps
CPU time 1.11 seconds
Started Aug 09 07:09:13 PM PDT 24
Finished Aug 09 07:09:14 PM PDT 24
Peak memory 217516 kb
Host smart-3e99dec2-e3d0-462e-b83f-e773f4188f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921675550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.921675550
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3948298435
Short name T260
Test name
Test status
Simulation time 202230875 ps
CPU time 0.99 seconds
Started Aug 09 07:09:28 PM PDT 24
Finished Aug 09 07:09:29 PM PDT 24
Peak memory 200152 kb
Host smart-6b2bf1f9-8590-4c46-8cf7-26ecece546be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948298435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3948298435
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3052024481
Short name T294
Test name
Test status
Simulation time 748988471 ps
CPU time 4.2 seconds
Started Aug 09 07:09:22 PM PDT 24
Finished Aug 09 07:09:26 PM PDT 24
Peak memory 200580 kb
Host smart-cbc6728e-7603-4e0b-8972-5b5d30e508e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052024481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3052024481
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1821551636
Short name T65
Test name
Test status
Simulation time 8292762389 ps
CPU time 17.53 seconds
Started Aug 09 07:09:11 PM PDT 24
Finished Aug 09 07:09:28 PM PDT 24
Peak memory 217108 kb
Host smart-0d3f8d69-9cf3-42bf-a9dc-c2af1fdba9b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821551636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1821551636
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2205376669
Short name T417
Test name
Test status
Simulation time 200149293 ps
CPU time 1.41 seconds
Started Aug 09 07:09:06 PM PDT 24
Finished Aug 09 07:09:07 PM PDT 24
Peak memory 200476 kb
Host smart-26ebe22b-2ff3-4dd8-a107-2fef3ac2db66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205376669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2205376669
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2817079776
Short name T92
Test name
Test status
Simulation time 2400098794 ps
CPU time 8.13 seconds
Started Aug 09 07:09:25 PM PDT 24
Finished Aug 09 07:09:33 PM PDT 24
Peak memory 210148 kb
Host smart-73b0711e-9cef-4062-9b26-6c8de375fb65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817079776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2817079776
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.4196703137
Short name T377
Test name
Test status
Simulation time 438704431 ps
CPU time 2.4 seconds
Started Aug 09 07:09:25 PM PDT 24
Finished Aug 09 07:09:28 PM PDT 24
Peak memory 200248 kb
Host smart-c7310caf-55f2-4921-a6dd-48e53529e895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196703137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.4196703137
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1389903250
Short name T383
Test name
Test status
Simulation time 177413625 ps
CPU time 1.33 seconds
Started Aug 09 07:09:19 PM PDT 24
Finished Aug 09 07:09:20 PM PDT 24
Peak memory 200364 kb
Host smart-0fe621cc-08d6-4ba4-9d7f-1a71fe12f6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389903250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1389903250
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.4222914151
Short name T461
Test name
Test status
Simulation time 79872023 ps
CPU time 0.8 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200156 kb
Host smart-e31b6ef8-4195-4e94-8076-45df548d6d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222914151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4222914151
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1942675304
Short name T459
Test name
Test status
Simulation time 243940215 ps
CPU time 1.16 seconds
Started Aug 09 07:09:41 PM PDT 24
Finished Aug 09 07:09:42 PM PDT 24
Peak memory 217592 kb
Host smart-5c6ad33b-4d1a-4f7e-93ff-aac9ea902512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942675304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1942675304
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.284105034
Short name T430
Test name
Test status
Simulation time 103410637 ps
CPU time 0.77 seconds
Started Aug 09 07:09:37 PM PDT 24
Finished Aug 09 07:09:38 PM PDT 24
Peak memory 200136 kb
Host smart-74689b65-6be8-49a3-a79e-855cbb52d4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284105034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.284105034
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.3220172098
Short name T297
Test name
Test status
Simulation time 1995376426 ps
CPU time 6.67 seconds
Started Aug 09 07:09:40 PM PDT 24
Finished Aug 09 07:09:46 PM PDT 24
Peak memory 200548 kb
Host smart-9a81b766-3fff-43fa-8fc9-0cebff529d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220172098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3220172098
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.590150314
Short name T286
Test name
Test status
Simulation time 105536377 ps
CPU time 1.05 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200344 kb
Host smart-9b6c05a5-5f5e-42dc-b500-78e0a7895535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590150314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.590150314
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.3602520248
Short name T159
Test name
Test status
Simulation time 111861535 ps
CPU time 1.16 seconds
Started Aug 09 07:09:40 PM PDT 24
Finished Aug 09 07:09:42 PM PDT 24
Peak memory 200532 kb
Host smart-f431d822-a698-48eb-8518-20eca655dc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602520248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3602520248
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1500521571
Short name T182
Test name
Test status
Simulation time 8913346218 ps
CPU time 29.45 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:10:16 PM PDT 24
Peak memory 208808 kb
Host smart-78fdd54b-b749-403d-92ea-aa372962d973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500521571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1500521571
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2745738771
Short name T283
Test name
Test status
Simulation time 430997554 ps
CPU time 2.52 seconds
Started Aug 09 07:09:45 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 208500 kb
Host smart-5ad7299e-6a3e-413e-ac6f-a092692f6da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745738771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2745738771
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.9616862
Short name T345
Test name
Test status
Simulation time 198290878 ps
CPU time 1.29 seconds
Started Aug 09 07:09:45 PM PDT 24
Finished Aug 09 07:09:46 PM PDT 24
Peak memory 200368 kb
Host smart-c5d1ba59-3b79-4cd5-8ac3-e4c4b2941c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9616862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.9616862
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1075458950
Short name T195
Test name
Test status
Simulation time 72608844 ps
CPU time 0.8 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200172 kb
Host smart-cba6811e-2961-467e-a2ee-403f59cffd48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075458950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1075458950
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3285631618
Short name T50
Test name
Test status
Simulation time 1234876821 ps
CPU time 5.74 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 217768 kb
Host smart-2c0551e5-4950-4deb-b994-54a557033a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285631618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3285631618
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3374006696
Short name T213
Test name
Test status
Simulation time 244238388 ps
CPU time 1.08 seconds
Started Aug 09 07:09:41 PM PDT 24
Finished Aug 09 07:09:42 PM PDT 24
Peak memory 217516 kb
Host smart-18fba4f0-63f8-4f0c-84f8-ad7be808abca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374006696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3374006696
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3110268856
Short name T162
Test name
Test status
Simulation time 193623320 ps
CPU time 0.85 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200188 kb
Host smart-fe90f0e9-d77f-422c-bf21-a075108fbce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110268856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3110268856
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2269187173
Short name T323
Test name
Test status
Simulation time 1422838041 ps
CPU time 5.4 seconds
Started Aug 09 07:09:43 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200544 kb
Host smart-888afe17-92dc-46b5-9d01-af04a0b2b284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269187173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2269187173
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2435205457
Short name T166
Test name
Test status
Simulation time 100693620 ps
CPU time 1.02 seconds
Started Aug 09 07:09:34 PM PDT 24
Finished Aug 09 07:09:35 PM PDT 24
Peak memory 200304 kb
Host smart-a0f8807e-da06-49d8-bf78-d6f27cef8c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435205457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2435205457
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2481141100
Short name T427
Test name
Test status
Simulation time 123578683 ps
CPU time 1.18 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200460 kb
Host smart-1852af28-fa11-4ad8-b253-448478e26919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481141100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2481141100
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2955680282
Short name T158
Test name
Test status
Simulation time 1476792702 ps
CPU time 7.46 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200628 kb
Host smart-a4bec47a-6218-4601-877b-e15d0fa0aa49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955680282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2955680282
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.4084257024
Short name T472
Test name
Test status
Simulation time 144156663 ps
CPU time 1.74 seconds
Started Aug 09 07:09:40 PM PDT 24
Finished Aug 09 07:09:42 PM PDT 24
Peak memory 200488 kb
Host smart-60074f2a-6f8e-477f-a93f-6ae443aa0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084257024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.4084257024
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3867180431
Short name T202
Test name
Test status
Simulation time 152774637 ps
CPU time 1.08 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200276 kb
Host smart-13dd702f-2ba8-47da-a54b-a6adaf0af05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867180431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3867180431
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.103223961
Short name T143
Test name
Test status
Simulation time 56405959 ps
CPU time 0.7 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:47 PM PDT 24
Peak memory 200156 kb
Host smart-756f8053-9195-4b57-9077-34aef51308d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103223961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.103223961
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.612924370
Short name T32
Test name
Test status
Simulation time 1906426782 ps
CPU time 7.3 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 217700 kb
Host smart-fa04585e-3fa5-409b-9595-c89d1a1d004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612924370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.612924370
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3433588015
Short name T343
Test name
Test status
Simulation time 244820232 ps
CPU time 1.02 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 217476 kb
Host smart-48119935-cc73-4753-addd-3ed5f45cfe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433588015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3433588015
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1678172930
Short name T541
Test name
Test status
Simulation time 1637217420 ps
CPU time 6.68 seconds
Started Aug 09 07:09:42 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200552 kb
Host smart-68636788-a1a5-45f1-bd31-6e71d24a9f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678172930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1678172930
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1254200149
Short name T525
Test name
Test status
Simulation time 170197391 ps
CPU time 1.11 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:47 PM PDT 24
Peak memory 200320 kb
Host smart-f404c019-0170-464c-940a-400c6ca45488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254200149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1254200149
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.974351076
Short name T183
Test name
Test status
Simulation time 194031632 ps
CPU time 1.44 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200472 kb
Host smart-0f8f93eb-21ff-4420-badb-4d220b5f2eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974351076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.974351076
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3557106675
Short name T230
Test name
Test status
Simulation time 1394706902 ps
CPU time 6.1 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:10:00 PM PDT 24
Peak memory 200572 kb
Host smart-dc941fda-cad2-41dd-a7c5-8d596d748b28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557106675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3557106675
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.16515470
Short name T468
Test name
Test status
Simulation time 463324000 ps
CPU time 2.75 seconds
Started Aug 09 07:09:44 PM PDT 24
Finished Aug 09 07:09:47 PM PDT 24
Peak memory 200268 kb
Host smart-aa420599-9499-40b0-993a-534130d3a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16515470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.16515470
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3404383201
Short name T184
Test name
Test status
Simulation time 132744370 ps
CPU time 1.19 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200328 kb
Host smart-8989f081-08ba-4e6e-a6db-57aa2cf3378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404383201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3404383201
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2609887326
Short name T324
Test name
Test status
Simulation time 56064493 ps
CPU time 0.72 seconds
Started Aug 09 07:09:40 PM PDT 24
Finished Aug 09 07:09:41 PM PDT 24
Peak memory 200360 kb
Host smart-67cc7357-d54c-4177-b301-d9af58ea6588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609887326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2609887326
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1474046130
Short name T442
Test name
Test status
Simulation time 1875552553 ps
CPU time 7.29 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:59 PM PDT 24
Peak memory 217772 kb
Host smart-61e935ed-1f5f-41ff-9863-6539ebe07bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474046130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1474046130
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.442780246
Short name T523
Test name
Test status
Simulation time 244487726 ps
CPU time 1.05 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:52 PM PDT 24
Peak memory 217276 kb
Host smart-8edd61e7-f585-46d9-97a0-1d77a4faf7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442780246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.442780246
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2025575121
Short name T20
Test name
Test status
Simulation time 216664134 ps
CPU time 0.95 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200084 kb
Host smart-a7a60f4c-547b-494b-ab32-247198db5e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025575121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2025575121
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1907686118
Short name T251
Test name
Test status
Simulation time 840574591 ps
CPU time 4.24 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200596 kb
Host smart-eed31035-32b4-491b-afd9-d3ccb5be132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907686118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1907686118
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.155705517
Short name T186
Test name
Test status
Simulation time 106703726 ps
CPU time 0.98 seconds
Started Aug 09 07:09:41 PM PDT 24
Finished Aug 09 07:09:42 PM PDT 24
Peak memory 200304 kb
Host smart-51b42378-5f97-445f-9e30-14d7352b888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155705517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.155705517
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1840544293
Short name T257
Test name
Test status
Simulation time 123691105 ps
CPU time 1.22 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200528 kb
Host smart-8ac136da-d711-4075-9235-af61b23d35bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840544293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1840544293
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3571385252
Short name T224
Test name
Test status
Simulation time 313404514 ps
CPU time 1.93 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200332 kb
Host smart-7185bdc9-fe3a-48f1-9551-db97325f5fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571385252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3571385252
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.1516504357
Short name T404
Test name
Test status
Simulation time 73909395 ps
CPU time 0.8 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:47 PM PDT 24
Peak memory 200328 kb
Host smart-bda44e8c-21ec-44a4-bf14-59e66ee41a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516504357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1516504357
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1627531643
Short name T465
Test name
Test status
Simulation time 54897336 ps
CPU time 0.74 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200144 kb
Host smart-42713e38-6721-4a14-9b3e-7886f839bddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627531643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1627531643
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.1492431788
Short name T37
Test name
Test status
Simulation time 1226550473 ps
CPU time 5.58 seconds
Started Aug 09 07:09:42 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 217592 kb
Host smart-863e7800-f977-4d29-9e7b-f7a8201a178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492431788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.1492431788
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1159099291
Short name T135
Test name
Test status
Simulation time 246120202 ps
CPU time 1.06 seconds
Started Aug 09 07:09:38 PM PDT 24
Finished Aug 09 07:09:39 PM PDT 24
Peak memory 217432 kb
Host smart-d7d905d7-d23f-43f2-b39a-fdd0bb292b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159099291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1159099291
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1812949420
Short name T253
Test name
Test status
Simulation time 190065394 ps
CPU time 0.88 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:52 PM PDT 24
Peak memory 200068 kb
Host smart-c9f79d95-0629-4710-90cb-e2e97ed0dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812949420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1812949420
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2479492090
Short name T293
Test name
Test status
Simulation time 787212743 ps
CPU time 4.63 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200540 kb
Host smart-293a5b7b-d461-46ae-9768-50090713f51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479492090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2479492090
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.272741548
Short name T538
Test name
Test status
Simulation time 110166605 ps
CPU time 1.08 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200372 kb
Host smart-3ba6ed38-9538-47f1-95ae-5f1755036b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272741548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.272741548
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3061834129
Short name T319
Test name
Test status
Simulation time 114862287 ps
CPU time 1.17 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200488 kb
Host smart-ae8380f3-4079-46f2-86c6-77e483834a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061834129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3061834129
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3584942351
Short name T205
Test name
Test status
Simulation time 1097951576 ps
CPU time 5.46 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200584 kb
Host smart-54e47113-b303-4593-861b-65833a16e6d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584942351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3584942351
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1826792639
Short name T164
Test name
Test status
Simulation time 479400212 ps
CPU time 2.6 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200328 kb
Host smart-50232190-b9b1-4b3c-96c3-3cd0ecda85e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826792639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1826792639
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2775109195
Short name T370
Test name
Test status
Simulation time 83663840 ps
CPU time 0.89 seconds
Started Aug 09 07:09:43 PM PDT 24
Finished Aug 09 07:09:44 PM PDT 24
Peak memory 200368 kb
Host smart-d9c18263-dabc-4c99-b1eb-fa6972adfd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775109195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2775109195
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3805234123
Short name T393
Test name
Test status
Simulation time 72484776 ps
CPU time 0.76 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200172 kb
Host smart-49f723c6-6fbe-4c41-be63-de465d1ca954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805234123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3805234123
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2181738847
Short name T332
Test name
Test status
Simulation time 2149682633 ps
CPU time 7.34 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 217544 kb
Host smart-837de7e3-9836-4f53-8cee-c60784cd1f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181738847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2181738847
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3215826147
Short name T223
Test name
Test status
Simulation time 245779356 ps
CPU time 1.05 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 217496 kb
Host smart-9a912a98-6914-4969-9f98-ec003e3191f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215826147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3215826147
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2281214624
Short name T527
Test name
Test status
Simulation time 101784987 ps
CPU time 0.75 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200152 kb
Host smart-686c3c0f-ef97-4168-bb69-d6396104f2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281214624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2281214624
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2352073115
Short name T338
Test name
Test status
Simulation time 1623257096 ps
CPU time 6.58 seconds
Started Aug 09 07:09:44 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200572 kb
Host smart-76662956-ae31-49cf-b76f-a6e0f96addd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352073115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2352073115
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2480932264
Short name T206
Test name
Test status
Simulation time 102027606 ps
CPU time 0.98 seconds
Started Aug 09 07:09:45 PM PDT 24
Finished Aug 09 07:09:46 PM PDT 24
Peak memory 200384 kb
Host smart-324e1ec7-8332-42e4-8fe0-49c785a765d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480932264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2480932264
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4115077144
Short name T413
Test name
Test status
Simulation time 121153162 ps
CPU time 1.2 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200480 kb
Host smart-31d616f3-4740-4b88-939e-862facdf6266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115077144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4115077144
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.825118616
Short name T335
Test name
Test status
Simulation time 3468143143 ps
CPU time 13.08 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:10:06 PM PDT 24
Peak memory 200592 kb
Host smart-a6326454-f0f7-4adb-916b-8842c1256baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825118616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.825118616
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2407402508
Short name T424
Test name
Test status
Simulation time 134123542 ps
CPU time 1.6 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 208532 kb
Host smart-8cddcdf4-bbbf-46e2-8168-7b7558676bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407402508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2407402508
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1585799816
Short name T191
Test name
Test status
Simulation time 77649398 ps
CPU time 0.83 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200128 kb
Host smart-ef4d1080-baf6-4fe0-a76e-ec2f76e6f27c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585799816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1585799816
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1876088770
Short name T405
Test name
Test status
Simulation time 1227210550 ps
CPU time 5.98 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 221616 kb
Host smart-cdbdb5c2-b61a-4d8c-b9b7-b027a3762cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876088770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1876088770
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1023662111
Short name T473
Test name
Test status
Simulation time 244358512 ps
CPU time 1.07 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 217496 kb
Host smart-7167c97a-3f6b-4ccd-89d8-b47e0e8e34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023662111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1023662111
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2452679172
Short name T220
Test name
Test status
Simulation time 205649263 ps
CPU time 0.96 seconds
Started Aug 09 07:09:44 PM PDT 24
Finished Aug 09 07:09:46 PM PDT 24
Peak memory 200168 kb
Host smart-e41376af-41a8-45e3-b138-cf806dd346bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452679172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2452679172
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3891119492
Short name T197
Test name
Test status
Simulation time 1562593748 ps
CPU time 5.49 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200592 kb
Host smart-56936eee-ea6e-447d-9f95-6b15bc49bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891119492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3891119492
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2762086941
Short name T287
Test name
Test status
Simulation time 111996252 ps
CPU time 1.09 seconds
Started Aug 09 07:09:45 PM PDT 24
Finished Aug 09 07:09:46 PM PDT 24
Peak memory 200360 kb
Host smart-729db4f5-e5b2-42ce-9815-bf3a2fc2e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762086941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2762086941
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3978838224
Short name T129
Test name
Test status
Simulation time 118862182 ps
CPU time 1.2 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200480 kb
Host smart-38dd9141-72b2-4c45-b119-831082d295b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978838224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3978838224
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3153580184
Short name T302
Test name
Test status
Simulation time 1879338702 ps
CPU time 7.89 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200556 kb
Host smart-69d313b3-49e3-4661-8494-871ddb23ee17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153580184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3153580184
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2458293253
Short name T363
Test name
Test status
Simulation time 280328852 ps
CPU time 1.91 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200280 kb
Host smart-9c028f7c-7125-4650-8720-766c42a9a2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458293253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2458293253
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2724467534
Short name T241
Test name
Test status
Simulation time 102484355 ps
CPU time 0.87 seconds
Started Aug 09 07:09:42 PM PDT 24
Finished Aug 09 07:09:43 PM PDT 24
Peak memory 200304 kb
Host smart-af3adcf0-9b86-4df4-af47-a3bee2cd7c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724467534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2724467534
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4037802995
Short name T126
Test name
Test status
Simulation time 73242398 ps
CPU time 0.79 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200128 kb
Host smart-10657fc5-ef3b-41d0-a328-9d949d27fb19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037802995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4037802995
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1222265281
Short name T358
Test name
Test status
Simulation time 243356599 ps
CPU time 1.02 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 217528 kb
Host smart-67378d92-60e3-45d3-b22c-71a78d9e7c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222265281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1222265281
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3033168143
Short name T334
Test name
Test status
Simulation time 92822171 ps
CPU time 0.74 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:47 PM PDT 24
Peak memory 200152 kb
Host smart-c50aaa20-6ab7-46c7-b2c0-f1cf01ec8592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033168143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3033168143
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.3029929279
Short name T359
Test name
Test status
Simulation time 798458072 ps
CPU time 4.09 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200528 kb
Host smart-7514df2f-2d00-4d19-9091-c0f5e843a0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029929279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3029929279
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2848179423
Short name T439
Test name
Test status
Simulation time 152112801 ps
CPU time 1.25 seconds
Started Aug 09 07:09:44 PM PDT 24
Finished Aug 09 07:09:46 PM PDT 24
Peak memory 200324 kb
Host smart-b8d5290e-63b6-4db0-a130-866b7a2bbf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848179423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2848179423
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1099987220
Short name T28
Test name
Test status
Simulation time 259750312 ps
CPU time 1.64 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200460 kb
Host smart-87fe87fc-e2b3-49fa-a998-086f626e1342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099987220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1099987220
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3127727629
Short name T379
Test name
Test status
Simulation time 6944963918 ps
CPU time 33.57 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:10:26 PM PDT 24
Peak memory 208840 kb
Host smart-41747249-90a7-42a2-a41a-38724758fb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127727629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3127727629
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.3230944740
Short name T496
Test name
Test status
Simulation time 109365590 ps
CPU time 1.38 seconds
Started Aug 09 07:09:43 PM PDT 24
Finished Aug 09 07:09:45 PM PDT 24
Peak memory 200288 kb
Host smart-8932dd24-d468-4682-a260-5fb46341f6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230944740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3230944740
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.682685056
Short name T242
Test name
Test status
Simulation time 224776710 ps
CPU time 1.36 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200340 kb
Host smart-2a224b58-8905-49d6-8e5b-53239eaf5011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682685056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.682685056
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.1946552473
Short name T318
Test name
Test status
Simulation time 1228572474 ps
CPU time 6.01 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 217784 kb
Host smart-29155950-f27a-4bb9-8d91-4256996c90aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946552473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1946552473
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3905875087
Short name T24
Test name
Test status
Simulation time 233825016 ps
CPU time 0.96 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200164 kb
Host smart-d1d2e1ea-1718-4ae1-8d23-ad9d9da7171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905875087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3905875087
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.273695479
Short name T101
Test name
Test status
Simulation time 1037046665 ps
CPU time 5.56 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200556 kb
Host smart-a9ee1067-02d5-436d-826a-59dbd846c96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273695479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.273695479
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.4144930518
Short name T507
Test name
Test status
Simulation time 100649654 ps
CPU time 0.99 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200380 kb
Host smart-5372daa8-0976-4ae1-b070-6fa4b0ec9304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144930518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.4144930518
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1911614846
Short name T528
Test name
Test status
Simulation time 114207118 ps
CPU time 1.18 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200468 kb
Host smart-c4734c92-f998-4216-a6c8-7a81849eb596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911614846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1911614846
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2046634126
Short name T505
Test name
Test status
Simulation time 417358457 ps
CPU time 2.33 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200284 kb
Host smart-81f82e07-f4b7-43d4-85d4-8f58ac2013c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046634126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2046634126
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.248427986
Short name T409
Test name
Test status
Simulation time 92233209 ps
CPU time 0.85 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200324 kb
Host smart-05853c8b-8be9-4c32-bcfb-1c85510357a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248427986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.248427986
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2450030624
Short name T306
Test name
Test status
Simulation time 65273404 ps
CPU time 0.71 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200196 kb
Host smart-b13a9832-0c3f-4629-ad6c-c533c993ede7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450030624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2450030624
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2531909582
Short name T48
Test name
Test status
Simulation time 2395295217 ps
CPU time 8.55 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 221764 kb
Host smart-5aa0ca77-05ff-43a8-a7d0-0f582dceb332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531909582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2531909582
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.806888396
Short name T42
Test name
Test status
Simulation time 244981841 ps
CPU time 1.08 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 217532 kb
Host smart-77be8453-1b05-4521-903a-4b7cf8d809d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806888396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.806888396
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1566350490
Short name T444
Test name
Test status
Simulation time 181038099 ps
CPU time 0.95 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200184 kb
Host smart-8a161ecd-f39a-495f-9751-89492fc85520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566350490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1566350490
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1829785449
Short name T100
Test name
Test status
Simulation time 920793333 ps
CPU time 5.26 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200560 kb
Host smart-b952fa5d-d1e4-4b74-b53f-896bd7d62db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829785449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1829785449
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2822905772
Short name T237
Test name
Test status
Simulation time 145321753 ps
CPU time 1.09 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200364 kb
Host smart-678d90c1-2c73-4e5f-888e-7c888aab1ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822905772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2822905772
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1671512634
Short name T114
Test name
Test status
Simulation time 7261168548 ps
CPU time 25.22 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 200664 kb
Host smart-b2c1fbce-21f8-421d-bbf4-a371835b44fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671512634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1671512634
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1344510572
Short name T403
Test name
Test status
Simulation time 412575999 ps
CPU time 2.14 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200248 kb
Host smart-8306c94e-1ee0-4f9f-a645-e92db7b2abd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344510572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1344510572
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.645449192
Short name T516
Test name
Test status
Simulation time 302861666 ps
CPU time 1.62 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200740 kb
Host smart-b9a825a4-0373-41a6-86df-82e6b72fa2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645449192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.645449192
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.542823776
Short name T454
Test name
Test status
Simulation time 64196772 ps
CPU time 0.74 seconds
Started Aug 09 07:09:23 PM PDT 24
Finished Aug 09 07:09:24 PM PDT 24
Peak memory 200144 kb
Host smart-5b6d7388-03dc-4a87-aed1-0259c1237230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542823776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.542823776
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.456222891
Short name T178
Test name
Test status
Simulation time 244747926 ps
CPU time 1.19 seconds
Started Aug 09 07:09:23 PM PDT 24
Finished Aug 09 07:09:25 PM PDT 24
Peak memory 217504 kb
Host smart-e4967a2f-0223-40dc-b826-b19f3fbd3c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456222891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.456222891
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1918896981
Short name T317
Test name
Test status
Simulation time 81999386 ps
CPU time 0.75 seconds
Started Aug 09 07:09:31 PM PDT 24
Finished Aug 09 07:09:32 PM PDT 24
Peak memory 200152 kb
Host smart-bc226299-4823-487c-b7ba-ed9e5ff43da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918896981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1918896981
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2223700548
Short name T244
Test name
Test status
Simulation time 1054117928 ps
CPU time 4.86 seconds
Started Aug 09 07:09:24 PM PDT 24
Finished Aug 09 07:09:29 PM PDT 24
Peak memory 200476 kb
Host smart-fe4f3245-b1eb-4da1-87f0-0fc94ac29b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223700548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2223700548
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1087872319
Short name T69
Test name
Test status
Simulation time 16824538387 ps
CPU time 24.6 seconds
Started Aug 09 07:09:18 PM PDT 24
Finished Aug 09 07:09:42 PM PDT 24
Peak memory 217208 kb
Host smart-5b531208-499b-4937-a468-36b9bb1a9409
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087872319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1087872319
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.46168446
Short name T181
Test name
Test status
Simulation time 146863576 ps
CPU time 1.07 seconds
Started Aug 09 07:09:20 PM PDT 24
Finished Aug 09 07:09:21 PM PDT 24
Peak memory 200388 kb
Host smart-141e07da-8f7b-40fa-8caf-8633a1a45c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46168446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.46168446
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3664327518
Short name T322
Test name
Test status
Simulation time 195781843 ps
CPU time 1.42 seconds
Started Aug 09 07:09:25 PM PDT 24
Finished Aug 09 07:09:26 PM PDT 24
Peak memory 200484 kb
Host smart-a36c961a-4ec9-426e-b292-d8f425edd650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664327518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3664327518
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2522922831
Short name T170
Test name
Test status
Simulation time 3624521606 ps
CPU time 13.17 seconds
Started Aug 09 07:09:28 PM PDT 24
Finished Aug 09 07:09:41 PM PDT 24
Peak memory 208840 kb
Host smart-6907b67c-69b1-4e69-b3e5-7303523934fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522922831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2522922831
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.646237043
Short name T512
Test name
Test status
Simulation time 123609290 ps
CPU time 1.6 seconds
Started Aug 09 07:09:25 PM PDT 24
Finished Aug 09 07:09:27 PM PDT 24
Peak memory 208556 kb
Host smart-9316433c-b005-42f3-b645-d281282190b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646237043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.646237043
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.101336563
Short name T199
Test name
Test status
Simulation time 157537579 ps
CPU time 1.36 seconds
Started Aug 09 07:09:18 PM PDT 24
Finished Aug 09 07:09:20 PM PDT 24
Peak memory 200468 kb
Host smart-d7c9b7f8-6c88-48fa-b34a-2b1ff3cbbd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101336563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.101336563
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1006250026
Short name T173
Test name
Test status
Simulation time 70036388 ps
CPU time 0.77 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200188 kb
Host smart-c9150bc9-3540-4b98-9d4f-db59da4f2d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006250026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1006250026
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3372074418
Short name T445
Test name
Test status
Simulation time 1217212861 ps
CPU time 5.61 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:59 PM PDT 24
Peak memory 217692 kb
Host smart-281088a6-0fef-4251-9eb9-a95bbc05dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372074418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3372074418
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3160933055
Short name T381
Test name
Test status
Simulation time 244449879 ps
CPU time 1.15 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 217592 kb
Host smart-337c4d6d-c04a-4200-a385-ae7776f9af07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160933055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3160933055
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3124066344
Short name T291
Test name
Test status
Simulation time 143106351 ps
CPU time 0.88 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200160 kb
Host smart-b2d444b0-ac2a-4e21-a486-2184fddcbaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124066344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3124066344
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.945482405
Short name T95
Test name
Test status
Simulation time 1700163032 ps
CPU time 6.38 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:58 PM PDT 24
Peak memory 200468 kb
Host smart-dee3b5dc-2d4f-4dc6-b35e-0d9cbdc61fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945482405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.945482405
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.894755046
Short name T511
Test name
Test status
Simulation time 92743611 ps
CPU time 0.93 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200376 kb
Host smart-bd5de85a-bfaa-447f-9efc-96c0548c46f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894755046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.894755046
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1851836707
Short name T357
Test name
Test status
Simulation time 189540597 ps
CPU time 1.43 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200480 kb
Host smart-f693a5a8-2d25-44ba-84c2-8a15f192d57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851836707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1851836707
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.256161467
Short name T485
Test name
Test status
Simulation time 10199163268 ps
CPU time 33.13 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:10:25 PM PDT 24
Peak memory 200648 kb
Host smart-33b8228c-a2f6-453a-855d-be7d97345cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256161467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.256161467
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3814734049
Short name T493
Test name
Test status
Simulation time 151738973 ps
CPU time 1.89 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200264 kb
Host smart-aec33bd6-fcce-4dd0-9f2a-7b9cc56f15a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814734049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3814734049
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3631433044
Short name T149
Test name
Test status
Simulation time 171527349 ps
CPU time 1.32 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200564 kb
Host smart-c27b0dd5-95bd-437f-95db-a98b0370d304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631433044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3631433044
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1943084079
Short name T153
Test name
Test status
Simulation time 63572143 ps
CPU time 0.73 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200160 kb
Host smart-08415978-72ba-42b3-89e3-14d05b184bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943084079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1943084079
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.99726171
Short name T471
Test name
Test status
Simulation time 1231331250 ps
CPU time 5.95 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:10:00 PM PDT 24
Peak memory 217768 kb
Host smart-fa5e5de2-b4b2-4e6f-b389-20479a122fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99726171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.99726171
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2663961426
Short name T25
Test name
Test status
Simulation time 244947397 ps
CPU time 1.06 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 217540 kb
Host smart-6e7c0786-1542-4382-9201-1e14af6686b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663961426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2663961426
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1065126628
Short name T22
Test name
Test status
Simulation time 162275269 ps
CPU time 0.83 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200088 kb
Host smart-30827d29-9e04-4729-9541-5ba87caf20f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065126628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1065126628
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.345858405
Short name T151
Test name
Test status
Simulation time 2129797941 ps
CPU time 7.23 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200572 kb
Host smart-bffbaaba-4b5d-4cdd-a4f6-82ef4d4f2c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345858405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.345858405
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.291225767
Short name T214
Test name
Test status
Simulation time 108539255 ps
CPU time 1.04 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200388 kb
Host smart-c8c6a455-d80f-4d26-aa9a-c693527455ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291225767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.291225767
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1202146536
Short name T9
Test name
Test status
Simulation time 249365573 ps
CPU time 1.51 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200404 kb
Host smart-d8671391-0d9a-4715-a636-8dfae7b7b87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202146536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1202146536
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3482944922
Short name T255
Test name
Test status
Simulation time 10733567279 ps
CPU time 37.59 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:10:32 PM PDT 24
Peak memory 208768 kb
Host smart-b56d0fc3-74a6-4a1d-89d0-4e14b11fb419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482944922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3482944922
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2217011099
Short name T366
Test name
Test status
Simulation time 146785421 ps
CPU time 1.92 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200276 kb
Host smart-ea2f0e81-d66c-482b-8459-c83473991e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217011099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2217011099
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.416141831
Short name T275
Test name
Test status
Simulation time 114123843 ps
CPU time 0.91 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200256 kb
Host smart-0500d274-214a-4316-bfbb-0526a0f05d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416141831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.416141831
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.63222892
Short name T175
Test name
Test status
Simulation time 62329568 ps
CPU time 0.81 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200120 kb
Host smart-ec7fcbac-2d1f-4f56-b95b-011feec43f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63222892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.63222892
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2959972838
Short name T39
Test name
Test status
Simulation time 1891454140 ps
CPU time 7.4 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:10:02 PM PDT 24
Peak memory 221740 kb
Host smart-527348b2-adf3-4a02-be41-080ed67612f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959972838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2959972838
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3522891547
Short name T365
Test name
Test status
Simulation time 244573799 ps
CPU time 1.08 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 217496 kb
Host smart-7a2a7d80-5abb-4762-9e6c-721f14da9c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522891547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3522891547
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1493437321
Short name T304
Test name
Test status
Simulation time 189366999 ps
CPU time 0.89 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200156 kb
Host smart-837e95ff-55ac-4734-a9f3-e23f672d8cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493437321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1493437321
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3459923813
Short name T215
Test name
Test status
Simulation time 1720718575 ps
CPU time 6.32 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200576 kb
Host smart-b951db57-02db-4a88-80b2-18ef03de0923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459923813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3459923813
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.110088327
Short name T312
Test name
Test status
Simulation time 176993098 ps
CPU time 1.14 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200384 kb
Host smart-78df0c31-7269-463d-9ac6-6c624a7127a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110088327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.110088327
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3257557566
Short name T124
Test name
Test status
Simulation time 200650663 ps
CPU time 1.42 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200544 kb
Host smart-a6b28bcc-3952-4b5b-9034-89c6973a2694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257557566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3257557566
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.3840144809
Short name T480
Test name
Test status
Simulation time 12817883766 ps
CPU time 43.09 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:10:37 PM PDT 24
Peak memory 208660 kb
Host smart-81ebc1a3-f367-4a5a-9a21-c386eac10b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840144809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3840144809
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2316451211
Short name T530
Test name
Test status
Simulation time 362860049 ps
CPU time 2.32 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200216 kb
Host smart-74cf62a1-a3ad-4760-867c-28dc8b3b4b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316451211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2316451211
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1767529444
Short name T477
Test name
Test status
Simulation time 147737783 ps
CPU time 1.18 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200520 kb
Host smart-b04c74f7-b01f-47ba-ae2c-cea5b41a95a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767529444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1767529444
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3437061427
Short name T425
Test name
Test status
Simulation time 74290756 ps
CPU time 0.81 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200156 kb
Host smart-bd6fca8d-afde-4685-9a3d-313884d5a9cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437061427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3437061427
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1012676447
Short name T54
Test name
Test status
Simulation time 2337125999 ps
CPU time 9.14 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:59 PM PDT 24
Peak memory 221784 kb
Host smart-9ef8c50f-bddf-4e1e-bd28-d674e152e5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012676447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1012676447
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.384510702
Short name T522
Test name
Test status
Simulation time 244122493 ps
CPU time 1.16 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 217488 kb
Host smart-b1149793-7889-474a-99d2-49469a822656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384510702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.384510702
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3961684707
Short name T271
Test name
Test status
Simulation time 186659594 ps
CPU time 0.88 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200112 kb
Host smart-2b04dc69-1a85-48d1-b12d-2535bce75ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961684707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3961684707
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.54044891
Short name T502
Test name
Test status
Simulation time 1504047553 ps
CPU time 5.81 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200576 kb
Host smart-43ecb876-87cc-4322-af32-e76d6198ec46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54044891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.54044891
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1897622910
Short name T419
Test name
Test status
Simulation time 106662446 ps
CPU time 1.04 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200344 kb
Host smart-04efe1b3-2acf-45d6-bcca-6c04eacd4e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897622910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1897622910
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2329982036
Short name T210
Test name
Test status
Simulation time 201660452 ps
CPU time 1.41 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200472 kb
Host smart-564ad2b0-6db7-4b71-b60d-556fe81d3807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329982036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2329982036
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.803122338
Short name T44
Test name
Test status
Simulation time 2830516455 ps
CPU time 11.48 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:10:05 PM PDT 24
Peak memory 200624 kb
Host smart-dd0aafa1-4740-4ec5-9f6f-c3a6ab42b91a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803122338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.803122338
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3682244972
Short name T371
Test name
Test status
Simulation time 436070129 ps
CPU time 2.45 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200380 kb
Host smart-07bf13fc-3ff7-4af8-aa4b-1f02a08e94fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682244972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3682244972
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.624514087
Short name T490
Test name
Test status
Simulation time 76445729 ps
CPU time 0.84 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200556 kb
Host smart-bd95a309-89e1-4323-9128-ac568f9ae11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624514087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.624514087
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2625167620
Short name T519
Test name
Test status
Simulation time 69907331 ps
CPU time 0.81 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:52 PM PDT 24
Peak memory 200196 kb
Host smart-34d36ce6-b29c-4104-a453-ba1bb57a2ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625167620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2625167620
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2964480107
Short name T433
Test name
Test status
Simulation time 1875210151 ps
CPU time 6.83 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:59 PM PDT 24
Peak memory 217732 kb
Host smart-074ffbe2-e1ab-4f55-af3d-bcfc8d862fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964480107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2964480107
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1178136740
Short name T475
Test name
Test status
Simulation time 244791358 ps
CPU time 1.1 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:52 PM PDT 24
Peak memory 217544 kb
Host smart-ee102326-75c1-4677-aa27-41f8e8d1123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178136740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1178136740
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2989550386
Short name T460
Test name
Test status
Simulation time 224361206 ps
CPU time 1.02 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200156 kb
Host smart-0f6ede9d-97cd-4b7c-99c1-4d298843e2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989550386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2989550386
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3649618474
Short name T222
Test name
Test status
Simulation time 1541825411 ps
CPU time 5.9 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200552 kb
Host smart-dd3e2919-66e1-4056-a451-cfb8e2d75346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649618474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3649618474
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3397698353
Short name T504
Test name
Test status
Simulation time 102665162 ps
CPU time 1 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200364 kb
Host smart-305f5fab-8bed-4cde-bc6f-f1e43ab9e9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397698353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3397698353
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.4024167159
Short name T396
Test name
Test status
Simulation time 196082676 ps
CPU time 1.35 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200448 kb
Host smart-52ade70f-2e84-4ca9-98fa-2563e66f17c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024167159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.4024167159
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.332898867
Short name T51
Test name
Test status
Simulation time 9832273963 ps
CPU time 32.87 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:10:24 PM PDT 24
Peak memory 200484 kb
Host smart-919cd60c-0551-4f46-be3b-ca358d6a5b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332898867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.332898867
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1890485586
Short name T510
Test name
Test status
Simulation time 125950902 ps
CPU time 1.59 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200264 kb
Host smart-999dd346-ecac-4629-8302-855576590812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890485586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1890485586
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1637885521
Short name T426
Test name
Test status
Simulation time 127696415 ps
CPU time 1.09 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200304 kb
Host smart-cc456069-ea32-4db3-b7c7-486b91d78eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637885521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1637885521
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2219430531
Short name T277
Test name
Test status
Simulation time 70945937 ps
CPU time 0.78 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:47 PM PDT 24
Peak memory 200148 kb
Host smart-63ea1dbf-5d52-4821-b6fe-71bcef4478f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219430531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2219430531
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2428962417
Short name T300
Test name
Test status
Simulation time 2172175139 ps
CPU time 7.66 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 217116 kb
Host smart-42b493cb-1ce9-4191-9a68-dfbe22c97d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428962417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2428962417
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1479018498
Short name T360
Test name
Test status
Simulation time 244531279 ps
CPU time 1.07 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 217448 kb
Host smart-8d53007e-9707-4fcb-be61-fcf7fa2ab21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479018498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1479018498
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3419665681
Short name T236
Test name
Test status
Simulation time 114730925 ps
CPU time 0.8 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200140 kb
Host smart-6f44f1b6-65a5-4b11-b606-844620541064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419665681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3419665681
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3798641640
Short name T96
Test name
Test status
Simulation time 1702873177 ps
CPU time 6.28 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 200536 kb
Host smart-8b2dbde7-4205-42ac-8646-5f76c9258002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798641640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3798641640
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3125550293
Short name T221
Test name
Test status
Simulation time 113582171 ps
CPU time 1.02 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200344 kb
Host smart-b51f3779-1cc8-4e9e-9a3e-638a8305ceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125550293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3125550293
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.693623418
Short name T218
Test name
Test status
Simulation time 116897022 ps
CPU time 1.25 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200460 kb
Host smart-38f02be5-bd86-42c0-96c0-97885582a13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693623418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.693623418
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3464845281
Short name T140
Test name
Test status
Simulation time 4173805622 ps
CPU time 17.61 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:10:10 PM PDT 24
Peak memory 200400 kb
Host smart-f7003a84-4c67-4e78-881f-69d7648dcdda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464845281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3464845281
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.875464
Short name T194
Test name
Test status
Simulation time 133288588 ps
CPU time 1.58 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 208532 kb
Host smart-184dfbf2-7fd0-4deb-99d4-c5e36cf37c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.875464
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1884334424
Short name T89
Test name
Test status
Simulation time 113910486 ps
CPU time 1.09 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200344 kb
Host smart-2c872e97-0435-4c8b-82b7-d1565c233a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884334424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1884334424
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.1518968029
Short name T167
Test name
Test status
Simulation time 65441843 ps
CPU time 0.77 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 200156 kb
Host smart-79264ddd-5cd6-4aaa-aab1-9f0ef044d4bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518968029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1518968029
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1855494470
Short name T309
Test name
Test status
Simulation time 1221198262 ps
CPU time 5.36 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 221720 kb
Host smart-085f3d7f-411c-485d-9e45-42b437c4f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855494470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1855494470
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.137447598
Short name T292
Test name
Test status
Simulation time 245581830 ps
CPU time 1.05 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 209064 kb
Host smart-83f00844-2ff2-4114-90b6-c360124f346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137447598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.137447598
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2979129588
Short name T313
Test name
Test status
Simulation time 133855405 ps
CPU time 0.83 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 199956 kb
Host smart-503cae2c-3ff6-4127-8b75-6e00a224d608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979129588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2979129588
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2055704011
Short name T434
Test name
Test status
Simulation time 834336861 ps
CPU time 3.84 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200412 kb
Host smart-36e516d8-8738-43d3-9ba1-26e58351703c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055704011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2055704011
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1320370319
Short name T212
Test name
Test status
Simulation time 154038042 ps
CPU time 1.15 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200280 kb
Host smart-d1f3d0f6-5826-43ab-a205-682e78780e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320370319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1320370319
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2756805500
Short name T432
Test name
Test status
Simulation time 202861794 ps
CPU time 1.35 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200464 kb
Host smart-22cad3e4-472e-4920-9ec7-9001c3934908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756805500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2756805500
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2059624473
Short name T235
Test name
Test status
Simulation time 5731155012 ps
CPU time 23.8 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 200604 kb
Host smart-0ac89b3d-1ce1-4eae-84ca-728909e394cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059624473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2059624473
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.542488368
Short name T160
Test name
Test status
Simulation time 123987413 ps
CPU time 1.52 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:52 PM PDT 24
Peak memory 200256 kb
Host smart-0c9c283f-9e59-43ea-85a3-95ab3f7323c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542488368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.542488368
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.745988240
Short name T535
Test name
Test status
Simulation time 147749329 ps
CPU time 1.22 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200204 kb
Host smart-1d72d1e3-9fe7-4a98-859f-c66ad44729e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745988240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.745988240
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3839073273
Short name T311
Test name
Test status
Simulation time 54776786 ps
CPU time 0.71 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200148 kb
Host smart-70182490-0f40-415b-a0c8-aa07dab9f553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839073273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3839073273
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3414411866
Short name T35
Test name
Test status
Simulation time 1233211622 ps
CPU time 5.37 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 221660 kb
Host smart-e7a86df4-3221-4d79-84c7-e8419a8bfa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414411866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3414411866
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3719642100
Short name T122
Test name
Test status
Simulation time 244611235 ps
CPU time 1.02 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 217588 kb
Host smart-01f47061-21f3-40c7-9482-3a6bd6a741fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719642100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3719642100
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.2628785302
Short name T163
Test name
Test status
Simulation time 91493579 ps
CPU time 0.76 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200152 kb
Host smart-8e4b6a2a-b63d-4b1d-bb4b-b41da61bd55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628785302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.2628785302
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2078305964
Short name T514
Test name
Test status
Simulation time 1412491618 ps
CPU time 5.47 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:10:00 PM PDT 24
Peak memory 200552 kb
Host smart-c9b54eb5-2d09-4fe8-946b-501edda89b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078305964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2078305964
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2913774506
Short name T246
Test name
Test status
Simulation time 172869140 ps
CPU time 1.21 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200328 kb
Host smart-3673f987-8877-4578-b8ca-98242b3c32a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913774506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2913774506
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3742436455
Short name T326
Test name
Test status
Simulation time 122734736 ps
CPU time 1.22 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:09:58 PM PDT 24
Peak memory 200468 kb
Host smart-e0b0344d-1c84-4e0d-837a-5bd41cdd4618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742436455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3742436455
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3420813702
Short name T252
Test name
Test status
Simulation time 6210448500 ps
CPU time 22.59 seconds
Started Aug 09 07:09:58 PM PDT 24
Finished Aug 09 07:10:21 PM PDT 24
Peak memory 208796 kb
Host smart-73ad4e04-84b7-490a-893c-0ed29be4c9d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420813702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3420813702
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.600065542
Short name T234
Test name
Test status
Simulation time 139744939 ps
CPU time 1.85 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200276 kb
Host smart-5e4536f1-e47c-4c49-87e0-ce7b9e2b3b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600065542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.600065542
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1079746471
Short name T228
Test name
Test status
Simulation time 134277142 ps
CPU time 1.14 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200280 kb
Host smart-f9771dc9-ef8f-4822-b7cf-2ab84e4019bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079746471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1079746471
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4182860034
Short name T457
Test name
Test status
Simulation time 65870263 ps
CPU time 0.76 seconds
Started Aug 09 07:10:01 PM PDT 24
Finished Aug 09 07:10:02 PM PDT 24
Peak memory 200076 kb
Host smart-99b00572-734a-439a-9420-47e67ba2b14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182860034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4182860034
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2703201377
Short name T30
Test name
Test status
Simulation time 2358094993 ps
CPU time 9.25 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 221820 kb
Host smart-eea9df64-e0fb-47ac-8beb-94b2db75e83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703201377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2703201377
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.363154707
Short name T420
Test name
Test status
Simulation time 244786337 ps
CPU time 1.02 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 217528 kb
Host smart-f99d9301-e62e-4cf3-b581-b551acf94247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363154707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.363154707
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3503085938
Short name T17
Test name
Test status
Simulation time 185190453 ps
CPU time 0.87 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200136 kb
Host smart-8ecb950a-5c28-4dad-acf7-9e0e01b75071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503085938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3503085938
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.4259556416
Short name T352
Test name
Test status
Simulation time 1445413909 ps
CPU time 5.6 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:58 PM PDT 24
Peak memory 200488 kb
Host smart-b182ca5f-a2e0-4fdb-aa35-a133340d9112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259556416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.4259556416
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.367927556
Short name T73
Test name
Test status
Simulation time 106193093 ps
CPU time 1.09 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 200292 kb
Host smart-74b62efe-1b60-4952-9237-ae2ea0ee2316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367927556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.367927556
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3252258986
Short name T2
Test name
Test status
Simulation time 196570435 ps
CPU time 1.33 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200468 kb
Host smart-f86571d7-2ff9-4a26-9317-a997f1f81fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252258986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3252258986
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3299824290
Short name T192
Test name
Test status
Simulation time 14033137109 ps
CPU time 49.94 seconds
Started Aug 09 07:10:00 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200636 kb
Host smart-d9f93a3e-6eeb-49c5-9ec5-2a5e817e0002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299824290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3299824290
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.926238144
Short name T90
Test name
Test status
Simulation time 153785829 ps
CPU time 1.93 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200308 kb
Host smart-25dbdb1d-7e30-4516-859c-2ae1c9cc24ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926238144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.926238144
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1602969602
Short name T248
Test name
Test status
Simulation time 113157497 ps
CPU time 0.88 seconds
Started Aug 09 07:09:53 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200376 kb
Host smart-36d5af8c-8733-43df-ac22-84a79867b12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602969602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1602969602
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3480531905
Short name T346
Test name
Test status
Simulation time 73525640 ps
CPU time 0.78 seconds
Started Aug 09 07:10:02 PM PDT 24
Finished Aug 09 07:10:03 PM PDT 24
Peak memory 200160 kb
Host smart-23542517-b3f0-4cfa-85cb-54042735e8de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480531905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3480531905
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.3085544841
Short name T328
Test name
Test status
Simulation time 1888886317 ps
CPU time 6.58 seconds
Started Aug 09 07:09:57 PM PDT 24
Finished Aug 09 07:10:03 PM PDT 24
Peak memory 217752 kb
Host smart-16445e79-55de-4502-9d99-e8e953c8182e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085544841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3085544841
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1151130698
Short name T203
Test name
Test status
Simulation time 244374006 ps
CPU time 1.07 seconds
Started Aug 09 07:10:10 PM PDT 24
Finished Aug 09 07:10:11 PM PDT 24
Peak memory 217568 kb
Host smart-1459fa28-e7ee-4830-9eb7-c95cd244e86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151130698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1151130698
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3703978512
Short name T415
Test name
Test status
Simulation time 118330760 ps
CPU time 0.77 seconds
Started Aug 09 07:09:58 PM PDT 24
Finished Aug 09 07:09:59 PM PDT 24
Peak memory 200180 kb
Host smart-ad3db962-0fbd-4c09-a9e4-cd735a29ac6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703978512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3703978512
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.783607432
Short name T449
Test name
Test status
Simulation time 1380746689 ps
CPU time 5.64 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:10:02 PM PDT 24
Peak memory 200560 kb
Host smart-16d1fcbc-6ce0-4719-a1fe-3b1f9b4046ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783607432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.783607432
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1778686095
Short name T361
Test name
Test status
Simulation time 101530430 ps
CPU time 0.95 seconds
Started Aug 09 07:09:58 PM PDT 24
Finished Aug 09 07:09:59 PM PDT 24
Peak memory 200368 kb
Host smart-db6763ca-0310-4fcb-bc65-12345755ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778686095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1778686095
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.101589597
Short name T268
Test name
Test status
Simulation time 200152667 ps
CPU time 1.35 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200492 kb
Host smart-7c7f964d-801d-4d77-b191-d63eb2bdfadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101589597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.101589597
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2414827244
Short name T188
Test name
Test status
Simulation time 2061330660 ps
CPU time 10.11 seconds
Started Aug 09 07:10:00 PM PDT 24
Finished Aug 09 07:10:10 PM PDT 24
Peak memory 200560 kb
Host smart-44e5b902-2992-4e56-9a32-b10b66472c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414827244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2414827244
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1102947394
Short name T14
Test name
Test status
Simulation time 382497596 ps
CPU time 2.51 seconds
Started Aug 09 07:10:01 PM PDT 24
Finished Aug 09 07:10:03 PM PDT 24
Peak memory 200276 kb
Host smart-f3bed884-29af-48f4-ae8c-c6df23cc0ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102947394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1102947394
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.4079054888
Short name T348
Test name
Test status
Simulation time 73607470 ps
CPU time 0.81 seconds
Started Aug 09 07:09:54 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200316 kb
Host smart-23f9b0aa-4214-4047-98a6-dfd0cb61a38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079054888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.4079054888
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1564015486
Short name T506
Test name
Test status
Simulation time 77453840 ps
CPU time 0.8 seconds
Started Aug 09 07:09:25 PM PDT 24
Finished Aug 09 07:09:26 PM PDT 24
Peak memory 200144 kb
Host smart-cbe57d3c-d1cd-47b6-82f6-02c7559d2e16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564015486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1564015486
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.4167049377
Short name T428
Test name
Test status
Simulation time 1894829710 ps
CPU time 6.56 seconds
Started Aug 09 07:09:22 PM PDT 24
Finished Aug 09 07:09:28 PM PDT 24
Peak memory 221744 kb
Host smart-69abdbe2-af1c-4d48-8998-3a15507a4f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167049377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.4167049377
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.833943861
Short name T376
Test name
Test status
Simulation time 244120238 ps
CPU time 1.11 seconds
Started Aug 09 07:09:26 PM PDT 24
Finished Aug 09 07:09:27 PM PDT 24
Peak memory 216192 kb
Host smart-388b9735-0a00-46b3-a19c-694e69d3a62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833943861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.833943861
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1754846719
Short name T395
Test name
Test status
Simulation time 145778734 ps
CPU time 0.85 seconds
Started Aug 09 07:09:24 PM PDT 24
Finished Aug 09 07:09:25 PM PDT 24
Peak memory 200160 kb
Host smart-c87b31a9-62b0-4217-9a55-3529661e5d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754846719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1754846719
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.1490753376
Short name T226
Test name
Test status
Simulation time 1981661960 ps
CPU time 8.45 seconds
Started Aug 09 07:09:15 PM PDT 24
Finished Aug 09 07:09:24 PM PDT 24
Peak memory 200636 kb
Host smart-c71e515d-6018-4b62-8c20-fbad5ed67f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490753376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1490753376
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2544592600
Short name T66
Test name
Test status
Simulation time 16548997372 ps
CPU time 28.32 seconds
Started Aug 09 07:09:22 PM PDT 24
Finished Aug 09 07:09:50 PM PDT 24
Peak memory 217360 kb
Host smart-49ab0070-d8d8-4793-b42b-047649f6c488
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544592600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2544592600
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3405284294
Short name T397
Test name
Test status
Simulation time 107942320 ps
CPU time 0.99 seconds
Started Aug 09 07:09:34 PM PDT 24
Finished Aug 09 07:09:35 PM PDT 24
Peak memory 200324 kb
Host smart-f1b53234-87c5-4cab-8348-841b1049f1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405284294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3405284294
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4052428651
Short name T189
Test name
Test status
Simulation time 113486298 ps
CPU time 1.19 seconds
Started Aug 09 07:09:24 PM PDT 24
Finished Aug 09 07:09:25 PM PDT 24
Peak memory 200468 kb
Host smart-17c1a68a-e214-42ea-9e70-fc5fbcbd9243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052428651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4052428651
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1305897096
Short name T314
Test name
Test status
Simulation time 1036737470 ps
CPU time 4.5 seconds
Started Aug 09 07:09:15 PM PDT 24
Finished Aug 09 07:09:20 PM PDT 24
Peak memory 200452 kb
Host smart-0e6662a5-19ef-46cc-ba0b-acaa551971b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305897096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1305897096
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.4080176487
Short name T125
Test name
Test status
Simulation time 125617766 ps
CPU time 1.61 seconds
Started Aug 09 07:09:21 PM PDT 24
Finished Aug 09 07:09:23 PM PDT 24
Peak memory 199236 kb
Host smart-501c2745-a056-401b-aba6-ff9ef373b075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080176487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4080176487
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3105538539
Short name T176
Test name
Test status
Simulation time 271033446 ps
CPU time 1.6 seconds
Started Aug 09 07:09:21 PM PDT 24
Finished Aug 09 07:09:23 PM PDT 24
Peak memory 200720 kb
Host smart-6cbcf302-2f15-456e-993b-02668fe81937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105538539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3105538539
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.285802201
Short name T238
Test name
Test status
Simulation time 79732041 ps
CPU time 0.78 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200164 kb
Host smart-fd949fda-46a0-45de-ae3c-edfdf8626356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285802201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.285802201
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3104579800
Short name T6
Test name
Test status
Simulation time 1883263571 ps
CPU time 8.09 seconds
Started Aug 09 07:09:55 PM PDT 24
Finished Aug 09 07:10:04 PM PDT 24
Peak memory 217540 kb
Host smart-d3ad89d1-888e-4c99-a563-eac4759ced80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104579800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3104579800
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.232396575
Short name T285
Test name
Test status
Simulation time 244148234 ps
CPU time 1.05 seconds
Started Aug 09 07:10:12 PM PDT 24
Finished Aug 09 07:10:13 PM PDT 24
Peak memory 217512 kb
Host smart-6c896d0a-6a40-43a2-b70d-9b70eb767637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232396575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.232396575
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.407212220
Short name T482
Test name
Test status
Simulation time 120285014 ps
CPU time 0.79 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200068 kb
Host smart-a4bdae40-a980-4e67-bca3-8054a0599545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407212220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.407212220
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3976613810
Short name T295
Test name
Test status
Simulation time 1074873347 ps
CPU time 4.89 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 200556 kb
Host smart-feec2e5a-2f7e-43d7-8995-0446f800d39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976613810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3976613810
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2153605141
Short name T467
Test name
Test status
Simulation time 102163437 ps
CPU time 0.98 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:09:58 PM PDT 24
Peak memory 200352 kb
Host smart-bb252bbd-6272-4696-98e6-4038495a6440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153605141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2153605141
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.518345082
Short name T401
Test name
Test status
Simulation time 187280204 ps
CPU time 1.37 seconds
Started Aug 09 07:09:52 PM PDT 24
Finished Aug 09 07:09:55 PM PDT 24
Peak memory 200508 kb
Host smart-b197e8a6-0e1f-4f02-b32e-1a402a163ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518345082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.518345082
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3848207312
Short name T466
Test name
Test status
Simulation time 3250979750 ps
CPU time 11.63 seconds
Started Aug 09 07:09:57 PM PDT 24
Finished Aug 09 07:10:09 PM PDT 24
Peak memory 200560 kb
Host smart-33787104-78c0-45ec-b1d0-bbfe10933afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848207312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3848207312
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.4188120240
Short name T72
Test name
Test status
Simulation time 424040262 ps
CPU time 2.25 seconds
Started Aug 09 07:09:57 PM PDT 24
Finished Aug 09 07:09:59 PM PDT 24
Peak memory 208492 kb
Host smart-cb708923-fa8e-4a4b-b23c-02592e01106a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188120240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4188120240
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2157785468
Short name T269
Test name
Test status
Simulation time 71823877 ps
CPU time 0.79 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 200380 kb
Host smart-7888bf63-471f-490b-be4b-2269faaa160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157785468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2157785468
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2711962598
Short name T423
Test name
Test status
Simulation time 64771643 ps
CPU time 0.75 seconds
Started Aug 09 07:10:01 PM PDT 24
Finished Aug 09 07:10:02 PM PDT 24
Peak memory 200148 kb
Host smart-bc2a31a9-0836-458b-8f14-3fb25237f3e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711962598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2711962598
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2733150835
Short name T31
Test name
Test status
Simulation time 1898213497 ps
CPU time 7.19 seconds
Started Aug 09 07:09:59 PM PDT 24
Finished Aug 09 07:10:06 PM PDT 24
Peak memory 217328 kb
Host smart-d8bfb15d-7920-4764-ac4c-bc918724600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733150835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2733150835
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1599077863
Short name T290
Test name
Test status
Simulation time 243327103 ps
CPU time 1.11 seconds
Started Aug 09 07:10:05 PM PDT 24
Finished Aug 09 07:10:06 PM PDT 24
Peak memory 217592 kb
Host smart-df44ea1f-69c6-4b10-bacc-1981db5523a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599077863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1599077863
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.891329928
Short name T198
Test name
Test status
Simulation time 235989800 ps
CPU time 0.91 seconds
Started Aug 09 07:09:59 PM PDT 24
Finished Aug 09 07:10:00 PM PDT 24
Peak memory 200148 kb
Host smart-baf52cd4-b66b-4a51-8c9d-eb2e0229c65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891329928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.891329928
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2908872654
Short name T521
Test name
Test status
Simulation time 773320380 ps
CPU time 3.78 seconds
Started Aug 09 07:09:58 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 200564 kb
Host smart-f3ca0576-de99-4ec3-b5f3-855c2b1a85dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908872654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2908872654
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.4117239719
Short name T316
Test name
Test status
Simulation time 149273356 ps
CPU time 1.09 seconds
Started Aug 09 07:09:59 PM PDT 24
Finished Aug 09 07:10:00 PM PDT 24
Peak memory 200344 kb
Host smart-b2a3b1e6-a731-493c-9d53-82ba1e836811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117239719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.4117239719
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.657822194
Short name T382
Test name
Test status
Simulation time 252198157 ps
CPU time 1.53 seconds
Started Aug 09 07:09:57 PM PDT 24
Finished Aug 09 07:09:58 PM PDT 24
Peak memory 200496 kb
Host smart-55049040-6025-42d4-a91b-217938d550e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657822194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.657822194
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2019380821
Short name T148
Test name
Test status
Simulation time 1447127808 ps
CPU time 5.9 seconds
Started Aug 09 07:09:58 PM PDT 24
Finished Aug 09 07:10:04 PM PDT 24
Peak memory 200552 kb
Host smart-47d06984-e740-4990-9dd0-960ce5fd558d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019380821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2019380821
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.2338020016
Short name T132
Test name
Test status
Simulation time 348125119 ps
CPU time 2.48 seconds
Started Aug 09 07:10:02 PM PDT 24
Finished Aug 09 07:10:05 PM PDT 24
Peak memory 200348 kb
Host smart-c658be7f-707b-4dcd-b739-204bad5ffe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338020016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2338020016
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2030482007
Short name T329
Test name
Test status
Simulation time 140026531 ps
CPU time 0.94 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:09:57 PM PDT 24
Peak memory 199240 kb
Host smart-ac3dbd91-ce69-41b1-8023-e0c2b3533145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030482007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2030482007
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1856658973
Short name T336
Test name
Test status
Simulation time 80067615 ps
CPU time 0.78 seconds
Started Aug 09 07:10:06 PM PDT 24
Finished Aug 09 07:10:07 PM PDT 24
Peak memory 200176 kb
Host smart-0db3cf7a-4cac-4340-8963-ed9f886024be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856658973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1856658973
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3838399234
Short name T91
Test name
Test status
Simulation time 1226747431 ps
CPU time 5.27 seconds
Started Aug 09 07:10:01 PM PDT 24
Finished Aug 09 07:10:07 PM PDT 24
Peak memory 216760 kb
Host smart-e4e295b7-c51f-48c3-aed8-dc7488d6754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838399234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3838399234
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1516177098
Short name T8
Test name
Test status
Simulation time 244023220 ps
CPU time 1.05 seconds
Started Aug 09 07:10:11 PM PDT 24
Finished Aug 09 07:10:12 PM PDT 24
Peak memory 217572 kb
Host smart-c785a04b-e61b-4bc6-8693-2f3a34e9765a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516177098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1516177098
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.4096378343
Short name T174
Test name
Test status
Simulation time 175745118 ps
CPU time 0.9 seconds
Started Aug 09 07:10:01 PM PDT 24
Finished Aug 09 07:10:02 PM PDT 24
Peak memory 200160 kb
Host smart-db0b5a7e-9ee7-465e-94f1-f1f097992b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096378343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.4096378343
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2699508529
Short name T355
Test name
Test status
Simulation time 1821789990 ps
CPU time 7.56 seconds
Started Aug 09 07:10:01 PM PDT 24
Finished Aug 09 07:10:08 PM PDT 24
Peak memory 200552 kb
Host smart-7456dcf7-daa7-48f9-be21-ffe2e7d1540a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699508529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2699508529
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.480189300
Short name T121
Test name
Test status
Simulation time 147577749 ps
CPU time 1.12 seconds
Started Aug 09 07:10:03 PM PDT 24
Finished Aug 09 07:10:04 PM PDT 24
Peak memory 200340 kb
Host smart-55d76dd5-31b8-46f7-89f4-9edeaad66383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480189300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.480189300
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.3903848356
Short name T130
Test name
Test status
Simulation time 116621059 ps
CPU time 1.19 seconds
Started Aug 09 07:10:08 PM PDT 24
Finished Aug 09 07:10:09 PM PDT 24
Peak memory 200488 kb
Host smart-09ad43bb-3da9-40ce-9c7d-37e11fc0c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903848356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.3903848356
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2216986108
Short name T139
Test name
Test status
Simulation time 6582175676 ps
CPU time 23.79 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:41 PM PDT 24
Peak memory 208796 kb
Host smart-8426a64c-24cf-4a0a-8690-0973a02a8b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216986108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2216986108
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.822431273
Short name T239
Test name
Test status
Simulation time 534583921 ps
CPU time 2.63 seconds
Started Aug 09 07:09:58 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 200296 kb
Host smart-ae6209f5-4a0a-4ab2-8188-3d73f2bd47cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822431273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.822431273
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3990552959
Short name T340
Test name
Test status
Simulation time 167741164 ps
CPU time 1.23 seconds
Started Aug 09 07:09:56 PM PDT 24
Finished Aug 09 07:09:58 PM PDT 24
Peak memory 200464 kb
Host smart-c14f4dfa-c4a1-4ee9-b958-ef7b97ec4b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990552959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3990552959
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.4244981
Short name T193
Test name
Test status
Simulation time 99605559 ps
CPU time 0.83 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 200228 kb
Host smart-6c371572-1240-41d0-b68d-6324d1f44349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.4244981
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3990339895
Short name T431
Test name
Test status
Simulation time 1224591642 ps
CPU time 5.48 seconds
Started Aug 09 07:10:14 PM PDT 24
Finished Aug 09 07:10:20 PM PDT 24
Peak memory 217660 kb
Host smart-6feea061-e1aa-4fd8-a93f-3b36605c404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990339895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3990339895
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.4040811263
Short name T200
Test name
Test status
Simulation time 244611358 ps
CPU time 1.14 seconds
Started Aug 09 07:10:22 PM PDT 24
Finished Aug 09 07:10:23 PM PDT 24
Peak memory 217484 kb
Host smart-3f3719c1-721b-4315-97a4-50a234ea3fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040811263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.4040811263
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3598175795
Short name T330
Test name
Test status
Simulation time 82195340 ps
CPU time 0.72 seconds
Started Aug 09 07:09:59 PM PDT 24
Finished Aug 09 07:09:59 PM PDT 24
Peak memory 200168 kb
Host smart-ac2de342-0f41-41ae-a60c-ff548af9af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598175795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3598175795
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2821587318
Short name T380
Test name
Test status
Simulation time 882490499 ps
CPU time 4.2 seconds
Started Aug 09 07:09:57 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 200480 kb
Host smart-f30ecdaf-6cc9-4416-90b2-8d421fe40fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821587318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2821587318
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3218879665
Short name T347
Test name
Test status
Simulation time 106953946 ps
CPU time 1.1 seconds
Started Aug 09 07:10:24 PM PDT 24
Finished Aug 09 07:10:26 PM PDT 24
Peak memory 200228 kb
Host smart-5565f105-b505-4665-9680-0a6773c80f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218879665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3218879665
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2488491321
Short name T455
Test name
Test status
Simulation time 260744676 ps
CPU time 1.6 seconds
Started Aug 09 07:09:59 PM PDT 24
Finished Aug 09 07:10:00 PM PDT 24
Peak memory 200736 kb
Host smart-08ea0a95-177d-45fe-9448-4f6e776ce31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488491321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2488491321
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1287734287
Short name T102
Test name
Test status
Simulation time 2021133936 ps
CPU time 7.53 seconds
Started Aug 09 07:10:11 PM PDT 24
Finished Aug 09 07:10:19 PM PDT 24
Peak memory 200644 kb
Host smart-4a6ea5ac-3ae2-4f62-8f65-5d935c8b49a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287734287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1287734287
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.2852779252
Short name T282
Test name
Test status
Simulation time 391960047 ps
CPU time 2.21 seconds
Started Aug 09 07:10:18 PM PDT 24
Finished Aug 09 07:10:20 PM PDT 24
Peak memory 200152 kb
Host smart-904a11e5-de2e-49d2-b05c-de609f36c155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852779252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.2852779252
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.515661415
Short name T447
Test name
Test status
Simulation time 98868316 ps
CPU time 0.94 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 200368 kb
Host smart-8af3358c-7fb2-4269-9bd8-dff84255c231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515661415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.515661415
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2458879009
Short name T265
Test name
Test status
Simulation time 80730077 ps
CPU time 0.81 seconds
Started Aug 09 07:10:23 PM PDT 24
Finished Aug 09 07:10:24 PM PDT 24
Peak memory 200012 kb
Host smart-3e1ecaff-cc71-4f38-a54f-a89022fbb2bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458879009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2458879009
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3085638844
Short name T278
Test name
Test status
Simulation time 1883497252 ps
CPU time 7.23 seconds
Started Aug 09 07:10:06 PM PDT 24
Finished Aug 09 07:10:13 PM PDT 24
Peak memory 221716 kb
Host smart-9d6dac08-81c7-409f-91f0-6fa2f9bd7076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085638844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3085638844
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2586103253
Short name T500
Test name
Test status
Simulation time 244151139 ps
CPU time 1.04 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 217488 kb
Host smart-85db885b-7fe7-4c78-b40e-12680d287b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586103253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2586103253
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3328912108
Short name T273
Test name
Test status
Simulation time 215153912 ps
CPU time 0.88 seconds
Started Aug 09 07:10:09 PM PDT 24
Finished Aug 09 07:10:10 PM PDT 24
Peak memory 200344 kb
Host smart-7177a069-790d-4133-86e8-01730f171605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328912108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3328912108
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2757133485
Short name T144
Test name
Test status
Simulation time 882578558 ps
CPU time 4.3 seconds
Started Aug 09 07:10:05 PM PDT 24
Finished Aug 09 07:10:10 PM PDT 24
Peak memory 200712 kb
Host smart-2c03fc4b-a8b4-413c-a59b-b64a1ef6cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757133485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2757133485
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.513789143
Short name T208
Test name
Test status
Simulation time 104105758 ps
CPU time 1 seconds
Started Aug 09 07:10:15 PM PDT 24
Finished Aug 09 07:10:16 PM PDT 24
Peak memory 200364 kb
Host smart-ad6af7d7-e517-4455-aa3b-e5982078a923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513789143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.513789143
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.866409411
Short name T501
Test name
Test status
Simulation time 114282463 ps
CPU time 1.18 seconds
Started Aug 09 07:10:08 PM PDT 24
Finished Aug 09 07:10:10 PM PDT 24
Peak memory 200468 kb
Host smart-902bc259-efcd-4358-aede-14d1eccc6b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866409411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.866409411
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1661540162
Short name T487
Test name
Test status
Simulation time 6130073300 ps
CPU time 27.67 seconds
Started Aug 09 07:10:22 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200560 kb
Host smart-95aa21fe-abcd-4a5e-83db-8c3a46baa87c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661540162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1661540162
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3905687382
Short name T486
Test name
Test status
Simulation time 146416485 ps
CPU time 1.73 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:19 PM PDT 24
Peak memory 200292 kb
Host smart-c75edd6b-d229-4d7e-add9-dc49ba96cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905687382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3905687382
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.241900114
Short name T71
Test name
Test status
Simulation time 152399683 ps
CPU time 1.04 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 200224 kb
Host smart-70db0ee4-2d1b-49cf-93a9-b536e81cd7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241900114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.241900114
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.319699286
Short name T155
Test name
Test status
Simulation time 76989093 ps
CPU time 0.8 seconds
Started Aug 09 07:10:08 PM PDT 24
Finished Aug 09 07:10:08 PM PDT 24
Peak memory 200192 kb
Host smart-4e36d0f6-2c87-4478-9c6b-8ccddcfc79de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319699286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.319699286
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1979014905
Short name T474
Test name
Test status
Simulation time 2164300502 ps
CPU time 7.9 seconds
Started Aug 09 07:10:08 PM PDT 24
Finished Aug 09 07:10:16 PM PDT 24
Peak memory 221696 kb
Host smart-f83cb3f2-93c4-4ddb-9e62-b04a176b6ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979014905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1979014905
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.37165183
Short name T204
Test name
Test status
Simulation time 244822322 ps
CPU time 1.04 seconds
Started Aug 09 07:10:12 PM PDT 24
Finished Aug 09 07:10:13 PM PDT 24
Peak memory 217552 kb
Host smart-2acb15f5-7e71-4ead-aeec-6faef2500e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37165183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.37165183
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2699763870
Short name T421
Test name
Test status
Simulation time 164577262 ps
CPU time 0.8 seconds
Started Aug 09 07:10:15 PM PDT 24
Finished Aug 09 07:10:16 PM PDT 24
Peak memory 200192 kb
Host smart-dc667cf4-3960-4133-af7f-85e0e147ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699763870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2699763870
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3307879096
Short name T400
Test name
Test status
Simulation time 1452580034 ps
CPU time 5.23 seconds
Started Aug 09 07:10:08 PM PDT 24
Finished Aug 09 07:10:14 PM PDT 24
Peak memory 200536 kb
Host smart-f57e37f3-8f3d-49d6-8e90-1d6d77f32c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307879096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3307879096
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2018702238
Short name T245
Test name
Test status
Simulation time 142326493 ps
CPU time 1.15 seconds
Started Aug 09 07:10:07 PM PDT 24
Finished Aug 09 07:10:08 PM PDT 24
Peak memory 200384 kb
Host smart-08c041a7-c7a7-46a2-b399-36ab783a5e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018702238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2018702238
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2024032770
Short name T138
Test name
Test status
Simulation time 113316766 ps
CPU time 1.2 seconds
Started Aug 09 07:10:13 PM PDT 24
Finished Aug 09 07:10:14 PM PDT 24
Peak memory 200460 kb
Host smart-3dcf0c0d-9b0b-46a6-9d1d-2a48114b16cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024032770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2024032770
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3232492586
Short name T196
Test name
Test status
Simulation time 2043136246 ps
CPU time 9.03 seconds
Started Aug 09 07:10:12 PM PDT 24
Finished Aug 09 07:10:21 PM PDT 24
Peak memory 199456 kb
Host smart-7fa1ae41-0647-4f1f-8c6b-0b89dfa17655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232492586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3232492586
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2693771453
Short name T136
Test name
Test status
Simulation time 324198606 ps
CPU time 1.96 seconds
Started Aug 09 07:10:13 PM PDT 24
Finished Aug 09 07:10:15 PM PDT 24
Peak memory 200276 kb
Host smart-8c8c2f9e-9f7e-4ca7-b4ca-236b2ba6d9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693771453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2693771453
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1825437469
Short name T327
Test name
Test status
Simulation time 118624483 ps
CPU time 1.04 seconds
Started Aug 09 07:10:13 PM PDT 24
Finished Aug 09 07:10:15 PM PDT 24
Peak memory 200280 kb
Host smart-d8c51fd6-c433-43f5-a6c0-7678a050773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825437469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1825437469
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1459202837
Short name T263
Test name
Test status
Simulation time 75779640 ps
CPU time 0.77 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:17 PM PDT 24
Peak memory 200128 kb
Host smart-fee242cc-f921-4cf4-b290-337a6c8f0a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459202837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1459202837
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1308629704
Short name T440
Test name
Test status
Simulation time 1228499070 ps
CPU time 5.82 seconds
Started Aug 09 07:10:16 PM PDT 24
Finished Aug 09 07:10:21 PM PDT 24
Peak memory 217952 kb
Host smart-ae84015a-90f5-4159-bcf8-5ac6e522beb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308629704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1308629704
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.4245005710
Short name T456
Test name
Test status
Simulation time 243665884 ps
CPU time 1.09 seconds
Started Aug 09 07:10:25 PM PDT 24
Finished Aug 09 07:10:26 PM PDT 24
Peak memory 217400 kb
Host smart-4e876f66-86da-4f01-9382-ced09032b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245005710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.4245005710
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3368210247
Short name T372
Test name
Test status
Simulation time 136028405 ps
CPU time 0.78 seconds
Started Aug 09 07:10:16 PM PDT 24
Finished Aug 09 07:10:17 PM PDT 24
Peak memory 200156 kb
Host smart-6bd8eaa3-fe85-44e4-a5a1-285ad5be69df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368210247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3368210247
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.610597068
Short name T452
Test name
Test status
Simulation time 914197224 ps
CPU time 4.36 seconds
Started Aug 09 07:10:15 PM PDT 24
Finished Aug 09 07:10:20 PM PDT 24
Peak memory 200556 kb
Host smart-eb79ac7f-2a87-4842-9bcb-39ebc58e1cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610597068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.610597068
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2917714490
Short name T120
Test name
Test status
Simulation time 104152004 ps
CPU time 0.98 seconds
Started Aug 09 07:10:16 PM PDT 24
Finished Aug 09 07:10:17 PM PDT 24
Peak memory 200348 kb
Host smart-0a42379d-d164-4176-8444-93f5c290a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917714490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2917714490
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3221870474
Short name T353
Test name
Test status
Simulation time 190318281 ps
CPU time 1.34 seconds
Started Aug 09 07:10:15 PM PDT 24
Finished Aug 09 07:10:17 PM PDT 24
Peak memory 200476 kb
Host smart-41e6e9fa-18c5-4c22-b897-ae52c0e9d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221870474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3221870474
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2426574706
Short name T384
Test name
Test status
Simulation time 3344932093 ps
CPU time 12.79 seconds
Started Aug 09 07:10:13 PM PDT 24
Finished Aug 09 07:10:26 PM PDT 24
Peak memory 200556 kb
Host smart-fff2b8e6-c9f0-4844-afb4-237f443c88e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426574706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2426574706
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.195261710
Short name T342
Test name
Test status
Simulation time 141566319 ps
CPU time 1.68 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:19 PM PDT 24
Peak memory 200320 kb
Host smart-262041eb-5f6a-47ca-b924-f4aae0852346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195261710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.195261710
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.795376902
Short name T344
Test name
Test status
Simulation time 89736511 ps
CPU time 0.82 seconds
Started Aug 09 07:10:05 PM PDT 24
Finished Aug 09 07:10:06 PM PDT 24
Peak memory 200324 kb
Host smart-27d4e63b-13db-4606-870f-8068aa8c7b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795376902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.795376902
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2347127377
Short name T453
Test name
Test status
Simulation time 62067159 ps
CPU time 0.74 seconds
Started Aug 09 07:10:27 PM PDT 24
Finished Aug 09 07:10:28 PM PDT 24
Peak memory 200160 kb
Host smart-35ffec82-a336-4c1a-8361-5b4e7c48c1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347127377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2347127377
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3723899734
Short name T36
Test name
Test status
Simulation time 2364010198 ps
CPU time 8.64 seconds
Started Aug 09 07:10:16 PM PDT 24
Finished Aug 09 07:10:25 PM PDT 24
Peak memory 217876 kb
Host smart-a97b6592-2a81-444d-b98d-9fa0a4a078bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723899734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3723899734
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2310070972
Short name T540
Test name
Test status
Simulation time 244407053 ps
CPU time 1.06 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 217520 kb
Host smart-cd8dec80-1a55-45c6-9c22-e0fa4825d300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310070972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2310070972
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3349106441
Short name T532
Test name
Test status
Simulation time 176241574 ps
CPU time 0.83 seconds
Started Aug 09 07:10:18 PM PDT 24
Finished Aug 09 07:10:19 PM PDT 24
Peak memory 200028 kb
Host smart-7cc33d5c-800a-4d2b-99ad-84e578c2d3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349106441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3349106441
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.3428389670
Short name T232
Test name
Test status
Simulation time 981362292 ps
CPU time 4.65 seconds
Started Aug 09 07:10:10 PM PDT 24
Finished Aug 09 07:10:15 PM PDT 24
Peak memory 200536 kb
Host smart-89e1902c-ee3e-44ad-bc93-970c39ced47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428389670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3428389670
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2546399352
Short name T414
Test name
Test status
Simulation time 98661941 ps
CPU time 0.98 seconds
Started Aug 09 07:10:08 PM PDT 24
Finished Aug 09 07:10:09 PM PDT 24
Peak memory 200344 kb
Host smart-42d7daa3-bedf-4ed8-a88a-1f5793602ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546399352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2546399352
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2447307730
Short name T520
Test name
Test status
Simulation time 231285200 ps
CPU time 1.53 seconds
Started Aug 09 07:10:25 PM PDT 24
Finished Aug 09 07:10:27 PM PDT 24
Peak memory 200484 kb
Host smart-7c4517ee-6711-441e-a286-0fb5a985a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447307730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2447307730
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3544854583
Short name T249
Test name
Test status
Simulation time 217952121 ps
CPU time 1.6 seconds
Started Aug 09 07:10:20 PM PDT 24
Finished Aug 09 07:10:22 PM PDT 24
Peak memory 200256 kb
Host smart-412117e2-8a8f-4f3e-aba7-1ecacfc8065e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544854583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3544854583
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2241911299
Short name T207
Test name
Test status
Simulation time 472665684 ps
CPU time 2.71 seconds
Started Aug 09 07:10:25 PM PDT 24
Finished Aug 09 07:10:28 PM PDT 24
Peak memory 200208 kb
Host smart-43affdc7-4200-4b3f-a157-5127e30e35c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241911299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2241911299
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1387444093
Short name T469
Test name
Test status
Simulation time 166073685 ps
CPU time 1.28 seconds
Started Aug 09 07:10:19 PM PDT 24
Finished Aug 09 07:10:20 PM PDT 24
Peak memory 200532 kb
Host smart-c759696c-a5a2-443f-93dd-55211fd6f1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387444093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1387444093
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2616924949
Short name T276
Test name
Test status
Simulation time 63609722 ps
CPU time 0.75 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 200176 kb
Host smart-0ec14c58-673d-4dd2-b2d7-ba604d93f6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616924949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2616924949
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.4226042897
Short name T435
Test name
Test status
Simulation time 1229418820 ps
CPU time 6.14 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:23 PM PDT 24
Peak memory 217732 kb
Host smart-3fb49c48-53b1-4972-9f31-20830def1863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226042897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4226042897
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.609237859
Short name T250
Test name
Test status
Simulation time 245778382 ps
CPU time 1.06 seconds
Started Aug 09 07:10:21 PM PDT 24
Finished Aug 09 07:10:23 PM PDT 24
Peak memory 217516 kb
Host smart-8c6a7147-6246-4132-a3bc-d754ed2286e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609237859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.609237859
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2475284460
Short name T375
Test name
Test status
Simulation time 148282279 ps
CPU time 0.81 seconds
Started Aug 09 07:10:18 PM PDT 24
Finished Aug 09 07:10:19 PM PDT 24
Peak memory 200104 kb
Host smart-3112c21c-2857-4ce1-969e-dc22f0469281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475284460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2475284460
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1747125566
Short name T389
Test name
Test status
Simulation time 1482674996 ps
CPU time 5.34 seconds
Started Aug 09 07:10:24 PM PDT 24
Finished Aug 09 07:10:30 PM PDT 24
Peak memory 200548 kb
Host smart-f4c3eb4d-6287-477e-9fd3-6d7711141d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747125566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1747125566
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3422500378
Short name T539
Test name
Test status
Simulation time 137289047 ps
CPU time 1.13 seconds
Started Aug 09 07:10:14 PM PDT 24
Finished Aug 09 07:10:15 PM PDT 24
Peak memory 200304 kb
Host smart-8ef42ba3-d095-4fc2-9840-50b74786901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422500378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3422500378
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.346896270
Short name T534
Test name
Test status
Simulation time 203625243 ps
CPU time 1.54 seconds
Started Aug 09 07:10:18 PM PDT 24
Finished Aug 09 07:10:20 PM PDT 24
Peak memory 200484 kb
Host smart-0072b16b-43e2-4676-9553-241e80900c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346896270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.346896270
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.818186764
Short name T310
Test name
Test status
Simulation time 8148105380 ps
CPU time 31.05 seconds
Started Aug 09 07:10:23 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 208800 kb
Host smart-a893f930-7ed6-4741-8cc5-22c2a72046f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818186764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.818186764
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2845016710
Short name T339
Test name
Test status
Simulation time 123524152 ps
CPU time 1.65 seconds
Started Aug 09 07:10:21 PM PDT 24
Finished Aug 09 07:10:23 PM PDT 24
Peak memory 208408 kb
Host smart-0980b05d-b51b-42bc-884b-014e160c1021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845016710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2845016710
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4209683173
Short name T142
Test name
Test status
Simulation time 210535695 ps
CPU time 1.37 seconds
Started Aug 09 07:10:20 PM PDT 24
Finished Aug 09 07:10:21 PM PDT 24
Peak memory 200360 kb
Host smart-e1f09baa-e4b0-4c52-b0d3-64e38f7cfccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209683173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4209683173
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.92148977
Short name T68
Test name
Test status
Simulation time 83107326 ps
CPU time 0.84 seconds
Started Aug 09 07:10:17 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 200144 kb
Host smart-f542e99e-2a58-4f73-9b6b-c35b5b1d4765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92148977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.92148977
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.2255846040
Short name T458
Test name
Test status
Simulation time 2155457309 ps
CPU time 7.29 seconds
Started Aug 09 07:10:25 PM PDT 24
Finished Aug 09 07:10:33 PM PDT 24
Peak memory 220892 kb
Host smart-8b049317-0e13-4ad5-a368-5f35c5b712e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255846040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2255846040
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3564242207
Short name T5
Test name
Test status
Simulation time 244983330 ps
CPU time 1.05 seconds
Started Aug 09 07:10:21 PM PDT 24
Finished Aug 09 07:10:22 PM PDT 24
Peak memory 217592 kb
Host smart-73473200-beee-4b53-a288-73c26461ee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564242207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3564242207
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.419027045
Short name T321
Test name
Test status
Simulation time 93449840 ps
CPU time 0.82 seconds
Started Aug 09 07:10:21 PM PDT 24
Finished Aug 09 07:10:22 PM PDT 24
Peak memory 200112 kb
Host smart-8903dd52-71f1-4ec2-b401-0261b70cbd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419027045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.419027045
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2797588335
Short name T177
Test name
Test status
Simulation time 2025138917 ps
CPU time 7.75 seconds
Started Aug 09 07:10:21 PM PDT 24
Finished Aug 09 07:10:29 PM PDT 24
Peak memory 200592 kb
Host smart-9785e36a-2413-42e4-90de-2865ee42fce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797588335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2797588335
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.535789128
Short name T470
Test name
Test status
Simulation time 175945078 ps
CPU time 1.21 seconds
Started Aug 09 07:10:14 PM PDT 24
Finished Aug 09 07:10:16 PM PDT 24
Peak memory 200328 kb
Host smart-fb7ec5fc-ad4e-4bd2-b39e-a148f9e32cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535789128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.535789128
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2474182943
Short name T518
Test name
Test status
Simulation time 111565837 ps
CPU time 1.17 seconds
Started Aug 09 07:10:20 PM PDT 24
Finished Aug 09 07:10:21 PM PDT 24
Peak memory 200480 kb
Host smart-ee3b1be6-00a6-4960-97b3-d266494dfb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474182943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2474182943
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.4261453940
Short name T307
Test name
Test status
Simulation time 3696226906 ps
CPU time 13.01 seconds
Started Aug 09 07:10:18 PM PDT 24
Finished Aug 09 07:10:31 PM PDT 24
Peak memory 208860 kb
Host smart-921c2bc6-c1c3-41bd-bd33-7d8326dfeee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261453940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.4261453940
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1335380582
Short name T288
Test name
Test status
Simulation time 120106000 ps
CPU time 1.61 seconds
Started Aug 09 07:10:24 PM PDT 24
Finished Aug 09 07:10:26 PM PDT 24
Peak memory 200280 kb
Host smart-3027328d-1394-4170-a621-a18d264d3fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335380582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1335380582
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.583352086
Short name T147
Test name
Test status
Simulation time 234244738 ps
CPU time 1.5 seconds
Started Aug 09 07:10:20 PM PDT 24
Finished Aug 09 07:10:21 PM PDT 24
Peak memory 200416 kb
Host smart-46c9f41e-9ab8-4691-b733-e9f5d8df282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583352086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.583352086
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3163347175
Short name T448
Test name
Test status
Simulation time 74456921 ps
CPU time 0.78 seconds
Started Aug 09 07:09:31 PM PDT 24
Finished Aug 09 07:09:32 PM PDT 24
Peak memory 200164 kb
Host smart-159b2464-ee6f-4642-8b5e-667f8a16e3b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163347175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3163347175
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2655654238
Short name T305
Test name
Test status
Simulation time 2350546194 ps
CPU time 7.96 seconds
Started Aug 09 07:09:30 PM PDT 24
Finished Aug 09 07:09:38 PM PDT 24
Peak memory 217876 kb
Host smart-1939726c-aa26-43d6-817c-7f36e02ae269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655654238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2655654238
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2340242118
Short name T141
Test name
Test status
Simulation time 244454605 ps
CPU time 1.17 seconds
Started Aug 09 07:09:32 PM PDT 24
Finished Aug 09 07:09:33 PM PDT 24
Peak memory 217524 kb
Host smart-7fe38841-8246-4c78-ac8e-a260a8cbfc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340242118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2340242118
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1215358116
Short name T497
Test name
Test status
Simulation time 117823440 ps
CPU time 0.77 seconds
Started Aug 09 07:09:26 PM PDT 24
Finished Aug 09 07:09:26 PM PDT 24
Peak memory 200168 kb
Host smart-5a92efc2-f431-4d8a-b7ff-dbc7a5008720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215358116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1215358116
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.1359035246
Short name T97
Test name
Test status
Simulation time 730296360 ps
CPU time 3.61 seconds
Started Aug 09 07:09:23 PM PDT 24
Finished Aug 09 07:09:27 PM PDT 24
Peak memory 200576 kb
Host smart-72efd9a1-6ad6-4014-ab9c-d76299c63353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359035246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1359035246
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3423583922
Short name T133
Test name
Test status
Simulation time 178688977 ps
CPU time 1.2 seconds
Started Aug 09 07:09:29 PM PDT 24
Finished Aug 09 07:09:30 PM PDT 24
Peak memory 200276 kb
Host smart-46a01ba1-bef6-4e33-9e7f-798a6a9556a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423583922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3423583922
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.169209372
Short name T15
Test name
Test status
Simulation time 121109391 ps
CPU time 1.21 seconds
Started Aug 09 07:09:19 PM PDT 24
Finished Aug 09 07:09:20 PM PDT 24
Peak memory 200492 kb
Host smart-d2a7f913-df39-4726-825e-9d065ec44c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169209372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.169209372
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.684950013
Short name T74
Test name
Test status
Simulation time 6930257469 ps
CPU time 30 seconds
Started Aug 09 07:09:31 PM PDT 24
Finished Aug 09 07:10:01 PM PDT 24
Peak memory 200844 kb
Host smart-3a61d624-329f-4c8f-8f9e-eab0be85ac6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684950013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.684950013
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.4197145654
Short name T157
Test name
Test status
Simulation time 148374477 ps
CPU time 1.88 seconds
Started Aug 09 07:09:26 PM PDT 24
Finished Aug 09 07:09:28 PM PDT 24
Peak memory 200484 kb
Host smart-347a8b65-a6c4-468e-8695-7845ef37e4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197145654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.4197145654
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2320948744
Short name T137
Test name
Test status
Simulation time 125571016 ps
CPU time 1.06 seconds
Started Aug 09 07:09:10 PM PDT 24
Finished Aug 09 07:09:12 PM PDT 24
Peak memory 200360 kb
Host smart-16ab4129-5817-49c3-9daa-37dd6cbd76c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320948744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2320948744
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3567837024
Short name T227
Test name
Test status
Simulation time 78746861 ps
CPU time 0.81 seconds
Started Aug 09 07:10:20 PM PDT 24
Finished Aug 09 07:10:21 PM PDT 24
Peak memory 200160 kb
Host smart-d81c47f0-5e90-472f-9217-3421680b6d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567837024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3567837024
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2855149783
Short name T402
Test name
Test status
Simulation time 1895286006 ps
CPU time 7.1 seconds
Started Aug 09 07:10:22 PM PDT 24
Finished Aug 09 07:10:29 PM PDT 24
Peak memory 217768 kb
Host smart-d4db662d-7740-45bd-a73b-448dd5549464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855149783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2855149783
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.997458550
Short name T536
Test name
Test status
Simulation time 243399144 ps
CPU time 1.14 seconds
Started Aug 09 07:10:19 PM PDT 24
Finished Aug 09 07:10:20 PM PDT 24
Peak memory 217540 kb
Host smart-500cb902-7346-42da-aaaf-d961ff4a05c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997458550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.997458550
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2798783788
Short name T281
Test name
Test status
Simulation time 79206951 ps
CPU time 0.73 seconds
Started Aug 09 07:10:20 PM PDT 24
Finished Aug 09 07:10:20 PM PDT 24
Peak memory 200184 kb
Host smart-10c7a4e4-cd94-4bee-aa1b-8894a50e43d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798783788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2798783788
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1123542495
Short name T462
Test name
Test status
Simulation time 1560295538 ps
CPU time 6.98 seconds
Started Aug 09 07:10:26 PM PDT 24
Finished Aug 09 07:10:33 PM PDT 24
Peak memory 200568 kb
Host smart-d42df9b8-5292-4889-8f5d-22e459a30f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123542495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1123542495
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1488430058
Short name T172
Test name
Test status
Simulation time 103063943 ps
CPU time 1.04 seconds
Started Aug 09 07:10:29 PM PDT 24
Finished Aug 09 07:10:30 PM PDT 24
Peak memory 200340 kb
Host smart-b043e4f9-4448-4482-bfb2-9a89fc9982a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488430058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1488430058
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1891332928
Short name T179
Test name
Test status
Simulation time 241738886 ps
CPU time 1.58 seconds
Started Aug 09 07:10:18 PM PDT 24
Finished Aug 09 07:10:20 PM PDT 24
Peak memory 200440 kb
Host smart-c6eaf8f5-c67c-4341-bd5b-2af84b9f6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891332928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1891332928
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1287637559
Short name T262
Test name
Test status
Simulation time 1878879327 ps
CPU time 7.5 seconds
Started Aug 09 07:10:19 PM PDT 24
Finished Aug 09 07:10:27 PM PDT 24
Peak memory 200564 kb
Host smart-e20b6bdf-a8bc-45f8-b04a-7edda7654b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287637559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1287637559
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.326546076
Short name T185
Test name
Test status
Simulation time 318866340 ps
CPU time 2.21 seconds
Started Aug 09 07:10:20 PM PDT 24
Finished Aug 09 07:10:22 PM PDT 24
Peak memory 200320 kb
Host smart-ba2e94d6-930b-42cf-a67b-bb0a7df394e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326546076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.326546076
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1274714876
Short name T270
Test name
Test status
Simulation time 205776013 ps
CPU time 1.3 seconds
Started Aug 09 07:10:25 PM PDT 24
Finished Aug 09 07:10:26 PM PDT 24
Peak memory 200360 kb
Host smart-eac83f9e-f01c-46d4-9811-a6cd46714a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274714876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1274714876
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1796422217
Short name T301
Test name
Test status
Simulation time 64119135 ps
CPU time 0.77 seconds
Started Aug 09 07:10:34 PM PDT 24
Finished Aug 09 07:10:35 PM PDT 24
Peak memory 200160 kb
Host smart-4e132eb5-212e-4d19-ac97-d353f01b9ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796422217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1796422217
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2333933377
Short name T333
Test name
Test status
Simulation time 2157042954 ps
CPU time 7.86 seconds
Started Aug 09 07:10:33 PM PDT 24
Finished Aug 09 07:10:41 PM PDT 24
Peak memory 217496 kb
Host smart-e2bb184d-ad63-46fb-a19c-c5e2272eef83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333933377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2333933377
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.790174574
Short name T422
Test name
Test status
Simulation time 244870649 ps
CPU time 1.1 seconds
Started Aug 09 07:10:30 PM PDT 24
Finished Aug 09 07:10:31 PM PDT 24
Peak memory 217508 kb
Host smart-418e088c-eeb0-4602-8fa1-539b1e3fa560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790174574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.790174574
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2978206588
Short name T233
Test name
Test status
Simulation time 112285725 ps
CPU time 0.83 seconds
Started Aug 09 07:10:34 PM PDT 24
Finished Aug 09 07:10:35 PM PDT 24
Peak memory 200128 kb
Host smart-3c0bcd1a-fea4-4320-91c8-091ce3c18fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978206588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2978206588
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.264548598
Short name T481
Test name
Test status
Simulation time 1674173100 ps
CPU time 5.96 seconds
Started Aug 09 07:10:38 PM PDT 24
Finished Aug 09 07:10:44 PM PDT 24
Peak memory 200488 kb
Host smart-e6a22d26-f950-4e4f-9078-bd5491552406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264548598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.264548598
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1535256912
Short name T503
Test name
Test status
Simulation time 176403378 ps
CPU time 1.33 seconds
Started Aug 09 07:10:33 PM PDT 24
Finished Aug 09 07:10:35 PM PDT 24
Peak memory 200360 kb
Host smart-7fee6ca7-f61c-4b84-9892-8d34bca075a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535256912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1535256912
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1041699162
Short name T259
Test name
Test status
Simulation time 199412910 ps
CPU time 1.49 seconds
Started Aug 09 07:10:35 PM PDT 24
Finished Aug 09 07:10:36 PM PDT 24
Peak memory 200440 kb
Host smart-f6d8ae2b-4a71-4696-ac71-a8906c5d254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041699162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1041699162
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2761236898
Short name T478
Test name
Test status
Simulation time 286576858 ps
CPU time 1.71 seconds
Started Aug 09 07:10:33 PM PDT 24
Finished Aug 09 07:10:35 PM PDT 24
Peak memory 200112 kb
Host smart-1a67ca96-4b37-4c22-8485-ed1b6f97117c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761236898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2761236898
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.705794013
Short name T341
Test name
Test status
Simulation time 126201591 ps
CPU time 1.65 seconds
Started Aug 09 07:10:32 PM PDT 24
Finished Aug 09 07:10:34 PM PDT 24
Peak memory 208332 kb
Host smart-8b57bf44-26cb-4e07-b481-8fa307cd721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705794013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.705794013
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1237859413
Short name T279
Test name
Test status
Simulation time 176665981 ps
CPU time 1.23 seconds
Started Aug 09 07:10:34 PM PDT 24
Finished Aug 09 07:10:36 PM PDT 24
Peak memory 200348 kb
Host smart-3cc07c22-a640-44c9-a4b9-e6760a552844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237859413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1237859413
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1018131659
Short name T299
Test name
Test status
Simulation time 66039316 ps
CPU time 0.73 seconds
Started Aug 09 07:10:35 PM PDT 24
Finished Aug 09 07:10:36 PM PDT 24
Peak memory 200160 kb
Host smart-25e2d740-0e9d-44be-a0a2-2d60fbcd1433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018131659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1018131659
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1075804500
Short name T416
Test name
Test status
Simulation time 2362252933 ps
CPU time 8.26 seconds
Started Aug 09 07:10:33 PM PDT 24
Finished Aug 09 07:10:41 PM PDT 24
Peak memory 217868 kb
Host smart-25fbb6ee-44cf-46aa-9395-ccf8ee9a7713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075804500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1075804500
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.28008104
Short name T256
Test name
Test status
Simulation time 244247441 ps
CPU time 1.18 seconds
Started Aug 09 07:10:37 PM PDT 24
Finished Aug 09 07:10:38 PM PDT 24
Peak memory 217544 kb
Host smart-ccbf102e-97cc-4493-aa5e-a47eb092cf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28008104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.28008104
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3502055361
Short name T23
Test name
Test status
Simulation time 157411220 ps
CPU time 0.83 seconds
Started Aug 09 07:10:37 PM PDT 24
Finished Aug 09 07:10:38 PM PDT 24
Peak memory 200152 kb
Host smart-170ebd22-2723-460e-81b2-18bb9737abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502055361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3502055361
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.817722070
Short name T498
Test name
Test status
Simulation time 668578885 ps
CPU time 3.9 seconds
Started Aug 09 07:10:30 PM PDT 24
Finished Aug 09 07:10:34 PM PDT 24
Peak memory 200604 kb
Host smart-be9b09f5-ff1b-4900-8f44-f83247a9f63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817722070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.817722070
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3053342489
Short name T537
Test name
Test status
Simulation time 174749947 ps
CPU time 1.3 seconds
Started Aug 09 07:10:34 PM PDT 24
Finished Aug 09 07:10:35 PM PDT 24
Peak memory 200380 kb
Host smart-0b56beb6-c32f-4163-bd95-933a0978069b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053342489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3053342489
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2867216957
Short name T524
Test name
Test status
Simulation time 192149287 ps
CPU time 1.33 seconds
Started Aug 09 07:10:33 PM PDT 24
Finished Aug 09 07:10:35 PM PDT 24
Peak memory 200436 kb
Host smart-ebe169c7-a631-4f45-ae44-f239efe7084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867216957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2867216957
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3092439636
Short name T351
Test name
Test status
Simulation time 6430040479 ps
CPU time 24.16 seconds
Started Aug 09 07:10:33 PM PDT 24
Finished Aug 09 07:10:57 PM PDT 24
Peak memory 209592 kb
Host smart-ad5ca621-f299-43a4-ad98-d728e81c280f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092439636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3092439636
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.810268166
Short name T441
Test name
Test status
Simulation time 112200386 ps
CPU time 1.45 seconds
Started Aug 09 07:10:32 PM PDT 24
Finished Aug 09 07:10:34 PM PDT 24
Peak memory 200140 kb
Host smart-457d2a64-2ba1-41e4-863f-16683908d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810268166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.810268166
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3190738070
Short name T408
Test name
Test status
Simulation time 176204484 ps
CPU time 1.35 seconds
Started Aug 09 07:10:30 PM PDT 24
Finished Aug 09 07:10:32 PM PDT 24
Peak memory 200444 kb
Host smart-f37abc49-8c99-4ba0-a476-05ec7cc28dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190738070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3190738070
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.984144075
Short name T128
Test name
Test status
Simulation time 56564723 ps
CPU time 0.75 seconds
Started Aug 09 07:10:31 PM PDT 24
Finished Aug 09 07:10:32 PM PDT 24
Peak memory 200156 kb
Host smart-2546713e-fc64-4eeb-a27a-808d218f269f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984144075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.984144075
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.509818300
Short name T49
Test name
Test status
Simulation time 1236373742 ps
CPU time 6.1 seconds
Started Aug 09 07:10:38 PM PDT 24
Finished Aug 09 07:10:44 PM PDT 24
Peak memory 217320 kb
Host smart-d236725d-fef2-4697-b482-f6ecc0b76f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509818300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.509818300
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2704391710
Short name T272
Test name
Test status
Simulation time 244327909 ps
CPU time 1.21 seconds
Started Aug 09 07:10:32 PM PDT 24
Finished Aug 09 07:10:33 PM PDT 24
Peak memory 217568 kb
Host smart-0171364f-ac93-49a2-a4e5-7d2b924431ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704391710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2704391710
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.4086852944
Short name T16
Test name
Test status
Simulation time 180654333 ps
CPU time 0.97 seconds
Started Aug 09 07:10:32 PM PDT 24
Finished Aug 09 07:10:33 PM PDT 24
Peak memory 200088 kb
Host smart-6f03a72b-0fad-4e14-9c10-5da18f865cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086852944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.4086852944
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1967526701
Short name T394
Test name
Test status
Simulation time 1424623983 ps
CPU time 6.12 seconds
Started Aug 09 07:10:34 PM PDT 24
Finished Aug 09 07:10:40 PM PDT 24
Peak memory 200560 kb
Host smart-d3f5a627-0a8e-4d96-b0ba-9f188349a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967526701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1967526701
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.781009693
Short name T464
Test name
Test status
Simulation time 157665166 ps
CPU time 1.09 seconds
Started Aug 09 07:10:33 PM PDT 24
Finished Aug 09 07:10:34 PM PDT 24
Peak memory 200240 kb
Host smart-a9d2ee96-fbe4-43b8-a735-df51b656499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781009693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.781009693
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2006798498
Short name T247
Test name
Test status
Simulation time 116579023 ps
CPU time 1.18 seconds
Started Aug 09 07:10:31 PM PDT 24
Finished Aug 09 07:10:32 PM PDT 24
Peak memory 200488 kb
Host smart-94fd3b0b-80b7-48a3-b6bb-d27a4aa93f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006798498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2006798498
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.440333716
Short name T350
Test name
Test status
Simulation time 286148600 ps
CPU time 2.29 seconds
Started Aug 09 07:10:36 PM PDT 24
Finished Aug 09 07:10:38 PM PDT 24
Peak memory 208688 kb
Host smart-c6807b58-1dcf-401f-821e-88e748d67d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440333716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.440333716
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.1100804096
Short name T398
Test name
Test status
Simulation time 135414697 ps
CPU time 1.71 seconds
Started Aug 09 07:10:30 PM PDT 24
Finished Aug 09 07:10:31 PM PDT 24
Peak memory 208504 kb
Host smart-ce265260-44bb-4cf8-beed-a389fa2c54b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100804096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1100804096
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2586425697
Short name T526
Test name
Test status
Simulation time 78566455 ps
CPU time 0.86 seconds
Started Aug 09 07:10:32 PM PDT 24
Finished Aug 09 07:10:33 PM PDT 24
Peak memory 200344 kb
Host smart-fa072581-638f-4f8f-b0fd-b85b70520834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586425697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2586425697
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1755322998
Short name T229
Test name
Test status
Simulation time 62911421 ps
CPU time 0.83 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 200088 kb
Host smart-411a70a3-1075-4075-baaf-c7b6bb2f7c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755322998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1755322998
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.132738245
Short name T337
Test name
Test status
Simulation time 1907093843 ps
CPU time 7.31 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 221736 kb
Host smart-0ca24f2b-024a-466e-b033-a68296550c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132738245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.132738245
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4195928290
Short name T284
Test name
Test status
Simulation time 245490777 ps
CPU time 1.13 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 217452 kb
Host smart-b987628a-e7c3-47bb-b17c-7c7ca60afd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195928290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4195928290
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2603749565
Short name T513
Test name
Test status
Simulation time 100565886 ps
CPU time 0.82 seconds
Started Aug 09 07:10:34 PM PDT 24
Finished Aug 09 07:10:34 PM PDT 24
Peak memory 200160 kb
Host smart-df4a9588-50fa-485c-b775-6426e21b9f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603749565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2603749565
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2804330003
Short name T515
Test name
Test status
Simulation time 1233869874 ps
CPU time 5.26 seconds
Started Aug 09 07:10:35 PM PDT 24
Finished Aug 09 07:10:40 PM PDT 24
Peak memory 200548 kb
Host smart-6fe685e1-53c3-474b-8a7c-92eec0a00d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804330003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2804330003
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.797533658
Short name T243
Test name
Test status
Simulation time 102357308 ps
CPU time 1.01 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 200376 kb
Host smart-867c3e2e-23b9-419c-9f8d-64cb4b353c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797533658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.797533658
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2966325801
Short name T40
Test name
Test status
Simulation time 256281567 ps
CPU time 1.48 seconds
Started Aug 09 07:10:35 PM PDT 24
Finished Aug 09 07:10:37 PM PDT 24
Peak memory 200504 kb
Host smart-672853f2-824d-43e6-bce9-24c7a578e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966325801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2966325801
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.998961899
Short name T115
Test name
Test status
Simulation time 6560909624 ps
CPU time 22.47 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:11:10 PM PDT 24
Peak memory 216344 kb
Host smart-c6b7c87d-3501-46ce-919f-87efd828ff36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998961899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.998961899
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.383452244
Short name T123
Test name
Test status
Simulation time 361999587 ps
CPU time 2.38 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200308 kb
Host smart-6624b853-392f-4c1b-9055-98093f70287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383452244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.383452244
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2017352935
Short name T274
Test name
Test status
Simulation time 195110365 ps
CPU time 1.23 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:49 PM PDT 24
Peak memory 200156 kb
Host smart-516ecfa5-240c-44ef-90ef-702b671b2a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017352935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2017352935
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3027806509
Short name T494
Test name
Test status
Simulation time 67322402 ps
CPU time 0.74 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 200120 kb
Host smart-4d01c906-139a-4c23-9511-9f69b7e9ba51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027806509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3027806509
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1836463621
Short name T368
Test name
Test status
Simulation time 2349433111 ps
CPU time 8.03 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 221768 kb
Host smart-6b2e24d8-e2bb-479c-961b-e9c7f835b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836463621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1836463621
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2484442709
Short name T392
Test name
Test status
Simulation time 245231553 ps
CPU time 1.05 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:47 PM PDT 24
Peak memory 217520 kb
Host smart-a7770fe3-f4e5-411d-b305-70316d81b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484442709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2484442709
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2112081852
Short name T180
Test name
Test status
Simulation time 144282548 ps
CPU time 0.82 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:47 PM PDT 24
Peak memory 200184 kb
Host smart-c2eadb42-3ef2-42e9-bab6-ae5191026323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112081852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2112081852
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.711365157
Short name T484
Test name
Test status
Simulation time 1196871444 ps
CPU time 4.62 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200532 kb
Host smart-1276be1b-c9ec-47da-9e64-4a11bd999bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711365157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.711365157
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3919200825
Short name T499
Test name
Test status
Simulation time 162695609 ps
CPU time 1.17 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 200304 kb
Host smart-3d3ccd63-546d-461b-a307-df75556e3052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919200825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3919200825
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.200831013
Short name T264
Test name
Test status
Simulation time 111859649 ps
CPU time 1.14 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200476 kb
Host smart-82869c08-79a8-41ee-9a57-f92a9fbce55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200831013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.200831013
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2941398007
Short name T152
Test name
Test status
Simulation time 10553356470 ps
CPU time 40.31 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:11:26 PM PDT 24
Peak memory 200636 kb
Host smart-48af61c3-cb35-4ca7-afd8-5e2636df3bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941398007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2941398007
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1190342963
Short name T55
Test name
Test status
Simulation time 319534836 ps
CPU time 2.32 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:49 PM PDT 24
Peak memory 200308 kb
Host smart-865552a8-8424-4b3f-b962-2d4dbc2fd868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190342963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1190342963
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1076450317
Short name T508
Test name
Test status
Simulation time 150205057 ps
CPU time 1.05 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200308 kb
Host smart-be5e28e2-92e1-45ab-95b1-5299acfef783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076450317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1076450317
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.601495076
Short name T533
Test name
Test status
Simulation time 65813083 ps
CPU time 0.82 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200156 kb
Host smart-37ecc5bb-3a34-4531-846f-5f25ccaeb738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601495076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.601495076
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.3178928669
Short name T47
Test name
Test status
Simulation time 1224913844 ps
CPU time 5.43 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 221760 kb
Host smart-b1f2ab8f-722e-43ab-8698-171e48550261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178928669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3178928669
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2931030830
Short name T46
Test name
Test status
Simulation time 244083697 ps
CPU time 1.06 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 217572 kb
Host smart-51fcef33-c7a8-4518-b033-81c8b35acb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931030830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2931030830
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1263065021
Short name T225
Test name
Test status
Simulation time 206898801 ps
CPU time 0.93 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 200088 kb
Host smart-105fdb6e-2a40-44f9-bb30-bf3c60895313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263065021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1263065021
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.795556054
Short name T315
Test name
Test status
Simulation time 1327627160 ps
CPU time 5.31 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 200556 kb
Host smart-de2e342b-18d2-4d96-ae22-ee38642c0f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795556054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.795556054
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.334403220
Short name T412
Test name
Test status
Simulation time 154287836 ps
CPU time 1.17 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:47 PM PDT 24
Peak memory 200344 kb
Host smart-f7707070-8198-4831-973e-13f6d5590ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334403220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.334403220
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.3771664838
Short name T296
Test name
Test status
Simulation time 259779379 ps
CPU time 1.52 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200480 kb
Host smart-c79dd902-fe69-469f-bdf2-50a602bdccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771664838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3771664838
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1373684590
Short name T369
Test name
Test status
Simulation time 6153036585 ps
CPU time 21.68 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:11:09 PM PDT 24
Peak memory 209600 kb
Host smart-59ea38e3-d8e4-45e6-b73a-e34bda632c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373684590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1373684590
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2616076671
Short name T325
Test name
Test status
Simulation time 373525738 ps
CPU time 2.21 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:49 PM PDT 24
Peak memory 200260 kb
Host smart-2dc56a78-c760-4452-9465-7c9d7f7b611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616076671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2616076671
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2818455955
Short name T429
Test name
Test status
Simulation time 185868000 ps
CPU time 1.21 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:49 PM PDT 24
Peak memory 200304 kb
Host smart-621ba771-6950-4b91-894e-795bd0d42476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818455955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2818455955
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3059855957
Short name T378
Test name
Test status
Simulation time 94778789 ps
CPU time 0.81 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200140 kb
Host smart-db3e3657-b93b-43e1-9c95-ef922887b771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059855957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3059855957
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.888412046
Short name T446
Test name
Test status
Simulation time 1908886766 ps
CPU time 7.46 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:59 PM PDT 24
Peak memory 216924 kb
Host smart-cc2444ca-0f53-4674-83b8-84c3ca577337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888412046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.888412046
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3682496854
Short name T240
Test name
Test status
Simulation time 244902599 ps
CPU time 1.13 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 217516 kb
Host smart-619dd51d-0b9f-4cd1-94a9-dde9958215d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682496854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3682496854
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4017397932
Short name T476
Test name
Test status
Simulation time 211205571 ps
CPU time 0.9 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:49 PM PDT 24
Peak memory 200160 kb
Host smart-52630192-ec3a-48c5-84bd-c4711bfd2abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017397932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4017397932
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2056043242
Short name T463
Test name
Test status
Simulation time 1282123186 ps
CPU time 5.05 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:53 PM PDT 24
Peak memory 200484 kb
Host smart-c5030994-0484-4410-80c9-5e606235c46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056043242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2056043242
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3730887213
Short name T261
Test name
Test status
Simulation time 146411013 ps
CPU time 1.15 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:49 PM PDT 24
Peak memory 200392 kb
Host smart-07fa8d1f-54fc-4d98-9be4-f3355aa3abbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730887213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3730887213
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.2557549872
Short name T154
Test name
Test status
Simulation time 258447316 ps
CPU time 1.52 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200488 kb
Host smart-57588d46-0fac-4475-aad7-0e7fbc10217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557549872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2557549872
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2878236932
Short name T146
Test name
Test status
Simulation time 14399109201 ps
CPU time 51.09 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:11:37 PM PDT 24
Peak memory 208828 kb
Host smart-4e68d9ac-872a-4f83-bc1c-6ec2eb4e75ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878236932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2878236932
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2579813258
Short name T280
Test name
Test status
Simulation time 135774490 ps
CPU time 1.88 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200292 kb
Host smart-e6d5cf3d-01f1-4ba6-845c-215790513b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579813258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2579813258
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1234611505
Short name T308
Test name
Test status
Simulation time 136940418 ps
CPU time 1.01 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200224 kb
Host smart-c2e4a740-c94b-45b5-85b4-8f5879e3f258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234611505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1234611505
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.1648159742
Short name T266
Test name
Test status
Simulation time 66450156 ps
CPU time 0.77 seconds
Started Aug 09 07:10:51 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200144 kb
Host smart-cb437aaf-2e8b-4bb4-91e0-a85ae81becbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648159742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1648159742
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2667451557
Short name T362
Test name
Test status
Simulation time 2373547690 ps
CPU time 8.34 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:56 PM PDT 24
Peak memory 221812 kb
Host smart-76b2bfab-a3f1-4dea-9e08-ce8ab74bd5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667451557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2667451557
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.797868865
Short name T201
Test name
Test status
Simulation time 244439526 ps
CPU time 1.08 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 217352 kb
Host smart-fcd571c5-5941-4a19-aef7-80919a45c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797868865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.797868865
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1398283425
Short name T451
Test name
Test status
Simulation time 98076271 ps
CPU time 0.82 seconds
Started Aug 09 07:10:53 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 200160 kb
Host smart-093a20d5-b5e4-4c3c-add4-b0d3a0092ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398283425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1398283425
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2917633858
Short name T75
Test name
Test status
Simulation time 1552714243 ps
CPU time 6.19 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 200552 kb
Host smart-09d3ad49-524e-4c2f-a681-4dee6a6a20e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917633858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2917633858
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4043513157
Short name T443
Test name
Test status
Simulation time 147397522 ps
CPU time 1.12 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 200392 kb
Host smart-16090ce4-e8d4-4e9a-b44a-262210f21629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043513157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4043513157
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2973586955
Short name T289
Test name
Test status
Simulation time 200398562 ps
CPU time 1.46 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200440 kb
Host smart-6ef15cbf-f3b0-4324-9e25-94fc30922d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973586955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2973586955
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4000956131
Short name T113
Test name
Test status
Simulation time 11249953633 ps
CPU time 37.35 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:11:26 PM PDT 24
Peak memory 208824 kb
Host smart-326f7a2d-ad28-4bfb-be9f-1dc4f10459ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000956131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4000956131
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2209305206
Short name T320
Test name
Test status
Simulation time 353541121 ps
CPU time 2.24 seconds
Started Aug 09 07:10:50 PM PDT 24
Finished Aug 09 07:10:52 PM PDT 24
Peak memory 200288 kb
Host smart-5a0f03ea-62c3-4e9a-ae73-b778b0b15ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209305206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2209305206
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.1536135541
Short name T231
Test name
Test status
Simulation time 169208658 ps
CPU time 1.33 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 200460 kb
Host smart-6fee625b-473d-4eb0-adcd-b3c267571197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536135541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1536135541
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.1897513640
Short name T411
Test name
Test status
Simulation time 66411180 ps
CPU time 0.75 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200120 kb
Host smart-6100da9f-7796-4d78-922f-7aca41011e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897513640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1897513640
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.370878941
Short name T34
Test name
Test status
Simulation time 1895495723 ps
CPU time 6.89 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:55 PM PDT 24
Peak memory 221728 kb
Host smart-718cf371-f9e4-4a02-906e-89f167da1f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370878941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.370878941
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.672729246
Short name T169
Test name
Test status
Simulation time 244359532 ps
CPU time 1.15 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:54 PM PDT 24
Peak memory 217512 kb
Host smart-85e61fea-9676-464c-aff9-3db7d543e823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672729246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.672729246
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.137683245
Short name T21
Test name
Test status
Simulation time 243324977 ps
CPU time 0.93 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200140 kb
Host smart-36eb85e2-63e6-42a2-ad7d-dcfc6ab3b66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137683245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.137683245
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3923938553
Short name T29
Test name
Test status
Simulation time 1824049816 ps
CPU time 6.63 seconds
Started Aug 09 07:10:52 PM PDT 24
Finished Aug 09 07:10:59 PM PDT 24
Peak memory 200488 kb
Host smart-45ffb11f-c484-4c4c-ae0b-31c46ae62aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923938553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3923938553
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.222546473
Short name T190
Test name
Test status
Simulation time 151824655 ps
CPU time 1.28 seconds
Started Aug 09 07:10:46 PM PDT 24
Finished Aug 09 07:10:47 PM PDT 24
Peak memory 200352 kb
Host smart-5c272420-b7c2-4c5d-a6c0-ffc27e247d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222546473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.222546473
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3797133697
Short name T171
Test name
Test status
Simulation time 203316978 ps
CPU time 1.36 seconds
Started Aug 09 07:10:48 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200444 kb
Host smart-66d97920-5a78-4b68-8d9d-01168d7166f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797133697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3797133697
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3568900377
Short name T373
Test name
Test status
Simulation time 9786475235 ps
CPU time 33.79 seconds
Started Aug 09 07:10:49 PM PDT 24
Finished Aug 09 07:11:23 PM PDT 24
Peak memory 200600 kb
Host smart-6789e5f3-e7da-4486-ba53-4d0f7663822d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568900377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3568900377
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2722497135
Short name T483
Test name
Test status
Simulation time 265408859 ps
CPU time 1.88 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:50 PM PDT 24
Peak memory 200284 kb
Host smart-83b7dd4a-50b6-4218-80b9-995786a365df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722497135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2722497135
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.4241698092
Short name T267
Test name
Test status
Simulation time 155573834 ps
CPU time 1.13 seconds
Started Aug 09 07:10:47 PM PDT 24
Finished Aug 09 07:10:48 PM PDT 24
Peak memory 200368 kb
Host smart-edcf8331-c85b-4dc0-873c-b64b32bc737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241698092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.4241698092
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.111556861
Short name T209
Test name
Test status
Simulation time 92030105 ps
CPU time 0.89 seconds
Started Aug 09 07:09:30 PM PDT 24
Finished Aug 09 07:09:31 PM PDT 24
Peak memory 200092 kb
Host smart-b82f77f3-4714-4f46-af64-65e9064a3f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111556861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.111556861
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.694987238
Short name T303
Test name
Test status
Simulation time 1891963553 ps
CPU time 6.83 seconds
Started Aug 09 07:09:33 PM PDT 24
Finished Aug 09 07:09:40 PM PDT 24
Peak memory 216828 kb
Host smart-69db80c0-742c-4bc2-9102-31ee5157be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694987238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.694987238
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1877938325
Short name T43
Test name
Test status
Simulation time 243455253 ps
CPU time 1.13 seconds
Started Aug 09 07:09:24 PM PDT 24
Finished Aug 09 07:09:25 PM PDT 24
Peak memory 217504 kb
Host smart-99ab61ea-e249-4f8a-86e0-ea55daae9deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877938325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1877938325
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.118974102
Short name T19
Test name
Test status
Simulation time 98580317 ps
CPU time 0.77 seconds
Started Aug 09 07:09:30 PM PDT 24
Finished Aug 09 07:09:30 PM PDT 24
Peak memory 200140 kb
Host smart-01d5a514-ed85-4e3e-8687-ebd9c24ff14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118974102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.118974102
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.950144186
Short name T491
Test name
Test status
Simulation time 2080344049 ps
CPU time 8.05 seconds
Started Aug 09 07:09:35 PM PDT 24
Finished Aug 09 07:09:43 PM PDT 24
Peak memory 200808 kb
Host smart-7177a668-fbc6-411a-82d1-a4576242120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950144186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.950144186
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4230421831
Short name T492
Test name
Test status
Simulation time 188244346 ps
CPU time 1.19 seconds
Started Aug 09 07:09:24 PM PDT 24
Finished Aug 09 07:09:25 PM PDT 24
Peak memory 200376 kb
Host smart-55eb8460-1288-4aec-a176-ff5a757c36df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230421831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4230421831
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3398883605
Short name T418
Test name
Test status
Simulation time 124248604 ps
CPU time 1.23 seconds
Started Aug 09 07:09:28 PM PDT 24
Finished Aug 09 07:09:29 PM PDT 24
Peak memory 200464 kb
Host smart-db42e917-87b9-4c5f-995a-e43bd3a0dc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398883605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3398883605
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3873914695
Short name T356
Test name
Test status
Simulation time 2162262212 ps
CPU time 8.11 seconds
Started Aug 09 07:09:24 PM PDT 24
Finished Aug 09 07:09:32 PM PDT 24
Peak memory 200660 kb
Host smart-63fccb53-040b-4f82-b13d-3eaa7672b2e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873914695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3873914695
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1824145809
Short name T165
Test name
Test status
Simulation time 83362548 ps
CPU time 0.87 seconds
Started Aug 09 07:09:25 PM PDT 24
Finished Aug 09 07:09:26 PM PDT 24
Peak memory 200360 kb
Host smart-7471d8ab-affd-4cb3-8215-a8518da407a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824145809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1824145809
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2362260781
Short name T67
Test name
Test status
Simulation time 84281684 ps
CPU time 0.81 seconds
Started Aug 09 07:09:27 PM PDT 24
Finished Aug 09 07:09:28 PM PDT 24
Peak memory 200144 kb
Host smart-c2ca9b21-605d-46d1-9d30-96d7e78e5b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362260781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2362260781
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2695334547
Short name T364
Test name
Test status
Simulation time 1880343468 ps
CPU time 6.71 seconds
Started Aug 09 07:09:45 PM PDT 24
Finished Aug 09 07:09:52 PM PDT 24
Peak memory 221652 kb
Host smart-517cd888-8973-47c8-8f9a-6e4fd4ca8a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695334547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2695334547
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.447826826
Short name T216
Test name
Test status
Simulation time 245065580 ps
CPU time 1.12 seconds
Started Aug 09 07:09:28 PM PDT 24
Finished Aug 09 07:09:30 PM PDT 24
Peak memory 217532 kb
Host smart-3d97b4c1-c8b6-4999-9cb8-beb930dce2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447826826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.447826826
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.601307945
Short name T529
Test name
Test status
Simulation time 212113401 ps
CPU time 0.94 seconds
Started Aug 09 07:09:31 PM PDT 24
Finished Aug 09 07:09:32 PM PDT 24
Peak memory 200128 kb
Host smart-b9e69e12-e13a-4c78-b5c9-fe0f9f7f788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601307945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.601307945
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1050348004
Short name T438
Test name
Test status
Simulation time 1539593371 ps
CPU time 5.99 seconds
Started Aug 09 07:09:24 PM PDT 24
Finished Aug 09 07:09:30 PM PDT 24
Peak memory 200612 kb
Host smart-580e17a4-c4fb-4bc9-831a-336c396655f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050348004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1050348004
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1220517836
Short name T211
Test name
Test status
Simulation time 180112772 ps
CPU time 1.3 seconds
Started Aug 09 07:09:26 PM PDT 24
Finished Aug 09 07:09:28 PM PDT 24
Peak memory 200352 kb
Host smart-d59d4550-c8dd-426e-8a3b-0c496290ebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220517836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1220517836
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3978521336
Short name T127
Test name
Test status
Simulation time 251901962 ps
CPU time 1.55 seconds
Started Aug 09 07:09:30 PM PDT 24
Finished Aug 09 07:09:32 PM PDT 24
Peak memory 200528 kb
Host smart-d43febd6-a488-46d7-bcc8-375eff1bccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978521336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3978521336
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2221878911
Short name T99
Test name
Test status
Simulation time 10040698765 ps
CPU time 34 seconds
Started Aug 09 07:09:44 PM PDT 24
Finished Aug 09 07:10:18 PM PDT 24
Peak memory 200580 kb
Host smart-fde44752-1755-4a7f-b112-842dc90cbbb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221878911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2221878911
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.2172130683
Short name T479
Test name
Test status
Simulation time 335626670 ps
CPU time 2.24 seconds
Started Aug 09 07:09:33 PM PDT 24
Finished Aug 09 07:09:35 PM PDT 24
Peak memory 200184 kb
Host smart-a7aaa173-c24d-42b8-8199-150c5690c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172130683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2172130683
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3696409160
Short name T27
Test name
Test status
Simulation time 135663411 ps
CPU time 1 seconds
Started Aug 09 07:09:26 PM PDT 24
Finished Aug 09 07:09:27 PM PDT 24
Peak memory 200344 kb
Host smart-2d424c58-4919-4be7-a234-47a4fed64113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696409160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3696409160
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.83939274
Short name T391
Test name
Test status
Simulation time 71026226 ps
CPU time 0.72 seconds
Started Aug 09 07:09:34 PM PDT 24
Finished Aug 09 07:09:35 PM PDT 24
Peak memory 200160 kb
Host smart-7f399b59-0d03-4b0d-9983-aac607e7d263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83939274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.83939274
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3218309954
Short name T52
Test name
Test status
Simulation time 1906221164 ps
CPU time 7.17 seconds
Started Aug 09 07:09:27 PM PDT 24
Finished Aug 09 07:09:34 PM PDT 24
Peak memory 220820 kb
Host smart-0c6cde9d-139d-4e32-bdfc-210e08e9d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218309954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3218309954
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2017921515
Short name T26
Test name
Test status
Simulation time 244287706 ps
CPU time 1.19 seconds
Started Aug 09 07:09:31 PM PDT 24
Finished Aug 09 07:09:33 PM PDT 24
Peak memory 217508 kb
Host smart-d6b04879-9887-46a8-9011-8f6e77a11d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017921515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2017921515
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.901528723
Short name T354
Test name
Test status
Simulation time 182824978 ps
CPU time 0.9 seconds
Started Aug 09 07:09:27 PM PDT 24
Finished Aug 09 07:09:28 PM PDT 24
Peak memory 200140 kb
Host smart-bb440b0c-df8b-423e-92a6-1bf43f0ae26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901528723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.901528723
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1198091784
Short name T388
Test name
Test status
Simulation time 728237127 ps
CPU time 4.22 seconds
Started Aug 09 07:09:27 PM PDT 24
Finished Aug 09 07:09:32 PM PDT 24
Peak memory 200508 kb
Host smart-a528bfbf-d183-4644-a7db-2e8828d8399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198091784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1198091784
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2142609374
Short name T437
Test name
Test status
Simulation time 154206296 ps
CPU time 1.14 seconds
Started Aug 09 07:09:28 PM PDT 24
Finished Aug 09 07:09:29 PM PDT 24
Peak memory 200340 kb
Host smart-0a23df32-c2dc-4f79-8040-4678b5dca249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142609374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2142609374
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1721624394
Short name T436
Test name
Test status
Simulation time 117200209 ps
CPU time 1.23 seconds
Started Aug 09 07:09:34 PM PDT 24
Finished Aug 09 07:09:35 PM PDT 24
Peak memory 200508 kb
Host smart-accfe3e3-b290-47c1-a4ec-1cbe847adff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721624394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1721624394
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3245646691
Short name T331
Test name
Test status
Simulation time 4265770888 ps
CPU time 15.98 seconds
Started Aug 09 07:09:32 PM PDT 24
Finished Aug 09 07:09:48 PM PDT 24
Peak memory 200696 kb
Host smart-d9b53724-0dcf-42aa-8d56-f16a029253c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245646691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3245646691
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3816841560
Short name T45
Test name
Test status
Simulation time 281914246 ps
CPU time 2 seconds
Started Aug 09 07:09:28 PM PDT 24
Finished Aug 09 07:09:30 PM PDT 24
Peak memory 200248 kb
Host smart-73ec17b7-0c60-4ae3-867a-fe42381a82d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816841560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3816841560
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.973142838
Short name T374
Test name
Test status
Simulation time 203356816 ps
CPU time 1.3 seconds
Started Aug 09 07:09:36 PM PDT 24
Finished Aug 09 07:09:37 PM PDT 24
Peak memory 200556 kb
Host smart-fac60f35-b21d-4f5d-821e-e01d012e5dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973142838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.973142838
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.97658487
Short name T495
Test name
Test status
Simulation time 59035128 ps
CPU time 0.73 seconds
Started Aug 09 07:09:45 PM PDT 24
Finished Aug 09 07:09:46 PM PDT 24
Peak memory 200192 kb
Host smart-818a890f-0a29-48b9-b426-8dfd70e539a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97658487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.97658487
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1242250914
Short name T38
Test name
Test status
Simulation time 2367885530 ps
CPU time 7.8 seconds
Started Aug 09 07:09:39 PM PDT 24
Finished Aug 09 07:09:47 PM PDT 24
Peak memory 217808 kb
Host smart-821c0270-f1ac-44b5-8a7d-f34ee15fcf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242250914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1242250914
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.319386805
Short name T385
Test name
Test status
Simulation time 244709156 ps
CPU time 1.04 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:52 PM PDT 24
Peak memory 217316 kb
Host smart-2b8f1808-cc3e-4ecd-afb5-902474d7667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319386805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.319386805
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1270868032
Short name T11
Test name
Test status
Simulation time 93120535 ps
CPU time 0.78 seconds
Started Aug 09 07:09:25 PM PDT 24
Finished Aug 09 07:09:26 PM PDT 24
Peak memory 200144 kb
Host smart-e2fbf791-2f0e-4737-9010-0f1786164d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270868032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1270868032
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1279191779
Short name T531
Test name
Test status
Simulation time 1855429006 ps
CPU time 7.55 seconds
Started Aug 09 07:09:46 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200560 kb
Host smart-80a87e84-918a-463d-9eb3-88ee0f2e24f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279191779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1279191779
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.706379599
Short name T134
Test name
Test status
Simulation time 106066270 ps
CPU time 0.98 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200372 kb
Host smart-8633a3c5-3a9a-4731-b7a4-5ad67ede8947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706379599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.706379599
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.523476140
Short name T488
Test name
Test status
Simulation time 192571472 ps
CPU time 1.35 seconds
Started Aug 09 07:09:29 PM PDT 24
Finished Aug 09 07:09:30 PM PDT 24
Peak memory 200528 kb
Host smart-8dbc1f1b-a500-4e09-9678-de104e65c439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523476140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.523476140
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.40965429
Short name T386
Test name
Test status
Simulation time 7527623338 ps
CPU time 28.54 seconds
Started Aug 09 07:09:40 PM PDT 24
Finished Aug 09 07:10:09 PM PDT 24
Peak memory 200664 kb
Host smart-f67725ed-b730-4fc0-b9ec-3262ac52b875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40965429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.40965429
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2661597671
Short name T410
Test name
Test status
Simulation time 119916438 ps
CPU time 1.49 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200324 kb
Host smart-15f93125-74f1-4d4d-b31f-65263fc89df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661597671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2661597671
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2154365547
Short name T12
Test name
Test status
Simulation time 209996135 ps
CPU time 1.36 seconds
Started Aug 09 07:09:39 PM PDT 24
Finished Aug 09 07:09:40 PM PDT 24
Peak memory 200344 kb
Host smart-a41a110e-f208-4111-9f06-cff57b766db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154365547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2154365547
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2099634405
Short name T145
Test name
Test status
Simulation time 87075263 ps
CPU time 1.06 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:52 PM PDT 24
Peak memory 200088 kb
Host smart-51422dbb-236a-48cc-8e27-eceb43b85183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099634405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2099634405
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.776767858
Short name T450
Test name
Test status
Simulation time 1221956366 ps
CPU time 5.78 seconds
Started Aug 09 07:09:47 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 221748 kb
Host smart-9601bd53-8c0e-45a8-9e8e-b7d8ee3e246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776767858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.776767858
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1366241743
Short name T131
Test name
Test status
Simulation time 244282638 ps
CPU time 1.09 seconds
Started Aug 09 07:09:51 PM PDT 24
Finished Aug 09 07:09:54 PM PDT 24
Peak memory 217436 kb
Host smart-5527ed97-e6cf-470e-a0ce-d46a750e26f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366241743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1366241743
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3809142072
Short name T219
Test name
Test status
Simulation time 120110026 ps
CPU time 0.79 seconds
Started Aug 09 07:09:48 PM PDT 24
Finished Aug 09 07:09:49 PM PDT 24
Peak memory 200088 kb
Host smart-978a6fae-7888-48a1-87aa-f6235d42076b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809142072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3809142072
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3680194089
Short name T489
Test name
Test status
Simulation time 1552375915 ps
CPU time 6.38 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:56 PM PDT 24
Peak memory 200556 kb
Host smart-3047e926-dbb7-419a-8529-1f1f90c3383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680194089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3680194089
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.674947483
Short name T187
Test name
Test status
Simulation time 174734461 ps
CPU time 1.31 seconds
Started Aug 09 07:09:45 PM PDT 24
Finished Aug 09 07:09:46 PM PDT 24
Peak memory 200364 kb
Host smart-ebea7f51-027c-4e21-9bbb-7f3460730371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674947483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.674947483
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2672704916
Short name T407
Test name
Test status
Simulation time 253328105 ps
CPU time 1.54 seconds
Started Aug 09 07:09:49 PM PDT 24
Finished Aug 09 07:09:51 PM PDT 24
Peak memory 200496 kb
Host smart-85e8f2bb-3ab4-4053-8752-763644fcbd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672704916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2672704916
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2875581515
Short name T387
Test name
Test status
Simulation time 8890777110 ps
CPU time 37.44 seconds
Started Aug 09 07:09:39 PM PDT 24
Finished Aug 09 07:10:16 PM PDT 24
Peak memory 200640 kb
Host smart-c64c8636-d89e-4a34-9c7a-bed07293565c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875581515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2875581515
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2025980084
Short name T254
Test name
Test status
Simulation time 327364743 ps
CPU time 2.26 seconds
Started Aug 09 07:09:38 PM PDT 24
Finished Aug 09 07:09:40 PM PDT 24
Peak memory 200348 kb
Host smart-40ed55dc-ec58-44e4-947e-25f83ccfab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025980084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2025980084
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3224134182
Short name T168
Test name
Test status
Simulation time 152445084 ps
CPU time 1.26 seconds
Started Aug 09 07:09:50 PM PDT 24
Finished Aug 09 07:09:53 PM PDT 24
Peak memory 200456 kb
Host smart-c653681d-2436-4294-9294-61c36b2d5af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224134182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3224134182
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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