Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8933

1

T3

187

T8

262

T9

39

auto[1]

11749

1

T1

4

T3

124

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6371	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6954	1			T1	2		T2	1		T3	103
reset_info_cp[2]	3156	1			T1	1		T3	40		T5	1
reset_info_cp[4]	4232	1			T1	1		T3	79		T5	1
reset_info_cp[8]	118	1			T3	2		T8	2		T9	1
reset_info_cp[16]	123	1			T3	3		T8	3		T10	1
reset_info_cp[32]	127	1			T3	2		T8	4		T9	1
reset_info_cp[64]	105	1			T3	2		T8	3		T10	1
reset_info_cp[128]	116	1			T8	3		T10	2		T12	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3353	1			T3	49		T8	85		T9	12
reset_info_cp[1]	auto[1]	2981	1			T1	1		T3	53		T5	1
reset_info_cp[2]	auto[0]	998	1			T3	27		T8	48		T9	4
reset_info_cp[2]	auto[1]	2158	1			T1	1		T3	13		T5	1
reset_info_cp[4]	auto[0]	1570	1			T3	39		T8	55		T9	8
reset_info_cp[4]	auto[1]	2662	1			T1	1		T3	40		T5	1
reset_info_cp[8]	auto[0]	50	1			T3	1		T9	1		T125	5
reset_info_cp[8]	auto[1]	68	1			T3	1		T8	2		T10	1
reset_info_cp[16]	auto[0]	45	1			T3	3		T41	2		T127	2
reset_info_cp[16]	auto[1]	78	1			T8	3		T10	1		T83	1
reset_info_cp[32]	auto[0]	55	1			T8	3		T9	1		T10	1
reset_info_cp[32]	auto[1]	72	1			T3	2		T8	1		T60	1
reset_info_cp[64]	auto[0]	45	1			T8	3		T126	1		T128	1
reset_info_cp[64]	auto[1]	60	1			T3	2		T10	1		T74	1
reset_info_cp[128]	auto[0]	52	1			T8	2		T13	1		T36	1
reset_info_cp[128]	auto[1]	64	1			T8	1		T10	2		T12	1