Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8795

1

T3

178

T8

229

T9

31

auto[1]

11887

1

T1

4

T3

133

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6371	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6954	1			T1	2		T2	1		T3	103
reset_info_cp[2]	3156	1			T1	1		T3	40		T5	1
reset_info_cp[4]	4232	1			T1	1		T3	79		T5	1
reset_info_cp[8]	118	1			T3	2		T8	2		T9	1
reset_info_cp[16]	123	1			T3	3		T8	3		T10	1
reset_info_cp[32]	127	1			T3	2		T8	4		T9	1
reset_info_cp[64]	105	1			T3	2		T8	3		T10	1
reset_info_cp[128]	116	1			T8	3		T10	2		T12	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3224	1			T3	56		T8	75		T9	14
reset_info_cp[1]	auto[1]	3110	1			T1	1		T3	46		T5	1
reset_info_cp[2]	auto[0]	1024	1			T3	23		T8	37		T9	1
reset_info_cp[2]	auto[1]	2132	1			T1	1		T3	17		T5	1
reset_info_cp[4]	auto[0]	1550	1			T3	35		T8	50		T9	7
reset_info_cp[4]	auto[1]	2682	1			T1	1		T3	44		T5	1
reset_info_cp[8]	auto[0]	44	1			T8	1		T98	1		T125	5
reset_info_cp[8]	auto[1]	74	1			T3	2		T8	1		T9	1
reset_info_cp[16]	auto[0]	59	1			T3	1		T8	1		T10	1
reset_info_cp[16]	auto[1]	64	1			T3	2		T8	2		T50	1
reset_info_cp[32]	auto[0]	54	1			T3	2		T8	1		T9	1
reset_info_cp[32]	auto[1]	73	1			T8	3		T61	1		T48	3
reset_info_cp[64]	auto[0]	45	1			T3	1		T10	1		T126	1
reset_info_cp[64]	auto[1]	60	1			T3	1		T8	3		T74	1
reset_info_cp[128]	auto[0]	44	1			T8	2		T10	2		T13	3
reset_info_cp[128]	auto[1]	72	1			T8	1		T12	1		T74	1