Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T532 /workspace/coverage/default/20.rstmgr_sw_rst.1108638404 Aug 11 06:10:35 PM PDT 24 Aug 11 06:10:37 PM PDT 24 150314006 ps
T533 /workspace/coverage/default/24.rstmgr_por_stretcher.2699443321 Aug 11 06:10:49 PM PDT 24 Aug 11 06:10:50 PM PDT 24 227941607 ps
T534 /workspace/coverage/default/19.rstmgr_reset.3591388835 Aug 11 06:10:34 PM PDT 24 Aug 11 06:10:39 PM PDT 24 835581632 ps
T535 /workspace/coverage/default/41.rstmgr_smoke.2226851195 Aug 11 06:10:52 PM PDT 24 Aug 11 06:10:53 PM PDT 24 203040178 ps
T536 /workspace/coverage/default/31.rstmgr_sw_rst.1686736158 Aug 11 06:10:51 PM PDT 24 Aug 11 06:10:53 PM PDT 24 380708687 ps
T64 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.750813327 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:33 PM PDT 24 63743088 ps
T65 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1069978273 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:46 PM PDT 24 83900879 ps
T66 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1203410817 Aug 11 06:52:40 PM PDT 24 Aug 11 06:52:41 PM PDT 24 66784616 ps
T67 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1559362330 Aug 11 06:52:33 PM PDT 24 Aug 11 06:52:35 PM PDT 24 488989597 ps
T68 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2183843193 Aug 11 06:52:34 PM PDT 24 Aug 11 06:52:36 PM PDT 24 481252139 ps
T71 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1411376254 Aug 11 06:52:51 PM PDT 24 Aug 11 06:52:55 PM PDT 24 644741504 ps
T124 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3634472125 Aug 11 06:52:31 PM PDT 24 Aug 11 06:52:34 PM PDT 24 430490444 ps
T106 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3978000426 Aug 11 06:52:46 PM PDT 24 Aug 11 06:52:47 PM PDT 24 81075852 ps
T72 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3614852653 Aug 11 06:52:40 PM PDT 24 Aug 11 06:52:42 PM PDT 24 166579957 ps
T73 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.494089474 Aug 11 06:52:44 PM PDT 24 Aug 11 06:52:46 PM PDT 24 214033976 ps
T89 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1545701034 Aug 11 06:52:38 PM PDT 24 Aug 11 06:52:41 PM PDT 24 507790958 ps
T537 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1542814336 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:33 PM PDT 24 137203735 ps
T107 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.215919782 Aug 11 06:52:26 PM PDT 24 Aug 11 06:52:27 PM PDT 24 73206430 ps
T90 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1869581487 Aug 11 06:52:47 PM PDT 24 Aug 11 06:52:49 PM PDT 24 123707178 ps
T538 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2821386863 Aug 11 06:52:37 PM PDT 24 Aug 11 06:52:38 PM PDT 24 78314029 ps
T91 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.359875314 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:35 PM PDT 24 348582307 ps
T108 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4041611004 Aug 11 06:52:41 PM PDT 24 Aug 11 06:52:42 PM PDT 24 202071801 ps
T92 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2060473188 Aug 11 06:52:55 PM PDT 24 Aug 11 06:52:57 PM PDT 24 470442028 ps
T539 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1640646345 Aug 11 06:52:41 PM PDT 24 Aug 11 06:52:42 PM PDT 24 75940914 ps
T94 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4123115088 Aug 11 06:52:27 PM PDT 24 Aug 11 06:52:30 PM PDT 24 931754278 ps
T93 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1714856277 Aug 11 06:52:50 PM PDT 24 Aug 11 06:52:53 PM PDT 24 776540109 ps
T109 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.159683314 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:34 PM PDT 24 194862529 ps
T540 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3606795352 Aug 11 06:52:38 PM PDT 24 Aug 11 06:52:39 PM PDT 24 62238739 ps
T95 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1054393286 Aug 11 06:52:40 PM PDT 24 Aug 11 06:52:44 PM PDT 24 936903755 ps
T541 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4092182075 Aug 11 06:52:34 PM PDT 24 Aug 11 06:52:35 PM PDT 24 206790328 ps
T110 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.792584091 Aug 11 06:52:46 PM PDT 24 Aug 11 06:52:47 PM PDT 24 137777988 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3643233960 Aug 11 06:52:51 PM PDT 24 Aug 11 06:52:52 PM PDT 24 57822629 ps
T542 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1578784771 Aug 11 06:52:25 PM PDT 24 Aug 11 06:52:31 PM PDT 24 477949820 ps
T96 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3828088266 Aug 11 06:52:40 PM PDT 24 Aug 11 06:52:43 PM PDT 24 194320963 ps
T97 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2380923970 Aug 11 06:52:44 PM PDT 24 Aug 11 06:52:46 PM PDT 24 180833762 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4119822832 Aug 11 06:52:30 PM PDT 24 Aug 11 06:52:31 PM PDT 24 111988428 ps
T117 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4155875809 Aug 11 06:52:37 PM PDT 24 Aug 11 06:52:40 PM PDT 24 480233840 ps
T112 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2066982846 Aug 11 06:52:34 PM PDT 24 Aug 11 06:52:35 PM PDT 24 76151965 ps
T544 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.743200628 Aug 11 06:52:44 PM PDT 24 Aug 11 06:52:46 PM PDT 24 138863162 ps
T545 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.472312842 Aug 11 06:52:31 PM PDT 24 Aug 11 06:52:33 PM PDT 24 150612422 ps
T115 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1447799267 Aug 11 06:52:31 PM PDT 24 Aug 11 06:52:34 PM PDT 24 901741760 ps
T113 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2502358524 Aug 11 06:52:39 PM PDT 24 Aug 11 06:52:40 PM PDT 24 153776244 ps
T546 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2348813644 Aug 11 06:52:47 PM PDT 24 Aug 11 06:52:48 PM PDT 24 116117581 ps
T547 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1710600662 Aug 11 06:52:40 PM PDT 24 Aug 11 06:52:41 PM PDT 24 101318007 ps
T548 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3140856435 Aug 11 06:52:35 PM PDT 24 Aug 11 06:52:36 PM PDT 24 170027311 ps
T114 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2980196635 Aug 11 06:52:38 PM PDT 24 Aug 11 06:52:40 PM PDT 24 231897936 ps
T549 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.22137289 Aug 11 06:52:31 PM PDT 24 Aug 11 06:52:32 PM PDT 24 98529111 ps
T550 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2901178185 Aug 11 06:52:31 PM PDT 24 Aug 11 06:52:36 PM PDT 24 806168313 ps
T551 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2243545546 Aug 11 06:52:37 PM PDT 24 Aug 11 06:52:41 PM PDT 24 956877585 ps
T552 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2434951698 Aug 11 06:52:29 PM PDT 24 Aug 11 06:52:31 PM PDT 24 425329081 ps
T553 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.490043391 Aug 11 06:52:44 PM PDT 24 Aug 11 06:52:45 PM PDT 24 157082028 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1384112987 Aug 11 06:52:25 PM PDT 24 Aug 11 06:52:26 PM PDT 24 70207397 ps
T555 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.818706594 Aug 11 06:52:25 PM PDT 24 Aug 11 06:52:28 PM PDT 24 446158905 ps
T556 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4102051672 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:47 PM PDT 24 218165718 ps
T557 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.799099401 Aug 11 06:52:39 PM PDT 24 Aug 11 06:52:40 PM PDT 24 194193815 ps
T558 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.884855739 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:47 PM PDT 24 326941892 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.390785494 Aug 11 06:52:51 PM PDT 24 Aug 11 06:52:53 PM PDT 24 492113372 ps
T560 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2466736464 Aug 11 06:52:33 PM PDT 24 Aug 11 06:52:36 PM PDT 24 274274406 ps
T561 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3530155506 Aug 11 06:52:31 PM PDT 24 Aug 11 06:52:32 PM PDT 24 130828516 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1812585530 Aug 11 06:52:41 PM PDT 24 Aug 11 06:52:43 PM PDT 24 185454435 ps
T563 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2131080668 Aug 11 06:52:50 PM PDT 24 Aug 11 06:52:52 PM PDT 24 182440529 ps
T564 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2827289329 Aug 11 06:52:38 PM PDT 24 Aug 11 06:52:41 PM PDT 24 367489790 ps
T565 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.574924086 Aug 11 06:52:30 PM PDT 24 Aug 11 06:52:31 PM PDT 24 146487861 ps
T566 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1120568589 Aug 11 06:52:25 PM PDT 24 Aug 11 06:52:26 PM PDT 24 104615922 ps
T567 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2346106079 Aug 11 06:52:50 PM PDT 24 Aug 11 06:52:51 PM PDT 24 61909395 ps
T568 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.903344023 Aug 11 06:52:53 PM PDT 24 Aug 11 06:52:54 PM PDT 24 94788483 ps
T569 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1220236601 Aug 11 06:52:46 PM PDT 24 Aug 11 06:52:47 PM PDT 24 93563259 ps
T570 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3847221785 Aug 11 06:52:37 PM PDT 24 Aug 11 06:52:38 PM PDT 24 88660932 ps
T571 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.665089795 Aug 11 06:52:37 PM PDT 24 Aug 11 06:52:38 PM PDT 24 179284593 ps
T572 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2216064826 Aug 11 06:52:47 PM PDT 24 Aug 11 06:52:49 PM PDT 24 410441173 ps
T573 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2015482877 Aug 11 06:52:54 PM PDT 24 Aug 11 06:52:57 PM PDT 24 212660449 ps
T574 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3563573329 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:47 PM PDT 24 437042792 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2313325935 Aug 11 06:52:34 PM PDT 24 Aug 11 06:52:35 PM PDT 24 102564517 ps
T116 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.500689131 Aug 11 06:52:46 PM PDT 24 Aug 11 06:52:48 PM PDT 24 491117648 ps
T576 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4119416144 Aug 11 06:52:42 PM PDT 24 Aug 11 06:52:43 PM PDT 24 113357994 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1972215024 Aug 11 06:52:40 PM PDT 24 Aug 11 06:52:42 PM PDT 24 279159008 ps
T578 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3214244127 Aug 11 06:52:38 PM PDT 24 Aug 11 06:52:39 PM PDT 24 70369667 ps
T579 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2817001670 Aug 11 06:52:39 PM PDT 24 Aug 11 06:52:40 PM PDT 24 229982731 ps
T580 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2076962545 Aug 11 06:52:56 PM PDT 24 Aug 11 06:52:58 PM PDT 24 305486828 ps
T581 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3189601603 Aug 11 06:52:51 PM PDT 24 Aug 11 06:52:54 PM PDT 24 896251421 ps
T582 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.226538767 Aug 11 06:52:42 PM PDT 24 Aug 11 06:52:45 PM PDT 24 917662952 ps
T583 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1483685386 Aug 11 06:52:46 PM PDT 24 Aug 11 06:52:46 PM PDT 24 65783947 ps
T584 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.677588365 Aug 11 06:52:54 PM PDT 24 Aug 11 06:52:56 PM PDT 24 372452429 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.651803837 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:33 PM PDT 24 76694470 ps
T586 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2346293434 Aug 11 06:52:46 PM PDT 24 Aug 11 06:52:48 PM PDT 24 178537203 ps
T587 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1023855656 Aug 11 06:52:40 PM PDT 24 Aug 11 06:52:43 PM PDT 24 488400425 ps
T588 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3728005223 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:46 PM PDT 24 64534131 ps
T589 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2045621064 Aug 11 06:52:47 PM PDT 24 Aug 11 06:52:49 PM PDT 24 430524630 ps
T590 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.955537224 Aug 11 06:52:34 PM PDT 24 Aug 11 06:52:36 PM PDT 24 119661101 ps
T591 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4000248107 Aug 11 06:52:46 PM PDT 24 Aug 11 06:52:47 PM PDT 24 141611742 ps
T592 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.350169783 Aug 11 06:52:26 PM PDT 24 Aug 11 06:52:28 PM PDT 24 164911488 ps
T593 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3663201386 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:45 PM PDT 24 77323235 ps
T594 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.658522093 Aug 11 06:52:51 PM PDT 24 Aug 11 06:52:52 PM PDT 24 86738947 ps
T595 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.363334688 Aug 11 06:52:33 PM PDT 24 Aug 11 06:52:36 PM PDT 24 276568842 ps
T596 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1205815734 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:33 PM PDT 24 65232539 ps
T118 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3255387637 Aug 11 06:52:44 PM PDT 24 Aug 11 06:52:45 PM PDT 24 440663395 ps
T597 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.126453432 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:34 PM PDT 24 425041678 ps
T598 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3760022582 Aug 11 06:52:53 PM PDT 24 Aug 11 06:52:54 PM PDT 24 193736911 ps
T599 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2089484603 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:48 PM PDT 24 904422443 ps
T600 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.842967945 Aug 11 06:52:53 PM PDT 24 Aug 11 06:52:53 PM PDT 24 83067302 ps
T601 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.780143659 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:48 PM PDT 24 360527281 ps
T602 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1671146445 Aug 11 06:52:31 PM PDT 24 Aug 11 06:52:32 PM PDT 24 129956988 ps
T603 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2160438703 Aug 11 06:52:51 PM PDT 24 Aug 11 06:52:52 PM PDT 24 68120265 ps
T604 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.707079147 Aug 11 06:52:42 PM PDT 24 Aug 11 06:52:42 PM PDT 24 68782543 ps
T605 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.72347793 Aug 11 06:52:53 PM PDT 24 Aug 11 06:52:55 PM PDT 24 309283947 ps
T606 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.755111868 Aug 11 06:52:52 PM PDT 24 Aug 11 06:52:53 PM PDT 24 123274841 ps
T607 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2123769874 Aug 11 06:52:25 PM PDT 24 Aug 11 06:52:35 PM PDT 24 2313600745 ps
T608 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.741787414 Aug 11 06:52:28 PM PDT 24 Aug 11 06:52:31 PM PDT 24 281399227 ps
T609 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.203373988 Aug 11 06:52:50 PM PDT 24 Aug 11 06:52:52 PM PDT 24 98608974 ps
T610 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3233112316 Aug 11 06:52:47 PM PDT 24 Aug 11 06:52:48 PM PDT 24 65487966 ps
T611 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.185080971 Aug 11 06:52:45 PM PDT 24 Aug 11 06:52:46 PM PDT 24 69648383 ps
T612 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.973750414 Aug 11 06:52:31 PM PDT 24 Aug 11 06:52:33 PM PDT 24 120494219 ps
T613 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.486529239 Aug 11 06:52:50 PM PDT 24 Aug 11 06:52:52 PM PDT 24 77521470 ps
T614 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3338374564 Aug 11 06:52:50 PM PDT 24 Aug 11 06:52:51 PM PDT 24 130315761 ps
T615 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4158919404 Aug 11 06:52:50 PM PDT 24 Aug 11 06:52:51 PM PDT 24 75990089 ps
T616 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.668983970 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:34 PM PDT 24 125828495 ps
T617 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2728752712 Aug 11 06:52:47 PM PDT 24 Aug 11 06:52:48 PM PDT 24 251124044 ps
T618 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.957360539 Aug 11 06:52:38 PM PDT 24 Aug 11 06:52:40 PM PDT 24 464570622 ps
T619 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.658292085 Aug 11 06:52:32 PM PDT 24 Aug 11 06:52:33 PM PDT 24 183571943 ps
T620 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1276635625 Aug 11 06:52:27 PM PDT 24 Aug 11 06:52:28 PM PDT 24 128158812 ps

Test location /workspace/coverage/default/12.rstmgr_stress_all.2639776267
Short name T8
Test name
Test status
Simulation time 7891585570 ps
CPU time 34.3 seconds
Started Aug 11 06:10:27 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200556 kb
Host smart-1c6876e2-a0a3-454e-aef7-e1fd29e2d3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639776267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2639776267
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.974024507
Short name T86
Test name
Test status
Simulation time 452413308 ps
CPU time 2.42 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:07 PM PDT 24
Peak memory 200328 kb
Host smart-d2ccad9d-cf36-4dc4-84f4-618a9c36d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974024507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.974024507
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3614852653
Short name T72
Test name
Test status
Simulation time 166579957 ps
CPU time 1.57 seconds
Started Aug 11 06:52:40 PM PDT 24
Finished Aug 11 06:52:42 PM PDT 24
Peak memory 208464 kb
Host smart-cf1a3e18-dd6e-44d3-9455-1f0c987be6d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614852653 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3614852653
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1892405578
Short name T54
Test name
Test status
Simulation time 16674197364 ps
CPU time 24.44 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:10:15 PM PDT 24
Peak memory 217716 kb
Host smart-1cf3c3d2-3117-4eb5-a28f-a5ed7662ec2a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892405578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1892405578
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1939892283
Short name T25
Test name
Test status
Simulation time 2361006463 ps
CPU time 7.51 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:11:00 PM PDT 24
Peak memory 217792 kb
Host smart-3ac32239-3b10-492b-83a4-d7bdea4c1285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939892283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1939892283
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4123115088
Short name T94
Test name
Test status
Simulation time 931754278 ps
CPU time 3.35 seconds
Started Aug 11 06:52:27 PM PDT 24
Finished Aug 11 06:52:30 PM PDT 24
Peak memory 200160 kb
Host smart-0e0776c8-0a36-4fcc-8e68-1e217f95b88a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123115088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4123115088
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1626800283
Short name T4
Test name
Test status
Simulation time 62775197 ps
CPU time 0.73 seconds
Started Aug 11 06:10:24 PM PDT 24
Finished Aug 11 06:10:25 PM PDT 24
Peak memory 200100 kb
Host smart-226c35e3-62b0-4524-9c8f-e0c3d6834dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626800283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1626800283
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4155875809
Short name T117
Test name
Test status
Simulation time 480233840 ps
CPU time 3.13 seconds
Started Aug 11 06:52:37 PM PDT 24
Finished Aug 11 06:52:40 PM PDT 24
Peak memory 208368 kb
Host smart-8ccad737-8ec3-4353-8aa4-b2fc21fe722c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155875809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4155875809
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.766798276
Short name T150
Test name
Test status
Simulation time 160777189 ps
CPU time 1.17 seconds
Started Aug 11 06:10:07 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 200308 kb
Host smart-9df22297-6298-4c1f-8dcb-d306e4da473a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766798276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.766798276
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1275529101
Short name T167
Test name
Test status
Simulation time 197611166 ps
CPU time 1.25 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:37 PM PDT 24
Peak memory 200372 kb
Host smart-5dd335e5-e8dc-4604-8245-7e98cbb16c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275529101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1275529101
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3699462260
Short name T28
Test name
Test status
Simulation time 1878544049 ps
CPU time 7.46 seconds
Started Aug 11 06:11:01 PM PDT 24
Finished Aug 11 06:11:09 PM PDT 24
Peak memory 221716 kb
Host smart-63597163-fe5f-4580-8569-73db087c2aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699462260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3699462260
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.500689131
Short name T116
Test name
Test status
Simulation time 491117648 ps
CPU time 1.98 seconds
Started Aug 11 06:52:46 PM PDT 24
Finished Aug 11 06:52:48 PM PDT 24
Peak memory 200244 kb
Host smart-733c4a46-b9eb-4189-8f58-18748df9b73d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500689131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.500689131
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1545701034
Short name T89
Test name
Test status
Simulation time 507790958 ps
CPU time 3.06 seconds
Started Aug 11 06:52:38 PM PDT 24
Finished Aug 11 06:52:41 PM PDT 24
Peak memory 208372 kb
Host smart-328ebc6a-18e2-4e78-83c0-01dec174a212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545701034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1545701034
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_reset.639280930
Short name T119
Test name
Test status
Simulation time 1628961572 ps
CPU time 5.99 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:09:58 PM PDT 24
Peak memory 200492 kb
Host smart-bd6a6435-e0b8-45d5-aeae-9bf89b20d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639280930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.639280930
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.243644519
Short name T49
Test name
Test status
Simulation time 1877007322 ps
CPU time 7.55 seconds
Started Aug 11 06:10:10 PM PDT 24
Finished Aug 11 06:10:17 PM PDT 24
Peak memory 217632 kb
Host smart-0b8d4338-fe2d-4945-9dd1-3b9b02afb31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243644519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.243644519
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.215919782
Short name T107
Test name
Test status
Simulation time 73206430 ps
CPU time 0.85 seconds
Started Aug 11 06:52:26 PM PDT 24
Finished Aug 11 06:52:27 PM PDT 24
Peak memory 200052 kb
Host smart-06737737-d1d4-4fb1-9471-5176dcd4565c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215919782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.215919782
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1484626677
Short name T20
Test name
Test status
Simulation time 192699049 ps
CPU time 0.97 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 200164 kb
Host smart-fc9fa524-b379-4164-873c-831ef5179a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484626677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1484626677
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3255387637
Short name T118
Test name
Test status
Simulation time 440663395 ps
CPU time 1.8 seconds
Started Aug 11 06:52:44 PM PDT 24
Finished Aug 11 06:52:45 PM PDT 24
Peak memory 200200 kb
Host smart-a0846fa8-8055-48cb-bb96-e700a89f9a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255387637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3255387637
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2397986436
Short name T188
Test name
Test status
Simulation time 130624507 ps
CPU time 1.66 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 208492 kb
Host smart-ad3fb1a4-f1ce-4db5-b35d-19cf37349220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397986436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2397986436
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.350169783
Short name T592
Test name
Test status
Simulation time 164911488 ps
CPU time 1.88 seconds
Started Aug 11 06:52:26 PM PDT 24
Finished Aug 11 06:52:28 PM PDT 24
Peak memory 216556 kb
Host smart-1985fbdb-a0e4-4472-8bd5-42120e04a74c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350169783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.350169783
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2123769874
Short name T607
Test name
Test status
Simulation time 2313600745 ps
CPU time 9.57 seconds
Started Aug 11 06:52:25 PM PDT 24
Finished Aug 11 06:52:35 PM PDT 24
Peak memory 200172 kb
Host smart-7d3287a3-0c73-467b-bb14-648acb8b823b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123769874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
123769874
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.574924086
Short name T565
Test name
Test status
Simulation time 146487861 ps
CPU time 0.94 seconds
Started Aug 11 06:52:30 PM PDT 24
Finished Aug 11 06:52:31 PM PDT 24
Peak memory 200048 kb
Host smart-ed6980e1-2d99-4a63-8081-ba581460bcb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574924086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.574924086
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4119822832
Short name T543
Test name
Test status
Simulation time 111988428 ps
CPU time 0.91 seconds
Started Aug 11 06:52:30 PM PDT 24
Finished Aug 11 06:52:31 PM PDT 24
Peak memory 200140 kb
Host smart-ee9b3720-e32e-4ff2-8b67-a08544ad7986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119822832 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.4119822832
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1120568589
Short name T566
Test name
Test status
Simulation time 104615922 ps
CPU time 1.26 seconds
Started Aug 11 06:52:25 PM PDT 24
Finished Aug 11 06:52:26 PM PDT 24
Peak memory 200208 kb
Host smart-5d170e5d-6204-4bea-9cfe-b5d690d2c148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120568589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1120568589
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.741787414
Short name T608
Test name
Test status
Simulation time 281399227 ps
CPU time 2.29 seconds
Started Aug 11 06:52:28 PM PDT 24
Finished Aug 11 06:52:31 PM PDT 24
Peak memory 211232 kb
Host smart-413128f4-d8cb-4254-a974-10cf1d5947b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741787414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.741787414
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.4092182075
Short name T541
Test name
Test status
Simulation time 206790328 ps
CPU time 1.53 seconds
Started Aug 11 06:52:34 PM PDT 24
Finished Aug 11 06:52:35 PM PDT 24
Peak memory 200232 kb
Host smart-1027e66d-4638-4c3d-a651-92b9696a1272
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092182075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.4
092182075
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1578784771
Short name T542
Test name
Test status
Simulation time 477949820 ps
CPU time 5.71 seconds
Started Aug 11 06:52:25 PM PDT 24
Finished Aug 11 06:52:31 PM PDT 24
Peak memory 200100 kb
Host smart-4ecf1779-22e7-4278-ae42-58d2af80bc95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578784771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
578784771
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1276635625
Short name T620
Test name
Test status
Simulation time 128158812 ps
CPU time 0.93 seconds
Started Aug 11 06:52:27 PM PDT 24
Finished Aug 11 06:52:28 PM PDT 24
Peak memory 200048 kb
Host smart-0cc17a51-92d3-450a-9dd5-b409e4a684f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276635625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1
276635625
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.658292085
Short name T619
Test name
Test status
Simulation time 183571943 ps
CPU time 1.26 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 208364 kb
Host smart-0263bc89-5f73-4488-aee1-2584b266e1f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658292085 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.658292085
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1384112987
Short name T554
Test name
Test status
Simulation time 70207397 ps
CPU time 0.8 seconds
Started Aug 11 06:52:25 PM PDT 24
Finished Aug 11 06:52:26 PM PDT 24
Peak memory 200080 kb
Host smart-fc9175b6-ff0f-49ef-a8f4-2db793188555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384112987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1384112987
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.651803837
Short name T585
Test name
Test status
Simulation time 76694470 ps
CPU time 0.98 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 200108 kb
Host smart-8221d41a-6f0f-4028-af91-17c529185d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651803837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.651803837
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.818706594
Short name T555
Test name
Test status
Simulation time 446158905 ps
CPU time 3 seconds
Started Aug 11 06:52:25 PM PDT 24
Finished Aug 11 06:52:28 PM PDT 24
Peak memory 208312 kb
Host smart-a971f18d-2774-4caa-8ba8-9386a9eeae97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818706594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.818706594
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2434951698
Short name T552
Test name
Test status
Simulation time 425329081 ps
CPU time 1.76 seconds
Started Aug 11 06:52:29 PM PDT 24
Finished Aug 11 06:52:31 PM PDT 24
Peak memory 200208 kb
Host smart-739603df-601d-4366-909f-4612f268650e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434951698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2434951698
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2380923970
Short name T97
Test name
Test status
Simulation time 180833762 ps
CPU time 1.22 seconds
Started Aug 11 06:52:44 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 200348 kb
Host smart-195aab42-635e-4e08-a02c-77d108f5b633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380923970 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2380923970
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1483685386
Short name T583
Test name
Test status
Simulation time 65783947 ps
CPU time 0.74 seconds
Started Aug 11 06:52:46 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 199992 kb
Host smart-7b25d9fe-88b8-4dba-a774-63077d4ccec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483685386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1483685386
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4102051672
Short name T556
Test name
Test status
Simulation time 218165718 ps
CPU time 1.41 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:47 PM PDT 24
Peak memory 200140 kb
Host smart-20c5a349-dd61-47ef-ac26-83275fccc9e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102051672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.4102051672
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2980196635
Short name T114
Test name
Test status
Simulation time 231897936 ps
CPU time 1.75 seconds
Started Aug 11 06:52:38 PM PDT 24
Finished Aug 11 06:52:40 PM PDT 24
Peak memory 208404 kb
Host smart-f58abb20-9e28-4ced-aaa7-6a9aaa130e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980196635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2980196635
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.743200628
Short name T544
Test name
Test status
Simulation time 138863162 ps
CPU time 1.14 seconds
Started Aug 11 06:52:44 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 208396 kb
Host smart-e96a8c69-cbc5-4008-821e-f9b19d0704bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743200628 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.743200628
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.3728005223
Short name T588
Test name
Test status
Simulation time 64534131 ps
CPU time 0.87 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 200076 kb
Host smart-7e94ca61-f763-44ff-9a32-70c35f729577
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728005223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.3728005223
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.792584091
Short name T110
Test name
Test status
Simulation time 137777988 ps
CPU time 1.19 seconds
Started Aug 11 06:52:46 PM PDT 24
Finished Aug 11 06:52:47 PM PDT 24
Peak memory 200164 kb
Host smart-fe56be85-5b56-42a9-9916-d44ea5ed7217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792584091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.792584091
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.494089474
Short name T73
Test name
Test status
Simulation time 214033976 ps
CPU time 1.72 seconds
Started Aug 11 06:52:44 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 208344 kb
Host smart-f25b8814-c13a-4e07-8c1f-4904945bb165
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494089474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.494089474
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1220236601
Short name T569
Test name
Test status
Simulation time 93563259 ps
CPU time 0.88 seconds
Started Aug 11 06:52:46 PM PDT 24
Finished Aug 11 06:52:47 PM PDT 24
Peak memory 200184 kb
Host smart-ab0d4167-1586-40e5-b4ed-edae0ba00c60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220236601 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1220236601
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1069978273
Short name T65
Test name
Test status
Simulation time 83900879 ps
CPU time 0.86 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 200012 kb
Host smart-22d8fb13-5ff3-421a-8a33-1f4ff982c476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069978273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1069978273
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3978000426
Short name T106
Test name
Test status
Simulation time 81075852 ps
CPU time 0.99 seconds
Started Aug 11 06:52:46 PM PDT 24
Finished Aug 11 06:52:47 PM PDT 24
Peak memory 200068 kb
Host smart-5968383f-c7d0-4559-969a-91ad20ae3e5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978000426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3978000426
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1869581487
Short name T90
Test name
Test status
Simulation time 123707178 ps
CPU time 1.77 seconds
Started Aug 11 06:52:47 PM PDT 24
Finished Aug 11 06:52:49 PM PDT 24
Peak memory 208372 kb
Host smart-ce15d587-2f5b-4a84-8784-db475862148f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869581487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1869581487
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2045621064
Short name T589
Test name
Test status
Simulation time 430524630 ps
CPU time 1.79 seconds
Started Aug 11 06:52:47 PM PDT 24
Finished Aug 11 06:52:49 PM PDT 24
Peak memory 200236 kb
Host smart-4521ddff-0528-4d13-8792-1c8a20dc2e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045621064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2045621064
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4000248107
Short name T591
Test name
Test status
Simulation time 141611742 ps
CPU time 1.48 seconds
Started Aug 11 06:52:46 PM PDT 24
Finished Aug 11 06:52:47 PM PDT 24
Peak memory 208476 kb
Host smart-8265ca0d-ca06-4a76-89bd-ad4b968e4fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000248107 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4000248107
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3663201386
Short name T593
Test name
Test status
Simulation time 77323235 ps
CPU time 0.77 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:45 PM PDT 24
Peak memory 199944 kb
Host smart-56d37813-0652-4484-83cc-f98e84382f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663201386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3663201386
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.490043391
Short name T553
Test name
Test status
Simulation time 157082028 ps
CPU time 1.13 seconds
Started Aug 11 06:52:44 PM PDT 24
Finished Aug 11 06:52:45 PM PDT 24
Peak memory 200088 kb
Host smart-6cdaff8b-0165-4f2f-b76f-e8f480260c59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490043391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.490043391
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.780143659
Short name T601
Test name
Test status
Simulation time 360527281 ps
CPU time 2.46 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:48 PM PDT 24
Peak memory 208260 kb
Host smart-5a5b4224-e956-4e80-99b9-9c8f70df6480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780143659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.780143659
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3563573329
Short name T574
Test name
Test status
Simulation time 437042792 ps
CPU time 1.77 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:47 PM PDT 24
Peak memory 200264 kb
Host smart-19135511-458f-4eec-b136-2dde0478e806
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563573329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3563573329
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2348813644
Short name T546
Test name
Test status
Simulation time 116117581 ps
CPU time 1.29 seconds
Started Aug 11 06:52:47 PM PDT 24
Finished Aug 11 06:52:48 PM PDT 24
Peak memory 208456 kb
Host smart-a431ebad-6c5c-47ea-8ada-45bfc74c44d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348813644 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2348813644
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.185080971
Short name T611
Test name
Test status
Simulation time 69648383 ps
CPU time 0.84 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:46 PM PDT 24
Peak memory 200212 kb
Host smart-be97a586-2357-45ee-a2f7-b11a85603d61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185080971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.185080971
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2728752712
Short name T617
Test name
Test status
Simulation time 251124044 ps
CPU time 1.53 seconds
Started Aug 11 06:52:47 PM PDT 24
Finished Aug 11 06:52:48 PM PDT 24
Peak memory 200192 kb
Host smart-e3484565-8854-487c-af17-eb616b1c2aae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728752712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2728752712
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.884855739
Short name T558
Test name
Test status
Simulation time 326941892 ps
CPU time 2.24 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:47 PM PDT 24
Peak memory 210752 kb
Host smart-16c5490a-7123-43d3-b10e-d841222e4c34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884855739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.884855739
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2089484603
Short name T599
Test name
Test status
Simulation time 904422443 ps
CPU time 3.21 seconds
Started Aug 11 06:52:45 PM PDT 24
Finished Aug 11 06:52:48 PM PDT 24
Peak memory 200204 kb
Host smart-a5ac7730-8ffc-4630-9f5d-6e0be2299609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089484603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2089484603
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3760022582
Short name T598
Test name
Test status
Simulation time 193736911 ps
CPU time 1.35 seconds
Started Aug 11 06:52:53 PM PDT 24
Finished Aug 11 06:52:54 PM PDT 24
Peak memory 208412 kb
Host smart-e6c7ca33-475b-432f-a645-af62405e41c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760022582 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3760022582
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3233112316
Short name T610
Test name
Test status
Simulation time 65487966 ps
CPU time 0.79 seconds
Started Aug 11 06:52:47 PM PDT 24
Finished Aug 11 06:52:48 PM PDT 24
Peak memory 200004 kb
Host smart-7324f3c8-0a1e-49cd-91a9-8548858fd6b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233112316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3233112316
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.72347793
Short name T605
Test name
Test status
Simulation time 309283947 ps
CPU time 1.71 seconds
Started Aug 11 06:52:53 PM PDT 24
Finished Aug 11 06:52:55 PM PDT 24
Peak memory 200288 kb
Host smart-17546793-21b0-4a99-817a-732b2d2c91ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72347793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_sam
e_csr_outstanding.72347793
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2346293434
Short name T586
Test name
Test status
Simulation time 178537203 ps
CPU time 1.37 seconds
Started Aug 11 06:52:46 PM PDT 24
Finished Aug 11 06:52:48 PM PDT 24
Peak memory 216396 kb
Host smart-cc97dbb2-46ca-464c-9079-d8c118b15223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346293434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2346293434
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2216064826
Short name T572
Test name
Test status
Simulation time 410441173 ps
CPU time 1.67 seconds
Started Aug 11 06:52:47 PM PDT 24
Finished Aug 11 06:52:49 PM PDT 24
Peak memory 200184 kb
Host smart-f1c882ac-a1b8-40da-a170-53520998b8b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216064826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2216064826
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.203373988
Short name T609
Test name
Test status
Simulation time 98608974 ps
CPU time 0.87 seconds
Started Aug 11 06:52:50 PM PDT 24
Finished Aug 11 06:52:52 PM PDT 24
Peak memory 200192 kb
Host smart-5c014805-a765-427b-9483-78c852c80eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203373988 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.203373988
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3643233960
Short name T111
Test name
Test status
Simulation time 57822629 ps
CPU time 0.84 seconds
Started Aug 11 06:52:51 PM PDT 24
Finished Aug 11 06:52:52 PM PDT 24
Peak memory 199900 kb
Host smart-a62062de-48de-438e-a608-66e58ac437b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643233960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3643233960
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.658522093
Short name T594
Test name
Test status
Simulation time 86738947 ps
CPU time 0.95 seconds
Started Aug 11 06:52:51 PM PDT 24
Finished Aug 11 06:52:52 PM PDT 24
Peak memory 200076 kb
Host smart-2e7b5bcb-ec2c-4b1c-b28c-2c83cc1124d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658522093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.658522093
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.677588365
Short name T584
Test name
Test status
Simulation time 372452429 ps
CPU time 2.37 seconds
Started Aug 11 06:52:54 PM PDT 24
Finished Aug 11 06:52:56 PM PDT 24
Peak memory 208348 kb
Host smart-436e119a-0b97-416c-bf16-c5921abf7583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677588365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.677588365
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3189601603
Short name T581
Test name
Test status
Simulation time 896251421 ps
CPU time 3.01 seconds
Started Aug 11 06:52:51 PM PDT 24
Finished Aug 11 06:52:54 PM PDT 24
Peak memory 200204 kb
Host smart-b38f4038-5de6-4de9-bf44-b94e0ef98113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189601603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3189601603
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2015482877
Short name T573
Test name
Test status
Simulation time 212660449 ps
CPU time 2.1 seconds
Started Aug 11 06:52:54 PM PDT 24
Finished Aug 11 06:52:57 PM PDT 24
Peak memory 208460 kb
Host smart-8da9aef7-aea5-44cb-aed8-ddacc2c9a198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015482877 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2015482877
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.842967945
Short name T600
Test name
Test status
Simulation time 83067302 ps
CPU time 0.84 seconds
Started Aug 11 06:52:53 PM PDT 24
Finished Aug 11 06:52:53 PM PDT 24
Peak memory 199980 kb
Host smart-c07deb59-baca-4ffd-8085-507eed60f971
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842967945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.842967945
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.4158919404
Short name T615
Test name
Test status
Simulation time 75990089 ps
CPU time 0.94 seconds
Started Aug 11 06:52:50 PM PDT 24
Finished Aug 11 06:52:51 PM PDT 24
Peak memory 200132 kb
Host smart-53bc148f-2fce-42d6-bb2b-a2f2199694f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158919404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.4158919404
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1411376254
Short name T71
Test name
Test status
Simulation time 644741504 ps
CPU time 4.07 seconds
Started Aug 11 06:52:51 PM PDT 24
Finished Aug 11 06:52:55 PM PDT 24
Peak memory 208492 kb
Host smart-1ecc0381-db5f-47f7-82b6-d8402217d486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411376254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1411376254
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1714856277
Short name T93
Test name
Test status
Simulation time 776540109 ps
CPU time 2.97 seconds
Started Aug 11 06:52:50 PM PDT 24
Finished Aug 11 06:52:53 PM PDT 24
Peak memory 200172 kb
Host smart-c1ce233b-f2e5-4c65-be33-ed4828ffc14a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714856277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.1714856277
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2131080668
Short name T563
Test name
Test status
Simulation time 182440529 ps
CPU time 1.23 seconds
Started Aug 11 06:52:50 PM PDT 24
Finished Aug 11 06:52:52 PM PDT 24
Peak memory 208396 kb
Host smart-27103ed5-f030-4d8e-921a-67bd1c1d82c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131080668 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2131080668
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2160438703
Short name T603
Test name
Test status
Simulation time 68120265 ps
CPU time 0.88 seconds
Started Aug 11 06:52:51 PM PDT 24
Finished Aug 11 06:52:52 PM PDT 24
Peak memory 200004 kb
Host smart-e4fc3a6a-e442-4a01-8543-e7c04fa193f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160438703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2160438703
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.486529239
Short name T613
Test name
Test status
Simulation time 77521470 ps
CPU time 0.95 seconds
Started Aug 11 06:52:50 PM PDT 24
Finished Aug 11 06:52:52 PM PDT 24
Peak memory 200112 kb
Host smart-c8067bbc-d21e-4d89-9cbf-6b85fa7a984b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486529239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.486529239
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.903344023
Short name T568
Test name
Test status
Simulation time 94788483 ps
CPU time 1.18 seconds
Started Aug 11 06:52:53 PM PDT 24
Finished Aug 11 06:52:54 PM PDT 24
Peak memory 208248 kb
Host smart-d5257396-4119-4bf7-a24c-ea253186a6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903344023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.903344023
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2060473188
Short name T92
Test name
Test status
Simulation time 470442028 ps
CPU time 2.07 seconds
Started Aug 11 06:52:55 PM PDT 24
Finished Aug 11 06:52:57 PM PDT 24
Peak memory 200276 kb
Host smart-07a839a7-0254-441e-bb16-af82a8d72f99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060473188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2060473188
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3338374564
Short name T614
Test name
Test status
Simulation time 130315761 ps
CPU time 1.04 seconds
Started Aug 11 06:52:50 PM PDT 24
Finished Aug 11 06:52:51 PM PDT 24
Peak memory 200188 kb
Host smart-e2c9ca38-527b-4f1c-8e33-b9b03fcee90d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338374564 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3338374564
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2346106079
Short name T567
Test name
Test status
Simulation time 61909395 ps
CPU time 0.87 seconds
Started Aug 11 06:52:50 PM PDT 24
Finished Aug 11 06:52:51 PM PDT 24
Peak memory 200024 kb
Host smart-76ca704a-ef55-4e11-8f4e-a7bf60d18da0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346106079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2346106079
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.755111868
Short name T606
Test name
Test status
Simulation time 123274841 ps
CPU time 1.08 seconds
Started Aug 11 06:52:52 PM PDT 24
Finished Aug 11 06:52:53 PM PDT 24
Peak memory 200144 kb
Host smart-417cdd41-5133-438c-a796-01e027ac98b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755111868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.755111868
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2076962545
Short name T580
Test name
Test status
Simulation time 305486828 ps
CPU time 2.07 seconds
Started Aug 11 06:52:56 PM PDT 24
Finished Aug 11 06:52:58 PM PDT 24
Peak memory 208372 kb
Host smart-c7127b80-1314-4609-a135-6ae570f8d828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076962545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2076962545
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.390785494
Short name T559
Test name
Test status
Simulation time 492113372 ps
CPU time 1.91 seconds
Started Aug 11 06:52:51 PM PDT 24
Finished Aug 11 06:52:53 PM PDT 24
Peak memory 200252 kb
Host smart-77d2a440-42d5-4192-ba70-313c26ede6db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390785494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.390785494
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3634472125
Short name T124
Test name
Test status
Simulation time 430490444 ps
CPU time 2.57 seconds
Started Aug 11 06:52:31 PM PDT 24
Finished Aug 11 06:52:34 PM PDT 24
Peak memory 200148 kb
Host smart-42a0f06f-82b4-4c71-a71c-ef389143c335
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634472125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
634472125
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2466736464
Short name T560
Test name
Test status
Simulation time 274274406 ps
CPU time 3.32 seconds
Started Aug 11 06:52:33 PM PDT 24
Finished Aug 11 06:52:36 PM PDT 24
Peak memory 200088 kb
Host smart-d6ebfffa-1de3-4091-a974-d6a4e329024b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466736464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
466736464
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1542814336
Short name T537
Test name
Test status
Simulation time 137203735 ps
CPU time 0.91 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 200028 kb
Host smart-1d45ea64-0b19-41de-8424-2ea8ceb8ff77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542814336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1
542814336
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.22137289
Short name T549
Test name
Test status
Simulation time 98529111 ps
CPU time 0.94 seconds
Started Aug 11 06:52:31 PM PDT 24
Finished Aug 11 06:52:32 PM PDT 24
Peak memory 208444 kb
Host smart-7129b174-e144-4f61-8da0-5ce91f2bb7a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22137289 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.22137289
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.750813327
Short name T64
Test name
Test status
Simulation time 63743088 ps
CPU time 0.78 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 199840 kb
Host smart-f1718d92-7a14-4c40-a143-6de5b2a49a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750813327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.750813327
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.159683314
Short name T109
Test name
Test status
Simulation time 194862529 ps
CPU time 1.4 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:34 PM PDT 24
Peak memory 200232 kb
Host smart-3dfd835b-e314-49f5-9a88-557fed1483c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159683314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.159683314
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.955537224
Short name T590
Test name
Test status
Simulation time 119661101 ps
CPU time 1.6 seconds
Started Aug 11 06:52:34 PM PDT 24
Finished Aug 11 06:52:36 PM PDT 24
Peak memory 208352 kb
Host smart-a789425b-c0c1-45b1-8cb6-123ed175881e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955537224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.955537224
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1559362330
Short name T67
Test name
Test status
Simulation time 488989597 ps
CPU time 1.87 seconds
Started Aug 11 06:52:33 PM PDT 24
Finished Aug 11 06:52:35 PM PDT 24
Peak memory 200204 kb
Host smart-19c244fe-6fb2-4d41-98cf-2ad7cfbea4e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559362330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1559362330
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.472312842
Short name T545
Test name
Test status
Simulation time 150612422 ps
CPU time 1.92 seconds
Started Aug 11 06:52:31 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 208312 kb
Host smart-bbf4fc70-38df-49e3-b61d-8b421b72a245
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472312842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.472312842
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2901178185
Short name T550
Test name
Test status
Simulation time 806168313 ps
CPU time 4.31 seconds
Started Aug 11 06:52:31 PM PDT 24
Finished Aug 11 06:52:36 PM PDT 24
Peak memory 200144 kb
Host smart-df8cf165-9bf8-4b49-9da2-e10cad3ef2f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901178185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
901178185
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3530155506
Short name T561
Test name
Test status
Simulation time 130828516 ps
CPU time 0.92 seconds
Started Aug 11 06:52:31 PM PDT 24
Finished Aug 11 06:52:32 PM PDT 24
Peak memory 199980 kb
Host smart-9e7a02eb-03b9-4a72-a5c0-37abd1743a29
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530155506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
530155506
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3140856435
Short name T548
Test name
Test status
Simulation time 170027311 ps
CPU time 1.12 seconds
Started Aug 11 06:52:35 PM PDT 24
Finished Aug 11 06:52:36 PM PDT 24
Peak memory 208340 kb
Host smart-3170604b-93fc-4a04-818b-24cd0954311b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140856435 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3140856435
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1205815734
Short name T596
Test name
Test status
Simulation time 65232539 ps
CPU time 0.78 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 200056 kb
Host smart-9e1fb9b1-ec2e-40b4-a829-f559bd3ddbb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205815734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1205815734
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1671146445
Short name T602
Test name
Test status
Simulation time 129956988 ps
CPU time 1.06 seconds
Started Aug 11 06:52:31 PM PDT 24
Finished Aug 11 06:52:32 PM PDT 24
Peak memory 200096 kb
Host smart-32300b02-42a6-46fe-b10c-e6134a21fc2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671146445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1671146445
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.973750414
Short name T612
Test name
Test status
Simulation time 120494219 ps
CPU time 1.64 seconds
Started Aug 11 06:52:31 PM PDT 24
Finished Aug 11 06:52:33 PM PDT 24
Peak memory 208428 kb
Host smart-fe35ed74-80c1-421e-aa8d-2ccd9743836c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973750414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.973750414
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2183843193
Short name T68
Test name
Test status
Simulation time 481252139 ps
CPU time 1.76 seconds
Started Aug 11 06:52:34 PM PDT 24
Finished Aug 11 06:52:36 PM PDT 24
Peak memory 200256 kb
Host smart-b67c8db2-7352-401b-8eeb-bd08ae66d1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183843193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2183843193
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.126453432
Short name T597
Test name
Test status
Simulation time 425041678 ps
CPU time 2.48 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:34 PM PDT 24
Peak memory 200160 kb
Host smart-916347fe-6614-4cf7-b493-c4a2a0a69fd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126453432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.126453432
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.363334688
Short name T595
Test name
Test status
Simulation time 276568842 ps
CPU time 3.18 seconds
Started Aug 11 06:52:33 PM PDT 24
Finished Aug 11 06:52:36 PM PDT 24
Peak memory 200252 kb
Host smart-8415c20f-46f0-4b8d-9ff9-b20ab5241cdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363334688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.363334688
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2313325935
Short name T575
Test name
Test status
Simulation time 102564517 ps
CPU time 0.86 seconds
Started Aug 11 06:52:34 PM PDT 24
Finished Aug 11 06:52:35 PM PDT 24
Peak memory 200020 kb
Host smart-0664479e-a3cc-437d-85e6-5b4bc6d54df6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313325935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
313325935
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2817001670
Short name T579
Test name
Test status
Simulation time 229982731 ps
CPU time 1.22 seconds
Started Aug 11 06:52:39 PM PDT 24
Finished Aug 11 06:52:40 PM PDT 24
Peak memory 200156 kb
Host smart-39c2dd14-ea54-421f-91e5-0e4ca2955f9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817001670 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.2817001670
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.2066982846
Short name T112
Test name
Test status
Simulation time 76151965 ps
CPU time 0.85 seconds
Started Aug 11 06:52:34 PM PDT 24
Finished Aug 11 06:52:35 PM PDT 24
Peak memory 200068 kb
Host smart-ce17896a-66df-4b91-8cc9-c4d0311bf922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066982846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2066982846
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.668983970
Short name T616
Test name
Test status
Simulation time 125828495 ps
CPU time 1.19 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:34 PM PDT 24
Peak memory 200304 kb
Host smart-d66a8353-442c-4584-819a-7f1c46e68fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668983970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.668983970
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.359875314
Short name T91
Test name
Test status
Simulation time 348582307 ps
CPU time 2.49 seconds
Started Aug 11 06:52:32 PM PDT 24
Finished Aug 11 06:52:35 PM PDT 24
Peak memory 200216 kb
Host smart-70698da0-a160-4b3e-baec-9eebe65b53a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359875314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.359875314
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1447799267
Short name T115
Test name
Test status
Simulation time 901741760 ps
CPU time 2.86 seconds
Started Aug 11 06:52:31 PM PDT 24
Finished Aug 11 06:52:34 PM PDT 24
Peak memory 200292 kb
Host smart-da18e759-ac51-451a-92db-7d3739a3eb02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447799267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1447799267
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1710600662
Short name T547
Test name
Test status
Simulation time 101318007 ps
CPU time 1.04 seconds
Started Aug 11 06:52:40 PM PDT 24
Finished Aug 11 06:52:41 PM PDT 24
Peak memory 208368 kb
Host smart-5a8060e3-870b-4efc-a400-240bd8e58abd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710600662 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1710600662
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3606795352
Short name T540
Test name
Test status
Simulation time 62238739 ps
CPU time 0.72 seconds
Started Aug 11 06:52:38 PM PDT 24
Finished Aug 11 06:52:39 PM PDT 24
Peak memory 200100 kb
Host smart-3c9998e0-57dc-4dbd-9afd-04765278b55c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606795352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3606795352
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3214244127
Short name T578
Test name
Test status
Simulation time 70369667 ps
CPU time 0.94 seconds
Started Aug 11 06:52:38 PM PDT 24
Finished Aug 11 06:52:39 PM PDT 24
Peak memory 200156 kb
Host smart-d853b4e9-f60e-437f-8fdd-88314a96e473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214244127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3214244127
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.2827289329
Short name T564
Test name
Test status
Simulation time 367489790 ps
CPU time 2.6 seconds
Started Aug 11 06:52:38 PM PDT 24
Finished Aug 11 06:52:41 PM PDT 24
Peak memory 208404 kb
Host smart-0d89136d-a116-4e88-ad6b-5ca37c16a4b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827289329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2827289329
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1023855656
Short name T587
Test name
Test status
Simulation time 488400425 ps
CPU time 1.93 seconds
Started Aug 11 06:52:40 PM PDT 24
Finished Aug 11 06:52:43 PM PDT 24
Peak memory 200252 kb
Host smart-a7b37428-545d-4914-88f2-c3e77fa75673
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023855656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1023855656
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4119416144
Short name T576
Test name
Test status
Simulation time 113357994 ps
CPU time 1.21 seconds
Started Aug 11 06:52:42 PM PDT 24
Finished Aug 11 06:52:43 PM PDT 24
Peak memory 208348 kb
Host smart-789903c3-db09-43d7-96ca-7b6aa37d6e92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119416144 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4119416144
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2821386863
Short name T538
Test name
Test status
Simulation time 78314029 ps
CPU time 0.8 seconds
Started Aug 11 06:52:37 PM PDT 24
Finished Aug 11 06:52:38 PM PDT 24
Peak memory 200076 kb
Host smart-c20a04b4-389a-45b0-9822-2f97abafda07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821386863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2821386863
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1972215024
Short name T577
Test name
Test status
Simulation time 279159008 ps
CPU time 1.58 seconds
Started Aug 11 06:52:40 PM PDT 24
Finished Aug 11 06:52:42 PM PDT 24
Peak memory 200152 kb
Host smart-0173c230-a80c-4b57-afe5-cfd8fd8e7761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972215024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.1972215024
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.799099401
Short name T557
Test name
Test status
Simulation time 194193815 ps
CPU time 1.82 seconds
Started Aug 11 06:52:39 PM PDT 24
Finished Aug 11 06:52:40 PM PDT 24
Peak memory 208412 kb
Host smart-cc482d3d-a7a5-4f40-8502-83167f132fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799099401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.799099401
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2243545546
Short name T551
Test name
Test status
Simulation time 956877585 ps
CPU time 3.32 seconds
Started Aug 11 06:52:37 PM PDT 24
Finished Aug 11 06:52:41 PM PDT 24
Peak memory 200260 kb
Host smart-5cb8886c-bfd6-4a3a-ab32-803b564879df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243545546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2243545546
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1812585530
Short name T562
Test name
Test status
Simulation time 185454435 ps
CPU time 1.86 seconds
Started Aug 11 06:52:41 PM PDT 24
Finished Aug 11 06:52:43 PM PDT 24
Peak memory 208392 kb
Host smart-a6f24827-456f-499a-97e1-d894488bcd5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812585530 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1812585530
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1203410817
Short name T66
Test name
Test status
Simulation time 66784616 ps
CPU time 0.74 seconds
Started Aug 11 06:52:40 PM PDT 24
Finished Aug 11 06:52:41 PM PDT 24
Peak memory 199984 kb
Host smart-7ca6ccd6-6c4a-426f-8c49-3548bf91ca83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203410817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1203410817
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2502358524
Short name T113
Test name
Test status
Simulation time 153776244 ps
CPU time 1.11 seconds
Started Aug 11 06:52:39 PM PDT 24
Finished Aug 11 06:52:40 PM PDT 24
Peak memory 200132 kb
Host smart-419d2605-0488-4b4d-a0b7-3cbe71fd0162
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502358524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.2502358524
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.957360539
Short name T618
Test name
Test status
Simulation time 464570622 ps
CPU time 1.92 seconds
Started Aug 11 06:52:38 PM PDT 24
Finished Aug 11 06:52:40 PM PDT 24
Peak memory 200280 kb
Host smart-a54d7912-3d21-4e41-816e-e88a8b24a9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957360539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
957360539
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.665089795
Short name T571
Test name
Test status
Simulation time 179284593 ps
CPU time 1.27 seconds
Started Aug 11 06:52:37 PM PDT 24
Finished Aug 11 06:52:38 PM PDT 24
Peak memory 208376 kb
Host smart-d27b8adf-8a41-44cf-8469-0ad03395d74f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665089795 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.665089795
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1640646345
Short name T539
Test name
Test status
Simulation time 75940914 ps
CPU time 0.86 seconds
Started Aug 11 06:52:41 PM PDT 24
Finished Aug 11 06:52:42 PM PDT 24
Peak memory 199972 kb
Host smart-938c2d8c-27f3-4d2c-86d7-c1bdec4efc0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640646345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1640646345
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.4041611004
Short name T108
Test name
Test status
Simulation time 202071801 ps
CPU time 1.42 seconds
Started Aug 11 06:52:41 PM PDT 24
Finished Aug 11 06:52:42 PM PDT 24
Peak memory 200140 kb
Host smart-1e00693b-e6b5-4355-85ad-f3445822671a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041611004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.4041611004
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3828088266
Short name T96
Test name
Test status
Simulation time 194320963 ps
CPU time 2.86 seconds
Started Aug 11 06:52:40 PM PDT 24
Finished Aug 11 06:52:43 PM PDT 24
Peak memory 200148 kb
Host smart-4eba1dad-3305-4620-a0c2-1c6dc3e02608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828088266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3828088266
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1054393286
Short name T95
Test name
Test status
Simulation time 936903755 ps
CPU time 3.18 seconds
Started Aug 11 06:52:40 PM PDT 24
Finished Aug 11 06:52:44 PM PDT 24
Peak memory 200152 kb
Host smart-5b16f321-445d-4838-bf8f-efa6634b554a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054393286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1054393286
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.707079147
Short name T604
Test name
Test status
Simulation time 68782543 ps
CPU time 0.79 seconds
Started Aug 11 06:52:42 PM PDT 24
Finished Aug 11 06:52:42 PM PDT 24
Peak memory 200024 kb
Host smart-7ded9dca-edf1-4f35-bf08-038c1898c8cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707079147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.707079147
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3847221785
Short name T570
Test name
Test status
Simulation time 88660932 ps
CPU time 1 seconds
Started Aug 11 06:52:37 PM PDT 24
Finished Aug 11 06:52:38 PM PDT 24
Peak memory 200136 kb
Host smart-6cfcca53-2baf-447a-90d2-e915cde3181c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847221785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3847221785
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.226538767
Short name T582
Test name
Test status
Simulation time 917662952 ps
CPU time 3.06 seconds
Started Aug 11 06:52:42 PM PDT 24
Finished Aug 11 06:52:45 PM PDT 24
Peak memory 200204 kb
Host smart-ff30ee7b-8794-424a-8eb2-cbb67649251c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226538767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
226538767
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.570448118
Short name T486
Test name
Test status
Simulation time 54706575 ps
CPU time 0.68 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 200000 kb
Host smart-e03d0176-19f0-4f3d-8b89-9e7e2b2c6b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570448118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.570448118
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.956161661
Short name T470
Test name
Test status
Simulation time 1226962620 ps
CPU time 5.49 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:54 PM PDT 24
Peak memory 221620 kb
Host smart-ed6f25b9-7ba0-44d9-bca3-935852731a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956161661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.956161661
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3634174736
Short name T163
Test name
Test status
Simulation time 245232027 ps
CPU time 1.06 seconds
Started Aug 11 06:09:46 PM PDT 24
Finished Aug 11 06:09:47 PM PDT 24
Peak memory 217508 kb
Host smart-3b6949bd-6190-452f-b3ce-7111177d2aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634174736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3634174736
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2186847314
Short name T293
Test name
Test status
Simulation time 86565091 ps
CPU time 0.78 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 200132 kb
Host smart-dcd2f551-9615-4d38-aaad-d09c0cc4aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186847314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2186847314
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1406750109
Short name T80
Test name
Test status
Simulation time 8285144092 ps
CPU time 12.9 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 217296 kb
Host smart-594d6301-f193-4075-955f-47ab52b8808e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406750109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1406750109
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3705833518
Short name T253
Test name
Test status
Simulation time 112398282 ps
CPU time 1.15 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 200340 kb
Host smart-df1331a2-d221-4377-838e-11a9c2662cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705833518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3705833518
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.690953064
Short name T511
Test name
Test status
Simulation time 1823464173 ps
CPU time 8.7 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 208948 kb
Host smart-2c109332-44aa-414c-9a41-ab0773ea6e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690953064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.690953064
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1633967681
Short name T502
Test name
Test status
Simulation time 507527439 ps
CPU time 2.6 seconds
Started Aug 11 06:09:55 PM PDT 24
Finished Aug 11 06:09:58 PM PDT 24
Peak memory 200284 kb
Host smart-f854ff0c-5810-4a8d-ba0f-448e9e276ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633967681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1633967681
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3560743737
Short name T243
Test name
Test status
Simulation time 205916850 ps
CPU time 1.31 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 200216 kb
Host smart-9482467b-0a13-46e6-8c40-75e551490ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560743737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3560743737
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3878657436
Short name T387
Test name
Test status
Simulation time 57403432 ps
CPU time 0.77 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 199972 kb
Host smart-9c283076-a781-464d-95ca-ddba0899bb0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878657436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3878657436
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.4267285690
Short name T471
Test name
Test status
Simulation time 1232717156 ps
CPU time 5.57 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 217744 kb
Host smart-1e846879-22c2-4aaf-8859-a87be55dd57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267285690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4267285690
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3429622867
Short name T37
Test name
Test status
Simulation time 244948369 ps
CPU time 1.16 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 217504 kb
Host smart-87525db8-a3c9-487f-b275-807bbb91a75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429622867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3429622867
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2901622435
Short name T506
Test name
Test status
Simulation time 81491383 ps
CPU time 0.76 seconds
Started Aug 11 06:10:09 PM PDT 24
Finished Aug 11 06:10:10 PM PDT 24
Peak memory 200084 kb
Host smart-2c55331f-a22c-4e2a-84f4-8f8d6c996081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901622435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2901622435
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1769241279
Short name T83
Test name
Test status
Simulation time 1479917436 ps
CPU time 5.67 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:56 PM PDT 24
Peak memory 200536 kb
Host smart-9995bb8c-2d3b-41c2-96be-7cd47ed867de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769241279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1769241279
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3316200728
Short name T180
Test name
Test status
Simulation time 189695789 ps
CPU time 1.29 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 200296 kb
Host smart-77bda2bb-3426-4502-b6a3-9e8a0a7bdaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316200728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3316200728
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1297082335
Short name T122
Test name
Test status
Simulation time 251788302 ps
CPU time 1.45 seconds
Started Aug 11 06:09:56 PM PDT 24
Finished Aug 11 06:09:57 PM PDT 24
Peak memory 200424 kb
Host smart-a65f5189-42db-47f1-837f-f71e426d54ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297082335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1297082335
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.1574407243
Short name T256
Test name
Test status
Simulation time 11841662743 ps
CPU time 43 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:43 PM PDT 24
Peak memory 200528 kb
Host smart-828a16b8-693c-4e55-aa5c-fb900bd16b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574407243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.1574407243
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1777072873
Short name T303
Test name
Test status
Simulation time 134651000 ps
CPU time 1.74 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 208660 kb
Host smart-cac0af1a-930c-4930-8298-4b8715b92226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777072873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1777072873
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3533290927
Short name T127
Test name
Test status
Simulation time 133533431 ps
CPU time 1.16 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 200376 kb
Host smart-7526e8da-519c-42eb-aaae-8ad21c384c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533290927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3533290927
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3432400478
Short name T192
Test name
Test status
Simulation time 74704422 ps
CPU time 0.78 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200120 kb
Host smart-a0d74e03-2f14-47d3-999d-f601ea4d2847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432400478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3432400478
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1679956180
Short name T250
Test name
Test status
Simulation time 2157006448 ps
CPU time 8.23 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 217840 kb
Host smart-173a8a6e-5fa1-42bd-ac3f-00726f58dd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679956180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1679956180
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1269337082
Short name T297
Test name
Test status
Simulation time 244166848 ps
CPU time 1.14 seconds
Started Aug 11 06:10:06 PM PDT 24
Finished Aug 11 06:10:12 PM PDT 24
Peak memory 217392 kb
Host smart-cc41e9ec-f30a-4379-9d58-298db838c702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269337082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1269337082
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.404233951
Short name T9
Test name
Test status
Simulation time 2175962004 ps
CPU time 8.49 seconds
Started Aug 11 06:10:07 PM PDT 24
Finished Aug 11 06:10:16 PM PDT 24
Peak memory 200656 kb
Host smart-8cf7e06e-fff3-40cf-9d6a-fff3abcd3f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404233951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.404233951
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1559713466
Short name T462
Test name
Test status
Simulation time 99360751 ps
CPU time 1 seconds
Started Aug 11 06:10:07 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 200364 kb
Host smart-3a0e4467-ac9a-44f6-b10d-ba0653c9643f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559713466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1559713466
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.2659991696
Short name T345
Test name
Test status
Simulation time 111405879 ps
CPU time 1.24 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 200432 kb
Host smart-f8615466-93c5-4c95-b380-79a39eb8a439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659991696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2659991696
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4104199280
Short name T338
Test name
Test status
Simulation time 4119013988 ps
CPU time 14.01 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:18 PM PDT 24
Peak memory 208800 kb
Host smart-562bda39-ba9e-497e-8ca0-0fa8933a1b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104199280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4104199280
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3027086170
Short name T175
Test name
Test status
Simulation time 175359924 ps
CPU time 1.25 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 200248 kb
Host smart-19d3cf60-5bca-4be0-b8bc-f8adbba851ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027086170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3027086170
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1029051437
Short name T522
Test name
Test status
Simulation time 66036450 ps
CPU time 0.78 seconds
Started Aug 11 06:10:22 PM PDT 24
Finished Aug 11 06:10:23 PM PDT 24
Peak memory 200180 kb
Host smart-50a803e7-7b88-4c5e-98a6-1d27a977a7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029051437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1029051437
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2126525569
Short name T51
Test name
Test status
Simulation time 1220463309 ps
CPU time 5.34 seconds
Started Aug 11 06:10:24 PM PDT 24
Finished Aug 11 06:10:30 PM PDT 24
Peak memory 217336 kb
Host smart-4fc86f1d-86a8-44c1-aa70-2c0e75fd0abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126525569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2126525569
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.569661652
Short name T244
Test name
Test status
Simulation time 244162174 ps
CPU time 1.2 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:04 PM PDT 24
Peak memory 217540 kb
Host smart-6b82fe61-e63a-42ed-8eb2-37118fe7b8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569661652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.569661652
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1386360782
Short name T347
Test name
Test status
Simulation time 108498138 ps
CPU time 0.77 seconds
Started Aug 11 06:10:13 PM PDT 24
Finished Aug 11 06:10:14 PM PDT 24
Peak memory 200040 kb
Host smart-d649562b-3f7b-48fc-a15a-87d6c6e31340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386360782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1386360782
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1759119525
Short name T337
Test name
Test status
Simulation time 1816636070 ps
CPU time 7.11 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 200464 kb
Host smart-a6043b10-3910-4d81-a522-52613d68ba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759119525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1759119525
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.958006142
Short name T204
Test name
Test status
Simulation time 155412348 ps
CPU time 1.17 seconds
Started Aug 11 06:10:17 PM PDT 24
Finished Aug 11 06:10:18 PM PDT 24
Peak memory 200348 kb
Host smart-d8c6ec89-4498-4408-b504-7d085acb7506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958006142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.958006142
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.2442571527
Short name T307
Test name
Test status
Simulation time 199454314 ps
CPU time 1.47 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200496 kb
Host smart-df9fb085-ae88-4ad5-b44d-3f0c805777fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442571527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2442571527
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.363755213
Short name T334
Test name
Test status
Simulation time 7202880762 ps
CPU time 31.24 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:33 PM PDT 24
Peak memory 208840 kb
Host smart-70345046-316e-47a0-a090-6435b30b8902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363755213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.363755213
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2282387474
Short name T170
Test name
Test status
Simulation time 366149601 ps
CPU time 2.28 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200248 kb
Host smart-5af9ad08-3415-41af-b770-5afbd53e40af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282387474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2282387474
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3356608971
Short name T126
Test name
Test status
Simulation time 81656674 ps
CPU time 0.84 seconds
Started Aug 11 06:10:20 PM PDT 24
Finished Aug 11 06:10:21 PM PDT 24
Peak memory 200316 kb
Host smart-b90cb389-900e-4b49-90b5-2e24537b32a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356608971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3356608971
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.4173740089
Short name T439
Test name
Test status
Simulation time 66606004 ps
CPU time 0.76 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200120 kb
Host smart-8bb32646-4379-4e3d-bdef-f073124ed575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173740089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.4173740089
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.260267391
Short name T48
Test name
Test status
Simulation time 2343883871 ps
CPU time 9.63 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:10 PM PDT 24
Peak memory 217852 kb
Host smart-71c4bd4e-52c8-459b-b124-70f08068389c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260267391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.260267391
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.528204000
Short name T270
Test name
Test status
Simulation time 244702184 ps
CPU time 1.13 seconds
Started Aug 11 06:10:26 PM PDT 24
Finished Aug 11 06:10:27 PM PDT 24
Peak memory 217496 kb
Host smart-250de73a-2570-4b4a-92e8-b06e9d8ac956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528204000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.528204000
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1894209828
Short name T355
Test name
Test status
Simulation time 84821782 ps
CPU time 0.75 seconds
Started Aug 11 06:10:06 PM PDT 24
Finished Aug 11 06:10:07 PM PDT 24
Peak memory 200164 kb
Host smart-46eed8c5-2f3f-4b46-8694-4dcb1b86cf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894209828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1894209828
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2306942890
Short name T404
Test name
Test status
Simulation time 1351452967 ps
CPU time 5.3 seconds
Started Aug 11 06:10:28 PM PDT 24
Finished Aug 11 06:10:33 PM PDT 24
Peak memory 200444 kb
Host smart-11875f47-26bb-4d45-b3bb-e3213621d2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306942890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2306942890
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3267539306
Short name T245
Test name
Test status
Simulation time 150777048 ps
CPU time 1.14 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:07 PM PDT 24
Peak memory 200368 kb
Host smart-8acf43a4-eb12-4c3e-a434-64b55dc704cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267539306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3267539306
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.4264651809
Short name T457
Test name
Test status
Simulation time 250868705 ps
CPU time 1.72 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 200452 kb
Host smart-ef71a8b1-4884-4247-b8eb-b99f2b786e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264651809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.4264651809
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.4130536551
Short name T290
Test name
Test status
Simulation time 549039007 ps
CPU time 2.86 seconds
Started Aug 11 06:10:06 PM PDT 24
Finished Aug 11 06:10:09 PM PDT 24
Peak memory 200280 kb
Host smart-70f9f633-c5a7-4d82-ad95-7d918064fb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130536551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.4130536551
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3299411377
Short name T459
Test name
Test status
Simulation time 124281177 ps
CPU time 1.07 seconds
Started Aug 11 06:10:28 PM PDT 24
Finished Aug 11 06:10:29 PM PDT 24
Peak memory 200260 kb
Host smart-2bfe66a0-cc09-43b2-9a9c-a0ab0a33805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299411377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3299411377
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2599880180
Short name T155
Test name
Test status
Simulation time 64818715 ps
CPU time 0.77 seconds
Started Aug 11 06:10:11 PM PDT 24
Finished Aug 11 06:10:12 PM PDT 24
Peak memory 200148 kb
Host smart-ecd57af3-0d19-4b80-8518-0f6b4d72421f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599880180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2599880180
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1284138816
Short name T295
Test name
Test status
Simulation time 245070655 ps
CPU time 1.04 seconds
Started Aug 11 06:10:11 PM PDT 24
Finished Aug 11 06:10:12 PM PDT 24
Peak memory 217428 kb
Host smart-904e9b98-62c4-4d50-855d-f8e3bec7e2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284138816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1284138816
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3695627784
Short name T218
Test name
Test status
Simulation time 116025927 ps
CPU time 0.79 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 200128 kb
Host smart-7939ee76-9abb-49b1-944c-2740d512a43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695627784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3695627784
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2784634026
Short name T100
Test name
Test status
Simulation time 1984828343 ps
CPU time 8.57 seconds
Started Aug 11 06:10:11 PM PDT 24
Finished Aug 11 06:10:19 PM PDT 24
Peak memory 200404 kb
Host smart-6d1dc367-8848-4ae5-8d24-e6ac6c924b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784634026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2784634026
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.630344433
Short name T411
Test name
Test status
Simulation time 145494964 ps
CPU time 1.13 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 200308 kb
Host smart-90bba59e-bd1f-440a-bc42-94988084d851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630344433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.630344433
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2528946156
Short name T415
Test name
Test status
Simulation time 119864032 ps
CPU time 1.29 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:07 PM PDT 24
Peak memory 200480 kb
Host smart-462bb1a3-7712-4aec-95d0-d246ce79100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528946156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2528946156
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3109731242
Short name T450
Test name
Test status
Simulation time 2458185151 ps
CPU time 8.33 seconds
Started Aug 11 06:10:10 PM PDT 24
Finished Aug 11 06:10:23 PM PDT 24
Peak memory 200520 kb
Host smart-35c3f3c9-2b09-4aa0-9297-2d71f0b96751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109731242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3109731242
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4228908186
Short name T267
Test name
Test status
Simulation time 263989229 ps
CPU time 1.46 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 200300 kb
Host smart-d433589a-aec4-4e35-8945-044e02d40c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228908186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4228908186
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3132939502
Short name T311
Test name
Test status
Simulation time 76990254 ps
CPU time 0.84 seconds
Started Aug 11 06:10:23 PM PDT 24
Finished Aug 11 06:10:24 PM PDT 24
Peak memory 200120 kb
Host smart-81532151-a9aa-4ea7-a30a-18cb3b1da804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132939502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3132939502
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.852031637
Short name T31
Test name
Test status
Simulation time 1886919791 ps
CPU time 6.86 seconds
Started Aug 11 06:10:09 PM PDT 24
Finished Aug 11 06:10:16 PM PDT 24
Peak memory 217764 kb
Host smart-d34530c6-54d5-4bda-920e-cb93d36291cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852031637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.852031637
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.122883389
Short name T525
Test name
Test status
Simulation time 244657624 ps
CPU time 1.16 seconds
Started Aug 11 06:10:22 PM PDT 24
Finished Aug 11 06:10:24 PM PDT 24
Peak memory 217368 kb
Host smart-c2383882-b892-43cd-885e-4f707a1ef201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122883389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.122883389
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2591608912
Short name T520
Test name
Test status
Simulation time 146913060 ps
CPU time 0.82 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:41 PM PDT 24
Peak memory 200036 kb
Host smart-b91df5ef-faeb-42a6-bd0e-985293b5080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591608912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2591608912
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4285733017
Short name T328
Test name
Test status
Simulation time 1134450264 ps
CPU time 4.81 seconds
Started Aug 11 06:10:22 PM PDT 24
Finished Aug 11 06:10:27 PM PDT 24
Peak memory 200536 kb
Host smart-26acc2cc-1e47-4bdc-a922-0a59af9f1913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285733017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4285733017
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2946308687
Short name T479
Test name
Test status
Simulation time 141819555 ps
CPU time 1.08 seconds
Started Aug 11 06:10:20 PM PDT 24
Finished Aug 11 06:10:21 PM PDT 24
Peak memory 200192 kb
Host smart-06a43346-298b-4637-8eda-00c05c2e552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946308687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2946308687
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.444265667
Short name T240
Test name
Test status
Simulation time 125739330 ps
CPU time 1.25 seconds
Started Aug 11 06:10:25 PM PDT 24
Finished Aug 11 06:10:26 PM PDT 24
Peak memory 200464 kb
Host smart-5e68622a-c9ec-473b-b823-cb7420e3e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444265667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.444265667
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3562492848
Short name T393
Test name
Test status
Simulation time 14135302197 ps
CPU time 45.78 seconds
Started Aug 11 06:10:17 PM PDT 24
Finished Aug 11 06:11:03 PM PDT 24
Peak memory 200648 kb
Host smart-b253c717-5a81-4bf6-80ef-523b61525703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562492848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3562492848
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.4144653855
Short name T490
Test name
Test status
Simulation time 278459116 ps
CPU time 1.92 seconds
Started Aug 11 06:10:15 PM PDT 24
Finished Aug 11 06:10:18 PM PDT 24
Peak memory 200188 kb
Host smart-e3e978da-3a64-4144-814f-add5112fe721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144653855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4144653855
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3915171655
Short name T530
Test name
Test status
Simulation time 98407055 ps
CPU time 0.91 seconds
Started Aug 11 06:10:11 PM PDT 24
Finished Aug 11 06:10:12 PM PDT 24
Peak memory 200336 kb
Host smart-13d06a0f-9b1b-4990-a84a-85562237dd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915171655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3915171655
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3938984665
Short name T165
Test name
Test status
Simulation time 70232174 ps
CPU time 0.74 seconds
Started Aug 11 06:10:15 PM PDT 24
Finished Aug 11 06:10:16 PM PDT 24
Peak memory 200164 kb
Host smart-7b90a79d-c687-4ab0-b52d-7ea9dffc6def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938984665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3938984665
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.4033928751
Short name T358
Test name
Test status
Simulation time 2163470071 ps
CPU time 8.69 seconds
Started Aug 11 06:10:21 PM PDT 24
Finished Aug 11 06:10:30 PM PDT 24
Peak memory 221800 kb
Host smart-67cac506-4a81-4546-8363-5adca2cd89b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033928751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4033928751
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1806878565
Short name T133
Test name
Test status
Simulation time 243573834 ps
CPU time 1.12 seconds
Started Aug 11 06:10:22 PM PDT 24
Finished Aug 11 06:10:23 PM PDT 24
Peak memory 217536 kb
Host smart-8b0313bb-0dad-45ac-bb67-7fae374efc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806878565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1806878565
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.4208354111
Short name T11
Test name
Test status
Simulation time 154115906 ps
CPU time 0.82 seconds
Started Aug 11 06:10:16 PM PDT 24
Finished Aug 11 06:10:17 PM PDT 24
Peak memory 200036 kb
Host smart-89f3503a-f9ee-4aa7-b1bd-78092e59f43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208354111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.4208354111
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2546615495
Short name T424
Test name
Test status
Simulation time 860706146 ps
CPU time 4.46 seconds
Started Aug 11 06:10:10 PM PDT 24
Finished Aug 11 06:10:14 PM PDT 24
Peak memory 200612 kb
Host smart-7b2d8b11-f6a2-4691-a868-cdb1dd727307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546615495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2546615495
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3039036736
Short name T322
Test name
Test status
Simulation time 184817253 ps
CPU time 1.24 seconds
Started Aug 11 06:10:12 PM PDT 24
Finished Aug 11 06:10:13 PM PDT 24
Peak memory 200356 kb
Host smart-e8e66b29-ca2d-4709-8b4d-7f92c88e8bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039036736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3039036736
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4056022166
Short name T190
Test name
Test status
Simulation time 121079763 ps
CPU time 1.29 seconds
Started Aug 11 06:10:25 PM PDT 24
Finished Aug 11 06:10:27 PM PDT 24
Peak memory 200472 kb
Host smart-d94ac603-c20a-4c1c-a661-fe699af09d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056022166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4056022166
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2364738003
Short name T220
Test name
Test status
Simulation time 1480041956 ps
CPU time 6.81 seconds
Started Aug 11 06:10:21 PM PDT 24
Finished Aug 11 06:10:28 PM PDT 24
Peak memory 208724 kb
Host smart-d1358b5e-5195-4ad4-b7f2-81c238b8acfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364738003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2364738003
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.405579640
Short name T346
Test name
Test status
Simulation time 501987155 ps
CPU time 2.54 seconds
Started Aug 11 06:10:15 PM PDT 24
Finished Aug 11 06:10:18 PM PDT 24
Peak memory 200288 kb
Host smart-941b8667-e615-44b6-aed4-73f9ea0c0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405579640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.405579640
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2756995490
Short name T159
Test name
Test status
Simulation time 67611404 ps
CPU time 0.76 seconds
Started Aug 11 06:10:14 PM PDT 24
Finished Aug 11 06:10:15 PM PDT 24
Peak memory 200176 kb
Host smart-f05743c3-d46c-482a-b936-23adbadaa68e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756995490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2756995490
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2777298714
Short name T392
Test name
Test status
Simulation time 2353841534 ps
CPU time 7.69 seconds
Started Aug 11 06:10:21 PM PDT 24
Finished Aug 11 06:10:29 PM PDT 24
Peak memory 217624 kb
Host smart-3a1522cf-34ce-4dbf-9d6f-d6bfec3859f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777298714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2777298714
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1274481745
Short name T288
Test name
Test status
Simulation time 243832443 ps
CPU time 1.15 seconds
Started Aug 11 06:10:14 PM PDT 24
Finished Aug 11 06:10:15 PM PDT 24
Peak memory 217668 kb
Host smart-be55d2db-2858-45f7-a56f-257fe76bf52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274481745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1274481745
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3183484165
Short name T285
Test name
Test status
Simulation time 98207651 ps
CPU time 0.78 seconds
Started Aug 11 06:10:21 PM PDT 24
Finished Aug 11 06:10:22 PM PDT 24
Peak memory 200124 kb
Host smart-d13f558b-53cb-4a3d-b24e-0298d2fed1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183484165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3183484165
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.135585875
Short name T437
Test name
Test status
Simulation time 1574339102 ps
CPU time 6.6 seconds
Started Aug 11 06:10:15 PM PDT 24
Finished Aug 11 06:10:21 PM PDT 24
Peak memory 200496 kb
Host smart-b5a512fd-ca85-48dc-992c-960741bea453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135585875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.135585875
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.654751546
Short name T275
Test name
Test status
Simulation time 100999741 ps
CPU time 0.95 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:37 PM PDT 24
Peak memory 200240 kb
Host smart-3edf5b26-37a3-4130-a789-49219ff141ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654751546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.654751546
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2942407244
Short name T478
Test name
Test status
Simulation time 125909899 ps
CPU time 1.15 seconds
Started Aug 11 06:10:21 PM PDT 24
Finished Aug 11 06:10:23 PM PDT 24
Peak memory 200328 kb
Host smart-4b88e475-f6c0-4e76-a5e1-c59b1f448009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942407244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2942407244
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2479337427
Short name T361
Test name
Test status
Simulation time 311705001 ps
CPU time 1.77 seconds
Started Aug 11 06:10:35 PM PDT 24
Finished Aug 11 06:10:37 PM PDT 24
Peak memory 200456 kb
Host smart-4d38bc6b-8e8a-4fd1-a0f7-fe75c1072e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479337427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2479337427
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.495564513
Short name T429
Test name
Test status
Simulation time 310580387 ps
CPU time 2 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:38 PM PDT 24
Peak memory 208440 kb
Host smart-97b498f8-ea6a-42e6-ba44-efc1b9da6d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495564513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.495564513
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2896800658
Short name T489
Test name
Test status
Simulation time 177194185 ps
CPU time 1.24 seconds
Started Aug 11 06:10:14 PM PDT 24
Finished Aug 11 06:10:16 PM PDT 24
Peak memory 200244 kb
Host smart-cde666f7-c950-460d-9573-c825b5ccb4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896800658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2896800658
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3526139079
Short name T416
Test name
Test status
Simulation time 1223120577 ps
CPU time 5.94 seconds
Started Aug 11 06:10:23 PM PDT 24
Finished Aug 11 06:10:29 PM PDT 24
Peak memory 217724 kb
Host smart-0abcb339-5e0c-455a-8c74-eecdcb00ad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526139079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3526139079
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1576441741
Short name T460
Test name
Test status
Simulation time 244948573 ps
CPU time 1.08 seconds
Started Aug 11 06:10:33 PM PDT 24
Finished Aug 11 06:10:34 PM PDT 24
Peak memory 217528 kb
Host smart-659bc9bc-cf5d-47e2-8819-2497d21f4aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576441741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1576441741
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1820183541
Short name T376
Test name
Test status
Simulation time 191582079 ps
CPU time 0.9 seconds
Started Aug 11 06:10:16 PM PDT 24
Finished Aug 11 06:10:17 PM PDT 24
Peak memory 200156 kb
Host smart-461eff82-352b-4d05-b520-dfaae38dd195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820183541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1820183541
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2438770865
Short name T326
Test name
Test status
Simulation time 1825218490 ps
CPU time 6.33 seconds
Started Aug 11 06:10:13 PM PDT 24
Finished Aug 11 06:10:20 PM PDT 24
Peak memory 200536 kb
Host smart-33b8b1d8-2929-4f29-b5c2-1dacafd1a7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438770865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2438770865
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1936798113
Short name T363
Test name
Test status
Simulation time 151744685 ps
CPU time 1.13 seconds
Started Aug 11 06:10:29 PM PDT 24
Finished Aug 11 06:10:30 PM PDT 24
Peak memory 200320 kb
Host smart-df0212c1-a7e2-4d97-b8b9-b082d39efe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936798113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1936798113
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3113640905
Short name T70
Test name
Test status
Simulation time 193610543 ps
CPU time 1.5 seconds
Started Aug 11 06:10:29 PM PDT 24
Finished Aug 11 06:10:31 PM PDT 24
Peak memory 200496 kb
Host smart-4edd78cb-c88d-4d9c-86f4-fd7cacc9d8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113640905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3113640905
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3124960031
Short name T299
Test name
Test status
Simulation time 5160901446 ps
CPU time 24.74 seconds
Started Aug 11 06:10:13 PM PDT 24
Finished Aug 11 06:10:38 PM PDT 24
Peak memory 209792 kb
Host smart-a909e8a8-fb35-4c7a-b69d-5199469a4362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124960031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3124960031
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.4066278523
Short name T2
Test name
Test status
Simulation time 143566100 ps
CPU time 1.77 seconds
Started Aug 11 06:10:29 PM PDT 24
Finished Aug 11 06:10:31 PM PDT 24
Peak memory 200076 kb
Host smart-299e9f62-136c-4e23-830c-1e9887fc6c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066278523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4066278523
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4106131387
Short name T216
Test name
Test status
Simulation time 243403748 ps
CPU time 1.58 seconds
Started Aug 11 06:10:18 PM PDT 24
Finished Aug 11 06:10:20 PM PDT 24
Peak memory 200496 kb
Host smart-7bcf3196-de31-41ac-8e97-dcd45d1ea4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106131387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4106131387
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2729951069
Short name T426
Test name
Test status
Simulation time 64188548 ps
CPU time 0.79 seconds
Started Aug 11 06:10:26 PM PDT 24
Finished Aug 11 06:10:27 PM PDT 24
Peak memory 200048 kb
Host smart-9a47f9b1-4ba5-4b15-aa67-baeb6a6da1d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729951069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2729951069
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.700919056
Short name T521
Test name
Test status
Simulation time 2357458731 ps
CPU time 8.73 seconds
Started Aug 11 06:10:15 PM PDT 24
Finished Aug 11 06:10:23 PM PDT 24
Peak memory 217948 kb
Host smart-aaf694d6-6f8a-4199-a9f3-a193106c7fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700919056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.700919056
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1341732805
Short name T173
Test name
Test status
Simulation time 243500512 ps
CPU time 1.17 seconds
Started Aug 11 06:10:16 PM PDT 24
Finished Aug 11 06:10:17 PM PDT 24
Peak memory 217464 kb
Host smart-3e938b63-85da-4877-8ab4-5d23243071ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341732805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1341732805
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.402191216
Short name T343
Test name
Test status
Simulation time 115038157 ps
CPU time 0.79 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:47 PM PDT 24
Peak memory 200148 kb
Host smart-4b72be17-e24e-4978-8e2c-a07a8e5327d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402191216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.402191216
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3184598515
Short name T385
Test name
Test status
Simulation time 926504789 ps
CPU time 4.48 seconds
Started Aug 11 06:10:31 PM PDT 24
Finished Aug 11 06:10:35 PM PDT 24
Peak memory 200536 kb
Host smart-637a6bb6-4787-43fe-bc1e-fb8f163f86b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184598515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3184598515
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2028563317
Short name T154
Test name
Test status
Simulation time 98941162 ps
CPU time 0.98 seconds
Started Aug 11 06:10:14 PM PDT 24
Finished Aug 11 06:10:15 PM PDT 24
Peak memory 200248 kb
Host smart-a1875b2f-2318-4e23-a4b3-202aad7c384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028563317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2028563317
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2522643567
Short name T213
Test name
Test status
Simulation time 251534705 ps
CPU time 1.54 seconds
Started Aug 11 06:10:23 PM PDT 24
Finished Aug 11 06:10:25 PM PDT 24
Peak memory 200424 kb
Host smart-219dd277-d7c6-4ad3-b881-af214b16f979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522643567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2522643567
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1099922527
Short name T356
Test name
Test status
Simulation time 6938369541 ps
CPU time 24.63 seconds
Started Aug 11 06:10:25 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200800 kb
Host smart-a12ca1bf-9c8b-47dd-ab39-ca0d1b55d7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099922527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1099922527
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2465106222
Short name T431
Test name
Test status
Simulation time 122832016 ps
CPU time 1.53 seconds
Started Aug 11 06:10:19 PM PDT 24
Finished Aug 11 06:10:21 PM PDT 24
Peak memory 208500 kb
Host smart-2a12b40c-4dac-4ce1-849d-1e6a069b16fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465106222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2465106222
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.677494382
Short name T349
Test name
Test status
Simulation time 125957647 ps
CPU time 0.99 seconds
Started Aug 11 06:10:15 PM PDT 24
Finished Aug 11 06:10:16 PM PDT 24
Peak memory 200212 kb
Host smart-14761e25-ac6b-49b2-b27a-3fda52430534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677494382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.677494382
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1493051176
Short name T131
Test name
Test status
Simulation time 70398901 ps
CPU time 0.76 seconds
Started Aug 11 06:10:34 PM PDT 24
Finished Aug 11 06:10:35 PM PDT 24
Peak memory 200176 kb
Host smart-03b2d81a-e145-48f9-ba0f-56f6358e3d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493051176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1493051176
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1282342332
Short name T46
Test name
Test status
Simulation time 1893417142 ps
CPU time 6.57 seconds
Started Aug 11 06:10:34 PM PDT 24
Finished Aug 11 06:10:41 PM PDT 24
Peak memory 217720 kb
Host smart-6bb1e788-e592-4ae3-b4be-3c6e1280eb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282342332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1282342332
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.47798819
Short name T276
Test name
Test status
Simulation time 245667724 ps
CPU time 1.03 seconds
Started Aug 11 06:10:30 PM PDT 24
Finished Aug 11 06:10:31 PM PDT 24
Peak memory 217544 kb
Host smart-2525a047-2465-49d9-a6af-27fd7c6396e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47798819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.47798819
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1334392467
Short name T265
Test name
Test status
Simulation time 99453418 ps
CPU time 0.78 seconds
Started Aug 11 06:10:35 PM PDT 24
Finished Aug 11 06:10:36 PM PDT 24
Peak memory 200144 kb
Host smart-524013b4-c923-450b-8f7a-d54c405b5a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334392467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1334392467
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3591388835
Short name T534
Test name
Test status
Simulation time 835581632 ps
CPU time 4.45 seconds
Started Aug 11 06:10:34 PM PDT 24
Finished Aug 11 06:10:39 PM PDT 24
Peak memory 200716 kb
Host smart-5ad8b59e-c90b-46a9-9867-ecda7dc8293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591388835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3591388835
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3472034165
Short name T512
Test name
Test status
Simulation time 194482517 ps
CPU time 1.32 seconds
Started Aug 11 06:10:32 PM PDT 24
Finished Aug 11 06:10:34 PM PDT 24
Peak memory 200244 kb
Host smart-65bd25dd-4a3d-478b-a1fd-c988a36905a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472034165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3472034165
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1807498541
Short name T529
Test name
Test status
Simulation time 115772393 ps
CPU time 1.17 seconds
Started Aug 11 06:10:15 PM PDT 24
Finished Aug 11 06:10:17 PM PDT 24
Peak memory 200348 kb
Host smart-00994f94-1446-4ab0-966a-1bf87388e7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807498541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1807498541
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3085312816
Short name T443
Test name
Test status
Simulation time 130695717 ps
CPU time 0.97 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:10:44 PM PDT 24
Peak memory 200088 kb
Host smart-35438c50-2199-447f-a38c-192d99ee92bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085312816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3085312816
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.651516514
Short name T183
Test name
Test status
Simulation time 245156004 ps
CPU time 1.86 seconds
Started Aug 11 06:10:38 PM PDT 24
Finished Aug 11 06:10:40 PM PDT 24
Peak memory 200268 kb
Host smart-66b4e979-559a-481b-bb88-e39b03cc195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651516514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.651516514
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4244502041
Short name T263
Test name
Test status
Simulation time 133115400 ps
CPU time 1.08 seconds
Started Aug 11 06:10:31 PM PDT 24
Finished Aug 11 06:10:33 PM PDT 24
Peak memory 200340 kb
Host smart-c58bd3a8-ee76-4557-ae2b-6462eb6b22ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244502041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4244502041
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.276264167
Short name T259
Test name
Test status
Simulation time 77739944 ps
CPU time 0.88 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 200124 kb
Host smart-ef98f232-78d4-471a-9170-13b7c76f8bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276264167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.276264167
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2943054578
Short name T47
Test name
Test status
Simulation time 2360301946 ps
CPU time 9.03 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 217788 kb
Host smart-b6f71bc9-c4ad-4929-8611-aeadf89d1a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943054578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2943054578
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.555958136
Short name T75
Test name
Test status
Simulation time 245112041 ps
CPU time 1.03 seconds
Started Aug 11 06:09:58 PM PDT 24
Finished Aug 11 06:09:59 PM PDT 24
Peak memory 217580 kb
Host smart-68c94d8c-f0fe-49a1-a417-7835e7f520d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555958136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.555958136
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.4143712310
Short name T365
Test name
Test status
Simulation time 81240076 ps
CPU time 0.78 seconds
Started Aug 11 06:09:53 PM PDT 24
Finished Aug 11 06:09:54 PM PDT 24
Peak memory 200132 kb
Host smart-66a50787-c8e8-40e4-8583-c80938d83094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143712310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4143712310
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3147141735
Short name T493
Test name
Test status
Simulation time 1539253767 ps
CPU time 6.65 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 200468 kb
Host smart-c1549cce-a234-49af-bd80-2c83f7eb88ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147141735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3147141735
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2790257228
Short name T77
Test name
Test status
Simulation time 8286347180 ps
CPU time 13.7 seconds
Started Aug 11 06:09:56 PM PDT 24
Finished Aug 11 06:10:09 PM PDT 24
Peak memory 217600 kb
Host smart-03b1ca61-d764-4597-b008-ff2ac6acfe84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790257228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2790257228
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.265675157
Short name T168
Test name
Test status
Simulation time 154991068 ps
CPU time 1.08 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 200248 kb
Host smart-46042946-015b-48f5-8690-824ab54b15b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265675157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.265675157
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1465557596
Short name T519
Test name
Test status
Simulation time 205357170 ps
CPU time 1.41 seconds
Started Aug 11 06:09:58 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 200520 kb
Host smart-639df3e8-acab-4dfe-98d9-5d15a1fb67f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465557596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1465557596
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2034956559
Short name T389
Test name
Test status
Simulation time 10679332655 ps
CPU time 39.42 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:10:31 PM PDT 24
Peak memory 208824 kb
Host smart-b83f4048-2569-4810-9e13-f4b7ec7ba789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034956559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2034956559
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.4106020380
Short name T210
Test name
Test status
Simulation time 126439884 ps
CPU time 1.62 seconds
Started Aug 11 06:09:57 PM PDT 24
Finished Aug 11 06:09:59 PM PDT 24
Peak memory 200188 kb
Host smart-df2a1716-c5ec-4c62-8e32-3400e96d7b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106020380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.4106020380
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1588608403
Short name T36
Test name
Test status
Simulation time 127066758 ps
CPU time 1.23 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 200536 kb
Host smart-c4564758-a123-44b7-af4c-ff78f4481815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588608403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1588608403
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1428843343
Short name T189
Test name
Test status
Simulation time 79902915 ps
CPU time 0.81 seconds
Started Aug 11 06:10:31 PM PDT 24
Finished Aug 11 06:10:32 PM PDT 24
Peak memory 200148 kb
Host smart-cd3dc967-8609-433a-b254-a3d9cf4b9a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428843343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1428843343
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1346000645
Short name T342
Test name
Test status
Simulation time 1223784144 ps
CPU time 5.72 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 221676 kb
Host smart-3b1ddee9-45dd-4b4b-91bb-6647292ca5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346000645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1346000645
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1012185443
Short name T279
Test name
Test status
Simulation time 244148721 ps
CPU time 1.07 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 217500 kb
Host smart-cfba0df5-47e4-4488-a3e9-1c56b65acc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012185443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1012185443
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.646763589
Short name T476
Test name
Test status
Simulation time 161105764 ps
CPU time 0.85 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:37 PM PDT 24
Peak memory 200100 kb
Host smart-7033acc9-14ef-4c72-a80a-34ba3a719fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646763589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.646763589
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2440243440
Short name T228
Test name
Test status
Simulation time 884030521 ps
CPU time 4.03 seconds
Started Aug 11 06:10:37 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 200500 kb
Host smart-7e7f8556-c6f3-48ee-9be8-7cd1d6bed444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440243440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2440243440
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.540846251
Short name T196
Test name
Test status
Simulation time 105079426 ps
CPU time 0.94 seconds
Started Aug 11 06:10:30 PM PDT 24
Finished Aug 11 06:10:31 PM PDT 24
Peak memory 200296 kb
Host smart-9c3bfe70-7602-4a7a-8ac9-364d886c5428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540846251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.540846251
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.3125034656
Short name T335
Test name
Test status
Simulation time 111284793 ps
CPU time 1.18 seconds
Started Aug 11 06:10:29 PM PDT 24
Finished Aug 11 06:10:30 PM PDT 24
Peak memory 200472 kb
Host smart-4753b7ae-3b6e-41ae-876d-1d9c6fb0cb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125034656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3125034656
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2644548604
Short name T3
Test name
Test status
Simulation time 4992118871 ps
CPU time 21.51 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:11:04 PM PDT 24
Peak memory 200692 kb
Host smart-baf46113-a887-4e1d-a588-0f1bcc2d42f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644548604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2644548604
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.1108638404
Short name T532
Test name
Test status
Simulation time 150314006 ps
CPU time 1.93 seconds
Started Aug 11 06:10:35 PM PDT 24
Finished Aug 11 06:10:37 PM PDT 24
Peak memory 200188 kb
Host smart-ca1cc95e-3cf5-41c6-a448-2ece53dd8c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108638404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1108638404
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1506986847
Short name T430
Test name
Test status
Simulation time 68787069 ps
CPU time 0.74 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:41 PM PDT 24
Peak memory 200360 kb
Host smart-2aa26b25-51f6-426c-a67c-615ccd52b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506986847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1506986847
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.4003286809
Short name T371
Test name
Test status
Simulation time 60662434 ps
CPU time 0.74 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:37 PM PDT 24
Peak memory 199936 kb
Host smart-69778ac2-49b4-43be-9e6f-62d9f423b923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003286809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.4003286809
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.858992809
Short name T388
Test name
Test status
Simulation time 1894636920 ps
CPU time 7.73 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:54 PM PDT 24
Peak memory 217460 kb
Host smart-b4a6463e-fede-4732-b3e6-32b1fc92d2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858992809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.858992809
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3298952783
Short name T197
Test name
Test status
Simulation time 244375064 ps
CPU time 1.14 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 217500 kb
Host smart-e49f479d-c625-46cd-a2c1-2eb947ece3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298952783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3298952783
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2412135796
Short name T233
Test name
Test status
Simulation time 219158295 ps
CPU time 0.88 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:10:44 PM PDT 24
Peak memory 200144 kb
Host smart-bec798e8-270f-4dce-9c77-eafd3a69d381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412135796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2412135796
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.947434392
Short name T351
Test name
Test status
Simulation time 653293572 ps
CPU time 3.54 seconds
Started Aug 11 06:10:31 PM PDT 24
Finished Aug 11 06:10:35 PM PDT 24
Peak memory 200612 kb
Host smart-f1d4f259-7e88-420f-8952-51bdccc77616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947434392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.947434392
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3000430647
Short name T162
Test name
Test status
Simulation time 103190693 ps
CPU time 1 seconds
Started Aug 11 06:10:32 PM PDT 24
Finished Aug 11 06:10:33 PM PDT 24
Peak memory 200368 kb
Host smart-476fc4b2-0849-4ee5-9718-7e7a70a72908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000430647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3000430647
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.4084343985
Short name T153
Test name
Test status
Simulation time 121655249 ps
CPU time 1.25 seconds
Started Aug 11 06:10:38 PM PDT 24
Finished Aug 11 06:10:39 PM PDT 24
Peak memory 200508 kb
Host smart-ca821d6c-73ed-489a-931d-05d980e9f949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084343985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.4084343985
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1649670287
Short name T410
Test name
Test status
Simulation time 1976667906 ps
CPU time 9.97 seconds
Started Aug 11 06:10:34 PM PDT 24
Finished Aug 11 06:10:44 PM PDT 24
Peak memory 209944 kb
Host smart-a384b6c9-6bc9-4f87-8457-3f987a9ea0ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649670287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1649670287
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2879255596
Short name T38
Test name
Test status
Simulation time 143107792 ps
CPU time 1.78 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:10:45 PM PDT 24
Peak memory 200280 kb
Host smart-fef1a5cb-9c6c-4afb-9ae9-fab4c82f1230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879255596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2879255596
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1954254701
Short name T252
Test name
Test status
Simulation time 93787702 ps
CPU time 0.93 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:10:46 PM PDT 24
Peak memory 200340 kb
Host smart-bfb0f802-b6fc-49a0-8703-31db1839f083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954254701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1954254701
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3549487787
Short name T247
Test name
Test status
Simulation time 88276834 ps
CPU time 0.81 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:43 PM PDT 24
Peak memory 200164 kb
Host smart-c7bd42eb-eca9-4c63-bfe9-eaeaca1136fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549487787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3549487787
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.556060710
Short name T27
Test name
Test status
Simulation time 1223462426 ps
CPU time 5.82 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 217528 kb
Host smart-81823e30-2153-4ca5-a63b-76d71697b048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556060710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.556060710
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1215242234
Short name T221
Test name
Test status
Simulation time 246817368 ps
CPU time 1.08 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 217540 kb
Host smart-b6c37a02-aeee-45ce-95d6-5e722f4928dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215242234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1215242234
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4153311309
Short name T212
Test name
Test status
Simulation time 103831271 ps
CPU time 0.78 seconds
Started Aug 11 06:10:32 PM PDT 24
Finished Aug 11 06:10:33 PM PDT 24
Peak memory 200048 kb
Host smart-12b9eae4-2acb-4570-807f-1622a1dc2fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153311309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4153311309
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.866478587
Short name T161
Test name
Test status
Simulation time 889168532 ps
CPU time 4.8 seconds
Started Aug 11 06:10:25 PM PDT 24
Finished Aug 11 06:10:30 PM PDT 24
Peak memory 200744 kb
Host smart-7129704e-2cd5-45dc-ae2b-8eafc66090bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866478587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.866478587
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3716070497
Short name T156
Test name
Test status
Simulation time 140747506 ps
CPU time 1.07 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200364 kb
Host smart-31df0b31-10d3-4a80-a443-599ef86b9e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716070497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3716070497
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2218138489
Short name T260
Test name
Test status
Simulation time 113400487 ps
CPU time 1.15 seconds
Started Aug 11 06:10:33 PM PDT 24
Finished Aug 11 06:10:34 PM PDT 24
Peak memory 200404 kb
Host smart-e9e92f9b-5ebd-4767-acde-fc4fa9dcf8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218138489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2218138489
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1929268677
Short name T394
Test name
Test status
Simulation time 4431817165 ps
CPU time 20.12 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 208692 kb
Host smart-b28af8e4-fda0-47bf-a75f-6f9a7792c3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929268677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1929268677
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.3674166878
Short name T286
Test name
Test status
Simulation time 413567728 ps
CPU time 2.44 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:45 PM PDT 24
Peak memory 208500 kb
Host smart-b0c65266-0b4b-4792-93d7-b1f8d7e9467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674166878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3674166878
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2240225043
Short name T185
Test name
Test status
Simulation time 126197777 ps
CPU time 1.06 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:38 PM PDT 24
Peak memory 200216 kb
Host smart-298e4b2b-4232-48c8-a5da-ed79f7ac83cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240225043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2240225043
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.4161458543
Short name T399
Test name
Test status
Simulation time 80866432 ps
CPU time 0.81 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200120 kb
Host smart-fba80b5e-1da4-42fb-ab9f-3887a4331f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161458543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.4161458543
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1886936438
Short name T306
Test name
Test status
Simulation time 1890036806 ps
CPU time 7.39 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 217504 kb
Host smart-522571bd-d558-4b2d-845d-2784a59ef523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886936438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1886936438
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2023495971
Short name T172
Test name
Test status
Simulation time 243829527 ps
CPU time 1.12 seconds
Started Aug 11 06:10:39 PM PDT 24
Finished Aug 11 06:10:40 PM PDT 24
Peak memory 217600 kb
Host smart-b40276da-49c4-40c3-a0a6-585cad99e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023495971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2023495971
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1642232292
Short name T455
Test name
Test status
Simulation time 143749721 ps
CPU time 0.84 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:45 PM PDT 24
Peak memory 200096 kb
Host smart-aae310fc-03ee-4150-8df1-03cb05af6e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642232292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1642232292
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1849602655
Short name T274
Test name
Test status
Simulation time 1727595065 ps
CPU time 6.24 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:43 PM PDT 24
Peak memory 200560 kb
Host smart-4de2c208-58fa-473f-9edd-5184df64558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849602655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1849602655
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.302641034
Short name T200
Test name
Test status
Simulation time 152027736 ps
CPU time 1.17 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:45 PM PDT 24
Peak memory 200308 kb
Host smart-45ba7bd1-ae54-4cb4-a69b-87a93c084bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302641034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.302641034
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2488411000
Short name T374
Test name
Test status
Simulation time 247031300 ps
CPU time 1.45 seconds
Started Aug 11 06:10:31 PM PDT 24
Finished Aug 11 06:10:33 PM PDT 24
Peak memory 200548 kb
Host smart-91bf2e2d-31c5-4bef-9f69-4d7de21796b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488411000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2488411000
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2816401299
Short name T214
Test name
Test status
Simulation time 12670920290 ps
CPU time 45.43 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:11:31 PM PDT 24
Peak memory 208752 kb
Host smart-f3f04a4f-050e-40c7-9e80-3e20bf7a658c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816401299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2816401299
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3514177592
Short name T62
Test name
Test status
Simulation time 137238201 ps
CPU time 1.67 seconds
Started Aug 11 06:10:37 PM PDT 24
Finished Aug 11 06:10:39 PM PDT 24
Peak memory 200264 kb
Host smart-807cca3f-27d7-419b-8dc2-b67d51d4b0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514177592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3514177592
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3712300716
Short name T226
Test name
Test status
Simulation time 230317727 ps
CPU time 1.43 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200480 kb
Host smart-d59d45ed-912e-4278-bfcb-581cc56e6f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712300716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3712300716
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3166662277
Short name T298
Test name
Test status
Simulation time 85246655 ps
CPU time 0.86 seconds
Started Aug 11 06:10:39 PM PDT 24
Finished Aug 11 06:10:40 PM PDT 24
Peak memory 200020 kb
Host smart-ca8fa96e-ec94-4424-a840-aa9f3397d43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166662277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3166662277
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.380398396
Short name T289
Test name
Test status
Simulation time 2335381872 ps
CPU time 8.79 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:10:51 PM PDT 24
Peak memory 221824 kb
Host smart-05430fe6-f238-48d9-965f-aebec1644026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380398396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.380398396
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3087634968
Short name T234
Test name
Test status
Simulation time 244451881 ps
CPU time 1.05 seconds
Started Aug 11 06:10:35 PM PDT 24
Finished Aug 11 06:10:36 PM PDT 24
Peak memory 217472 kb
Host smart-e53ad754-e02b-4dc2-bb53-b77f1dc9472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087634968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3087634968
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2699443321
Short name T533
Test name
Test status
Simulation time 227941607 ps
CPU time 1 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200152 kb
Host smart-b806f319-5403-45e7-a277-a9e92a21fe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699443321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2699443321
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3591256800
Short name T104
Test name
Test status
Simulation time 1398006743 ps
CPU time 4.75 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200456 kb
Host smart-562d7434-ce24-43b6-b86c-aa6d2dc7ec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591256800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3591256800
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.274223170
Short name T381
Test name
Test status
Simulation time 142494396 ps
CPU time 1.03 seconds
Started Aug 11 06:10:38 PM PDT 24
Finished Aug 11 06:10:39 PM PDT 24
Peak memory 200288 kb
Host smart-bf05cd13-908c-4a79-a12f-2d8081e2fcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274223170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.274223170
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1453468339
Short name T206
Test name
Test status
Simulation time 262452841 ps
CPU time 1.52 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:10:44 PM PDT 24
Peak memory 200344 kb
Host smart-a2ce56a5-dc52-4bce-8c91-3bd9570cab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453468339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1453468339
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2298057426
Short name T466
Test name
Test status
Simulation time 4699903006 ps
CPU time 21.52 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:11:05 PM PDT 24
Peak memory 200820 kb
Host smart-81a9fcc4-931b-4a63-85f1-96f9f5a935cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298057426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2298057426
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2033862980
Short name T59
Test name
Test status
Simulation time 373910289 ps
CPU time 2.39 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:47 PM PDT 24
Peak memory 200268 kb
Host smart-c46eddfb-ddc1-440e-9030-cbf2d05bd49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033862980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2033862980
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3931946535
Short name T369
Test name
Test status
Simulation time 137373548 ps
CPU time 1.19 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:43 PM PDT 24
Peak memory 200360 kb
Host smart-db73c480-e823-4311-9ebc-f40f03c5cd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931946535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3931946535
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.3598743643
Short name T222
Test name
Test status
Simulation time 70914138 ps
CPU time 0.76 seconds
Started Aug 11 06:10:31 PM PDT 24
Finished Aug 11 06:10:32 PM PDT 24
Peak memory 200048 kb
Host smart-3fc14342-6dee-4cc7-944e-03b055554dda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598743643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3598743643
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.4187337032
Short name T26
Test name
Test status
Simulation time 1218755519 ps
CPU time 5.95 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 229772 kb
Host smart-45f5baf2-3aef-45a6-8d13-47a10fead431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187337032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.4187337032
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1197933381
Short name T313
Test name
Test status
Simulation time 244034118 ps
CPU time 1.05 seconds
Started Aug 11 06:10:35 PM PDT 24
Finished Aug 11 06:10:37 PM PDT 24
Peak memory 217532 kb
Host smart-03f76117-ee57-469e-898c-241f9ea1f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197933381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1197933381
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.971018043
Short name T201
Test name
Test status
Simulation time 90163347 ps
CPU time 0.81 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200116 kb
Host smart-ba2fc1e8-a360-49a9-a17d-7ec369c1a2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971018043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.971018043
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2484039893
Short name T304
Test name
Test status
Simulation time 1352124934 ps
CPU time 5.47 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200316 kb
Host smart-4da1bbc0-20cd-4ab6-a2d3-167ea6027dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484039893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2484039893
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1955594573
Short name T357
Test name
Test status
Simulation time 148405217 ps
CPU time 1.18 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 200248 kb
Host smart-0b505638-4d2c-43b8-be18-291520081d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955594573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1955594573
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.362413625
Short name T324
Test name
Test status
Simulation time 253582648 ps
CPU time 1.44 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 200536 kb
Host smart-161b1f81-80f6-4c8f-abef-f5ee01c3407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362413625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.362413625
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2019448782
Short name T434
Test name
Test status
Simulation time 158281559 ps
CPU time 1.05 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:10:44 PM PDT 24
Peak memory 200320 kb
Host smart-2545124d-1dda-482c-8bb7-9e0dca685a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019448782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2019448782
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3377385514
Short name T509
Test name
Test status
Simulation time 422240815 ps
CPU time 2.47 seconds
Started Aug 11 06:10:39 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 208464 kb
Host smart-06be6142-e43e-4cf2-8061-53e968e5ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377385514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3377385514
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.284820384
Short name T339
Test name
Test status
Simulation time 81189185 ps
CPU time 0.84 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:10:46 PM PDT 24
Peak memory 200332 kb
Host smart-d034f9bc-243b-455e-96ae-269536f94bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284820384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.284820384
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2328965032
Short name T148
Test name
Test status
Simulation time 206109688 ps
CPU time 1.15 seconds
Started Aug 11 06:10:39 PM PDT 24
Finished Aug 11 06:10:40 PM PDT 24
Peak memory 200092 kb
Host smart-d2e5b9d1-ba68-478b-9025-26e851c18e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328965032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2328965032
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3015969121
Short name T441
Test name
Test status
Simulation time 1223284064 ps
CPU time 6.26 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:47 PM PDT 24
Peak memory 221672 kb
Host smart-2267a9ee-8699-4112-9598-91f0442a3f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015969121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3015969121
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.183622527
Short name T57
Test name
Test status
Simulation time 244749668 ps
CPU time 1.19 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:45 PM PDT 24
Peak memory 217356 kb
Host smart-08c282d0-7cc0-4479-845a-da1d1a3e0fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183622527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.183622527
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3517616999
Short name T384
Test name
Test status
Simulation time 213080545 ps
CPU time 0.9 seconds
Started Aug 11 06:10:37 PM PDT 24
Finished Aug 11 06:10:38 PM PDT 24
Peak memory 200052 kb
Host smart-26fbeee8-1a3f-4487-8af5-ed20265c9409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517616999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3517616999
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1959311578
Short name T60
Test name
Test status
Simulation time 1755913818 ps
CPU time 6.84 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200536 kb
Host smart-d70bff47-5d7c-4f7e-9833-dfda9405082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959311578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1959311578
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.519757777
Short name T255
Test name
Test status
Simulation time 103123943 ps
CPU time 0.96 seconds
Started Aug 11 06:10:39 PM PDT 24
Finished Aug 11 06:10:40 PM PDT 24
Peak memory 200376 kb
Host smart-ddcb215b-cc14-4029-892c-76489e489624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519757777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.519757777
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.576327384
Short name T211
Test name
Test status
Simulation time 251777634 ps
CPU time 1.53 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:46 PM PDT 24
Peak memory 200400 kb
Host smart-132cb364-dd9d-4613-9552-7b18cdf8d072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576327384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.576327384
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3731428288
Short name T120
Test name
Test status
Simulation time 4393067406 ps
CPU time 14.91 seconds
Started Aug 11 06:10:35 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200660 kb
Host smart-d849d935-2774-4c55-8bcf-2d34cb837059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731428288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3731428288
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2244452691
Short name T440
Test name
Test status
Simulation time 465532701 ps
CPU time 2.55 seconds
Started Aug 11 06:10:38 PM PDT 24
Finished Aug 11 06:10:41 PM PDT 24
Peak memory 200204 kb
Host smart-29c63175-a0c7-44d7-835e-279150cc790e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244452691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2244452691
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.449617984
Short name T152
Test name
Test status
Simulation time 71035468 ps
CPU time 0.82 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:43 PM PDT 24
Peak memory 200152 kb
Host smart-e9bc3a4f-0481-4bab-aa51-2a5023222152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449617984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.449617984
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3804295748
Short name T177
Test name
Test status
Simulation time 57564753 ps
CPU time 0.72 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:10:45 PM PDT 24
Peak memory 200164 kb
Host smart-559e6c28-0113-42a4-9df8-feb613a8d47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804295748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3804295748
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2681828837
Short name T30
Test name
Test status
Simulation time 2190762153 ps
CPU time 8.58 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 221728 kb
Host smart-9c5407f3-a23b-4b06-a4cd-712edcbb9f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681828837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2681828837
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1769088886
Short name T134
Test name
Test status
Simulation time 244278062 ps
CPU time 1.03 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 217444 kb
Host smart-2357723b-8a00-4a67-b9b4-a80e5036d7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769088886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1769088886
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1277755790
Short name T14
Test name
Test status
Simulation time 116698621 ps
CPU time 0.73 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:46 PM PDT 24
Peak memory 200116 kb
Host smart-f48271ba-cefa-4b69-9668-52d265c70f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277755790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1277755790
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2750536093
Short name T231
Test name
Test status
Simulation time 1705506454 ps
CPU time 7.5 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200584 kb
Host smart-46b47925-f5ae-4ffd-9a85-e5bd5b5ac359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750536093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2750536093
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2427885337
Short name T82
Test name
Test status
Simulation time 94401010 ps
CPU time 1.04 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 200336 kb
Host smart-c8aca084-661e-4c2a-9412-b4ea707a5648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427885337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2427885337
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3139240142
Short name T158
Test name
Test status
Simulation time 254955576 ps
CPU time 1.45 seconds
Started Aug 11 06:10:37 PM PDT 24
Finished Aug 11 06:10:39 PM PDT 24
Peak memory 200416 kb
Host smart-99b6d348-fb54-4273-86b3-afb9b8fd0ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139240142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3139240142
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1477177149
Short name T503
Test name
Test status
Simulation time 7401097368 ps
CPU time 26.63 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:11:03 PM PDT 24
Peak memory 200648 kb
Host smart-2f18c2de-6d85-445e-8455-ebec9dd1a8b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477177149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1477177149
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.42719661
Short name T87
Test name
Test status
Simulation time 544451685 ps
CPU time 2.87 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:44 PM PDT 24
Peak memory 200300 kb
Host smart-e7db5eb6-4b3b-475d-90fe-6ad7b593c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42719661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.42719661
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3042619073
Short name T477
Test name
Test status
Simulation time 102494579 ps
CPU time 0.89 seconds
Started Aug 11 06:10:39 PM PDT 24
Finished Aug 11 06:10:40 PM PDT 24
Peak memory 200352 kb
Host smart-1dcf08e6-eede-485d-aac5-91d0bbb2402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042619073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3042619073
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1465918007
Short name T291
Test name
Test status
Simulation time 90241136 ps
CPU time 0.82 seconds
Started Aug 11 06:10:32 PM PDT 24
Finished Aug 11 06:10:33 PM PDT 24
Peak memory 200060 kb
Host smart-33c557db-03dd-4222-8d19-9919ac57aaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465918007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1465918007
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.308454584
Short name T32
Test name
Test status
Simulation time 1224961848 ps
CPU time 5.49 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 216900 kb
Host smart-065c4c58-dd9d-4cce-a163-6b881784dd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308454584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.308454584
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1273364782
Short name T199
Test name
Test status
Simulation time 245065880 ps
CPU time 1.1 seconds
Started Aug 11 06:10:34 PM PDT 24
Finished Aug 11 06:10:36 PM PDT 24
Peak memory 217512 kb
Host smart-e0c52635-96cc-4964-b0ba-50cf045fe208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273364782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1273364782
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1679043947
Short name T15
Test name
Test status
Simulation time 127662365 ps
CPU time 0.81 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 200172 kb
Host smart-498f7aca-64e3-4794-9063-7283ebc5be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679043947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1679043947
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1445451657
Short name T380
Test name
Test status
Simulation time 1898497871 ps
CPU time 7.38 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200580 kb
Host smart-da7f21b4-f5a5-404d-a435-cdf34ff6862a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445451657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1445451657
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3583282723
Short name T488
Test name
Test status
Simulation time 152613305 ps
CPU time 1.12 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200216 kb
Host smart-d35a5a2e-5aaa-4a56-8eb2-cf9d83e5506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583282723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3583282723
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3798287083
Short name T496
Test name
Test status
Simulation time 115776873 ps
CPU time 1.14 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200444 kb
Host smart-eddaa1b6-531c-415b-9803-a02c72eb871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798287083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3798287083
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.500841909
Short name T510
Test name
Test status
Simulation time 5790194010 ps
CPU time 20.28 seconds
Started Aug 11 06:10:37 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 208724 kb
Host smart-fbe9d726-035c-4cbd-b642-ef5bc80936e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500841909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.500841909
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2817047015
Short name T186
Test name
Test status
Simulation time 149412809 ps
CPU time 1.82 seconds
Started Aug 11 06:10:31 PM PDT 24
Finished Aug 11 06:10:33 PM PDT 24
Peak memory 200244 kb
Host smart-c67868d7-651f-4825-87c8-35f73f9d4f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817047015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2817047015
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1589167367
Short name T125
Test name
Test status
Simulation time 202567410 ps
CPU time 1.23 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200376 kb
Host smart-402f36fa-5177-454c-9af9-f3b62d558199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589167367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1589167367
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.872745026
Short name T296
Test name
Test status
Simulation time 70407757 ps
CPU time 0.77 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 200060 kb
Host smart-3baa228c-5350-43df-8fbf-5658c5559949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872745026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.872745026
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1927821523
Short name T34
Test name
Test status
Simulation time 1225706637 ps
CPU time 5.65 seconds
Started Aug 11 06:10:34 PM PDT 24
Finished Aug 11 06:10:40 PM PDT 24
Peak memory 217412 kb
Host smart-b7078590-c7b4-4503-aacd-43fe50a00ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927821523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1927821523
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3569188066
Short name T454
Test name
Test status
Simulation time 244914699 ps
CPU time 1.06 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:38 PM PDT 24
Peak memory 217532 kb
Host smart-8f7194b8-2bf4-4107-9c48-e07ee99a020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569188066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3569188066
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1413985797
Short name T498
Test name
Test status
Simulation time 205857533 ps
CPU time 0.98 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 200144 kb
Host smart-a7150970-55be-4dd2-acba-cb4536bca559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413985797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1413985797
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.553259315
Short name T310
Test name
Test status
Simulation time 831835498 ps
CPU time 4.16 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:51 PM PDT 24
Peak memory 200604 kb
Host smart-95967f52-7bac-49ea-8c35-1095d4e48900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553259315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.553259315
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1467274821
Short name T368
Test name
Test status
Simulation time 106065378 ps
CPU time 0.97 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:47 PM PDT 24
Peak memory 200308 kb
Host smart-81a412e9-ba5c-433a-9437-e1621fb3ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467274821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1467274821
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1519171026
Short name T141
Test name
Test status
Simulation time 199904904 ps
CPU time 1.37 seconds
Started Aug 11 06:10:37 PM PDT 24
Finished Aug 11 06:10:38 PM PDT 24
Peak memory 200388 kb
Host smart-d9b751ec-b07e-43ba-9217-14b22cbfd69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519171026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1519171026
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.4109804510
Short name T317
Test name
Test status
Simulation time 12235203651 ps
CPU time 40.02 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:11:16 PM PDT 24
Peak memory 200524 kb
Host smart-d3a13d9e-f921-4f28-98ea-9e0a093b498c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109804510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.4109804510
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2276859812
Short name T257
Test name
Test status
Simulation time 136945126 ps
CPU time 1.73 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:51 PM PDT 24
Peak memory 200296 kb
Host smart-45d9d694-ee35-4c1d-af63-b4665e51151d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276859812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2276859812
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.3215912440
Short name T406
Test name
Test status
Simulation time 93027219 ps
CPU time 0.8 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:45 PM PDT 24
Peak memory 200360 kb
Host smart-a108c0a9-625e-4bef-bf0c-898f5533c599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215912440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3215912440
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1937813849
Short name T223
Test name
Test status
Simulation time 74653774 ps
CPU time 0.87 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 200168 kb
Host smart-a44b2892-9fd2-437d-89a9-34ef713bb682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937813849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1937813849
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1773069613
Short name T287
Test name
Test status
Simulation time 1899829704 ps
CPU time 6.76 seconds
Started Aug 11 06:09:55 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 217464 kb
Host smart-6bf27d6b-3cc8-4905-8af6-60b3410c376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773069613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1773069613
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2218154692
Short name T325
Test name
Test status
Simulation time 244237207 ps
CPU time 1.07 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 217532 kb
Host smart-384461b4-ab59-40ce-84f8-7c38e5a26cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218154692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2218154692
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.3178175652
Short name T524
Test name
Test status
Simulation time 225787853 ps
CPU time 0.98 seconds
Started Aug 11 06:10:07 PM PDT 24
Finished Aug 11 06:10:09 PM PDT 24
Peak memory 200176 kb
Host smart-9e145447-7c3e-4aa2-b863-f1e014cb904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178175652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3178175652
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2625579755
Short name T246
Test name
Test status
Simulation time 1716122594 ps
CPU time 6.67 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:09 PM PDT 24
Peak memory 200452 kb
Host smart-35f677a3-53ad-47e6-8479-94c7ef79cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625579755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2625579755
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2046673939
Short name T76
Test name
Test status
Simulation time 8549803830 ps
CPU time 13.95 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:13 PM PDT 24
Peak memory 217320 kb
Host smart-a3f89543-ea56-4411-b05e-50bf013a594c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046673939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2046673939
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.247383826
Short name T321
Test name
Test status
Simulation time 144190535 ps
CPU time 1.17 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:04 PM PDT 24
Peak memory 200376 kb
Host smart-e8e80f0d-1471-41fd-a70a-b34bc56ef5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247383826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.247383826
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1436736760
Short name T413
Test name
Test status
Simulation time 126956714 ps
CPU time 1.21 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200504 kb
Host smart-a769d4a1-c603-4b61-aa6f-febbd9556be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436736760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1436736760
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.223634836
Short name T329
Test name
Test status
Simulation time 5100206009 ps
CPU time 23.96 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:25 PM PDT 24
Peak memory 200528 kb
Host smart-dcbf7257-4d27-4536-b3eb-b9a658e454f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223634836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.223634836
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2950913979
Short name T366
Test name
Test status
Simulation time 247947532 ps
CPU time 1.75 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 200292 kb
Host smart-42222508-b0d8-4816-bf3c-7063243f47fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950913979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2950913979
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.503673428
Short name T360
Test name
Test status
Simulation time 71149793 ps
CPU time 0.82 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 200152 kb
Host smart-a5ab3b27-892d-4834-8cf6-7097cf8bbc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503673428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.503673428
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1283994026
Short name T129
Test name
Test status
Simulation time 90567800 ps
CPU time 0.83 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200152 kb
Host smart-d6341b14-227d-49e3-93c7-906d7ccd3470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283994026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1283994026
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1594564483
Short name T283
Test name
Test status
Simulation time 1226918677 ps
CPU time 5.63 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:11:00 PM PDT 24
Peak memory 217648 kb
Host smart-2894ce99-b6d1-48ec-9a89-17c7744d6130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594564483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1594564483
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.376299233
Short name T137
Test name
Test status
Simulation time 243622239 ps
CPU time 1.08 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:43 PM PDT 24
Peak memory 217568 kb
Host smart-17296e12-08fa-42a9-b691-17ac9f478807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376299233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.376299233
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.169672902
Short name T495
Test name
Test status
Simulation time 132450497 ps
CPU time 0.82 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200160 kb
Host smart-2d5a0950-b9c4-4ad6-bcc8-4804e0dee5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169672902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.169672902
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3538752159
Short name T277
Test name
Test status
Simulation time 1541299820 ps
CPU time 7.24 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200528 kb
Host smart-c727774b-15bd-4c01-9b2b-38bb0628f45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538752159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3538752159
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2940419554
Short name T340
Test name
Test status
Simulation time 177908789 ps
CPU time 1.13 seconds
Started Aug 11 06:10:36 PM PDT 24
Finished Aug 11 06:10:38 PM PDT 24
Peak memory 200268 kb
Host smart-0687538b-1da8-4a2c-a09a-c50dc651a149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940419554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2940419554
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2224855964
Short name T407
Test name
Test status
Simulation time 122940679 ps
CPU time 1.2 seconds
Started Aug 11 06:10:40 PM PDT 24
Finished Aug 11 06:10:41 PM PDT 24
Peak memory 200496 kb
Host smart-d2ddf55c-f60f-43d5-93f6-eda811ef520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224855964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2224855964
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.4201015336
Short name T101
Test name
Test status
Simulation time 5446078283 ps
CPU time 21.09 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:11:03 PM PDT 24
Peak memory 200616 kb
Host smart-301e570a-3dec-47cb-accf-2feef2e67c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201015336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.4201015336
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1795391551
Short name T527
Test name
Test status
Simulation time 143731872 ps
CPU time 1.79 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200304 kb
Host smart-9bd01eae-e446-481f-b5f2-8c63d79bc071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795391551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1795391551
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.875260401
Short name T174
Test name
Test status
Simulation time 71196378 ps
CPU time 0.86 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200360 kb
Host smart-610e05a9-0ce5-4c0c-9ee0-cb61807bfb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875260401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.875260401
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.3640495354
Short name T451
Test name
Test status
Simulation time 75160463 ps
CPU time 0.83 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200092 kb
Host smart-385c09a7-5ba1-4973-829d-abb0162ebe9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640495354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3640495354
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.1530747107
Short name T421
Test name
Test status
Simulation time 2367543136 ps
CPU time 8.68 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:10:51 PM PDT 24
Peak memory 217812 kb
Host smart-a1b1edb3-d945-4880-bf66-534d7908e4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530747107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1530747107
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.93169760
Short name T7
Test name
Test status
Simulation time 244240680 ps
CPU time 1.06 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 217436 kb
Host smart-3f2ddc0a-3850-4927-bbed-021cb52ca0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93169760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.93169760
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1011693408
Short name T408
Test name
Test status
Simulation time 207073964 ps
CPU time 0.98 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200168 kb
Host smart-ba4f0583-672b-4923-959a-f0b2d3bc1405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011693408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1011693408
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3807510286
Short name T379
Test name
Test status
Simulation time 2037874217 ps
CPU time 7.68 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200500 kb
Host smart-b6176f16-27fa-4301-853a-562ac2497a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807510286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3807510286
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3768784289
Short name T5
Test name
Test status
Simulation time 103564762 ps
CPU time 1 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200276 kb
Host smart-48b3e1d6-ec14-4182-b2aa-9a118efffc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768784289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3768784289
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2130616383
Short name T236
Test name
Test status
Simulation time 261315912 ps
CPU time 1.51 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:42 PM PDT 24
Peak memory 199460 kb
Host smart-0861330b-2ad4-4336-aeb9-be925d21d01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130616383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2130616383
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1473530968
Short name T377
Test name
Test status
Simulation time 8409852947 ps
CPU time 36.66 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:11:29 PM PDT 24
Peak memory 200692 kb
Host smart-46ecaeb4-5fd3-492f-9ba0-1d5f565323c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473530968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1473530968
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1686736158
Short name T536
Test name
Test status
Simulation time 380708687 ps
CPU time 2.12 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200284 kb
Host smart-69a32c96-a475-4728-ab24-64f798647a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686736158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1686736158
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.1713255134
Short name T336
Test name
Test status
Simulation time 98859494 ps
CPU time 0.9 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:54 PM PDT 24
Peak memory 200512 kb
Host smart-2f1080b2-d6ff-40a1-a459-12f42b26e165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713255134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1713255134
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1540397183
Short name T500
Test name
Test status
Simulation time 69164956 ps
CPU time 0.76 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:47 PM PDT 24
Peak memory 200104 kb
Host smart-af92c36c-b4b9-44a2-b2d9-f9a403965a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540397183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1540397183
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.858395018
Short name T53
Test name
Test status
Simulation time 2170675241 ps
CPU time 8.94 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:11:06 PM PDT 24
Peak memory 217560 kb
Host smart-a78c20cb-14d9-4cf7-813a-c2eef34c0368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858395018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.858395018
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.190595108
Short name T508
Test name
Test status
Simulation time 244954260 ps
CPU time 1.13 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:47 PM PDT 24
Peak memory 217496 kb
Host smart-3db7f7c0-67f8-4306-bbfd-4f5ac417bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190595108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.190595108
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.946410559
Short name T217
Test name
Test status
Simulation time 189656868 ps
CPU time 0.89 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200172 kb
Host smart-1c0a3a4d-7288-45f8-84c6-b69bb242d909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946410559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.946410559
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1709043992
Short name T409
Test name
Test status
Simulation time 1833344632 ps
CPU time 6.61 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:51 PM PDT 24
Peak memory 200400 kb
Host smart-f10e7704-22ae-4008-a83e-c914cb8c6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709043992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1709043992
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1031843520
Short name T39
Test name
Test status
Simulation time 108904164 ps
CPU time 1.03 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200360 kb
Host smart-f0e7e5f5-9a76-458a-81ac-85e6d6c0fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031843520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1031843520
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1190654654
Short name T24
Test name
Test status
Simulation time 250744722 ps
CPU time 1.48 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200484 kb
Host smart-90b752a4-9b53-4d84-b956-9d55f178cc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190654654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1190654654
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2152952365
Short name T235
Test name
Test status
Simulation time 792001139 ps
CPU time 3.33 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 200432 kb
Host smart-0e95f40b-e579-4c1b-966a-20d7f662d372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152952365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2152952365
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4192139745
Short name T318
Test name
Test status
Simulation time 134523632 ps
CPU time 1.77 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:54 PM PDT 24
Peak memory 199252 kb
Host smart-c006d93d-298e-4115-9f1f-86e7177da9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192139745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4192139745
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.4092465538
Short name T449
Test name
Test status
Simulation time 167450809 ps
CPU time 1.35 seconds
Started Aug 11 06:10:44 PM PDT 24
Finished Aug 11 06:10:46 PM PDT 24
Peak memory 200492 kb
Host smart-74e87bca-1e6f-45ab-90a1-5e03cf950aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092465538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.4092465538
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.3976647690
Short name T78
Test name
Test status
Simulation time 76532161 ps
CPU time 0.81 seconds
Started Aug 11 06:10:42 PM PDT 24
Finished Aug 11 06:10:43 PM PDT 24
Peak memory 200132 kb
Host smart-c0b8dc30-4628-4046-8447-32e92d8d0068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976647690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3976647690
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3370874118
Short name T445
Test name
Test status
Simulation time 2374094602 ps
CPU time 8.08 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:11:00 PM PDT 24
Peak memory 221824 kb
Host smart-1464d7a8-ca85-4465-bdcc-1ba6433f2658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370874118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3370874118
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1788551515
Short name T230
Test name
Test status
Simulation time 243113404 ps
CPU time 1.12 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 217460 kb
Host smart-18c974c1-42ff-48bf-a3a8-656f76aed6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788551515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1788551515
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2894460332
Short name T312
Test name
Test status
Simulation time 110583263 ps
CPU time 0.76 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200112 kb
Host smart-3e661e43-eced-480b-986c-0bdb72e2834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894460332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2894460332
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.585190095
Short name T184
Test name
Test status
Simulation time 790700925 ps
CPU time 4.08 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:54 PM PDT 24
Peak memory 200496 kb
Host smart-23961df8-cf2d-423f-bbec-5ffae6b479f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585190095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.585190095
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2551443601
Short name T146
Test name
Test status
Simulation time 95702161 ps
CPU time 0.96 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200364 kb
Host smart-8a1d327f-275b-4442-b0bc-b41414008cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551443601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2551443601
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2459822316
Short name T181
Test name
Test status
Simulation time 196243757 ps
CPU time 1.34 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:10:46 PM PDT 24
Peak memory 200440 kb
Host smart-e00f0665-85a0-44d6-9df2-032b647ba8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459822316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2459822316
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2576485810
Short name T528
Test name
Test status
Simulation time 11671745467 ps
CPU time 41.15 seconds
Started Aug 11 06:10:37 PM PDT 24
Finished Aug 11 06:11:19 PM PDT 24
Peak memory 208568 kb
Host smart-c780fb01-ed82-4bc6-818f-1864a493e3cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576485810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2576485810
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1846324450
Short name T292
Test name
Test status
Simulation time 436194097 ps
CPU time 2.47 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 208500 kb
Host smart-7d5097dc-1f9a-4891-8033-7bd1a2894123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846324450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1846324450
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1657032892
Short name T227
Test name
Test status
Simulation time 78816358 ps
CPU time 0.83 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200352 kb
Host smart-2bc56644-3565-44d0-8752-ae07e6a8ba9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657032892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1657032892
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.1172282806
Short name T378
Test name
Test status
Simulation time 69403358 ps
CPU time 0.77 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200168 kb
Host smart-c6a54e7b-2249-46a1-b42c-edcb2964a971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172282806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1172282806
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3931779242
Short name T405
Test name
Test status
Simulation time 1884092211 ps
CPU time 7.57 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 221372 kb
Host smart-6408b237-1c3e-413c-9ce2-deba8bee8a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931779242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3931779242
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2269648686
Short name T215
Test name
Test status
Simulation time 271067065 ps
CPU time 1.09 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 217448 kb
Host smart-a02b9ae7-0809-424a-b52d-a9d5ec68503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269648686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2269648686
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.3742196848
Short name T473
Test name
Test status
Simulation time 235114221 ps
CPU time 0.95 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 199108 kb
Host smart-0d92daac-1a02-49c1-80b3-55555dcd9904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742196848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3742196848
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.1713529494
Short name T84
Test name
Test status
Simulation time 779866946 ps
CPU time 4.07 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200452 kb
Host smart-50bd6600-a8c4-4e72-b5c1-57c1302f7d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713529494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1713529494
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.645972661
Short name T251
Test name
Test status
Simulation time 152575807 ps
CPU time 1.1 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200264 kb
Host smart-0c11551f-632f-4837-a491-fdebe39e8d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645972661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.645972661
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2074563716
Short name T241
Test name
Test status
Simulation time 189150201 ps
CPU time 1.31 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200496 kb
Host smart-003bb73b-a90f-4c2e-8ec9-6ec954d63426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074563716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2074563716
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3804631092
Short name T98
Test name
Test status
Simulation time 4470975769 ps
CPU time 22.96 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:11:11 PM PDT 24
Peak memory 200560 kb
Host smart-5bcebb75-927d-46ab-9539-e67cc4fdef99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804631092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3804631092
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3969523817
Short name T323
Test name
Test status
Simulation time 497029743 ps
CPU time 2.64 seconds
Started Aug 11 06:10:41 PM PDT 24
Finished Aug 11 06:10:44 PM PDT 24
Peak memory 200188 kb
Host smart-9237207f-19a6-4293-9dae-5555f053785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969523817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3969523817
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.4099150709
Short name T145
Test name
Test status
Simulation time 138449796 ps
CPU time 1.16 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200356 kb
Host smart-e0783005-f409-4d06-803f-eec8f6f5f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099150709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.4099150709
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1575686008
Short name T517
Test name
Test status
Simulation time 64077688 ps
CPU time 0.79 seconds
Started Aug 11 06:10:45 PM PDT 24
Finished Aug 11 06:10:46 PM PDT 24
Peak memory 200344 kb
Host smart-2954996d-ad0a-4c4d-8589-6a47383711f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575686008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1575686008
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3241369429
Short name T44
Test name
Test status
Simulation time 2361558325 ps
CPU time 8.45 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:11:02 PM PDT 24
Peak memory 217432 kb
Host smart-4dee6d57-1475-4899-9aba-955a66cbd453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241369429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3241369429
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1661638614
Short name T453
Test name
Test status
Simulation time 244245734 ps
CPU time 1.11 seconds
Started Aug 11 06:10:43 PM PDT 24
Finished Aug 11 06:10:44 PM PDT 24
Peak memory 217544 kb
Host smart-960d6a1e-d09a-4c77-81fb-b63115ce4f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661638614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1661638614
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2770140823
Short name T464
Test name
Test status
Simulation time 206692763 ps
CPU time 0.92 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:54 PM PDT 24
Peak memory 200164 kb
Host smart-1d8dc2e3-8b0c-4ac2-a229-713bc5b5e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770140823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2770140823
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1459880047
Short name T331
Test name
Test status
Simulation time 890588340 ps
CPU time 4.71 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200560 kb
Host smart-5d37b96d-8c54-46ea-811c-36cde038780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459880047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1459880047
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3353798538
Short name T309
Test name
Test status
Simulation time 157453479 ps
CPU time 1.17 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200328 kb
Host smart-16850989-fe19-4d16-8571-be28fd7e69c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353798538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3353798538
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.3297619313
Short name T354
Test name
Test status
Simulation time 114871521 ps
CPU time 1.24 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200476 kb
Host smart-f032ff5b-dc86-4ec0-83ee-5f831fc1ec58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297619313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3297619313
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1558356959
Short name T513
Test name
Test status
Simulation time 7693087177 ps
CPU time 24.93 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:11:15 PM PDT 24
Peak memory 208784 kb
Host smart-e301cc82-6eeb-430e-84de-a6cb0f60e77a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558356959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1558356959
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3821879934
Short name T238
Test name
Test status
Simulation time 334952125 ps
CPU time 2.41 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 208480 kb
Host smart-87428532-27d6-4bfb-ae87-8466c7cc3a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821879934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3821879934
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.732387555
Short name T151
Test name
Test status
Simulation time 108440037 ps
CPU time 0.91 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200340 kb
Host smart-086c96ea-20e2-4edf-87c6-762375a3d2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732387555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.732387555
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2601775021
Short name T209
Test name
Test status
Simulation time 92412120 ps
CPU time 0.83 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:54 PM PDT 24
Peak memory 200156 kb
Host smart-79c0e092-24cf-4b3b-a3ae-ad98a35e6aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601775021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2601775021
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.549517075
Short name T319
Test name
Test status
Simulation time 2365752270 ps
CPU time 8.71 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:11:02 PM PDT 24
Peak memory 217904 kb
Host smart-616ab7a0-315e-4a1e-801d-e171d743ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549517075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.549517075
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3653180371
Short name T395
Test name
Test status
Simulation time 243831439 ps
CPU time 1.06 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 217544 kb
Host smart-8f1fb00e-4237-4018-9ebd-533a1d7427f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653180371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3653180371
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.457826522
Short name T442
Test name
Test status
Simulation time 156413874 ps
CPU time 0.84 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200140 kb
Host smart-763b4000-5bee-4228-a014-181c5b69c0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457826522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.457826522
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2209440982
Short name T417
Test name
Test status
Simulation time 1734043073 ps
CPU time 7 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200604 kb
Host smart-78efee69-c074-4b6a-bb3e-526a5ee5abf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209440982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2209440982
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3655569730
Short name T281
Test name
Test status
Simulation time 148661157 ps
CPU time 1.14 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:49 PM PDT 24
Peak memory 200340 kb
Host smart-30ab871b-1123-4ef9-879d-b071c3d14372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655569730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3655569730
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3260813184
Short name T12
Test name
Test status
Simulation time 192195611 ps
CPU time 1.4 seconds
Started Aug 11 06:11:03 PM PDT 24
Finished Aug 11 06:11:04 PM PDT 24
Peak memory 200452 kb
Host smart-90e42475-1194-4eb6-835a-d88a85f6b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260813184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3260813184
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3926483665
Short name T422
Test name
Test status
Simulation time 1119045989 ps
CPU time 5.99 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 216896 kb
Host smart-4a1dce4b-7afa-430e-af30-d45ff22a0898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926483665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3926483665
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2029931881
Short name T362
Test name
Test status
Simulation time 120108627 ps
CPU time 1.47 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200304 kb
Host smart-5cdee91f-701a-400e-a48b-03ec26a9e27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029931881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2029931881
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.45236996
Short name T475
Test name
Test status
Simulation time 231241915 ps
CPU time 1.41 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 200364 kb
Host smart-9006f51f-283e-4141-ae31-f2eae56d5975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45236996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.45236996
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3436220326
Short name T138
Test name
Test status
Simulation time 65457069 ps
CPU time 0.76 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200092 kb
Host smart-71c16c0f-0e6b-4ec6-91e6-e6487250edee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436220326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3436220326
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.4161014867
Short name T436
Test name
Test status
Simulation time 1213494773 ps
CPU time 5.72 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:11:00 PM PDT 24
Peak memory 217656 kb
Host smart-ca4800fa-52e0-454d-a998-7a2c30a9dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161014867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.4161014867
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.799108473
Short name T301
Test name
Test status
Simulation time 244317191 ps
CPU time 1.06 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:02 PM PDT 24
Peak memory 217492 kb
Host smart-24207b74-4a33-4d9a-9eaa-9f24cfa9b7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799108473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.799108473
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2466768408
Short name T420
Test name
Test status
Simulation time 215899596 ps
CPU time 0.87 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200100 kb
Host smart-73529312-a56e-4198-a1af-3c753316dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466768408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2466768408
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1001080134
Short name T518
Test name
Test status
Simulation time 1512343753 ps
CPU time 6.04 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 200488 kb
Host smart-083bc6c8-8a87-424f-b490-de7ef87d7def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001080134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1001080134
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3741324219
Short name T140
Test name
Test status
Simulation time 103950693 ps
CPU time 0.96 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200364 kb
Host smart-4ad8f42f-4452-4188-9e90-1f953d174ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741324219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3741324219
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.4136903984
Short name T69
Test name
Test status
Simulation time 190872249 ps
CPU time 1.33 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200480 kb
Host smart-f27c35de-0489-4be1-8eaa-c8beb4f554fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136903984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4136903984
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.1077012601
Short name T487
Test name
Test status
Simulation time 11057360486 ps
CPU time 38.32 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:11:32 PM PDT 24
Peak memory 200632 kb
Host smart-1a1dc480-a5b4-4577-99f8-d2e897f86fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077012601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1077012601
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3954307829
Short name T232
Test name
Test status
Simulation time 285865452 ps
CPU time 1.83 seconds
Started Aug 11 06:11:03 PM PDT 24
Finished Aug 11 06:11:05 PM PDT 24
Peak memory 200260 kb
Host smart-72c38439-cdd5-4d1b-920e-dc19e963cf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954307829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3954307829
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3028505053
Short name T268
Test name
Test status
Simulation time 250825206 ps
CPU time 1.53 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200336 kb
Host smart-0cdefa3f-4683-43b0-a834-e58788e97a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028505053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3028505053
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2173360967
Short name T316
Test name
Test status
Simulation time 60778883 ps
CPU time 0.75 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200056 kb
Host smart-ea051336-0ece-4ef3-a4b5-2cf7ee63d8d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173360967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2173360967
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.170440040
Short name T45
Test name
Test status
Simulation time 1231003589 ps
CPU time 5.45 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 221620 kb
Host smart-940c2be6-e902-4fe1-ba30-be7f840bdc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170440040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.170440040
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1792150777
Short name T418
Test name
Test status
Simulation time 248705776 ps
CPU time 1.05 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 217484 kb
Host smart-e23d41e5-24c7-4837-a080-9468773cc014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792150777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1792150777
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2516455086
Short name T435
Test name
Test status
Simulation time 130039413 ps
CPU time 0.86 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200144 kb
Host smart-4385ec4a-5d97-49fd-814e-844b2a76d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516455086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2516455086
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.255865450
Short name T400
Test name
Test status
Simulation time 1215090687 ps
CPU time 5.42 seconds
Started Aug 11 06:11:03 PM PDT 24
Finished Aug 11 06:11:08 PM PDT 24
Peak memory 200520 kb
Host smart-5d63bc94-43ed-47c2-9e53-0c5cbdb75fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255865450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.255865450
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3391766978
Short name T427
Test name
Test status
Simulation time 184955792 ps
CPU time 1.18 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 200296 kb
Host smart-4533648e-866f-4a06-a9c1-7d84ec4b6119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391766978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3391766978
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.685014505
Short name T458
Test name
Test status
Simulation time 195706506 ps
CPU time 1.33 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 199412 kb
Host smart-8fdd11b4-2513-431c-857c-fc2a9bd38827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685014505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.685014505
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.159021612
Short name T483
Test name
Test status
Simulation time 9952157097 ps
CPU time 40 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:11:31 PM PDT 24
Peak memory 208724 kb
Host smart-da1ab9cf-66d8-4f9c-9820-0357663f759e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159021612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.159021612
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2781812505
Short name T225
Test name
Test status
Simulation time 436825734 ps
CPU time 2.39 seconds
Started Aug 11 06:11:03 PM PDT 24
Finished Aug 11 06:11:05 PM PDT 24
Peak memory 200260 kb
Host smart-731b96a9-608c-4b89-8e80-0d2f1cec66d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781812505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2781812505
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3387985069
Short name T359
Test name
Test status
Simulation time 212289939 ps
CPU time 1.35 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200340 kb
Host smart-8fdb6103-b565-49d1-b42c-89d8f6c3b367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387985069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3387985069
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3493560353
Short name T505
Test name
Test status
Simulation time 68942192 ps
CPU time 0.75 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200120 kb
Host smart-4a20685a-5dd6-4a6f-b016-e048dbb0dc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493560353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3493560353
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.4101481801
Short name T33
Test name
Test status
Simulation time 2376513881 ps
CPU time 8.86 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:11:07 PM PDT 24
Peak memory 221760 kb
Host smart-07122517-0d0e-456e-a2db-d3ae53b3a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101481801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.4101481801
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.4075258722
Short name T352
Test name
Test status
Simulation time 244122765 ps
CPU time 1.08 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 217456 kb
Host smart-75bd07e4-9998-4cdf-b32b-6a92175fe754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075258722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.4075258722
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3652297979
Short name T332
Test name
Test status
Simulation time 96447708 ps
CPU time 0.76 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:10:52 PM PDT 24
Peak memory 200112 kb
Host smart-5b37e370-8cf5-410d-ac0c-c75dadf8ed96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652297979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3652297979
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2924294721
Short name T266
Test name
Test status
Simulation time 2139139755 ps
CPU time 7.6 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:08 PM PDT 24
Peak memory 200516 kb
Host smart-0b451582-7747-415a-a52b-9336c1b1eafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924294721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2924294721
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3433159199
Short name T401
Test name
Test status
Simulation time 151038165 ps
CPU time 1.07 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200340 kb
Host smart-2b7ced03-a95c-4927-b49f-418bdba05395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433159199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3433159199
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.119047993
Short name T456
Test name
Test status
Simulation time 228165418 ps
CPU time 1.43 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200468 kb
Host smart-01560bbc-cd10-4582-8f78-8d48b27cdec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119047993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.119047993
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2371869481
Short name T10
Test name
Test status
Simulation time 5520231692 ps
CPU time 20.77 seconds
Started Aug 11 06:10:48 PM PDT 24
Finished Aug 11 06:11:09 PM PDT 24
Peak memory 208804 kb
Host smart-9e9a15bf-2645-4a58-96f8-3d923d411b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371869481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2371869481
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4138725580
Short name T383
Test name
Test status
Simulation time 382369260 ps
CPU time 2.44 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 208444 kb
Host smart-cfb8abae-3501-41bc-a2ba-ca42a281d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138725580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4138725580
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4185620105
Short name T41
Test name
Test status
Simulation time 284829976 ps
CPU time 1.48 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:04 PM PDT 24
Peak memory 200288 kb
Host smart-b97bc9e2-32ce-4a49-930a-ac210714b57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185620105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4185620105
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2554456099
Short name T367
Test name
Test status
Simulation time 64241139 ps
CPU time 0.76 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 200148 kb
Host smart-cef3c7af-9369-41af-87f7-fd0e59eb931a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554456099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2554456099
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.69601330
Short name T74
Test name
Test status
Simulation time 1230206245 ps
CPU time 5.87 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 221748 kb
Host smart-ec0b3854-0ed6-495d-8efb-4fe8f7fd83f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69601330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.69601330
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.856383762
Short name T208
Test name
Test status
Simulation time 244150757 ps
CPU time 1.12 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 217540 kb
Host smart-065ec8ae-9515-4e95-b5fc-d34107df469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856383762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.856383762
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3618402419
Short name T19
Test name
Test status
Simulation time 173856610 ps
CPU time 0.83 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 200108 kb
Host smart-f90cf4d5-a970-4a7c-925f-e12bb8ee6180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618402419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3618402419
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3108190990
Short name T382
Test name
Test status
Simulation time 1056123334 ps
CPU time 4.91 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 200428 kb
Host smart-79c96662-4f5e-4b5c-9d72-ae01cc7ce872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108190990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3108190990
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.313840799
Short name T81
Test name
Test status
Simulation time 16524278381 ps
CPU time 27.89 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:27 PM PDT 24
Peak memory 217296 kb
Host smart-cc60816c-df51-462a-b721-76528fc85c3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313840799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.313840799
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2922979867
Short name T294
Test name
Test status
Simulation time 146948550 ps
CPU time 1.09 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 200308 kb
Host smart-76bcf59e-d832-4fe5-bbef-1abfa1411c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922979867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2922979867
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3925042451
Short name T143
Test name
Test status
Simulation time 116331194 ps
CPU time 1.19 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:09:54 PM PDT 24
Peak memory 200476 kb
Host smart-5436ef0c-008a-4344-81e1-75004785d013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925042451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3925042451
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1587549608
Short name T142
Test name
Test status
Simulation time 192690486 ps
CPU time 1.14 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200336 kb
Host smart-545b85b9-87e7-4a24-b3fa-c6fa0ab66ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587549608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1587549608
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1393675322
Short name T139
Test name
Test status
Simulation time 125943637 ps
CPU time 1.65 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 208400 kb
Host smart-dbb72413-cba4-42cf-bba0-e432d1798e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393675322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1393675322
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3453330119
Short name T128
Test name
Test status
Simulation time 89743422 ps
CPU time 0.92 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 200308 kb
Host smart-e70812b1-cfd7-415b-9bcc-d0d9eca2f659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453330119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3453330119
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2832661082
Short name T373
Test name
Test status
Simulation time 55480373 ps
CPU time 0.73 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:47 PM PDT 24
Peak memory 200148 kb
Host smart-18c0ce0c-5197-4b01-9fa0-13c1c36a0645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832661082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2832661082
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2548110510
Short name T282
Test name
Test status
Simulation time 1885715781 ps
CPU time 7.02 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:09 PM PDT 24
Peak memory 221648 kb
Host smart-b98509f1-e53c-4a45-9003-9bf778cfac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548110510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2548110510
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1231972766
Short name T273
Test name
Test status
Simulation time 244911928 ps
CPU time 1.05 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:03 PM PDT 24
Peak memory 217440 kb
Host smart-74d5e88e-dbaf-4efe-a04b-56dc2d98f20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231972766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1231972766
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3526587871
Short name T193
Test name
Test status
Simulation time 168280723 ps
CPU time 0.92 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200100 kb
Host smart-40a5ba80-d288-4857-9490-b38ab91153ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526587871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3526587871
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2609645546
Short name T469
Test name
Test status
Simulation time 709544265 ps
CPU time 3.8 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200564 kb
Host smart-f0d3f1b0-8330-4567-bd9c-f257928e7c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609645546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2609645546
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3032126966
Short name T182
Test name
Test status
Simulation time 150456456 ps
CPU time 1.06 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:10:47 PM PDT 24
Peak memory 200248 kb
Host smart-ca437b23-f2a6-4b05-8dea-9e95736e1ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032126966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3032126966
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.476629088
Short name T23
Test name
Test status
Simulation time 117490893 ps
CPU time 1.11 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:03 PM PDT 24
Peak memory 200404 kb
Host smart-c0c06fb9-6a38-4595-9d60-7132444d3135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476629088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.476629088
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.675260457
Short name T494
Test name
Test status
Simulation time 1606344827 ps
CPU time 6.63 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200596 kb
Host smart-5e360a4f-2c29-4bb1-9ef9-c57692c08ea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675260457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.675260457
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.581613693
Short name T55
Test name
Test status
Simulation time 123313875 ps
CPU time 1.54 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 200256 kb
Host smart-bbf217a3-0451-439a-a75b-b3b575948314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581613693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.581613693
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2949808949
Short name T278
Test name
Test status
Simulation time 278232147 ps
CPU time 1.54 seconds
Started Aug 11 06:11:04 PM PDT 24
Finished Aug 11 06:11:06 PM PDT 24
Peak memory 200452 kb
Host smart-481523bc-28a4-4f80-be6d-2973304bc80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949808949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2949808949
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.2369351019
Short name T452
Test name
Test status
Simulation time 74032176 ps
CPU time 0.78 seconds
Started Aug 11 06:11:08 PM PDT 24
Finished Aug 11 06:11:09 PM PDT 24
Peak memory 200116 kb
Host smart-5c8b96b3-ddb8-4be6-9eca-220ca2ea1fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369351019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2369351019
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.443976091
Short name T50
Test name
Test status
Simulation time 2182832421 ps
CPU time 7.87 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:11:02 PM PDT 24
Peak memory 217480 kb
Host smart-415fb7b4-248f-48ad-8b48-2a390a33d6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443976091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.443976091
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1374658018
Short name T136
Test name
Test status
Simulation time 245700256 ps
CPU time 1.04 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 217452 kb
Host smart-1f056246-8261-4b15-809e-488f19cc88bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374658018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1374658018
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2048952661
Short name T258
Test name
Test status
Simulation time 126163791 ps
CPU time 0.82 seconds
Started Aug 11 06:11:06 PM PDT 24
Finished Aug 11 06:11:07 PM PDT 24
Peak memory 200136 kb
Host smart-8351a477-65cf-4448-a183-5c35fcae3694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048952661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2048952661
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3046565604
Short name T353
Test name
Test status
Simulation time 1366843387 ps
CPU time 5.42 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200500 kb
Host smart-93049118-57d0-4712-b9fa-44d01c4f8272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046565604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3046565604
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.4263971587
Short name T144
Test name
Test status
Simulation time 151072153 ps
CPU time 1.1 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 200332 kb
Host smart-990dda54-c032-4d10-a3c8-e76f5fd684d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263971587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.4263971587
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2226851195
Short name T535
Test name
Test status
Simulation time 203040178 ps
CPU time 1.35 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200544 kb
Host smart-14528f6a-614c-43a4-a315-f22fda6510a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226851195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2226851195
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3746235383
Short name T467
Test name
Test status
Simulation time 10161324184 ps
CPU time 34.95 seconds
Started Aug 11 06:10:46 PM PDT 24
Finished Aug 11 06:11:22 PM PDT 24
Peak memory 200612 kb
Host smart-c92ac7da-d49b-4c76-95b0-82ec901a2894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746235383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3746235383
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.4113736868
Short name T468
Test name
Test status
Simulation time 330982145 ps
CPU time 2.24 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:51 PM PDT 24
Peak memory 200228 kb
Host smart-2e4e9f34-ba42-4f2c-99b4-109b2816b3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113736868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.4113736868
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.4211539502
Short name T271
Test name
Test status
Simulation time 298398592 ps
CPU time 1.52 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:11:00 PM PDT 24
Peak memory 200468 kb
Host smart-3892484e-2a47-432d-ab8a-b4af6bdf05a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211539502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.4211539502
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2821669481
Short name T341
Test name
Test status
Simulation time 72191746 ps
CPU time 0.78 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:50 PM PDT 24
Peak memory 200088 kb
Host smart-32908069-653c-4343-8136-e141a99af380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821669481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2821669481
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.154500916
Short name T219
Test name
Test status
Simulation time 244483337 ps
CPU time 1.05 seconds
Started Aug 11 06:11:05 PM PDT 24
Finished Aug 11 06:11:06 PM PDT 24
Peak memory 217480 kb
Host smart-597c76c7-6b4f-4b12-a50e-6b1664e3385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154500916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.154500916
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.230194732
Short name T438
Test name
Test status
Simulation time 124742354 ps
CPU time 0.76 seconds
Started Aug 11 06:10:47 PM PDT 24
Finished Aug 11 06:10:48 PM PDT 24
Peak memory 200164 kb
Host smart-ff8e1468-dcc3-4e22-8f2f-a612a77ad654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230194732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.230194732
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.469711866
Short name T397
Test name
Test status
Simulation time 1438368431 ps
CPU time 5.93 seconds
Started Aug 11 06:10:51 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200564 kb
Host smart-f4b36f03-337d-4369-8c31-003dc555dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469711866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.469711866
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2531157270
Short name T132
Test name
Test status
Simulation time 144039835 ps
CPU time 1.08 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 200332 kb
Host smart-fe34c4af-685b-4914-af94-cf4dcb8361fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531157270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2531157270
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.688112088
Short name T531
Test name
Test status
Simulation time 192201602 ps
CPU time 1.32 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:54 PM PDT 24
Peak memory 200480 kb
Host smart-36f3618b-4ac4-457a-bb09-1c514a7a5817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688112088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.688112088
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3186958484
Short name T348
Test name
Test status
Simulation time 1960218157 ps
CPU time 9.33 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:11:04 PM PDT 24
Peak memory 200756 kb
Host smart-66b308c6-927c-4cd3-8c8f-38e9bd6734de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186958484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3186958484
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3628264580
Short name T135
Test name
Test status
Simulation time 116443696 ps
CPU time 1.46 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200200 kb
Host smart-c8a2ee8f-7c91-4dab-807e-461a2c959202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628264580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3628264580
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1648830915
Short name T179
Test name
Test status
Simulation time 289658333 ps
CPU time 1.59 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200484 kb
Host smart-a4b07f9e-1fe6-420d-8131-f3ff7a57ccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648830915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1648830915
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.4222288183
Short name T79
Test name
Test status
Simulation time 68198219 ps
CPU time 0.74 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 199964 kb
Host smart-000219cd-f40f-4831-8cb7-3d4c59cf93b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222288183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.4222288183
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2226662175
Short name T52
Test name
Test status
Simulation time 2336514294 ps
CPU time 8.56 seconds
Started Aug 11 06:10:49 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 229968 kb
Host smart-a76756a0-3de8-4258-aaeb-1fba408f9de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226662175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2226662175
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1835635899
Short name T35
Test name
Test status
Simulation time 244874082 ps
CPU time 1.07 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 217420 kb
Host smart-cf65a67e-776c-4a44-a348-59bbb626ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835635899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1835635899
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1811268548
Short name T203
Test name
Test status
Simulation time 102539559 ps
CPU time 0.8 seconds
Started Aug 11 06:10:53 PM PDT 24
Finished Aug 11 06:10:54 PM PDT 24
Peak memory 200164 kb
Host smart-6c30a9de-afc4-4c41-ae15-1ac4f286ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811268548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1811268548
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3699053912
Short name T42
Test name
Test status
Simulation time 788659232 ps
CPU time 4.08 seconds
Started Aug 11 06:11:04 PM PDT 24
Finished Aug 11 06:11:08 PM PDT 24
Peak memory 200556 kb
Host smart-2f041e5b-7bc9-41eb-bd2d-1831ceb27453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699053912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3699053912
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1180091897
Short name T1
Test name
Test status
Simulation time 150313669 ps
CPU time 1.12 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:51 PM PDT 24
Peak memory 200332 kb
Host smart-f2649db6-97da-48c3-84e8-c5f53ad2c2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180091897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1180091897
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.156514716
Short name T178
Test name
Test status
Simulation time 184080719 ps
CPU time 1.33 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200468 kb
Host smart-72382b77-625e-4836-ac99-eadb7fa75cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156514716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.156514716
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.933771753
Short name T315
Test name
Test status
Simulation time 10844833602 ps
CPU time 36.02 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:11:34 PM PDT 24
Peak memory 200672 kb
Host smart-c9dd7d77-1e73-4ced-be03-61a5ca8e7a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933771753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.933771753
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.128170248
Short name T187
Test name
Test status
Simulation time 118411404 ps
CPU time 1.5 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200236 kb
Host smart-d46c91b6-0ae8-4de2-9d5f-6aa35582d204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128170248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.128170248
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.4095528041
Short name T448
Test name
Test status
Simulation time 175648672 ps
CPU time 1.1 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200288 kb
Host smart-2378281d-4e60-43c1-b516-f428dd32d564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095528041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4095528041
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3161035781
Short name T350
Test name
Test status
Simulation time 65033820 ps
CPU time 0.8 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200160 kb
Host smart-fade8b46-1878-4f08-aef5-fef040a3ebf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161035781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3161035781
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2438243280
Short name T262
Test name
Test status
Simulation time 1230966626 ps
CPU time 5.42 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 217784 kb
Host smart-001934a5-88bb-42fa-9e9d-5bc9c9d9b1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438243280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2438243280
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.163343020
Short name T516
Test name
Test status
Simulation time 245483546 ps
CPU time 1.05 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 217512 kb
Host smart-6185794d-a701-4eb3-9d8b-a92deb040249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163343020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.163343020
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3084979679
Short name T507
Test name
Test status
Simulation time 147197539 ps
CPU time 0.79 seconds
Started Aug 11 06:11:03 PM PDT 24
Finished Aug 11 06:11:04 PM PDT 24
Peak memory 200140 kb
Host smart-771a90b6-647e-40b9-b98b-734ed30979c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084979679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3084979679
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.133775827
Short name T249
Test name
Test status
Simulation time 1561797862 ps
CPU time 6.51 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:07 PM PDT 24
Peak memory 200516 kb
Host smart-b3e571fc-765f-44d5-8fb6-01c49e17482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133775827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.133775827
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.601249640
Short name T176
Test name
Test status
Simulation time 99539022 ps
CPU time 1 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:55 PM PDT 24
Peak memory 200360 kb
Host smart-154c1bed-03a3-4b7d-8b3f-1c068ea56503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601249640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.601249640
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.3497467398
Short name T428
Test name
Test status
Simulation time 121065579 ps
CPU time 1.21 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:53 PM PDT 24
Peak memory 200484 kb
Host smart-47fbda11-da93-4231-9de7-1e0df0a15a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497467398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3497467398
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3753920788
Short name T102
Test name
Test status
Simulation time 6171244027 ps
CPU time 20.54 seconds
Started Aug 11 06:11:04 PM PDT 24
Finished Aug 11 06:11:24 PM PDT 24
Peak memory 208796 kb
Host smart-816ed3a5-e5c8-4767-b3f4-adcf3d49ddb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753920788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3753920788
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.899935237
Short name T320
Test name
Test status
Simulation time 381698423 ps
CPU time 2.23 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 200088 kb
Host smart-45b81dca-646b-4c4c-83c7-e596673f64b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899935237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.899935237
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.169101117
Short name T224
Test name
Test status
Simulation time 159699918 ps
CPU time 1.08 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200212 kb
Host smart-e9fa8646-f1cd-456b-aa59-b9f816538516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169101117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.169101117
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.3045827478
Short name T22
Test name
Test status
Simulation time 54647931 ps
CPU time 0.73 seconds
Started Aug 11 06:11:01 PM PDT 24
Finished Aug 11 06:11:02 PM PDT 24
Peak memory 200156 kb
Host smart-5a94b2a1-e201-4c7c-934c-d706436ed4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045827478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3045827478
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1470135780
Short name T372
Test name
Test status
Simulation time 1911218326 ps
CPU time 7.02 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:09 PM PDT 24
Peak memory 216828 kb
Host smart-ff13e72d-b8d5-450b-a33a-958ecd2ef59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470135780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1470135780
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1687654559
Short name T85
Test name
Test status
Simulation time 243748166 ps
CPU time 1.13 seconds
Started Aug 11 06:11:01 PM PDT 24
Finished Aug 11 06:11:02 PM PDT 24
Peak memory 217540 kb
Host smart-9ed10f95-35d9-4f5a-a86b-cce6fae8fd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687654559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1687654559
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1667336308
Short name T242
Test name
Test status
Simulation time 116941277 ps
CPU time 0.83 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200344 kb
Host smart-510594aa-ea8e-4f55-a078-5133b054732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667336308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1667336308
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.3383647124
Short name T480
Test name
Test status
Simulation time 720541557 ps
CPU time 3.7 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200536 kb
Host smart-3187424d-916b-4426-a86c-77887afa7c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383647124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3383647124
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.17683237
Short name T147
Test name
Test status
Simulation time 143952312 ps
CPU time 1.11 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 200204 kb
Host smart-c28edd9b-0ad9-4332-8d87-f7063f754475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17683237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.17683237
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2155293400
Short name T157
Test name
Test status
Simulation time 125164541 ps
CPU time 1.17 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 200348 kb
Host smart-e8e6b24b-5ffd-41ee-8687-3875d8a0317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155293400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2155293400
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3868915691
Short name T254
Test name
Test status
Simulation time 5400442744 ps
CPU time 23.21 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:11:18 PM PDT 24
Peak memory 208828 kb
Host smart-a8f597a4-4152-49b3-8322-a214afc50dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868915691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3868915691
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2744670739
Short name T492
Test name
Test status
Simulation time 309741265 ps
CPU time 2.14 seconds
Started Aug 11 06:10:59 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 208456 kb
Host smart-e8619b87-7e2f-4cdb-a2a7-742d820edf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744670739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2744670739
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3402907149
Short name T485
Test name
Test status
Simulation time 179157363 ps
CPU time 1.16 seconds
Started Aug 11 06:10:55 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200332 kb
Host smart-70337e0a-98b1-46ba-b557-1af60af42cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402907149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3402907149
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3738209159
Short name T130
Test name
Test status
Simulation time 69449617 ps
CPU time 0.8 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200120 kb
Host smart-54921103-4cd0-47da-af7e-a25cc6a6f53d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738209159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3738209159
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.509461052
Short name T402
Test name
Test status
Simulation time 2341551863 ps
CPU time 9.14 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:11:08 PM PDT 24
Peak memory 217800 kb
Host smart-af3cc0e6-3e57-4981-bb6e-28a60b0e1584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509461052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.509461052
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2592456109
Short name T302
Test name
Test status
Simulation time 247874655 ps
CPU time 1.14 seconds
Started Aug 11 06:10:50 PM PDT 24
Finished Aug 11 06:10:51 PM PDT 24
Peak memory 217548 kb
Host smart-f2e5d147-8057-4fe4-9d26-a2a44fdd9ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592456109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2592456109
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.687779660
Short name T205
Test name
Test status
Simulation time 199736220 ps
CPU time 0.87 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200120 kb
Host smart-edf747d6-fb29-445a-b75f-468cd9a48a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687779660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.687779660
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1871288648
Short name T446
Test name
Test status
Simulation time 1768210989 ps
CPU time 6.47 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200504 kb
Host smart-f7dec7c6-85c1-498f-b99f-59aa6f997f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871288648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1871288648
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3012314315
Short name T229
Test name
Test status
Simulation time 103416599 ps
CPU time 1 seconds
Started Aug 11 06:11:03 PM PDT 24
Finished Aug 11 06:11:04 PM PDT 24
Peak memory 200228 kb
Host smart-8ebdd088-b9a0-424b-8296-2e15660cb5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012314315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3012314315
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.4235616278
Short name T58
Test name
Test status
Simulation time 258360722 ps
CPU time 1.59 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200520 kb
Host smart-9e6bcae4-3ba4-4c41-b575-c4248d476f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235616278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4235616278
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1551478425
Short name T425
Test name
Test status
Simulation time 3487775093 ps
CPU time 15.44 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:11:12 PM PDT 24
Peak memory 216972 kb
Host smart-f1871019-7bc1-4340-839a-9c51966a8ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551478425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1551478425
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2925470571
Short name T333
Test name
Test status
Simulation time 421322240 ps
CPU time 2.41 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200272 kb
Host smart-0ee12237-a315-4844-9211-004e05f3bbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925470571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2925470571
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.462042603
Short name T344
Test name
Test status
Simulation time 160164319 ps
CPU time 1.06 seconds
Started Aug 11 06:10:57 PM PDT 24
Finished Aug 11 06:10:58 PM PDT 24
Peak memory 200204 kb
Host smart-12f7bb41-fbc1-4cee-8def-a7b6d1d305ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462042603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.462042603
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.537879664
Short name T432
Test name
Test status
Simulation time 57068395 ps
CPU time 0.73 seconds
Started Aug 11 06:11:17 PM PDT 24
Finished Aug 11 06:11:18 PM PDT 24
Peak memory 200088 kb
Host smart-6dd2542e-e1ac-4092-a8fd-3b5f9d56dcf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537879664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.537879664
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1916541810
Short name T29
Test name
Test status
Simulation time 1901426283 ps
CPU time 6.69 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:09 PM PDT 24
Peak memory 221612 kb
Host smart-a710c067-b71e-4613-b85e-068f5d91c972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916541810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1916541810
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.587771655
Short name T280
Test name
Test status
Simulation time 244817573 ps
CPU time 1.09 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 217508 kb
Host smart-ec741783-2452-491c-a277-485bef86b6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587771655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.587771655
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.106511212
Short name T16
Test name
Test status
Simulation time 94322059 ps
CPU time 0.82 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200088 kb
Host smart-72895d18-16e7-43c9-99eb-d637c9a06e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106511212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.106511212
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1584227524
Short name T423
Test name
Test status
Simulation time 961044238 ps
CPU time 4.7 seconds
Started Aug 11 06:10:52 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200564 kb
Host smart-56ae098c-82b9-48b5-9151-724ae7159d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584227524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1584227524
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2444387269
Short name T248
Test name
Test status
Simulation time 182375042 ps
CPU time 1.25 seconds
Started Aug 11 06:11:00 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200360 kb
Host smart-83c5b6d1-9a48-44ab-beb5-9d85e19d61c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444387269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2444387269
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.4207363631
Short name T88
Test name
Test status
Simulation time 117997302 ps
CPU time 1.24 seconds
Started Aug 11 06:10:54 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200472 kb
Host smart-61b8bada-1307-4cb6-9de8-c813cea6a400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207363631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.4207363631
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.211149268
Short name T284
Test name
Test status
Simulation time 1433242982 ps
CPU time 5.53 seconds
Started Aug 11 06:11:23 PM PDT 24
Finished Aug 11 06:11:28 PM PDT 24
Peak memory 200540 kb
Host smart-dcb5b529-8c96-44fb-94d3-aaf14d3fc7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211149268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.211149268
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.722308543
Short name T491
Test name
Test status
Simulation time 416107820 ps
CPU time 2.36 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:11:00 PM PDT 24
Peak memory 208452 kb
Host smart-50c12093-2d97-44e0-98a7-95ffdc0c9cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722308543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.722308543
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2124784327
Short name T482
Test name
Test status
Simulation time 218160747 ps
CPU time 1.36 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:04 PM PDT 24
Peak memory 200372 kb
Host smart-6af0a396-0a72-4b2e-a3b8-1b70f2288ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124784327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2124784327
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3716831292
Short name T419
Test name
Test status
Simulation time 66530695 ps
CPU time 0.75 seconds
Started Aug 11 06:11:06 PM PDT 24
Finished Aug 11 06:11:07 PM PDT 24
Peak memory 200144 kb
Host smart-460cad8b-4690-4470-8add-b5af64b7d546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716831292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3716831292
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1198032738
Short name T370
Test name
Test status
Simulation time 2182801006 ps
CPU time 7.66 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:11:06 PM PDT 24
Peak memory 221608 kb
Host smart-abfed253-0244-40e8-8a71-cb9f58d6da5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198032738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1198032738
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1110872795
Short name T327
Test name
Test status
Simulation time 244163186 ps
CPU time 1.09 seconds
Started Aug 11 06:11:10 PM PDT 24
Finished Aug 11 06:11:12 PM PDT 24
Peak memory 217480 kb
Host smart-71b7b35d-aec5-485b-80a4-a2eac1a50351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110872795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1110872795
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3499523800
Short name T6
Test name
Test status
Simulation time 133747028 ps
CPU time 0.94 seconds
Started Aug 11 06:11:01 PM PDT 24
Finished Aug 11 06:11:02 PM PDT 24
Peak memory 200132 kb
Host smart-84c67143-4058-4f0f-b0eb-5faac91f73d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499523800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3499523800
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2420303579
Short name T121
Test name
Test status
Simulation time 1830004437 ps
CPU time 6.47 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:08 PM PDT 24
Peak memory 200716 kb
Host smart-3495ce44-4551-435c-9d86-069394261626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420303579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2420303579
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.574023167
Short name T396
Test name
Test status
Simulation time 156532451 ps
CPU time 1.12 seconds
Started Aug 11 06:11:10 PM PDT 24
Finished Aug 11 06:11:11 PM PDT 24
Peak memory 200364 kb
Host smart-71f9c3e3-6d6f-48e2-947b-b657fa83a51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574023167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.574023167
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1457221478
Short name T264
Test name
Test status
Simulation time 119487132 ps
CPU time 1.25 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 200496 kb
Host smart-d63cc4cc-3cdb-4ed4-a1e4-d093661057ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457221478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1457221478
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1201551582
Short name T99
Test name
Test status
Simulation time 6264072910 ps
CPU time 28.52 seconds
Started Aug 11 06:11:02 PM PDT 24
Finished Aug 11 06:11:30 PM PDT 24
Peak memory 209568 kb
Host smart-7f0152d6-6b58-423d-9301-26ebc19aaaf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201551582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1201551582
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3990775986
Short name T461
Test name
Test status
Simulation time 142331410 ps
CPU time 1.76 seconds
Started Aug 11 06:11:06 PM PDT 24
Finished Aug 11 06:11:08 PM PDT 24
Peak memory 200188 kb
Host smart-6f4f500b-49fc-4099-8412-17b259469c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990775986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3990775986
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2379044166
Short name T375
Test name
Test status
Simulation time 191698819 ps
CPU time 1.34 seconds
Started Aug 11 06:10:59 PM PDT 24
Finished Aug 11 06:11:01 PM PDT 24
Peak memory 200364 kb
Host smart-38b4cace-9bbe-4972-9ef5-73243106dd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379044166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2379044166
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4002168747
Short name T308
Test name
Test status
Simulation time 62564058 ps
CPU time 0.83 seconds
Started Aug 11 06:11:01 PM PDT 24
Finished Aug 11 06:11:02 PM PDT 24
Peak memory 200164 kb
Host smart-07dc2954-8882-4028-9606-67d778654869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002168747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4002168747
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3274750759
Short name T56
Test name
Test status
Simulation time 244037211 ps
CPU time 1.12 seconds
Started Aug 11 06:10:58 PM PDT 24
Finished Aug 11 06:10:59 PM PDT 24
Peak memory 217480 kb
Host smart-0fae6396-f81b-45d9-9f73-48702e32c9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274750759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3274750759
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1569763307
Short name T18
Test name
Test status
Simulation time 137786958 ps
CPU time 0.83 seconds
Started Aug 11 06:10:56 PM PDT 24
Finished Aug 11 06:10:56 PM PDT 24
Peak memory 200156 kb
Host smart-670ade0a-dd96-4d87-80d4-8c34896a08b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569763307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1569763307
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.377067061
Short name T261
Test name
Test status
Simulation time 1609053110 ps
CPU time 5.7 seconds
Started Aug 11 06:11:23 PM PDT 24
Finished Aug 11 06:11:29 PM PDT 24
Peak memory 200536 kb
Host smart-7549566e-ceb2-4f7a-971c-89fbf5ddc4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377067061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.377067061
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3086282348
Short name T239
Test name
Test status
Simulation time 153499944 ps
CPU time 1.07 seconds
Started Aug 11 06:11:11 PM PDT 24
Finished Aug 11 06:11:12 PM PDT 24
Peak memory 200336 kb
Host smart-3be7445d-da14-45b2-834f-3e2ffee27cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086282348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3086282348
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3241165191
Short name T444
Test name
Test status
Simulation time 109908979 ps
CPU time 1.15 seconds
Started Aug 11 06:11:15 PM PDT 24
Finished Aug 11 06:11:17 PM PDT 24
Peak memory 200340 kb
Host smart-38f8c658-7a6b-4714-ac2f-6c01ff837d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241165191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3241165191
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3908456196
Short name T105
Test name
Test status
Simulation time 9001315579 ps
CPU time 31.38 seconds
Started Aug 11 06:11:22 PM PDT 24
Finished Aug 11 06:11:54 PM PDT 24
Peak memory 216960 kb
Host smart-16ccd008-d6e7-4692-bf47-d93073697aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908456196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3908456196
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3267157764
Short name T465
Test name
Test status
Simulation time 535571105 ps
CPU time 2.64 seconds
Started Aug 11 06:11:16 PM PDT 24
Finished Aug 11 06:11:19 PM PDT 24
Peak memory 200212 kb
Host smart-729070f3-9701-476a-a1ed-5544c6173252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267157764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3267157764
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.83302366
Short name T391
Test name
Test status
Simulation time 217458245 ps
CPU time 1.35 seconds
Started Aug 11 06:11:21 PM PDT 24
Finished Aug 11 06:11:23 PM PDT 24
Peak memory 200264 kb
Host smart-471687c2-a25b-4ad9-b2f6-a1c7f23a1221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83302366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.83302366
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.252545394
Short name T314
Test name
Test status
Simulation time 78824371 ps
CPU time 0.78 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 200156 kb
Host smart-8f036a80-f43c-47f6-8a10-b148b0fc7d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252545394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.252545394
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2296885598
Short name T472
Test name
Test status
Simulation time 1221706547 ps
CPU time 6.03 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 221272 kb
Host smart-350b6a90-0ccc-4adc-8e15-9c0e362014cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296885598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2296885598
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4156171984
Short name T390
Test name
Test status
Simulation time 244821164 ps
CPU time 1.1 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 217520 kb
Host smart-ae6d19b9-f3f2-4bec-9f8f-3e83aa20d0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156171984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4156171984
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1515248720
Short name T17
Test name
Test status
Simulation time 159694854 ps
CPU time 0.81 seconds
Started Aug 11 06:09:56 PM PDT 24
Finished Aug 11 06:09:57 PM PDT 24
Peak memory 200032 kb
Host smart-4ca8fffd-8bfb-404e-b015-53a9113b417c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515248720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1515248720
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2888906033
Short name T40
Test name
Test status
Simulation time 1884920988 ps
CPU time 7.03 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 200512 kb
Host smart-10ccc039-1a74-4c7d-9949-2f58b91059ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888906033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2888906033
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.51276325
Short name T272
Test name
Test status
Simulation time 104289458 ps
CPU time 1.09 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 200380 kb
Host smart-b8e36212-1856-43ed-abee-90f5fc2f8b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51276325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.51276325
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3720276171
Short name T481
Test name
Test status
Simulation time 234414185 ps
CPU time 1.5 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 200492 kb
Host smart-1632a920-c45b-41f1-b86f-7b498d0cce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720276171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3720276171
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.4141703232
Short name T103
Test name
Test status
Simulation time 17494338948 ps
CPU time 56.65 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:57 PM PDT 24
Peak memory 200496 kb
Host smart-dd990d24-52c0-4396-938f-a2e514dbd4c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141703232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4141703232
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1968341231
Short name T171
Test name
Test status
Simulation time 418333240 ps
CPU time 2.25 seconds
Started Aug 11 06:10:14 PM PDT 24
Finished Aug 11 06:10:16 PM PDT 24
Peak memory 200328 kb
Host smart-937a7507-32da-4cfe-b1d0-cd4c0a22af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968341231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1968341231
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.3940093368
Short name T504
Test name
Test status
Simulation time 162982953 ps
CPU time 1.36 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:09:54 PM PDT 24
Peak memory 200544 kb
Host smart-20ee39d7-6cda-4b4d-92fa-40b59f5c15b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940093368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3940093368
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.307779506
Short name T412
Test name
Test status
Simulation time 83731100 ps
CPU time 0.81 seconds
Started Aug 11 06:09:57 PM PDT 24
Finished Aug 11 06:09:58 PM PDT 24
Peak memory 200060 kb
Host smart-23301c22-12d6-4e81-b4e0-6a864424d6f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307779506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.307779506
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.3911503128
Short name T61
Test name
Test status
Simulation time 1890633903 ps
CPU time 7.28 seconds
Started Aug 11 06:10:14 PM PDT 24
Finished Aug 11 06:10:22 PM PDT 24
Peak memory 217560 kb
Host smart-b30306c6-7cd4-46b0-a8cf-b2d738486887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911503128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3911503128
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.112629459
Short name T169
Test name
Test status
Simulation time 244407072 ps
CPU time 1.06 seconds
Started Aug 11 06:09:58 PM PDT 24
Finished Aug 11 06:09:59 PM PDT 24
Peak memory 217444 kb
Host smart-e3e7719b-90b0-464e-95b7-6807c2094d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112629459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.112629459
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.1267196471
Short name T21
Test name
Test status
Simulation time 117606139 ps
CPU time 0.83 seconds
Started Aug 11 06:10:14 PM PDT 24
Finished Aug 11 06:10:15 PM PDT 24
Peak memory 199964 kb
Host smart-88699a5a-99a1-40c7-ae8a-41b2ffcc25b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267196471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1267196471
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2177673458
Short name T149
Test name
Test status
Simulation time 1320616341 ps
CPU time 5.22 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 200524 kb
Host smart-4d316d7a-83bb-4985-8616-2dcb5f719f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177673458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2177673458
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.432230922
Short name T198
Test name
Test status
Simulation time 175913993 ps
CPU time 1.11 seconds
Started Aug 11 06:09:55 PM PDT 24
Finished Aug 11 06:09:56 PM PDT 24
Peak memory 200188 kb
Host smart-6ace0a92-d4f7-4889-8162-7ccfe4e64d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432230922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.432230922
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.2577219607
Short name T123
Test name
Test status
Simulation time 242732620 ps
CPU time 1.57 seconds
Started Aug 11 06:09:57 PM PDT 24
Finished Aug 11 06:09:58 PM PDT 24
Peak memory 200456 kb
Host smart-953d6271-0ab4-4d63-a8cc-a9cc3438b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577219607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2577219607
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1413877569
Short name T398
Test name
Test status
Simulation time 4245221445 ps
CPU time 14.36 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:14 PM PDT 24
Peak memory 200608 kb
Host smart-404c9e7d-70d7-4e5e-b72d-2a9f3a94967f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413877569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1413877569
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.733757796
Short name T166
Test name
Test status
Simulation time 314249771 ps
CPU time 2.41 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 200244 kb
Host smart-9a7bb29a-783b-488f-907b-b5b32c7a8744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733757796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.733757796
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.983030665
Short name T484
Test name
Test status
Simulation time 175829679 ps
CPU time 1.39 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:04 PM PDT 24
Peak memory 200384 kb
Host smart-9749b7ba-38c6-4837-acac-242178222b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983030665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.983030665
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.402809054
Short name T447
Test name
Test status
Simulation time 76814692 ps
CPU time 0.86 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 200008 kb
Host smart-ea68ddb8-09ce-497a-a0d0-d801ee586c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402809054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.402809054
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1088832952
Short name T364
Test name
Test status
Simulation time 2368017844 ps
CPU time 8.46 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:11 PM PDT 24
Peak memory 217796 kb
Host smart-4a1ec693-d42c-453b-aa13-d11fe89de8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088832952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1088832952
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2647973104
Short name T499
Test name
Test status
Simulation time 244984012 ps
CPU time 1.12 seconds
Started Aug 11 06:10:04 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 217492 kb
Host smart-fe1624a8-96c2-4c59-8e07-e002771a4634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647973104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2647973104
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2860402517
Short name T501
Test name
Test status
Simulation time 119122761 ps
CPU time 0.82 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 200112 kb
Host smart-9f21b441-3a99-49ae-9da3-2446cb27a639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860402517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2860402517
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3628505941
Short name T160
Test name
Test status
Simulation time 1536117620 ps
CPU time 5.98 seconds
Started Aug 11 06:10:07 PM PDT 24
Finished Aug 11 06:10:13 PM PDT 24
Peak memory 200568 kb
Host smart-4d91a405-a137-46db-a1da-c7bf27af4b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628505941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3628505941
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2916769050
Short name T386
Test name
Test status
Simulation time 95449591 ps
CPU time 0.98 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 200188 kb
Host smart-511d58bf-8133-47e9-b8a7-dd62f772363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916769050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2916769050
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.2445376275
Short name T514
Test name
Test status
Simulation time 196732115 ps
CPU time 1.51 seconds
Started Aug 11 06:09:58 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 200332 kb
Host smart-3307e806-2e7f-4043-8b4c-a0abd6f43981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445376275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2445376275
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1820728877
Short name T13
Test name
Test status
Simulation time 3417105532 ps
CPU time 15.39 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:16 PM PDT 24
Peak memory 200592 kb
Host smart-7a9acf8d-c998-4da0-8e53-8ae05fe0d95d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820728877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1820728877
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3063094310
Short name T63
Test name
Test status
Simulation time 131986783 ps
CPU time 1.51 seconds
Started Aug 11 06:10:09 PM PDT 24
Finished Aug 11 06:10:11 PM PDT 24
Peak memory 200184 kb
Host smart-deb1f5ff-4abd-4877-adc4-8091ba93616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063094310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3063094310
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1273918194
Short name T497
Test name
Test status
Simulation time 128861622 ps
CPU time 1.09 seconds
Started Aug 11 06:10:07 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 200348 kb
Host smart-4ac60b60-d2db-4058-9a54-7ee86ec992fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273918194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1273918194
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3993263325
Short name T191
Test name
Test status
Simulation time 61609834 ps
CPU time 0.71 seconds
Started Aug 11 06:10:12 PM PDT 24
Finished Aug 11 06:10:12 PM PDT 24
Peak memory 200048 kb
Host smart-994aebf1-ef1a-4668-bf12-8ef4fc71e8a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993263325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3993263325
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.441667033
Short name T433
Test name
Test status
Simulation time 1216171288 ps
CPU time 5.73 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:08 PM PDT 24
Peak memory 217496 kb
Host smart-700fff54-3d44-42c9-8bbd-4d2341671c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441667033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.441667033
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3326241924
Short name T463
Test name
Test status
Simulation time 243990765 ps
CPU time 1.14 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 217536 kb
Host smart-f35f5d2c-8257-458b-9831-e1342dff1c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326241924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3326241924
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3250594519
Short name T194
Test name
Test status
Simulation time 216911995 ps
CPU time 0.89 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 200136 kb
Host smart-7d773395-91c2-44da-958f-21f009c247cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250594519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3250594519
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3747602482
Short name T414
Test name
Test status
Simulation time 2131633113 ps
CPU time 8.39 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:13 PM PDT 24
Peak memory 200556 kb
Host smart-7ee35d12-1c01-4b00-9d03-50bbd812cdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747602482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3747602482
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.944835675
Short name T195
Test name
Test status
Simulation time 148868291 ps
CPU time 1.21 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200264 kb
Host smart-dca0e5d4-7ea0-4ac1-9afb-dde1f3cad5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944835675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.944835675
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2742064183
Short name T164
Test name
Test status
Simulation time 246816791 ps
CPU time 1.57 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:04 PM PDT 24
Peak memory 200388 kb
Host smart-a06082d7-5820-4c9c-bee6-f98651f24362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742064183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2742064183
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3807722106
Short name T403
Test name
Test status
Simulation time 986036936 ps
CPU time 4.3 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:09 PM PDT 24
Peak memory 200408 kb
Host smart-9aced57b-767a-4107-9e2f-20e12dc8b61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807722106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3807722106
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3463467157
Short name T305
Test name
Test status
Simulation time 297152390 ps
CPU time 2.17 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 208500 kb
Host smart-674af4c4-8d45-4b05-919c-b8e0f469414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463467157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3463467157
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.173042783
Short name T526
Test name
Test status
Simulation time 152871038 ps
CPU time 1.21 seconds
Started Aug 11 06:10:06 PM PDT 24
Finished Aug 11 06:10:07 PM PDT 24
Peak memory 200448 kb
Host smart-4aca67db-270f-47bc-b4f2-f4fe9686c258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173042783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.173042783
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2549949334
Short name T237
Test name
Test status
Simulation time 85368288 ps
CPU time 0.8 seconds
Started Aug 11 06:10:05 PM PDT 24
Finished Aug 11 06:10:06 PM PDT 24
Peak memory 200180 kb
Host smart-6f605150-872d-402b-a5b0-d51befc6a4f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549949334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2549949334
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.278063658
Short name T43
Test name
Test status
Simulation time 1214250862 ps
CPU time 5.97 seconds
Started Aug 11 06:10:11 PM PDT 24
Finished Aug 11 06:10:17 PM PDT 24
Peak memory 217524 kb
Host smart-5647b5fc-292b-45da-82d9-5fcfc1627766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278063658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.278063658
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1280863907
Short name T515
Test name
Test status
Simulation time 244194864 ps
CPU time 1.09 seconds
Started Aug 11 06:10:10 PM PDT 24
Finished Aug 11 06:10:11 PM PDT 24
Peak memory 217548 kb
Host smart-8b880324-d1d1-4701-92b9-5801440c3fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280863907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1280863907
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2979430925
Short name T269
Test name
Test status
Simulation time 171034432 ps
CPU time 0.84 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 200084 kb
Host smart-3a564ed2-01c0-41a6-b0ce-93d805ae9d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979430925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2979430925
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3099016580
Short name T207
Test name
Test status
Simulation time 847995085 ps
CPU time 4.67 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200792 kb
Host smart-c7b5c554-dc86-4e5a-ae0a-2bb4f67ec422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099016580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3099016580
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4238644617
Short name T300
Test name
Test status
Simulation time 142199854 ps
CPU time 1.07 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:05 PM PDT 24
Peak memory 200364 kb
Host smart-6f755131-5d39-4bfa-b65c-b763acb6c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238644617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.4238644617
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2943228187
Short name T330
Test name
Test status
Simulation time 190023527 ps
CPU time 1.37 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:04 PM PDT 24
Peak memory 200348 kb
Host smart-2cee5884-8539-491c-a4f8-ef0f811ce3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943228187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2943228187
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.3503286135
Short name T202
Test name
Test status
Simulation time 10426326127 ps
CPU time 36.57 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:38 PM PDT 24
Peak memory 210140 kb
Host smart-fe728cfe-6722-4c97-82da-fd3de186aac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503286135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3503286135
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2340508927
Short name T523
Test name
Test status
Simulation time 351703507 ps
CPU time 2.33 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 200188 kb
Host smart-bf356a5b-0757-4513-ae15-c9ff285f4037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340508927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2340508927
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.517328
Short name T474
Test name
Test status
Simulation time 133733414 ps
CPU time 1.09 seconds
Started Aug 11 06:10:01 PM PDT 24
Finished Aug 11 06:10:02 PM PDT 24
Peak memory 200364 kb
Host smart-83e14577-ad36-46ce-abf4-2549a3397e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.517328
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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