Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7748

1

T1

20

T3

18

T11

18

auto[1]

10921

1

T1

81

T3

83

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5831	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6315	1			T1	27		T2	1		T3	27
reset_info_cp[2]	2839	1			T1	17		T3	12		T4	1
reset_info_cp[4]	3751	1			T1	14		T3	21		T4	1
reset_info_cp[8]	108	1			T1	2		T11	1		T14	1
reset_info_cp[16]	121	1			T12	1		T14	1		T79	1
reset_info_cp[32]	83	1			T3	1		T12	2		T33	1
reset_info_cp[64]	124	1			T1	2		T11	2		T12	1
reset_info_cp[128]	117	1			T7	1		T12	1		T33	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2996	1			T1	20		T3	18		T11	18
reset_info_cp[1]	auto[1]	2699	1			T1	6		T3	8		T4	1
reset_info_cp[2]	auto[0]	858	1			T14	13		T79	2		T29	11
reset_info_cp[2]	auto[1]	1981	1			T1	17		T3	12		T4	1
reset_info_cp[4]	auto[0]	1265	1			T14	24		T79	7		T29	17
reset_info_cp[4]	auto[1]	2486	1			T1	14		T3	21		T4	1
reset_info_cp[8]	auto[0]	37	1			T97	3		T138	1		T102	1
reset_info_cp[8]	auto[1]	71	1			T1	2		T11	1		T14	1
reset_info_cp[16]	auto[0]	52	1			T12	1		T14	1		T136	2
reset_info_cp[16]	auto[1]	69	1			T79	1		T29	1		T91	1
reset_info_cp[32]	auto[0]	31	1			T12	2		T97	2		T100	1
reset_info_cp[32]	auto[1]	52	1			T3	1		T33	1		T29	2
reset_info_cp[64]	auto[0]	59	1			T12	1		T29	1		T137	1
reset_info_cp[64]	auto[1]	65	1			T1	2		T11	2		T14	2
reset_info_cp[128]	auto[0]	40	1			T12	1		T79	1		T29	1
reset_info_cp[128]	auto[1]	77	1			T7	1		T33	1		T29	2