Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
count_cp	4	0	4	100.00	100	1	1	0
length_cp	8	0	8	100.00	100	1	1	0

Summary for Variable count_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for count_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9717	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cb[0]	1298	1			T1	3		T2	1		T3	3
cb[1]	1146	1			T1	4		T3	4		T5	20
cb[2]	1076	1			T1	4		T3	4		T5	20
cb[3]	1010	1			T1	4		T3	4		T5	20

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Summary for Variable length_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for length_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11605	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lb[0]	414	1			T1	3		T3	1		T5	27
lb[1]	341	1			T1	1		T5	18		T11	3
lb[2]	344	1			T1	2		T3	1		T5	19
lb[3]	309	1			T1	4		T3	1		T5	21
lb[4]	333	1			T3	1		T5	21		T11	1
lb[5]	314	1			T5	16		T14	2		T33	3
lb[6]	335	1			T5	30		T14	1		T33	2
lb[7]	252	1			T1	1		T3	1		T5	23