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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T541 /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2988942089 Aug 12 05:19:01 PM PDT 24 Aug 12 05:19:02 PM PDT 24 106747478 ps
T542 /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3229795068 Aug 12 05:19:00 PM PDT 24 Aug 12 05:19:01 PM PDT 24 244986912 ps
T543 /workspace/coverage/default/17.rstmgr_stress_all.749873311 Aug 12 05:18:23 PM PDT 24 Aug 12 05:18:41 PM PDT 24 5033121994 ps
T544 /workspace/coverage/default/37.rstmgr_sw_rst.3393339617 Aug 12 05:18:47 PM PDT 24 Aug 12 05:18:49 PM PDT 24 129773744 ps
T545 /workspace/coverage/default/29.rstmgr_reset.2727374171 Aug 12 05:18:42 PM PDT 24 Aug 12 05:18:48 PM PDT 24 1421051208 ps
T65 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3113543214 Aug 12 05:17:24 PM PDT 24 Aug 12 05:17:25 PM PDT 24 187247080 ps
T66 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.472674863 Aug 12 05:17:13 PM PDT 24 Aug 12 05:17:17 PM PDT 24 274153080 ps
T67 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2729828252 Aug 12 05:17:27 PM PDT 24 Aug 12 05:17:28 PM PDT 24 84290706 ps
T69 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.888642248 Aug 12 05:17:22 PM PDT 24 Aug 12 05:17:24 PM PDT 24 221782811 ps
T68 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3710452790 Aug 12 05:17:16 PM PDT 24 Aug 12 05:17:17 PM PDT 24 73068628 ps
T70 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4265933443 Aug 12 05:17:13 PM PDT 24 Aug 12 05:17:14 PM PDT 24 113821544 ps
T71 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3504611308 Aug 12 05:17:25 PM PDT 24 Aug 12 05:17:26 PM PDT 24 191452845 ps
T72 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3461642863 Aug 12 05:17:29 PM PDT 24 Aug 12 05:17:31 PM PDT 24 427245661 ps
T73 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4059153465 Aug 12 05:17:37 PM PDT 24 Aug 12 05:17:39 PM PDT 24 129397368 ps
T85 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.476489227 Aug 12 05:17:24 PM PDT 24 Aug 12 05:17:27 PM PDT 24 503121009 ps
T86 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2548701420 Aug 12 05:17:28 PM PDT 24 Aug 12 05:17:29 PM PDT 24 212571143 ps
T87 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1551538601 Aug 12 05:17:22 PM PDT 24 Aug 12 05:17:23 PM PDT 24 127902610 ps
T88 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1297276036 Aug 12 05:17:40 PM PDT 24 Aug 12 05:17:41 PM PDT 24 105985257 ps
T105 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1173345834 Aug 12 05:17:37 PM PDT 24 Aug 12 05:17:39 PM PDT 24 131036349 ps
T74 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1514545029 Aug 12 05:17:24 PM PDT 24 Aug 12 05:17:26 PM PDT 24 480406798 ps
T89 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3637354415 Aug 12 05:17:15 PM PDT 24 Aug 12 05:17:16 PM PDT 24 95703448 ps
T122 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1209227460 Aug 12 05:17:22 PM PDT 24 Aug 12 05:17:24 PM PDT 24 497959710 ps
T106 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2728420751 Aug 12 05:17:31 PM PDT 24 Aug 12 05:17:32 PM PDT 24 77289894 ps
T90 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1346681620 Aug 12 05:17:13 PM PDT 24 Aug 12 05:17:17 PM PDT 24 959951644 ps
T107 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2404059935 Aug 12 05:17:24 PM PDT 24 Aug 12 05:17:25 PM PDT 24 58870081 ps
T546 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.726009203 Aug 12 05:17:15 PM PDT 24 Aug 12 05:17:16 PM PDT 24 113825674 ps
T113 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.666434194 Aug 12 05:17:22 PM PDT 24 Aug 12 05:17:24 PM PDT 24 170405642 ps
T547 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3771802255 Aug 12 05:17:28 PM PDT 24 Aug 12 05:17:29 PM PDT 24 92239042 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2833408363 Aug 12 05:17:06 PM PDT 24 Aug 12 05:17:07 PM PDT 24 80988622 ps
T549 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2067953881 Aug 12 05:17:27 PM PDT 24 Aug 12 05:17:29 PM PDT 24 512360273 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2168749516 Aug 12 05:17:05 PM PDT 24 Aug 12 05:17:06 PM PDT 24 196125436 ps
T120 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3209045140 Aug 12 05:17:25 PM PDT 24 Aug 12 05:17:28 PM PDT 24 1083781453 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2955939534 Aug 12 05:17:02 PM PDT 24 Aug 12 05:17:04 PM PDT 24 165367475 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1192884501 Aug 12 05:17:03 PM PDT 24 Aug 12 05:17:04 PM PDT 24 108748572 ps
T124 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2081517678 Aug 12 05:17:24 PM PDT 24 Aug 12 05:17:25 PM PDT 24 186234492 ps
T108 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.467610665 Aug 12 05:17:17 PM PDT 24 Aug 12 05:17:18 PM PDT 24 82622829 ps
T115 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2190035917 Aug 12 05:17:08 PM PDT 24 Aug 12 05:17:10 PM PDT 24 190997455 ps
T123 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3010010182 Aug 12 05:17:10 PM PDT 24 Aug 12 05:17:12 PM PDT 24 151902949 ps
T109 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3975836685 Aug 12 05:17:30 PM PDT 24 Aug 12 05:17:31 PM PDT 24 64365797 ps
T553 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.601527101 Aug 12 05:17:12 PM PDT 24 Aug 12 05:17:13 PM PDT 24 189661471 ps
T110 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3187353815 Aug 12 05:17:06 PM PDT 24 Aug 12 05:17:08 PM PDT 24 195981238 ps
T554 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2008851544 Aug 12 05:17:00 PM PDT 24 Aug 12 05:17:01 PM PDT 24 89331977 ps
T555 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1008303281 Aug 12 05:17:23 PM PDT 24 Aug 12 05:17:24 PM PDT 24 66737165 ps
T556 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3101437401 Aug 12 05:17:03 PM PDT 24 Aug 12 05:17:04 PM PDT 24 98646628 ps
T557 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3129637473 Aug 12 05:17:30 PM PDT 24 Aug 12 05:17:31 PM PDT 24 69489885 ps
T111 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3284738210 Aug 12 05:17:24 PM PDT 24 Aug 12 05:17:26 PM PDT 24 67229995 ps
T116 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1962262762 Aug 12 05:17:16 PM PDT 24 Aug 12 05:17:19 PM PDT 24 909128821 ps
T558 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2270639618 Aug 12 05:16:58 PM PDT 24 Aug 12 05:16:59 PM PDT 24 127076343 ps
T559 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.234557258 Aug 12 05:17:13 PM PDT 24 Aug 12 05:17:14 PM PDT 24 82576671 ps
T125 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4075769997 Aug 12 05:17:04 PM PDT 24 Aug 12 05:17:05 PM PDT 24 429702929 ps
T560 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1992702836 Aug 12 05:17:14 PM PDT 24 Aug 12 05:17:16 PM PDT 24 421861330 ps
T117 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3374023980 Aug 12 05:17:20 PM PDT 24 Aug 12 05:17:22 PM PDT 24 312731743 ps
T561 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.871821001 Aug 12 05:17:27 PM PDT 24 Aug 12 05:17:28 PM PDT 24 197280164 ps
T114 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3913399463 Aug 12 05:17:28 PM PDT 24 Aug 12 05:17:31 PM PDT 24 215444057 ps
T562 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3351528139 Aug 12 05:17:22 PM PDT 24 Aug 12 05:17:26 PM PDT 24 598988180 ps
T118 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1784329778 Aug 12 05:17:27 PM PDT 24 Aug 12 05:17:30 PM PDT 24 826002450 ps
T563 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3678611643 Aug 12 05:17:04 PM PDT 24 Aug 12 05:17:07 PM PDT 24 570955228 ps
T564 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1889502960 Aug 12 05:17:04 PM PDT 24 Aug 12 05:17:05 PM PDT 24 126273235 ps
T565 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2836677405 Aug 12 05:17:12 PM PDT 24 Aug 12 05:17:15 PM PDT 24 459650816 ps
T566 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1398955116 Aug 12 05:17:02 PM PDT 24 Aug 12 05:17:07 PM PDT 24 803488182 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4034918748 Aug 12 05:17:17 PM PDT 24 Aug 12 05:17:18 PM PDT 24 119702211 ps
T568 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3927303655 Aug 12 05:17:15 PM PDT 24 Aug 12 05:17:18 PM PDT 24 530294782 ps
T569 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.550722141 Aug 12 05:17:30 PM PDT 24 Aug 12 05:17:32 PM PDT 24 122784483 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.194749715 Aug 12 05:17:08 PM PDT 24 Aug 12 05:17:10 PM PDT 24 361280736 ps
T112 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3735149023 Aug 12 05:17:29 PM PDT 24 Aug 12 05:17:30 PM PDT 24 107454654 ps
T571 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3888791252 Aug 12 05:17:15 PM PDT 24 Aug 12 05:17:16 PM PDT 24 59317086 ps
T572 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3943372385 Aug 12 05:17:09 PM PDT 24 Aug 12 05:17:10 PM PDT 24 91152306 ps
T133 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.182174704 Aug 12 05:17:22 PM PDT 24 Aug 12 05:17:24 PM PDT 24 536703573 ps
T573 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.68265345 Aug 12 05:17:13 PM PDT 24 Aug 12 05:17:14 PM PDT 24 116573355 ps
T135 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1083236385 Aug 12 05:17:06 PM PDT 24 Aug 12 05:17:08 PM PDT 24 426362963 ps
T574 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4022778357 Aug 12 05:17:08 PM PDT 24 Aug 12 05:17:10 PM PDT 24 216740779 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4236617322 Aug 12 05:17:34 PM PDT 24 Aug 12 05:17:35 PM PDT 24 114896790 ps
T576 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3807785724 Aug 12 05:17:29 PM PDT 24 Aug 12 05:17:31 PM PDT 24 112413152 ps
T134 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3340454344 Aug 12 05:17:07 PM PDT 24 Aug 12 05:17:10 PM PDT 24 902586204 ps
T577 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3740676250 Aug 12 05:17:13 PM PDT 24 Aug 12 05:17:15 PM PDT 24 132625163 ps
T578 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.913959429 Aug 12 05:17:30 PM PDT 24 Aug 12 05:17:31 PM PDT 24 108526020 ps
T579 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4151259771 Aug 12 05:17:38 PM PDT 24 Aug 12 05:17:39 PM PDT 24 116492310 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.963335857 Aug 12 05:17:06 PM PDT 24 Aug 12 05:17:07 PM PDT 24 75903795 ps
T581 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4002264052 Aug 12 05:17:21 PM PDT 24 Aug 12 05:17:24 PM PDT 24 422950371 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.140025961 Aug 12 05:17:12 PM PDT 24 Aug 12 05:17:15 PM PDT 24 336872513 ps
T583 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4169268856 Aug 12 05:17:27 PM PDT 24 Aug 12 05:17:29 PM PDT 24 132652791 ps
T584 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2739146214 Aug 12 05:17:39 PM PDT 24 Aug 12 05:17:40 PM PDT 24 67404471 ps
T585 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.106712126 Aug 12 05:17:25 PM PDT 24 Aug 12 05:17:26 PM PDT 24 223956264 ps
T586 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3197783708 Aug 12 05:17:16 PM PDT 24 Aug 12 05:17:17 PM PDT 24 87318598 ps
T587 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.139827238 Aug 12 05:17:22 PM PDT 24 Aug 12 05:17:25 PM PDT 24 325873033 ps
T588 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3713197759 Aug 12 05:17:14 PM PDT 24 Aug 12 05:17:15 PM PDT 24 423986463 ps
T589 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1256272630 Aug 12 05:17:29 PM PDT 24 Aug 12 05:17:30 PM PDT 24 60491735 ps
T590 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3058812186 Aug 12 05:17:32 PM PDT 24 Aug 12 05:17:34 PM PDT 24 445331972 ps
T591 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2141231713 Aug 12 05:17:23 PM PDT 24 Aug 12 05:17:25 PM PDT 24 77566382 ps
T592 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2863993760 Aug 12 05:17:29 PM PDT 24 Aug 12 05:17:31 PM PDT 24 192196217 ps
T593 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1002299600 Aug 12 05:17:04 PM PDT 24 Aug 12 05:17:05 PM PDT 24 62912229 ps
T594 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2387158420 Aug 12 05:17:10 PM PDT 24 Aug 12 05:17:16 PM PDT 24 484151148 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1182123778 Aug 12 05:17:03 PM PDT 24 Aug 12 05:17:04 PM PDT 24 59991609 ps
T119 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4228338454 Aug 12 05:17:12 PM PDT 24 Aug 12 05:17:14 PM PDT 24 495158118 ps
T596 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1026262717 Aug 12 05:17:30 PM PDT 24 Aug 12 05:17:32 PM PDT 24 127188884 ps
T597 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.830193040 Aug 12 05:17:09 PM PDT 24 Aug 12 05:17:10 PM PDT 24 102610850 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2980441558 Aug 12 05:17:05 PM PDT 24 Aug 12 05:17:06 PM PDT 24 140454875 ps
T599 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1594971357 Aug 12 05:17:14 PM PDT 24 Aug 12 05:17:15 PM PDT 24 75914034 ps
T600 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1084425395 Aug 12 05:17:06 PM PDT 24 Aug 12 05:17:07 PM PDT 24 173660012 ps
T601 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.931336772 Aug 12 05:17:13 PM PDT 24 Aug 12 05:17:15 PM PDT 24 419992842 ps
T602 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.851786603 Aug 12 05:17:03 PM PDT 24 Aug 12 05:17:05 PM PDT 24 246491334 ps
T603 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3473606672 Aug 12 05:17:10 PM PDT 24 Aug 12 05:17:11 PM PDT 24 116159453 ps
T604 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3659962747 Aug 12 05:17:21 PM PDT 24 Aug 12 05:17:22 PM PDT 24 69829330 ps
T605 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2862378488 Aug 12 05:17:05 PM PDT 24 Aug 12 05:17:07 PM PDT 24 471501607 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1666314745 Aug 12 05:17:30 PM PDT 24 Aug 12 05:17:33 PM PDT 24 351365804 ps
T607 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3728649453 Aug 12 05:17:15 PM PDT 24 Aug 12 05:17:16 PM PDT 24 130736072 ps
T608 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1786396070 Aug 12 05:17:24 PM PDT 24 Aug 12 05:17:25 PM PDT 24 161913805 ps
T609 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.339332267 Aug 12 05:17:16 PM PDT 24 Aug 12 05:17:18 PM PDT 24 240035751 ps
T610 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3449025403 Aug 12 05:17:29 PM PDT 24 Aug 12 05:17:31 PM PDT 24 139957430 ps
T611 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.943029698 Aug 12 05:17:15 PM PDT 24 Aug 12 05:17:16 PM PDT 24 75527569 ps
T612 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3426466262 Aug 12 05:17:13 PM PDT 24 Aug 12 05:17:14 PM PDT 24 125786919 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2166681973 Aug 12 05:17:00 PM PDT 24 Aug 12 05:17:02 PM PDT 24 200939590 ps
T614 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3336001632 Aug 12 05:17:12 PM PDT 24 Aug 12 05:17:14 PM PDT 24 133827528 ps
T121 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2852021948 Aug 12 05:17:38 PM PDT 24 Aug 12 05:17:41 PM PDT 24 786504165 ps
T615 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3516717022 Aug 12 05:17:15 PM PDT 24 Aug 12 05:17:17 PM PDT 24 93082547 ps
T616 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2712653321 Aug 12 05:17:02 PM PDT 24 Aug 12 05:17:07 PM PDT 24 1181406989 ps
T617 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3725745919 Aug 12 05:17:22 PM PDT 24 Aug 12 05:17:23 PM PDT 24 77903406 ps
T618 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1787112873 Aug 12 05:17:21 PM PDT 24 Aug 12 05:17:23 PM PDT 24 269023277 ps
T619 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2635934492 Aug 12 05:17:03 PM PDT 24 Aug 12 05:17:13 PM PDT 24 2300384236 ps
T620 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.24691480 Aug 12 05:17:09 PM PDT 24 Aug 12 05:17:12 PM PDT 24 785042822 ps

Test location /workspace/coverage/default/34.rstmgr_smoke.2709721799
Short name T7
Test name
Test status
Simulation time 251069102 ps
CPU time 1.59 seconds
Started Aug 12 05:18:52 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 200676 kb
Host smart-a0187820-1edc-491f-bb0a-04d585ffe06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709721799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2709721799
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3840724041
Short name T14
Test name
Test status
Simulation time 6584835419 ps
CPU time 21.8 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:22 PM PDT 24
Peak memory 200772 kb
Host smart-114e427f-7b20-42c2-8090-c8c51e60f25f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840724041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3840724041
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.759370643
Short name T5
Test name
Test status
Simulation time 16587409934 ps
CPU time 24.88 seconds
Started Aug 12 05:17:45 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 217268 kb
Host smart-b517aeb2-9db0-4892-bb29-630237245c97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759370643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.759370643
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3504611308
Short name T71
Test name
Test status
Simulation time 191452845 ps
CPU time 1.21 seconds
Started Aug 12 05:17:25 PM PDT 24
Finished Aug 12 05:17:26 PM PDT 24
Peak memory 200912 kb
Host smart-025c7126-2415-49aa-889b-27bec5e2a2b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504611308 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3504611308
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1250724033
Short name T6
Test name
Test status
Simulation time 135953251 ps
CPU time 1.68 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:25 PM PDT 24
Peak memory 208696 kb
Host smart-109f603b-6dde-456a-ad5a-fb28bec88724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250724033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1250724033
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.4207298476
Short name T11
Test name
Test status
Simulation time 2155956516 ps
CPU time 7.46 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:18:04 PM PDT 24
Peak memory 218064 kb
Host smart-f35afee9-cd5f-4747-b761-002088bee15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207298476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.4207298476
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1962262762
Short name T116
Test name
Test status
Simulation time 909128821 ps
CPU time 3.15 seconds
Started Aug 12 05:17:16 PM PDT 24
Finished Aug 12 05:17:19 PM PDT 24
Peak memory 200996 kb
Host smart-2cb164f4-1bdf-4dd6-9c0c-a3ad7a447810
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962262762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1962262762
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3375322590
Short name T97
Test name
Test status
Simulation time 11529872629 ps
CPU time 36.78 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:18:23 PM PDT 24
Peak memory 209088 kb
Host smart-ad6857d9-0f8d-41d5-87e0-ea7dc90b3ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375322590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3375322590
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.3913399463
Short name T114
Test name
Test status
Simulation time 215444057 ps
CPU time 3.16 seconds
Started Aug 12 05:17:28 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 212420 kb
Host smart-413c9e2e-277c-4f86-94ac-8b4d4f678ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913399463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3913399463
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.89282774
Short name T37
Test name
Test status
Simulation time 2367556286 ps
CPU time 8.68 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:09 PM PDT 24
Peak memory 218004 kb
Host smart-aa4a6c8d-ada6-4c04-a451-7ab504303928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89282774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.89282774
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.260283311
Short name T148
Test name
Test status
Simulation time 148693185 ps
CPU time 1.11 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 200528 kb
Host smart-70cb9b00-d0e3-402a-bb94-ae84942bf568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260283311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.260283311
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.275787423
Short name T58
Test name
Test status
Simulation time 61871444 ps
CPU time 0.74 seconds
Started Aug 12 05:18:02 PM PDT 24
Finished Aug 12 05:18:03 PM PDT 24
Peak memory 200512 kb
Host smart-8e8dc19c-98a0-41f6-bf8e-c99af16a1b56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275787423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.275787423
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2127288714
Short name T12
Test name
Test status
Simulation time 171245042 ps
CPU time 1.29 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200684 kb
Host smart-4723a190-2dc7-412e-ab8a-3d8de1b2e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127288714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2127288714
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1346681620
Short name T90
Test name
Test status
Simulation time 959951644 ps
CPU time 3.09 seconds
Started Aug 12 05:17:13 PM PDT 24
Finished Aug 12 05:17:17 PM PDT 24
Peak memory 200992 kb
Host smart-1f2689b4-a4fa-452d-8e0d-5e10ec3e6ec5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346681620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1346681620
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.369618684
Short name T30
Test name
Test status
Simulation time 2369180407 ps
CPU time 8.23 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 221984 kb
Host smart-913a3f55-5b3e-42b6-a158-0a2c8b7081af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369618684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.369618684
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3187353815
Short name T110
Test name
Test status
Simulation time 195981238 ps
CPU time 1.48 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:17:08 PM PDT 24
Peak memory 200968 kb
Host smart-005f831a-604a-42f9-bb19-4cef1d33cd9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187353815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3187353815
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2649525483
Short name T18
Test name
Test status
Simulation time 193197393 ps
CPU time 0.9 seconds
Started Aug 12 05:17:37 PM PDT 24
Finished Aug 12 05:17:38 PM PDT 24
Peak memory 200448 kb
Host smart-6c5c1b5c-eec1-462c-8ba0-40653a453af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649525483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2649525483
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3101437401
Short name T556
Test name
Test status
Simulation time 98646628 ps
CPU time 0.95 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:17:04 PM PDT 24
Peak memory 200852 kb
Host smart-c79027cb-a69b-4f6b-bc6a-bc8085be3673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101437401 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3101437401
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1514545029
Short name T74
Test name
Test status
Simulation time 480406798 ps
CPU time 2.05 seconds
Started Aug 12 05:17:24 PM PDT 24
Finished Aug 12 05:17:26 PM PDT 24
Peak memory 200896 kb
Host smart-52d83f4a-3509-448d-9745-23c799c6e18b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514545029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.1514545029
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.476489227
Short name T85
Test name
Test status
Simulation time 503121009 ps
CPU time 2.01 seconds
Started Aug 12 05:17:24 PM PDT 24
Finished Aug 12 05:17:27 PM PDT 24
Peak memory 200984 kb
Host smart-2260e9e0-ae12-44cc-bf5d-e7736a8603bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476489227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.476489227
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1784329778
Short name T118
Test name
Test status
Simulation time 826002450 ps
CPU time 2.62 seconds
Started Aug 12 05:17:27 PM PDT 24
Finished Aug 12 05:17:30 PM PDT 24
Peak memory 200968 kb
Host smart-2a577b70-0d73-4b13-bc31-366c006bfc2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784329778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1784329778
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3022255933
Short name T172
Test name
Test status
Simulation time 119999352 ps
CPU time 1.42 seconds
Started Aug 12 05:18:13 PM PDT 24
Finished Aug 12 05:18:15 PM PDT 24
Peak memory 200496 kb
Host smart-b0d2d003-f2fb-42f3-a48b-899cb3f200e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022255933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3022255933
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.2168749516
Short name T550
Test name
Test status
Simulation time 196125436 ps
CPU time 1.46 seconds
Started Aug 12 05:17:05 PM PDT 24
Finished Aug 12 05:17:06 PM PDT 24
Peak memory 200960 kb
Host smart-54cf41b5-ded1-43cd-86ad-2cc5e4d8dc9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168749516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.2
168749516
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2712653321
Short name T616
Test name
Test status
Simulation time 1181406989 ps
CPU time 5.12 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:17:07 PM PDT 24
Peak memory 200988 kb
Host smart-def8cbaa-568b-441f-b3d0-afce33129efe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712653321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
712653321
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2980441558
Short name T598
Test name
Test status
Simulation time 140454875 ps
CPU time 0.89 seconds
Started Aug 12 05:17:05 PM PDT 24
Finished Aug 12 05:17:06 PM PDT 24
Peak memory 200584 kb
Host smart-fb3989a2-a373-49a0-8227-ca48d64bb1fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980441558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
980441558
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1182123778
Short name T595
Test name
Test status
Simulation time 59991609 ps
CPU time 0.79 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:17:04 PM PDT 24
Peak memory 200744 kb
Host smart-d51412e4-ed53-4a87-ad1a-8134e8d289cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182123778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1182123778
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2166681973
Short name T613
Test name
Test status
Simulation time 200939590 ps
CPU time 1.46 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:17:02 PM PDT 24
Peak memory 200988 kb
Host smart-1223e7e8-5c34-49a3-be62-eb1a6e7ca41f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166681973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2166681973
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1084425395
Short name T600
Test name
Test status
Simulation time 173660012 ps
CPU time 1.46 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:17:07 PM PDT 24
Peak memory 211992 kb
Host smart-585c97a2-e284-4fb3-a065-f442db716f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084425395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1084425395
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1083236385
Short name T135
Test name
Test status
Simulation time 426362963 ps
CPU time 1.93 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:17:08 PM PDT 24
Peak memory 209184 kb
Host smart-6441f5c2-99df-43d3-8325-3e2f19ac4a72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083236385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1083236385
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2955939534
Short name T551
Test name
Test status
Simulation time 165367475 ps
CPU time 1.94 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:17:04 PM PDT 24
Peak memory 200976 kb
Host smart-434ea3c3-0773-46bf-a104-d4d84e424d81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955939534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
955939534
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1398955116
Short name T566
Test name
Test status
Simulation time 803488182 ps
CPU time 4.77 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:17:07 PM PDT 24
Peak memory 200912 kb
Host smart-263b5e2f-5c78-44e5-b4ff-e2fa5dc588f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398955116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
398955116
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2270639618
Short name T558
Test name
Test status
Simulation time 127076343 ps
CPU time 0.9 seconds
Started Aug 12 05:16:58 PM PDT 24
Finished Aug 12 05:16:59 PM PDT 24
Peak memory 200872 kb
Host smart-118d8530-9ef3-44d0-b552-89292a92acf9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270639618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
270639618
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1889502960
Short name T564
Test name
Test status
Simulation time 126273235 ps
CPU time 0.97 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:17:05 PM PDT 24
Peak memory 200860 kb
Host smart-a800596c-e44e-4350-8a75-15ca34067491
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889502960 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1889502960
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2008851544
Short name T554
Test name
Test status
Simulation time 89331977 ps
CPU time 0.84 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:17:01 PM PDT 24
Peak memory 200748 kb
Host smart-c06ece00-6732-4c46-b49a-b4fca4115cf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008851544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2008851544
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3678611643
Short name T563
Test name
Test status
Simulation time 570955228 ps
CPU time 3.66 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:17:07 PM PDT 24
Peak memory 212592 kb
Host smart-b17bf879-9e60-42f6-af0a-17d88cd35956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678611643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3678611643
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.4075769997
Short name T125
Test name
Test status
Simulation time 429702929 ps
CPU time 1.69 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:17:05 PM PDT 24
Peak memory 200920 kb
Host smart-6ba24985-8bb5-45b6-8fa4-60272301d65d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075769997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.4075769997
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3113543214
Short name T65
Test name
Test status
Simulation time 187247080 ps
CPU time 1.35 seconds
Started Aug 12 05:17:24 PM PDT 24
Finished Aug 12 05:17:25 PM PDT 24
Peak memory 200780 kb
Host smart-29149192-8ba1-4329-9e8e-d6621bfb8677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113543214 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3113543214
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2404059935
Short name T107
Test name
Test status
Simulation time 58870081 ps
CPU time 0.78 seconds
Started Aug 12 05:17:24 PM PDT 24
Finished Aug 12 05:17:25 PM PDT 24
Peak memory 200788 kb
Host smart-6c15b1e7-d229-4eab-b4ed-cf06f2910b07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404059935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2404059935
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.106712126
Short name T585
Test name
Test status
Simulation time 223956264 ps
CPU time 1.57 seconds
Started Aug 12 05:17:25 PM PDT 24
Finished Aug 12 05:17:26 PM PDT 24
Peak memory 200984 kb
Host smart-731fd2e2-261b-4dc6-9843-fd4622a048bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106712126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.106712126
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3374023980
Short name T117
Test name
Test status
Simulation time 312731743 ps
CPU time 2.2 seconds
Started Aug 12 05:17:20 PM PDT 24
Finished Aug 12 05:17:22 PM PDT 24
Peak memory 211920 kb
Host smart-3c766324-6a4a-4e11-b253-054993fbe1d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374023980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3374023980
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.182174704
Short name T133
Test name
Test status
Simulation time 536703573 ps
CPU time 1.89 seconds
Started Aug 12 05:17:22 PM PDT 24
Finished Aug 12 05:17:24 PM PDT 24
Peak memory 200936 kb
Host smart-99c8c2d1-1eed-422a-a483-82f0be9c09db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182174704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.182174704
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.666434194
Short name T113
Test name
Test status
Simulation time 170405642 ps
CPU time 1.66 seconds
Started Aug 12 05:17:22 PM PDT 24
Finished Aug 12 05:17:24 PM PDT 24
Peak memory 217372 kb
Host smart-fd5b388a-fd8b-4c4b-95d4-807aefece05c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666434194 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.666434194
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1008303281
Short name T555
Test name
Test status
Simulation time 66737165 ps
CPU time 0.79 seconds
Started Aug 12 05:17:23 PM PDT 24
Finished Aug 12 05:17:24 PM PDT 24
Peak memory 200796 kb
Host smart-b532ce21-4743-4bc2-9dce-a71d464c534d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008303281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1008303281
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3725745919
Short name T617
Test name
Test status
Simulation time 77903406 ps
CPU time 0.97 seconds
Started Aug 12 05:17:22 PM PDT 24
Finished Aug 12 05:17:23 PM PDT 24
Peak memory 200724 kb
Host smart-5ac8c471-7e9a-42f5-a287-981106aabb08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725745919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.3725745919
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.888642248
Short name T69
Test name
Test status
Simulation time 221782811 ps
CPU time 1.55 seconds
Started Aug 12 05:17:22 PM PDT 24
Finished Aug 12 05:17:24 PM PDT 24
Peak memory 200860 kb
Host smart-7d5880b2-da7d-48ab-9139-cbad35235572
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888642248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.888642248
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1786396070
Short name T608
Test name
Test status
Simulation time 161913805 ps
CPU time 1.05 seconds
Started Aug 12 05:17:24 PM PDT 24
Finished Aug 12 05:17:25 PM PDT 24
Peak memory 200840 kb
Host smart-b6380dd1-8e58-4203-82e8-b9c38345471b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786396070 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1786396070
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3284738210
Short name T111
Test name
Test status
Simulation time 67229995 ps
CPU time 0.84 seconds
Started Aug 12 05:17:24 PM PDT 24
Finished Aug 12 05:17:26 PM PDT 24
Peak memory 200768 kb
Host smart-801c563e-3ab7-47a6-9e75-54a49df90f97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284738210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3284738210
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1787112873
Short name T618
Test name
Test status
Simulation time 269023277 ps
CPU time 1.83 seconds
Started Aug 12 05:17:21 PM PDT 24
Finished Aug 12 05:17:23 PM PDT 24
Peak memory 200916 kb
Host smart-f539d430-9416-4e56-bdfe-c21702e26630
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787112873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1787112873
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.139827238
Short name T587
Test name
Test status
Simulation time 325873033 ps
CPU time 2.5 seconds
Started Aug 12 05:17:22 PM PDT 24
Finished Aug 12 05:17:25 PM PDT 24
Peak memory 209060 kb
Host smart-2ec54a3f-c52a-4c9d-a3d1-67736bc77da8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139827238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.139827238
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3209045140
Short name T120
Test name
Test status
Simulation time 1083781453 ps
CPU time 3.23 seconds
Started Aug 12 05:17:25 PM PDT 24
Finished Aug 12 05:17:28 PM PDT 24
Peak memory 200944 kb
Host smart-d0931e91-c127-4590-b3b3-248ac05ba0ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209045140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3209045140
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2081517678
Short name T124
Test name
Test status
Simulation time 186234492 ps
CPU time 1.29 seconds
Started Aug 12 05:17:24 PM PDT 24
Finished Aug 12 05:17:25 PM PDT 24
Peak memory 209064 kb
Host smart-9ecc1795-481a-4f87-8950-48d8a97216c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081517678 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2081517678
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3659962747
Short name T604
Test name
Test status
Simulation time 69829330 ps
CPU time 0.77 seconds
Started Aug 12 05:17:21 PM PDT 24
Finished Aug 12 05:17:22 PM PDT 24
Peak memory 200828 kb
Host smart-d155ec98-6edf-4185-9481-d0f795e50010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659962747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3659962747
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2141231713
Short name T591
Test name
Test status
Simulation time 77566382 ps
CPU time 0.98 seconds
Started Aug 12 05:17:23 PM PDT 24
Finished Aug 12 05:17:25 PM PDT 24
Peak memory 200796 kb
Host smart-e5ef4b69-854e-45e0-a96a-e3766f5a5f8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141231713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2141231713
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3351528139
Short name T562
Test name
Test status
Simulation time 598988180 ps
CPU time 4.02 seconds
Started Aug 12 05:17:22 PM PDT 24
Finished Aug 12 05:17:26 PM PDT 24
Peak memory 209140 kb
Host smart-b96b0e2e-3146-48df-9c6f-82216aa63bf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351528139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3351528139
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1209227460
Short name T122
Test name
Test status
Simulation time 497959710 ps
CPU time 1.91 seconds
Started Aug 12 05:17:22 PM PDT 24
Finished Aug 12 05:17:24 PM PDT 24
Peak memory 200880 kb
Host smart-fe483d1d-6ac3-4790-b6da-a92b6bfa4c04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209227460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1209227460
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.913959429
Short name T578
Test name
Test status
Simulation time 108526020 ps
CPU time 1.05 seconds
Started Aug 12 05:17:30 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 209080 kb
Host smart-226b7b0e-e219-4586-84bb-c915c309704f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913959429 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.913959429
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.3129637473
Short name T557
Test name
Test status
Simulation time 69489885 ps
CPU time 0.8 seconds
Started Aug 12 05:17:30 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 200744 kb
Host smart-ec864034-aeca-4de1-880e-bb7934716abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129637473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3129637473
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3449025403
Short name T610
Test name
Test status
Simulation time 139957430 ps
CPU time 1.43 seconds
Started Aug 12 05:17:29 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 200892 kb
Host smart-df819e6e-6c2a-4668-b832-e5e5053582e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449025403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3449025403
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4002264052
Short name T581
Test name
Test status
Simulation time 422950371 ps
CPU time 2.77 seconds
Started Aug 12 05:17:21 PM PDT 24
Finished Aug 12 05:17:24 PM PDT 24
Peak memory 212300 kb
Host smart-8209dcb9-2353-47b1-93f2-d59b23c63f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002264052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4002264052
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4169268856
Short name T583
Test name
Test status
Simulation time 132652791 ps
CPU time 1.03 seconds
Started Aug 12 05:17:27 PM PDT 24
Finished Aug 12 05:17:29 PM PDT 24
Peak memory 209012 kb
Host smart-4c4685fa-c4ca-4678-aa5d-187f4ff50085
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169268856 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.4169268856
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.3771802255
Short name T547
Test name
Test status
Simulation time 92239042 ps
CPU time 0.88 seconds
Started Aug 12 05:17:28 PM PDT 24
Finished Aug 12 05:17:29 PM PDT 24
Peak memory 200776 kb
Host smart-d6d8452f-4292-40ac-b0e3-4d6f9d8f68e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771802255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3771802255
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1026262717
Short name T596
Test name
Test status
Simulation time 127188884 ps
CPU time 1.12 seconds
Started Aug 12 05:17:30 PM PDT 24
Finished Aug 12 05:17:32 PM PDT 24
Peak memory 200812 kb
Host smart-d303eabb-8168-4adb-aaf5-5e66503dbd14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026262717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1026262717
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.871821001
Short name T561
Test name
Test status
Simulation time 197280164 ps
CPU time 1.67 seconds
Started Aug 12 05:17:27 PM PDT 24
Finished Aug 12 05:17:28 PM PDT 24
Peak memory 209200 kb
Host smart-face4f3c-13bd-4f7c-9ab9-47e6044406ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871821001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.871821001
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4236617322
Short name T575
Test name
Test status
Simulation time 114896790 ps
CPU time 1 seconds
Started Aug 12 05:17:34 PM PDT 24
Finished Aug 12 05:17:35 PM PDT 24
Peak memory 200860 kb
Host smart-a411d734-84f9-4443-a84b-f812d7be5a49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236617322 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.4236617322
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3975836685
Short name T109
Test name
Test status
Simulation time 64365797 ps
CPU time 0.83 seconds
Started Aug 12 05:17:30 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 200828 kb
Host smart-c13f6f12-c546-48e5-9e81-b307af9aa6a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975836685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3975836685
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3735149023
Short name T112
Test name
Test status
Simulation time 107454654 ps
CPU time 1.26 seconds
Started Aug 12 05:17:29 PM PDT 24
Finished Aug 12 05:17:30 PM PDT 24
Peak memory 200984 kb
Host smart-bd1e9e0b-4139-40ef-929e-5a4fee3ba856
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735149023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3735149023
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3807785724
Short name T576
Test name
Test status
Simulation time 112413152 ps
CPU time 1.53 seconds
Started Aug 12 05:17:29 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 209268 kb
Host smart-be558e9e-eec8-4fdc-93ca-a25d20938fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807785724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3807785724
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3461642863
Short name T72
Test name
Test status
Simulation time 427245661 ps
CPU time 1.87 seconds
Started Aug 12 05:17:29 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 200968 kb
Host smart-eafb01f4-631a-4501-b0ac-a3bd6925383f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461642863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3461642863
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.550722141
Short name T569
Test name
Test status
Simulation time 122784483 ps
CPU time 1.04 seconds
Started Aug 12 05:17:30 PM PDT 24
Finished Aug 12 05:17:32 PM PDT 24
Peak memory 200892 kb
Host smart-c264899a-1ad4-48c5-a7d4-ac53d01154fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550722141 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.550722141
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2728420751
Short name T106
Test name
Test status
Simulation time 77289894 ps
CPU time 0.82 seconds
Started Aug 12 05:17:31 PM PDT 24
Finished Aug 12 05:17:32 PM PDT 24
Peak memory 200812 kb
Host smart-6ad6d6d0-3ca5-4e5e-b356-bc5ea3a36ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728420751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2728420751
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2729828252
Short name T67
Test name
Test status
Simulation time 84290706 ps
CPU time 0.98 seconds
Started Aug 12 05:17:27 PM PDT 24
Finished Aug 12 05:17:28 PM PDT 24
Peak memory 200816 kb
Host smart-948227d0-0139-44e7-b46a-27e487d9364b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729828252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2729828252
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3058812186
Short name T590
Test name
Test status
Simulation time 445331972 ps
CPU time 1.69 seconds
Started Aug 12 05:17:32 PM PDT 24
Finished Aug 12 05:17:34 PM PDT 24
Peak memory 201004 kb
Host smart-139c948b-1ff8-4fa0-9cbe-0e4e067b3a96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058812186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3058812186
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1297276036
Short name T88
Test name
Test status
Simulation time 105985257 ps
CPU time 1.01 seconds
Started Aug 12 05:17:40 PM PDT 24
Finished Aug 12 05:17:41 PM PDT 24
Peak memory 200880 kb
Host smart-f9899f9c-a22a-4f63-b024-c065df1411f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297276036 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1297276036
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1256272630
Short name T589
Test name
Test status
Simulation time 60491735 ps
CPU time 0.75 seconds
Started Aug 12 05:17:29 PM PDT 24
Finished Aug 12 05:17:30 PM PDT 24
Peak memory 200832 kb
Host smart-5fa67179-5f7e-41f9-b277-8ebbaec7f14c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256272630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1256272630
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2863993760
Short name T592
Test name
Test status
Simulation time 192196217 ps
CPU time 1.38 seconds
Started Aug 12 05:17:29 PM PDT 24
Finished Aug 12 05:17:31 PM PDT 24
Peak memory 200980 kb
Host smart-d78ac021-e1b2-41c5-950d-c44d69376899
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863993760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2863993760
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1666314745
Short name T606
Test name
Test status
Simulation time 351365804 ps
CPU time 2.57 seconds
Started Aug 12 05:17:30 PM PDT 24
Finished Aug 12 05:17:33 PM PDT 24
Peak memory 209172 kb
Host smart-3781bcdd-0d58-4fc5-8923-432fe99437cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666314745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1666314745
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2067953881
Short name T549
Test name
Test status
Simulation time 512360273 ps
CPU time 2.02 seconds
Started Aug 12 05:17:27 PM PDT 24
Finished Aug 12 05:17:29 PM PDT 24
Peak memory 201124 kb
Host smart-6a83dc15-07aa-424e-98f4-32fe1c22b1a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067953881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2067953881
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4151259771
Short name T579
Test name
Test status
Simulation time 116492310 ps
CPU time 0.97 seconds
Started Aug 12 05:17:38 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 200872 kb
Host smart-2e585f31-053e-49b6-a273-3f331f5c4f69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151259771 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4151259771
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2739146214
Short name T584
Test name
Test status
Simulation time 67404471 ps
CPU time 0.78 seconds
Started Aug 12 05:17:39 PM PDT 24
Finished Aug 12 05:17:40 PM PDT 24
Peak memory 200752 kb
Host smart-e01ed548-a39f-4138-b3d9-7b26ee9de2d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739146214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2739146214
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1173345834
Short name T105
Test name
Test status
Simulation time 131036349 ps
CPU time 1.1 seconds
Started Aug 12 05:17:37 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 200792 kb
Host smart-c87a1d1c-b87b-4a91-9496-dec9ae818ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173345834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1173345834
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4059153465
Short name T73
Test name
Test status
Simulation time 129397368 ps
CPU time 1.72 seconds
Started Aug 12 05:17:37 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 209184 kb
Host smart-aa1cc1fd-6084-46aa-9f2f-69998c3ca4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059153465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4059153465
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2852021948
Short name T121
Test name
Test status
Simulation time 786504165 ps
CPU time 2.71 seconds
Started Aug 12 05:17:38 PM PDT 24
Finished Aug 12 05:17:41 PM PDT 24
Peak memory 201040 kb
Host smart-2c60c200-11d3-4be4-ace5-2cf4705fc169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852021948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2852021948
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.194749715
Short name T570
Test name
Test status
Simulation time 361280736 ps
CPU time 2.46 seconds
Started Aug 12 05:17:08 PM PDT 24
Finished Aug 12 05:17:10 PM PDT 24
Peak memory 200928 kb
Host smart-e3b69401-3ca3-4f48-b843-6c5130b2f4f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194749715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.194749715
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2387158420
Short name T594
Test name
Test status
Simulation time 484151148 ps
CPU time 5.61 seconds
Started Aug 12 05:17:10 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 200924 kb
Host smart-f9f28460-c67b-46d1-9566-81fcf5913fae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387158420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
387158420
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.830193040
Short name T597
Test name
Test status
Simulation time 102610850 ps
CPU time 0.85 seconds
Started Aug 12 05:17:09 PM PDT 24
Finished Aug 12 05:17:10 PM PDT 24
Peak memory 200800 kb
Host smart-4dabcd56-9c07-4e31-b6e5-b93bbcb04ce5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830193040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.830193040
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2548701420
Short name T86
Test name
Test status
Simulation time 212571143 ps
CPU time 1.34 seconds
Started Aug 12 05:17:28 PM PDT 24
Finished Aug 12 05:17:29 PM PDT 24
Peak memory 209076 kb
Host smart-9f3e6c6c-d1fb-436f-9d3a-c9ac707213ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548701420 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2548701420
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2833408363
Short name T548
Test name
Test status
Simulation time 80988622 ps
CPU time 0.79 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:17:07 PM PDT 24
Peak memory 200828 kb
Host smart-5d3008af-fd9d-4b1a-8fe8-8d2d49b04441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833408363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2833408363
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.851786603
Short name T602
Test name
Test status
Simulation time 246491334 ps
CPU time 1.49 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:17:05 PM PDT 24
Peak memory 200972 kb
Host smart-cc737dc3-65b0-4b60-a77b-1eb75890c144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851786603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.851786603
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.140025961
Short name T582
Test name
Test status
Simulation time 336872513 ps
CPU time 2.2 seconds
Started Aug 12 05:17:12 PM PDT 24
Finished Aug 12 05:17:15 PM PDT 24
Peak memory 217328 kb
Host smart-36709034-788d-4365-84e0-57fd2e01dc38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140025961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.140025961
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3340454344
Short name T134
Test name
Test status
Simulation time 902586204 ps
CPU time 2.98 seconds
Started Aug 12 05:17:07 PM PDT 24
Finished Aug 12 05:17:10 PM PDT 24
Peak memory 200996 kb
Host smart-c5afe187-44da-4451-90ab-7246b3af10b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340454344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3340454344
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.726009203
Short name T546
Test name
Test status
Simulation time 113825674 ps
CPU time 1.33 seconds
Started Aug 12 05:17:15 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 200972 kb
Host smart-ef726784-b9df-449a-b38a-30043f750c6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726009203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.726009203
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2635934492
Short name T619
Test name
Test status
Simulation time 2300384236 ps
CPU time 10.17 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:17:13 PM PDT 24
Peak memory 201012 kb
Host smart-3951d7bb-dab7-4413-8805-4e9e174034d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635934492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
635934492
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3473606672
Short name T603
Test name
Test status
Simulation time 116159453 ps
CPU time 0.88 seconds
Started Aug 12 05:17:10 PM PDT 24
Finished Aug 12 05:17:11 PM PDT 24
Peak memory 200804 kb
Host smart-099bd9f7-3a44-46a5-ad0e-ed99a9fb933d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473606672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
473606672
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2190035917
Short name T115
Test name
Test status
Simulation time 190997455 ps
CPU time 1.8 seconds
Started Aug 12 05:17:08 PM PDT 24
Finished Aug 12 05:17:10 PM PDT 24
Peak memory 209216 kb
Host smart-4dd69ace-f230-4ef2-ae5e-65863bd1d574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190035917 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2190035917
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.963335857
Short name T580
Test name
Test status
Simulation time 75903795 ps
CPU time 0.76 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:17:07 PM PDT 24
Peak memory 200860 kb
Host smart-e4773055-1689-4d63-944f-d046f63a0d48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963335857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.963335857
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3943372385
Short name T572
Test name
Test status
Simulation time 91152306 ps
CPU time 0.95 seconds
Started Aug 12 05:17:09 PM PDT 24
Finished Aug 12 05:17:10 PM PDT 24
Peak memory 200832 kb
Host smart-fd5d2d20-fd0b-43e6-a562-1c73e105d286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943372385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.3943372385
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.4022778357
Short name T574
Test name
Test status
Simulation time 216740779 ps
CPU time 1.58 seconds
Started Aug 12 05:17:08 PM PDT 24
Finished Aug 12 05:17:10 PM PDT 24
Peak memory 209164 kb
Host smart-003f30ae-b0f3-4329-9b06-e1f567107d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022778357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.4022778357
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.24691480
Short name T620
Test name
Test status
Simulation time 785042822 ps
CPU time 2.73 seconds
Started Aug 12 05:17:09 PM PDT 24
Finished Aug 12 05:17:12 PM PDT 24
Peak memory 200924 kb
Host smart-e5defc17-acbf-40bf-a8b1-3dd207fc5182
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24691480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.24691480
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1992702836
Short name T560
Test name
Test status
Simulation time 421861330 ps
CPU time 2.63 seconds
Started Aug 12 05:17:14 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 200980 kb
Host smart-8eb50641-7606-4bd3-8958-09187809ef83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992702836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
992702836
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.472674863
Short name T66
Test name
Test status
Simulation time 274153080 ps
CPU time 3.21 seconds
Started Aug 12 05:17:13 PM PDT 24
Finished Aug 12 05:17:17 PM PDT 24
Peak memory 201000 kb
Host smart-5f1253fa-9cc3-4d6c-8d13-5928d0fd7d92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472674863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.472674863
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1192884501
Short name T552
Test name
Test status
Simulation time 108748572 ps
CPU time 0.83 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:17:04 PM PDT 24
Peak memory 200736 kb
Host smart-062a4347-0420-4254-bd4a-61227c9abfed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192884501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
192884501
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4034918748
Short name T567
Test name
Test status
Simulation time 119702211 ps
CPU time 0.93 seconds
Started Aug 12 05:17:17 PM PDT 24
Finished Aug 12 05:17:18 PM PDT 24
Peak memory 200880 kb
Host smart-e5cbc95f-92d5-4395-95ae-8a021d286a75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034918748 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.4034918748
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1002299600
Short name T593
Test name
Test status
Simulation time 62912229 ps
CPU time 0.75 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:17:05 PM PDT 24
Peak memory 200784 kb
Host smart-2852a4a8-c7ce-4646-bf5c-5e7eb3dbb8fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002299600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1002299600
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3740676250
Short name T577
Test name
Test status
Simulation time 132625163 ps
CPU time 1.28 seconds
Started Aug 12 05:17:13 PM PDT 24
Finished Aug 12 05:17:15 PM PDT 24
Peak memory 200996 kb
Host smart-89094168-c2c2-4d5e-8c69-33fdd8f1477c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740676250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3740676250
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3010010182
Short name T123
Test name
Test status
Simulation time 151902949 ps
CPU time 2.17 seconds
Started Aug 12 05:17:10 PM PDT 24
Finished Aug 12 05:17:12 PM PDT 24
Peak memory 209184 kb
Host smart-d2854dd9-cb63-40dd-a7d6-d6baf951e767
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010010182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3010010182
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2862378488
Short name T605
Test name
Test status
Simulation time 471501607 ps
CPU time 2.04 seconds
Started Aug 12 05:17:05 PM PDT 24
Finished Aug 12 05:17:07 PM PDT 24
Peak memory 200980 kb
Host smart-f3c17ea4-4b91-462d-94d0-85024c0515c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862378488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2862378488
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3728649453
Short name T607
Test name
Test status
Simulation time 130736072 ps
CPU time 0.98 seconds
Started Aug 12 05:17:15 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 208904 kb
Host smart-b5aca07c-4b9c-4b0b-995a-bec6e78c3be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728649453 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3728649453
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.234557258
Short name T559
Test name
Test status
Simulation time 82576671 ps
CPU time 0.8 seconds
Started Aug 12 05:17:13 PM PDT 24
Finished Aug 12 05:17:14 PM PDT 24
Peak memory 200832 kb
Host smart-ef2a3ae3-0cb3-4db5-8e99-6aefd7d2f1af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234557258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.234557258
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.339332267
Short name T609
Test name
Test status
Simulation time 240035751 ps
CPU time 1.67 seconds
Started Aug 12 05:17:16 PM PDT 24
Finished Aug 12 05:17:18 PM PDT 24
Peak memory 200944 kb
Host smart-f22c0209-6267-4746-ac93-62e5c8ac5e67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339332267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sam
e_csr_outstanding.339332267
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3927303655
Short name T568
Test name
Test status
Simulation time 530294782 ps
CPU time 3.62 seconds
Started Aug 12 05:17:15 PM PDT 24
Finished Aug 12 05:17:18 PM PDT 24
Peak memory 209320 kb
Host smart-b2a46881-1d6c-46e1-96a6-39692a1227be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927303655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3927303655
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.3888791252
Short name T571
Test name
Test status
Simulation time 59317086 ps
CPU time 0.81 seconds
Started Aug 12 05:17:15 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 200828 kb
Host smart-2cb35367-8d69-4002-83b2-6e50c94f31ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888791252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3888791252
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3426466262
Short name T612
Test name
Test status
Simulation time 125786919 ps
CPU time 1.1 seconds
Started Aug 12 05:17:13 PM PDT 24
Finished Aug 12 05:17:14 PM PDT 24
Peak memory 200736 kb
Host smart-572f1641-82d3-48be-9b26-a8c6b0e20186
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426466262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3426466262
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3197783708
Short name T586
Test name
Test status
Simulation time 87318598 ps
CPU time 1.23 seconds
Started Aug 12 05:17:16 PM PDT 24
Finished Aug 12 05:17:17 PM PDT 24
Peak memory 200828 kb
Host smart-43d379d7-a5ae-4242-b70b-11ebdedc74f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197783708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3197783708
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.931336772
Short name T601
Test name
Test status
Simulation time 419992842 ps
CPU time 1.8 seconds
Started Aug 12 05:17:13 PM PDT 24
Finished Aug 12 05:17:15 PM PDT 24
Peak memory 200948 kb
Host smart-0c5794ac-98e9-4f48-9e8f-d8e3f9e945bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931336772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
931336772
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.4265933443
Short name T70
Test name
Test status
Simulation time 113821544 ps
CPU time 0.98 seconds
Started Aug 12 05:17:13 PM PDT 24
Finished Aug 12 05:17:14 PM PDT 24
Peak memory 200876 kb
Host smart-507c6b01-edd6-4226-bbbc-53c5419b212c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265933443 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.4265933443
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.943029698
Short name T611
Test name
Test status
Simulation time 75527569 ps
CPU time 0.86 seconds
Started Aug 12 05:17:15 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 200824 kb
Host smart-e51306ec-712a-48a2-8a5f-ee8e4ae64391
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943029698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.943029698
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3516717022
Short name T615
Test name
Test status
Simulation time 93082547 ps
CPU time 1.03 seconds
Started Aug 12 05:17:15 PM PDT 24
Finished Aug 12 05:17:17 PM PDT 24
Peak memory 200780 kb
Host smart-7981f960-bb7b-48df-b152-fc06c793f221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516717022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3516717022
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.3637354415
Short name T89
Test name
Test status
Simulation time 95703448 ps
CPU time 1.16 seconds
Started Aug 12 05:17:15 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 208940 kb
Host smart-68149758-3dfb-4f7e-a81f-5112e7ccc9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637354415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3637354415
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3713197759
Short name T588
Test name
Test status
Simulation time 423986463 ps
CPU time 1.78 seconds
Started Aug 12 05:17:14 PM PDT 24
Finished Aug 12 05:17:15 PM PDT 24
Peak memory 201052 kb
Host smart-b8e4e7b3-74ee-4ddb-8954-14fe43a97ea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713197759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3713197759
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.601527101
Short name T553
Test name
Test status
Simulation time 189661471 ps
CPU time 1.27 seconds
Started Aug 12 05:17:12 PM PDT 24
Finished Aug 12 05:17:13 PM PDT 24
Peak memory 209088 kb
Host smart-2dda59a8-477d-48ce-b0c8-164e3a8b7e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601527101 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.601527101
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3710452790
Short name T68
Test name
Test status
Simulation time 73068628 ps
CPU time 0.79 seconds
Started Aug 12 05:17:16 PM PDT 24
Finished Aug 12 05:17:17 PM PDT 24
Peak memory 200652 kb
Host smart-8c96c45a-fa29-4c65-82f9-9aa3e5a0b063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710452790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3710452790
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.467610665
Short name T108
Test name
Test status
Simulation time 82622829 ps
CPU time 0.94 seconds
Started Aug 12 05:17:17 PM PDT 24
Finished Aug 12 05:17:18 PM PDT 24
Peak memory 200872 kb
Host smart-ed86dd5a-f245-45e6-932c-34273667a71b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467610665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.467610665
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.68265345
Short name T573
Test name
Test status
Simulation time 116573355 ps
CPU time 1.52 seconds
Started Aug 12 05:17:13 PM PDT 24
Finished Aug 12 05:17:14 PM PDT 24
Peak memory 200984 kb
Host smart-6376a57c-da20-4b88-a380-3eff87916cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68265345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.68265345
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1551538601
Short name T87
Test name
Test status
Simulation time 127902610 ps
CPU time 0.99 seconds
Started Aug 12 05:17:22 PM PDT 24
Finished Aug 12 05:17:23 PM PDT 24
Peak memory 200892 kb
Host smart-bc7c1935-df91-4696-9597-39f2aa1990fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551538601 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1551538601
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1594971357
Short name T599
Test name
Test status
Simulation time 75914034 ps
CPU time 0.74 seconds
Started Aug 12 05:17:14 PM PDT 24
Finished Aug 12 05:17:15 PM PDT 24
Peak memory 200700 kb
Host smart-7a2e3db0-91c7-4740-8e15-6783e698e830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594971357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1594971357
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.3336001632
Short name T614
Test name
Test status
Simulation time 133827528 ps
CPU time 1.16 seconds
Started Aug 12 05:17:12 PM PDT 24
Finished Aug 12 05:17:14 PM PDT 24
Peak memory 200764 kb
Host smart-ec9e0073-94c5-4874-b7e1-2aea77a1bfe2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336001632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.3336001632
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2836677405
Short name T565
Test name
Test status
Simulation time 459650816 ps
CPU time 2.96 seconds
Started Aug 12 05:17:12 PM PDT 24
Finished Aug 12 05:17:15 PM PDT 24
Peak memory 209132 kb
Host smart-f5b60b09-6520-480a-b008-e9baf01037f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836677405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2836677405
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.4228338454
Short name T119
Test name
Test status
Simulation time 495158118 ps
CPU time 1.9 seconds
Started Aug 12 05:17:12 PM PDT 24
Finished Aug 12 05:17:14 PM PDT 24
Peak memory 200912 kb
Host smart-f3a5caac-01c1-44f0-aed3-8def57f4890e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228338454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.4228338454
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3782016364
Short name T168
Test name
Test status
Simulation time 68078594 ps
CPU time 0.75 seconds
Started Aug 12 05:17:37 PM PDT 24
Finished Aug 12 05:17:38 PM PDT 24
Peak memory 200396 kb
Host smart-aef2faeb-08a8-4aa0-b42f-32b5cb06555d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782016364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3782016364
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.716988765
Short name T40
Test name
Test status
Simulation time 1220004467 ps
CPU time 5.31 seconds
Started Aug 12 05:17:36 PM PDT 24
Finished Aug 12 05:17:41 PM PDT 24
Peak memory 217956 kb
Host smart-8227933a-449b-4e67-b1c2-fdd1ea191194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716988765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.716988765
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.69004458
Short name T219
Test name
Test status
Simulation time 244863403 ps
CPU time 1.02 seconds
Started Aug 12 05:17:36 PM PDT 24
Finished Aug 12 05:17:38 PM PDT 24
Peak memory 217772 kb
Host smart-1fbb7e46-616f-4000-8bdb-a6c55a34cbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69004458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.69004458
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.84482619
Short name T442
Test name
Test status
Simulation time 211414158 ps
CPU time 0.9 seconds
Started Aug 12 05:17:38 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 200384 kb
Host smart-6a4c9953-20e3-442c-b82d-632716848f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84482619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.84482619
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3758877830
Short name T317
Test name
Test status
Simulation time 1356167066 ps
CPU time 6.19 seconds
Started Aug 12 05:17:38 PM PDT 24
Finished Aug 12 05:17:44 PM PDT 24
Peak memory 200704 kb
Host smart-f53ec275-d74f-4d6c-bb50-32f3e4d23068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758877830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3758877830
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.343115384
Short name T77
Test name
Test status
Simulation time 16667793386 ps
CPU time 24.69 seconds
Started Aug 12 05:17:36 PM PDT 24
Finished Aug 12 05:18:01 PM PDT 24
Peak memory 217404 kb
Host smart-a562baae-db2e-4a6c-9d20-4c81df2bb597
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343115384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.343115384
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.88716285
Short name T238
Test name
Test status
Simulation time 175909215 ps
CPU time 1.17 seconds
Started Aug 12 05:17:37 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 200640 kb
Host smart-4edf098f-4e92-4eec-a99b-28dede9e57e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88716285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.88716285
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.981436308
Short name T265
Test name
Test status
Simulation time 114196024 ps
CPU time 1.17 seconds
Started Aug 12 05:17:36 PM PDT 24
Finished Aug 12 05:17:37 PM PDT 24
Peak memory 200684 kb
Host smart-cdfc66c0-4516-47f7-a62a-a954e974f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981436308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.981436308
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1116769439
Short name T387
Test name
Test status
Simulation time 650071709 ps
CPU time 3.04 seconds
Started Aug 12 05:17:42 PM PDT 24
Finished Aug 12 05:17:46 PM PDT 24
Peak memory 200640 kb
Host smart-f9a3a879-0eb7-44db-b71c-127e57e68fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116769439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1116769439
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3638331183
Short name T425
Test name
Test status
Simulation time 121662547 ps
CPU time 1.55 seconds
Started Aug 12 05:17:36 PM PDT 24
Finished Aug 12 05:17:37 PM PDT 24
Peak memory 200284 kb
Host smart-9ea30578-26b4-4937-94fb-746343ccd151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638331183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3638331183
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.103753472
Short name T446
Test name
Test status
Simulation time 122497383 ps
CPU time 0.96 seconds
Started Aug 12 05:17:39 PM PDT 24
Finished Aug 12 05:17:40 PM PDT 24
Peak memory 200572 kb
Host smart-6139080a-ffba-484b-826d-b9a2ff23d91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103753472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.103753472
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4192332438
Short name T319
Test name
Test status
Simulation time 80249697 ps
CPU time 0.8 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:47 PM PDT 24
Peak memory 200396 kb
Host smart-a6604f4d-18a4-4562-af50-17090765b842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192332438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4192332438
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.2879907428
Short name T513
Test name
Test status
Simulation time 2192465196 ps
CPU time 7.32 seconds
Started Aug 12 05:17:45 PM PDT 24
Finished Aug 12 05:17:52 PM PDT 24
Peak memory 222024 kb
Host smart-69ba01d7-58fe-4dce-8d52-bb2e23ee95f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879907428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2879907428
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1389240218
Short name T52
Test name
Test status
Simulation time 245166362 ps
CPU time 1.01 seconds
Started Aug 12 05:17:48 PM PDT 24
Finished Aug 12 05:17:49 PM PDT 24
Peak memory 217728 kb
Host smart-a59e6376-55dc-48d8-8736-110082f6d02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389240218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1389240218
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2313008750
Short name T331
Test name
Test status
Simulation time 1478914062 ps
CPU time 5.79 seconds
Started Aug 12 05:17:36 PM PDT 24
Finished Aug 12 05:17:42 PM PDT 24
Peak memory 200732 kb
Host smart-d02ed1fb-59b5-4000-8d51-2b751799c9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313008750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2313008750
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1080266657
Short name T76
Test name
Test status
Simulation time 8284766978 ps
CPU time 14.9 seconds
Started Aug 12 05:17:45 PM PDT 24
Finished Aug 12 05:18:00 PM PDT 24
Peak memory 217356 kb
Host smart-bb000828-6c53-4e46-83fc-3c6278f4efd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080266657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1080266657
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1989548801
Short name T430
Test name
Test status
Simulation time 177656103 ps
CPU time 1.23 seconds
Started Aug 12 05:17:48 PM PDT 24
Finished Aug 12 05:17:49 PM PDT 24
Peak memory 200620 kb
Host smart-a31e9815-3c6b-4d39-8db1-934ac16310cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989548801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1989548801
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.3592421517
Short name T373
Test name
Test status
Simulation time 233814985 ps
CPU time 1.6 seconds
Started Aug 12 05:17:42 PM PDT 24
Finished Aug 12 05:17:44 PM PDT 24
Peak memory 200712 kb
Host smart-e5081957-9f8f-4cc5-83a5-eeff370e0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592421517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3592421517
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1926676436
Short name T406
Test name
Test status
Simulation time 123161826 ps
CPU time 1.62 seconds
Started Aug 12 05:17:48 PM PDT 24
Finished Aug 12 05:17:50 PM PDT 24
Peak memory 200544 kb
Host smart-dd27977e-e55f-408f-8cb0-1263e74fc21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926676436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1926676436
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3636931489
Short name T521
Test name
Test status
Simulation time 234833227 ps
CPU time 1.46 seconds
Started Aug 12 05:17:42 PM PDT 24
Finished Aug 12 05:17:44 PM PDT 24
Peak memory 200564 kb
Host smart-0a7f189c-8656-427b-ab90-0320fb212096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636931489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3636931489
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.590712973
Short name T361
Test name
Test status
Simulation time 60164125 ps
CPU time 0.73 seconds
Started Aug 12 05:17:59 PM PDT 24
Finished Aug 12 05:18:00 PM PDT 24
Peak memory 200432 kb
Host smart-38d19877-db10-4a23-9682-dd1489a564db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590712973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.590712973
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1735251572
Short name T462
Test name
Test status
Simulation time 2348180364 ps
CPU time 7.83 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:09 PM PDT 24
Peak memory 230320 kb
Host smart-28ef718f-77b2-48d1-9a92-0acc5d0cb5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735251572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1735251572
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2342398222
Short name T471
Test name
Test status
Simulation time 244871080 ps
CPU time 1.06 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 217732 kb
Host smart-8aaf9f5a-162f-4682-89c3-be1969f2388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342398222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2342398222
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.4220037780
Short name T419
Test name
Test status
Simulation time 159649816 ps
CPU time 0.86 seconds
Started Aug 12 05:18:00 PM PDT 24
Finished Aug 12 05:18:01 PM PDT 24
Peak memory 200436 kb
Host smart-43452210-b657-4baa-8f54-5d900aa1018d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220037780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.4220037780
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.720621040
Short name T417
Test name
Test status
Simulation time 926663347 ps
CPU time 4.59 seconds
Started Aug 12 05:18:02 PM PDT 24
Finished Aug 12 05:18:07 PM PDT 24
Peak memory 200788 kb
Host smart-753af8b4-86db-4330-a256-b40ae46c1f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720621040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.720621040
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.496472722
Short name T461
Test name
Test status
Simulation time 122283259 ps
CPU time 1.2 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 200684 kb
Host smart-52cbd613-d018-4225-96fc-daeb61193153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496472722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.496472722
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.381110977
Short name T94
Test name
Test status
Simulation time 5788693122 ps
CPU time 21.25 seconds
Started Aug 12 05:18:03 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 200684 kb
Host smart-4906f9d4-f43c-404d-bd98-ff5396765b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381110977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.381110977
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1781483556
Short name T296
Test name
Test status
Simulation time 124241643 ps
CPU time 1.44 seconds
Started Aug 12 05:18:03 PM PDT 24
Finished Aug 12 05:18:05 PM PDT 24
Peak memory 200500 kb
Host smart-0bbc637e-5a3c-44f5-84c0-beb811f28122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781483556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1781483556
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1474546498
Short name T449
Test name
Test status
Simulation time 185872677 ps
CPU time 1.34 seconds
Started Aug 12 05:18:00 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 200744 kb
Host smart-52b3e00c-6c70-48b6-8bbc-47c981895446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474546498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1474546498
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.4267203844
Short name T334
Test name
Test status
Simulation time 2372500754 ps
CPU time 8.06 seconds
Started Aug 12 05:18:02 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 222000 kb
Host smart-abf72f54-0eb2-4c88-8d3c-ec32da0dda4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267203844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.4267203844
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.845536525
Short name T420
Test name
Test status
Simulation time 244693852 ps
CPU time 1.06 seconds
Started Aug 12 05:18:03 PM PDT 24
Finished Aug 12 05:18:04 PM PDT 24
Peak memory 217800 kb
Host smart-01c6c24e-5b50-45c0-8210-4c3d701ecb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845536525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.845536525
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2872101929
Short name T293
Test name
Test status
Simulation time 118247892 ps
CPU time 0.84 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 200488 kb
Host smart-26da36da-28c1-45d1-bc2f-b854e7f8d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872101929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2872101929
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2179515400
Short name T91
Test name
Test status
Simulation time 677700343 ps
CPU time 3.57 seconds
Started Aug 12 05:18:02 PM PDT 24
Finished Aug 12 05:18:06 PM PDT 24
Peak memory 200752 kb
Host smart-cc068607-523a-4598-ac40-17a41d2b3a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179515400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2179515400
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1950805042
Short name T502
Test name
Test status
Simulation time 113406230 ps
CPU time 0.99 seconds
Started Aug 12 05:18:04 PM PDT 24
Finished Aug 12 05:18:05 PM PDT 24
Peak memory 200668 kb
Host smart-cdfee561-10fd-48ac-ab17-9704aceb0ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950805042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1950805042
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3013003041
Short name T9
Test name
Test status
Simulation time 256108955 ps
CPU time 1.47 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:03 PM PDT 24
Peak memory 200736 kb
Host smart-c3a15880-66f3-43e7-a4b4-afdb51d89857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013003041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3013003041
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2676974323
Short name T185
Test name
Test status
Simulation time 338118902 ps
CPU time 2.17 seconds
Started Aug 12 05:18:04 PM PDT 24
Finished Aug 12 05:18:06 PM PDT 24
Peak memory 200696 kb
Host smart-63c5cf04-890a-4964-aa37-3ea52c33c6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676974323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2676974323
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.291666511
Short name T379
Test name
Test status
Simulation time 133360863 ps
CPU time 1.6 seconds
Started Aug 12 05:18:06 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 208768 kb
Host smart-65097753-9838-49d3-bd05-60778e3b45d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291666511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.291666511
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2604890405
Short name T260
Test name
Test status
Simulation time 226074464 ps
CPU time 1.44 seconds
Started Aug 12 05:18:05 PM PDT 24
Finished Aug 12 05:18:06 PM PDT 24
Peak memory 200688 kb
Host smart-1ec90cac-1404-4a8f-9948-bd3a88964134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604890405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2604890405
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.467188408
Short name T360
Test name
Test status
Simulation time 69613157 ps
CPU time 0.78 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 200484 kb
Host smart-8b7fff93-fe63-4ca5-8db2-6d5207b26cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467188408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.467188408
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.477298492
Short name T383
Test name
Test status
Simulation time 1234248549 ps
CPU time 5.22 seconds
Started Aug 12 05:18:00 PM PDT 24
Finished Aug 12 05:18:05 PM PDT 24
Peak memory 221856 kb
Host smart-c747e476-8d38-47b9-acde-002040b0eb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477298492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.477298492
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2166520459
Short name T182
Test name
Test status
Simulation time 244401441 ps
CPU time 1.07 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:03 PM PDT 24
Peak memory 217764 kb
Host smart-630416a8-403f-4524-9825-00eb372b81f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166520459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2166520459
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.2742964826
Short name T496
Test name
Test status
Simulation time 104416004 ps
CPU time 0.79 seconds
Started Aug 12 05:18:04 PM PDT 24
Finished Aug 12 05:18:05 PM PDT 24
Peak memory 200416 kb
Host smart-bd586f8b-1c2a-4fea-9c35-d0b8275d63ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742964826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2742964826
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3007969917
Short name T384
Test name
Test status
Simulation time 1237086256 ps
CPU time 4.81 seconds
Started Aug 12 05:18:04 PM PDT 24
Finished Aug 12 05:18:09 PM PDT 24
Peak memory 200760 kb
Host smart-58024b6c-5477-457b-827c-7254b5dae7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007969917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3007969917
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3487966588
Short name T506
Test name
Test status
Simulation time 186237568 ps
CPU time 1.14 seconds
Started Aug 12 05:18:07 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 200616 kb
Host smart-a7b34a5e-dd3c-4b4c-b520-4a5855cf34ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487966588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3487966588
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1765139072
Short name T493
Test name
Test status
Simulation time 121775327 ps
CPU time 1.18 seconds
Started Aug 12 05:18:07 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 200692 kb
Host smart-eeeaf168-9a89-4f67-b768-3e9e30a8b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765139072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1765139072
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2677803158
Short name T213
Test name
Test status
Simulation time 2798754623 ps
CPU time 10.32 seconds
Started Aug 12 05:18:02 PM PDT 24
Finished Aug 12 05:18:12 PM PDT 24
Peak memory 200824 kb
Host smart-6df610cf-3f6e-4d63-90e9-1678e2fc24de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677803158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2677803158
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.724770269
Short name T337
Test name
Test status
Simulation time 320191782 ps
CPU time 2.06 seconds
Started Aug 12 05:18:03 PM PDT 24
Finished Aug 12 05:18:05 PM PDT 24
Peak memory 200500 kb
Host smart-b4f57d8e-835b-4a1a-80cb-08e2fefe4cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724770269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.724770269
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.4289957435
Short name T480
Test name
Test status
Simulation time 75663105 ps
CPU time 0.82 seconds
Started Aug 12 05:18:04 PM PDT 24
Finished Aug 12 05:18:05 PM PDT 24
Peak memory 200648 kb
Host smart-07d6160c-357e-4e67-9a15-fb4c46e87f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289957435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.4289957435
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3612536153
Short name T2
Test name
Test status
Simulation time 80775587 ps
CPU time 0.79 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200508 kb
Host smart-5e4d4dc7-95cb-46c5-9d32-8fa70fdd63c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612536153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3612536153
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3187730946
Short name T41
Test name
Test status
Simulation time 2173135760 ps
CPU time 7.8 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 217192 kb
Host smart-834a9367-0d53-4756-ae99-d99895159f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187730946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3187730946
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.182104364
Short name T346
Test name
Test status
Simulation time 244375249 ps
CPU time 1.01 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 217820 kb
Host smart-5a0678ff-a78b-4103-a129-789aab7600f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182104364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.182104364
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1324650268
Short name T326
Test name
Test status
Simulation time 179074592 ps
CPU time 0.88 seconds
Started Aug 12 05:18:03 PM PDT 24
Finished Aug 12 05:18:04 PM PDT 24
Peak memory 200472 kb
Host smart-124e2aa2-f445-490e-8364-da803f8e7ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324650268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1324650268
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3408385880
Short name T279
Test name
Test status
Simulation time 841505368 ps
CPU time 4.24 seconds
Started Aug 12 05:17:59 PM PDT 24
Finished Aug 12 05:18:04 PM PDT 24
Peak memory 200796 kb
Host smart-c23300b9-38ed-45e2-bc66-a030d9236504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408385880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3408385880
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1468054258
Short name T143
Test name
Test status
Simulation time 112360462 ps
CPU time 0.98 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:11 PM PDT 24
Peak memory 200648 kb
Host smart-e46e4968-9317-4475-83b0-88f683a10192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468054258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1468054258
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3436499143
Short name T273
Test name
Test status
Simulation time 240748468 ps
CPU time 1.42 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 200716 kb
Host smart-9b53d7f9-f084-41b5-b5da-d6cc2fd2a3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436499143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3436499143
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2753511323
Short name T457
Test name
Test status
Simulation time 2062664600 ps
CPU time 9.27 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:19 PM PDT 24
Peak memory 200772 kb
Host smart-bdd7fb4e-4eb0-4afc-b9e6-c78d6ea7e1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753511323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2753511323
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.4180190120
Short name T517
Test name
Test status
Simulation time 234235584 ps
CPU time 1.45 seconds
Started Aug 12 05:18:08 PM PDT 24
Finished Aug 12 05:18:09 PM PDT 24
Peak memory 200752 kb
Host smart-9f0858c1-5d43-4eec-b65b-4f4c0c4153de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180190120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4180190120
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.660927866
Short name T450
Test name
Test status
Simulation time 53239389 ps
CPU time 0.68 seconds
Started Aug 12 05:18:08 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 200464 kb
Host smart-bca83df8-6f7d-496e-b85d-de8ef040435c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660927866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.660927866
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.4128351331
Short name T428
Test name
Test status
Simulation time 2172927900 ps
CPU time 7.31 seconds
Started Aug 12 05:18:08 PM PDT 24
Finished Aug 12 05:18:16 PM PDT 24
Peak memory 218056 kb
Host smart-24183792-d583-4724-9e3a-a125882e9196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128351331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.4128351331
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3668015521
Short name T529
Test name
Test status
Simulation time 244497075 ps
CPU time 1.05 seconds
Started Aug 12 05:18:14 PM PDT 24
Finished Aug 12 05:18:16 PM PDT 24
Peak memory 217828 kb
Host smart-130e1e23-da78-4411-b22a-3a0d968db3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668015521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3668015521
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1222850523
Short name T460
Test name
Test status
Simulation time 86149290 ps
CPU time 0.77 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200416 kb
Host smart-1349bb16-0100-41f1-aaa6-3f49896623a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222850523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1222850523
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3769697835
Short name T100
Test name
Test status
Simulation time 1351337851 ps
CPU time 5.32 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:14 PM PDT 24
Peak memory 200788 kb
Host smart-ce10a14b-f20b-4c07-b43d-1c5419d30643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769697835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3769697835
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2843021500
Short name T270
Test name
Test status
Simulation time 156234104 ps
CPU time 1.14 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:11 PM PDT 24
Peak memory 200628 kb
Host smart-e55d649c-194c-4233-82d9-d45423a9d4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843021500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2843021500
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3962990588
Short name T500
Test name
Test status
Simulation time 118109532 ps
CPU time 1.16 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200692 kb
Host smart-c1c83d73-1d96-41a6-9b08-774ff0fddf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962990588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3962990588
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2191594857
Short name T472
Test name
Test status
Simulation time 2283840906 ps
CPU time 9.35 seconds
Started Aug 12 05:18:07 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 200860 kb
Host smart-2825e6e7-2887-4ce7-8bdd-c844743fd851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191594857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2191594857
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2836773105
Short name T158
Test name
Test status
Simulation time 137622877 ps
CPU time 1.69 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:11 PM PDT 24
Peak memory 200516 kb
Host smart-6b087737-4f65-4291-9cb0-b16deed38fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836773105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2836773105
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.2079081211
Short name T282
Test name
Test status
Simulation time 152787261 ps
CPU time 1.11 seconds
Started Aug 12 05:18:07 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 200628 kb
Host smart-83592f3c-f46d-4d5d-b3ae-9332577f3ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079081211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2079081211
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2669643497
Short name T27
Test name
Test status
Simulation time 80025291 ps
CPU time 0.82 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:11 PM PDT 24
Peak memory 200492 kb
Host smart-2f3cce2d-6c7d-4d28-9928-30f123d0c7d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669643497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2669643497
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2333406273
Short name T36
Test name
Test status
Simulation time 2364301433 ps
CPU time 7.56 seconds
Started Aug 12 05:18:05 PM PDT 24
Finished Aug 12 05:18:13 PM PDT 24
Peak memory 218024 kb
Host smart-96d370aa-9581-4b94-b818-59ce8bf6d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333406273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2333406273
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.202852764
Short name T170
Test name
Test status
Simulation time 243817973 ps
CPU time 1.11 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 217824 kb
Host smart-fd52dfe7-80e3-4233-a39d-b9f9b88554d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202852764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.202852764
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2096036288
Short name T526
Test name
Test status
Simulation time 86289459 ps
CPU time 0.75 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200448 kb
Host smart-1c2ac140-55b2-4358-99ab-8fcc969853e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096036288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2096036288
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2724264399
Short name T531
Test name
Test status
Simulation time 1538006003 ps
CPU time 6.88 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 200768 kb
Host smart-4012977a-fe98-44a9-afe0-cd7c0b8036ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724264399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2724264399
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1287270780
Short name T286
Test name
Test status
Simulation time 147745314 ps
CPU time 1.1 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200636 kb
Host smart-1517857e-2f66-4511-a06a-2d2e4a057373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287270780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1287270780
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.1552402713
Short name T157
Test name
Test status
Simulation time 201164641 ps
CPU time 1.38 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:11 PM PDT 24
Peak memory 200876 kb
Host smart-c48430da-caa9-45a4-bb70-cf4402982a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552402713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1552402713
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1235754237
Short name T29
Test name
Test status
Simulation time 5789860449 ps
CPU time 19.34 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:30 PM PDT 24
Peak memory 209052 kb
Host smart-4cc0f65f-00e2-44ad-a3bb-a90c388a8aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235754237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1235754237
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2708886370
Short name T252
Test name
Test status
Simulation time 123744472 ps
CPU time 1.62 seconds
Started Aug 12 05:18:11 PM PDT 24
Finished Aug 12 05:18:13 PM PDT 24
Peak memory 208664 kb
Host smart-af4355db-cdb1-4907-8c32-c6eb378dcca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708886370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2708886370
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1279118250
Short name T200
Test name
Test status
Simulation time 161488078 ps
CPU time 1.24 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:12 PM PDT 24
Peak memory 200732 kb
Host smart-048b9767-6396-4606-8c62-006be51856b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279118250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1279118250
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3426480816
Short name T321
Test name
Test status
Simulation time 93405179 ps
CPU time 0.82 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200476 kb
Host smart-fba4dd84-0d13-4c78-8de0-5f1c611cf77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426480816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3426480816
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1647172997
Short name T310
Test name
Test status
Simulation time 1877179125 ps
CPU time 6.98 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 217808 kb
Host smart-d1ffa0b4-5b9a-4dba-a09d-6940ecda6682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647172997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1647172997
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2015559531
Short name T528
Test name
Test status
Simulation time 250528781 ps
CPU time 1.05 seconds
Started Aug 12 05:18:11 PM PDT 24
Finished Aug 12 05:18:12 PM PDT 24
Peak memory 217836 kb
Host smart-9ea6a002-edf3-41c7-8f08-5bfdafa7c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015559531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2015559531
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3051830472
Short name T366
Test name
Test status
Simulation time 166749138 ps
CPU time 0.89 seconds
Started Aug 12 05:18:08 PM PDT 24
Finished Aug 12 05:18:09 PM PDT 24
Peak memory 200412 kb
Host smart-eb7629cc-fad6-43ed-8d12-0f4c3290f994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051830472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3051830472
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1271042645
Short name T499
Test name
Test status
Simulation time 1066703700 ps
CPU time 4.19 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:13 PM PDT 24
Peak memory 200724 kb
Host smart-886eb1fe-ac6d-46a1-ae26-919c54724770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271042645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1271042645
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3300868870
Short name T215
Test name
Test status
Simulation time 107871490 ps
CPU time 0.98 seconds
Started Aug 12 05:18:12 PM PDT 24
Finished Aug 12 05:18:13 PM PDT 24
Peak memory 200612 kb
Host smart-1bcbe246-4a6a-418c-8168-8f05008a40dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300868870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3300868870
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.206262696
Short name T253
Test name
Test status
Simulation time 197025168 ps
CPU time 1.43 seconds
Started Aug 12 05:18:08 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200744 kb
Host smart-3859c8c2-eb48-4961-b66b-15cd9bc40f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206262696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.206262696
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2689021370
Short name T336
Test name
Test status
Simulation time 6748832029 ps
CPU time 23.72 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 209048 kb
Host smart-d4ab9e9c-6d51-4f54-b89a-18f9ea151cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689021370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2689021370
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.327159716
Short name T515
Test name
Test status
Simulation time 142374637 ps
CPU time 1.73 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:12 PM PDT 24
Peak memory 200516 kb
Host smart-c126c114-1069-49b6-a297-83f3501d4076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327159716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.327159716
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1523626232
Short name T205
Test name
Test status
Simulation time 160371591 ps
CPU time 1.23 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200700 kb
Host smart-06a69d3c-5fb7-4441-bfdd-74d8fcdd67fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523626232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1523626232
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3578763833
Short name T214
Test name
Test status
Simulation time 67028283 ps
CPU time 0.72 seconds
Started Aug 12 05:18:16 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 200504 kb
Host smart-fb4c33df-663d-480e-b83a-84318eebe1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578763833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3578763833
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3535457290
Short name T441
Test name
Test status
Simulation time 2343505523 ps
CPU time 8.04 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 221844 kb
Host smart-0f567969-af0a-472c-b766-dd5c4918f087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535457290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3535457290
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3913193967
Short name T349
Test name
Test status
Simulation time 244408276 ps
CPU time 1.04 seconds
Started Aug 12 05:18:19 PM PDT 24
Finished Aug 12 05:18:20 PM PDT 24
Peak memory 217856 kb
Host smart-5f7f9139-124c-4302-8524-1db65fc601e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913193967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3913193967
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2075308331
Short name T396
Test name
Test status
Simulation time 89287136 ps
CPU time 0.74 seconds
Started Aug 12 05:18:09 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 200436 kb
Host smart-482281c0-e583-4268-bc8d-2bcbd1ac04db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075308331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2075308331
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2734535393
Short name T527
Test name
Test status
Simulation time 934037722 ps
CPU time 4.68 seconds
Started Aug 12 05:18:07 PM PDT 24
Finished Aug 12 05:18:12 PM PDT 24
Peak memory 200772 kb
Host smart-689f2bdc-abd8-4abd-bb10-7d622fea44cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734535393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2734535393
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1307151809
Short name T423
Test name
Test status
Simulation time 104066033 ps
CPU time 0.96 seconds
Started Aug 12 05:18:07 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 200552 kb
Host smart-2658937a-b565-4e25-9854-98508ffec493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307151809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1307151809
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1682532380
Short name T10
Test name
Test status
Simulation time 255115901 ps
CPU time 1.58 seconds
Started Aug 12 05:18:10 PM PDT 24
Finished Aug 12 05:18:11 PM PDT 24
Peak memory 200704 kb
Host smart-c0eb1f68-0b16-40b4-b718-acd05c41fde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682532380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1682532380
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.749873311
Short name T543
Test name
Test status
Simulation time 5033121994 ps
CPU time 18.47 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200896 kb
Host smart-6eb32a9d-d8d3-4c61-92a6-19cd1da2e2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749873311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.749873311
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2977123592
Short name T444
Test name
Test status
Simulation time 128079872 ps
CPU time 1.68 seconds
Started Aug 12 05:18:11 PM PDT 24
Finished Aug 12 05:18:13 PM PDT 24
Peak memory 200472 kb
Host smart-6df9e7dc-3131-498b-b7ff-bb6cc50dd84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977123592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2977123592
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3636745731
Short name T382
Test name
Test status
Simulation time 121739775 ps
CPU time 1.04 seconds
Started Aug 12 05:18:08 PM PDT 24
Finished Aug 12 05:18:09 PM PDT 24
Peak memory 200656 kb
Host smart-8550fcd6-2aa8-431e-8c36-c11a55914048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636745731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3636745731
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1884825110
Short name T443
Test name
Test status
Simulation time 57287616 ps
CPU time 0.71 seconds
Started Aug 12 05:18:14 PM PDT 24
Finished Aug 12 05:18:15 PM PDT 24
Peak memory 200296 kb
Host smart-c89e5c0c-948f-4c2b-91fa-b6dd68f077c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884825110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1884825110
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2546815540
Short name T33
Test name
Test status
Simulation time 1223744756 ps
CPU time 5.95 seconds
Started Aug 12 05:18:21 PM PDT 24
Finished Aug 12 05:18:27 PM PDT 24
Peak memory 221916 kb
Host smart-0cb1ab67-d470-4258-a648-462c240959e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546815540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2546815540
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4225517529
Short name T328
Test name
Test status
Simulation time 243451662 ps
CPU time 1.09 seconds
Started Aug 12 05:18:22 PM PDT 24
Finished Aug 12 05:18:23 PM PDT 24
Peak memory 217868 kb
Host smart-a8544476-d100-4c55-96ba-49f6af62fa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225517529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4225517529
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1920401340
Short name T370
Test name
Test status
Simulation time 167274879 ps
CPU time 0.83 seconds
Started Aug 12 05:18:15 PM PDT 24
Finished Aug 12 05:18:16 PM PDT 24
Peak memory 200428 kb
Host smart-b83cd179-a9fa-41e3-934d-1811e52aedc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920401340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1920401340
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3670955903
Short name T102
Test name
Test status
Simulation time 747213089 ps
CPU time 3.76 seconds
Started Aug 12 05:18:16 PM PDT 24
Finished Aug 12 05:18:20 PM PDT 24
Peak memory 200780 kb
Host smart-4f2ac714-c0e9-4482-9785-10c3651b0566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670955903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3670955903
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3373437123
Short name T145
Test name
Test status
Simulation time 151030360 ps
CPU time 1.12 seconds
Started Aug 12 05:18:16 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 200636 kb
Host smart-23d45ab4-cb49-4295-afdc-b67a3210f6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373437123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3373437123
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2109302787
Short name T305
Test name
Test status
Simulation time 121245865 ps
CPU time 1.21 seconds
Started Aug 12 05:18:22 PM PDT 24
Finished Aug 12 05:18:23 PM PDT 24
Peak memory 200736 kb
Host smart-b51a4040-0067-472f-ac06-319a77b09db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109302787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2109302787
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2941251676
Short name T412
Test name
Test status
Simulation time 6278323247 ps
CPU time 26.15 seconds
Started Aug 12 05:18:16 PM PDT 24
Finished Aug 12 05:18:42 PM PDT 24
Peak memory 209048 kb
Host smart-beaa3031-1e0e-4a44-9261-58361cb75765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941251676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2941251676
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2918156868
Short name T269
Test name
Test status
Simulation time 368531679 ps
CPU time 2.03 seconds
Started Aug 12 05:18:17 PM PDT 24
Finished Aug 12 05:18:19 PM PDT 24
Peak memory 200500 kb
Host smart-bf9245d5-1847-49d4-a0d9-4c1cdd8aad04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918156868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2918156868
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3937814607
Short name T152
Test name
Test status
Simulation time 106282404 ps
CPU time 0.96 seconds
Started Aug 12 05:18:15 PM PDT 24
Finished Aug 12 05:18:16 PM PDT 24
Peak memory 200604 kb
Host smart-97019345-da98-4560-8486-d97ce6051f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937814607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3937814607
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2489767074
Short name T371
Test name
Test status
Simulation time 64621301 ps
CPU time 0.74 seconds
Started Aug 12 05:18:14 PM PDT 24
Finished Aug 12 05:18:14 PM PDT 24
Peak memory 200408 kb
Host smart-7aced341-3833-4a68-8fe0-5888c7e0dfa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489767074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2489767074
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1180518244
Short name T451
Test name
Test status
Simulation time 2362382376 ps
CPU time 7.71 seconds
Started Aug 12 05:18:17 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 217996 kb
Host smart-4891887e-34c9-4739-b0ae-8de8e767e024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180518244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1180518244
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2951218527
Short name T453
Test name
Test status
Simulation time 244610517 ps
CPU time 1.06 seconds
Started Aug 12 05:18:16 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 217784 kb
Host smart-e63121c0-ba90-4fa7-96c7-5fc75c0eb72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951218527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2951218527
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.676585568
Short name T438
Test name
Test status
Simulation time 139789942 ps
CPU time 0.79 seconds
Started Aug 12 05:18:14 PM PDT 24
Finished Aug 12 05:18:15 PM PDT 24
Peak memory 200480 kb
Host smart-2f3012d4-7975-4c12-8420-9a0858f8087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676585568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.676585568
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.338605415
Short name T79
Test name
Test status
Simulation time 748611178 ps
CPU time 4.06 seconds
Started Aug 12 05:18:19 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 200764 kb
Host smart-6245ee19-5c4d-40d6-83f9-915f8f5efb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338605415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.338605415
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1247213661
Short name T381
Test name
Test status
Simulation time 105647784 ps
CPU time 0.99 seconds
Started Aug 12 05:18:16 PM PDT 24
Finished Aug 12 05:18:17 PM PDT 24
Peak memory 200620 kb
Host smart-9ca1ff91-c540-493c-854f-5c9a3d76d84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247213661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1247213661
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1666638568
Short name T176
Test name
Test status
Simulation time 182237202 ps
CPU time 1.32 seconds
Started Aug 12 05:18:18 PM PDT 24
Finished Aug 12 05:18:20 PM PDT 24
Peak memory 200772 kb
Host smart-4a88468b-2942-4fcb-99a1-7ceb5f00b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666638568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1666638568
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.1644533258
Short name T241
Test name
Test status
Simulation time 9695519708 ps
CPU time 38.07 seconds
Started Aug 12 05:18:19 PM PDT 24
Finished Aug 12 05:18:58 PM PDT 24
Peak memory 200828 kb
Host smart-0af0648a-27a5-44cb-9d64-e84fb1c093e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644533258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1644533258
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.687279335
Short name T230
Test name
Test status
Simulation time 378867227 ps
CPU time 2.18 seconds
Started Aug 12 05:18:15 PM PDT 24
Finished Aug 12 05:18:18 PM PDT 24
Peak memory 208676 kb
Host smart-e45ba942-64b5-4f7f-b464-497775108bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687279335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.687279335
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.3766245342
Short name T13
Test name
Test status
Simulation time 71582830 ps
CPU time 0.81 seconds
Started Aug 12 05:18:18 PM PDT 24
Finished Aug 12 05:18:19 PM PDT 24
Peak memory 200684 kb
Host smart-605b0e57-03b3-4279-a5d2-ead38f5b8ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766245342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3766245342
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3433288871
Short name T459
Test name
Test status
Simulation time 94860510 ps
CPU time 0.84 seconds
Started Aug 12 05:17:45 PM PDT 24
Finished Aug 12 05:17:46 PM PDT 24
Peak memory 200472 kb
Host smart-a4a5aaa4-262d-48f7-aa3a-d7ee57161e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433288871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3433288871
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2861515761
Short name T501
Test name
Test status
Simulation time 2360961508 ps
CPU time 8.15 seconds
Started Aug 12 05:17:44 PM PDT 24
Finished Aug 12 05:17:53 PM PDT 24
Peak memory 221968 kb
Host smart-67e92a07-0aa4-4214-95d0-6a0e93f1ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861515761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2861515761
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2052812724
Short name T362
Test name
Test status
Simulation time 244408052 ps
CPU time 1.05 seconds
Started Aug 12 05:17:51 PM PDT 24
Finished Aug 12 05:17:53 PM PDT 24
Peak memory 217764 kb
Host smart-60568a3c-2e0b-46c2-ba76-2b5e1e86eb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052812724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2052812724
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1650878834
Short name T372
Test name
Test status
Simulation time 138413311 ps
CPU time 0.9 seconds
Started Aug 12 05:17:49 PM PDT 24
Finished Aug 12 05:17:50 PM PDT 24
Peak memory 200416 kb
Host smart-80ceee28-6ef1-4ced-afb7-969209affbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650878834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1650878834
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3343405315
Short name T377
Test name
Test status
Simulation time 1720293171 ps
CPU time 5.84 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:52 PM PDT 24
Peak memory 200688 kb
Host smart-d9e6c2e1-6c77-432a-b951-88406e87720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343405315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3343405315
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2382257962
Short name T153
Test name
Test status
Simulation time 104105501 ps
CPU time 1.08 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:48 PM PDT 24
Peak memory 200632 kb
Host smart-8e729093-b054-47d1-bdec-82c1502788eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382257962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2382257962
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.931876939
Short name T539
Test name
Test status
Simulation time 108989939 ps
CPU time 1.16 seconds
Started Aug 12 05:17:50 PM PDT 24
Finished Aug 12 05:17:51 PM PDT 24
Peak memory 200744 kb
Host smart-1178638b-0a8e-42c6-95e1-181a3036b96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931876939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.931876939
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2825573959
Short name T126
Test name
Test status
Simulation time 2306934002 ps
CPU time 8.03 seconds
Started Aug 12 05:17:48 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 200804 kb
Host smart-5ec03cdf-76c4-4c2e-8b40-7c61267ebf71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825573959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2825573959
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1733805437
Short name T243
Test name
Test status
Simulation time 146249525 ps
CPU time 1.65 seconds
Started Aug 12 05:17:45 PM PDT 24
Finished Aug 12 05:17:47 PM PDT 24
Peak memory 200440 kb
Host smart-d5b7af73-0899-447e-b1ea-9de454bc5cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733805437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1733805437
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2498634765
Short name T311
Test name
Test status
Simulation time 70736951 ps
CPU time 0.82 seconds
Started Aug 12 05:17:47 PM PDT 24
Finished Aug 12 05:17:48 PM PDT 24
Peak memory 200600 kb
Host smart-450d79ef-fdec-43a0-b570-781c43d09d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498634765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2498634765
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3989398530
Short name T266
Test name
Test status
Simulation time 66408755 ps
CPU time 0.74 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 200408 kb
Host smart-00b28a31-eeb8-49a0-9537-adfbf16ba75a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989398530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3989398530
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3315512069
Short name T475
Test name
Test status
Simulation time 2355081330 ps
CPU time 9.61 seconds
Started Aug 12 05:18:24 PM PDT 24
Finished Aug 12 05:18:34 PM PDT 24
Peak memory 222008 kb
Host smart-88d358ff-3bcd-4c64-815e-2a8be750e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315512069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3315512069
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3142445150
Short name T276
Test name
Test status
Simulation time 244368974 ps
CPU time 1.04 seconds
Started Aug 12 05:18:22 PM PDT 24
Finished Aug 12 05:18:23 PM PDT 24
Peak memory 217864 kb
Host smart-80cace17-7bbc-488c-980b-d8bd8ebb7f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142445150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3142445150
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.4152188764
Short name T25
Test name
Test status
Simulation time 155333168 ps
CPU time 0.83 seconds
Started Aug 12 05:18:18 PM PDT 24
Finished Aug 12 05:18:18 PM PDT 24
Peak memory 200488 kb
Host smart-2caaabf6-7208-4fa4-bd57-6bb25054180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152188764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.4152188764
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.2947237116
Short name T98
Test name
Test status
Simulation time 954755149 ps
CPU time 5.15 seconds
Started Aug 12 05:18:17 PM PDT 24
Finished Aug 12 05:18:22 PM PDT 24
Peak memory 200820 kb
Host smart-02e8e840-2da8-49f3-9283-47448a251289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947237116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2947237116
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3880708712
Short name T144
Test name
Test status
Simulation time 107065064 ps
CPU time 1.02 seconds
Started Aug 12 05:18:22 PM PDT 24
Finished Aug 12 05:18:23 PM PDT 24
Peak memory 200548 kb
Host smart-db23f523-e6c8-4e76-9dbd-6cdf2f2674fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880708712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3880708712
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2854870546
Short name T489
Test name
Test status
Simulation time 116903264 ps
CPU time 1.17 seconds
Started Aug 12 05:18:20 PM PDT 24
Finished Aug 12 05:18:21 PM PDT 24
Peak memory 200704 kb
Host smart-7803a28a-ae68-43da-8887-611498839aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854870546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2854870546
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2289470871
Short name T292
Test name
Test status
Simulation time 320959013 ps
CPU time 2.02 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:26 PM PDT 24
Peak memory 200780 kb
Host smart-674386e7-1444-4cf8-85ae-251a7dd83e19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289470871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2289470871
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3708330219
Short name T509
Test name
Test status
Simulation time 119371742 ps
CPU time 1.64 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:25 PM PDT 24
Peak memory 200504 kb
Host smart-744ec3d2-4bde-46dc-a658-9f14ef4cafe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708330219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3708330219
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.2167402742
Short name T188
Test name
Test status
Simulation time 121737177 ps
CPU time 1.14 seconds
Started Aug 12 05:18:24 PM PDT 24
Finished Aug 12 05:18:25 PM PDT 24
Peak memory 200608 kb
Host smart-4edd9207-ac99-426d-a179-c06dcb77fece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167402742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2167402742
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.71897876
Short name T226
Test name
Test status
Simulation time 75397713 ps
CPU time 0.76 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 200432 kb
Host smart-83f0ec88-433e-4d25-b698-59a54ba397d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71897876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.71897876
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2824114452
Short name T414
Test name
Test status
Simulation time 1886006887 ps
CPU time 6.81 seconds
Started Aug 12 05:18:24 PM PDT 24
Finished Aug 12 05:18:31 PM PDT 24
Peak memory 221912 kb
Host smart-ba2b943a-a57c-4986-a7bd-4ae425705774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824114452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2824114452
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2487324776
Short name T167
Test name
Test status
Simulation time 244785156 ps
CPU time 1.2 seconds
Started Aug 12 05:18:25 PM PDT 24
Finished Aug 12 05:18:26 PM PDT 24
Peak memory 217716 kb
Host smart-ab6cb6b5-7f51-4432-bde0-d4078fcc4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487324776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2487324776
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3722042210
Short name T231
Test name
Test status
Simulation time 167749337 ps
CPU time 0.85 seconds
Started Aug 12 05:18:24 PM PDT 24
Finished Aug 12 05:18:25 PM PDT 24
Peak memory 200456 kb
Host smart-66a265eb-e13c-42f4-98d0-4b5091759694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722042210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3722042210
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3311490840
Short name T476
Test name
Test status
Simulation time 1649919338 ps
CPU time 6.4 seconds
Started Aug 12 05:18:24 PM PDT 24
Finished Aug 12 05:18:31 PM PDT 24
Peak memory 200796 kb
Host smart-08a09512-8d2b-4560-b82d-0545f263dfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311490840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3311490840
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3584027620
Short name T524
Test name
Test status
Simulation time 184407349 ps
CPU time 1.2 seconds
Started Aug 12 05:18:22 PM PDT 24
Finished Aug 12 05:18:23 PM PDT 24
Peak memory 200612 kb
Host smart-456dc735-4c0c-48bd-af13-3e6c475e612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584027620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3584027620
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1088894257
Short name T436
Test name
Test status
Simulation time 121414609 ps
CPU time 1.19 seconds
Started Aug 12 05:18:22 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 200736 kb
Host smart-abbf6bd9-5114-46e8-a5d1-00526a3f13a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088894257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1088894257
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.4136533979
Short name T173
Test name
Test status
Simulation time 6249670436 ps
CPU time 21.93 seconds
Started Aug 12 05:18:25 PM PDT 24
Finished Aug 12 05:18:47 PM PDT 24
Peak memory 209052 kb
Host smart-62d7c9bf-d29e-48eb-b130-2c07b6a7bdcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136533979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4136533979
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1246279429
Short name T138
Test name
Test status
Simulation time 156981447 ps
CPU time 1.11 seconds
Started Aug 12 05:18:25 PM PDT 24
Finished Aug 12 05:18:26 PM PDT 24
Peak memory 200676 kb
Host smart-812fd6d1-98d8-4dc7-b5ba-332e49e7ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246279429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1246279429
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2143546093
Short name T204
Test name
Test status
Simulation time 82606817 ps
CPU time 0.86 seconds
Started Aug 12 05:18:28 PM PDT 24
Finished Aug 12 05:18:29 PM PDT 24
Peak memory 200296 kb
Host smart-b050b493-c71f-4e59-b51c-e55994b4bc41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143546093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2143546093
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3390438215
Short name T485
Test name
Test status
Simulation time 1229210627 ps
CPU time 5.47 seconds
Started Aug 12 05:18:22 PM PDT 24
Finished Aug 12 05:18:27 PM PDT 24
Peak memory 221840 kb
Host smart-2d605e83-d977-4e83-bd9e-cc8b4d5ce082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390438215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3390438215
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3276550365
Short name T302
Test name
Test status
Simulation time 243738249 ps
CPU time 1.09 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 217756 kb
Host smart-3fc52fb6-1da0-4190-94c4-16f2877ca0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276550365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3276550365
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.448743569
Short name T400
Test name
Test status
Simulation time 162064102 ps
CPU time 0.91 seconds
Started Aug 12 05:18:25 PM PDT 24
Finished Aug 12 05:18:26 PM PDT 24
Peak memory 200380 kb
Host smart-233dc08b-b6f9-49d4-96e5-90a774a42d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448743569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.448743569
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2720539251
Short name T479
Test name
Test status
Simulation time 1153377071 ps
CPU time 5.21 seconds
Started Aug 12 05:18:21 PM PDT 24
Finished Aug 12 05:18:27 PM PDT 24
Peak memory 200732 kb
Host smart-67254311-fa3d-4752-81eb-6abfbd3e4627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720539251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2720539251
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1856024301
Short name T327
Test name
Test status
Simulation time 110439180 ps
CPU time 1.09 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 200668 kb
Host smart-2b293e8c-7a08-4742-9a62-399f3d0ed50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856024301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1856024301
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3623163878
Short name T60
Test name
Test status
Simulation time 228987950 ps
CPU time 1.37 seconds
Started Aug 12 05:18:22 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 200728 kb
Host smart-23f04810-6f77-4f73-8e55-1ec68084ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623163878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3623163878
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.815489082
Short name T482
Test name
Test status
Simulation time 3407016657 ps
CPU time 15.2 seconds
Started Aug 12 05:18:24 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 200896 kb
Host smart-01811c5e-2639-4bce-b794-26c1b11b6144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815489082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.815489082
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2925224922
Short name T83
Test name
Test status
Simulation time 118989597 ps
CPU time 1.4 seconds
Started Aug 12 05:18:21 PM PDT 24
Finished Aug 12 05:18:23 PM PDT 24
Peak memory 200320 kb
Host smart-1e7af7d3-42c6-4f08-86ab-58d5eb2a0352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925224922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2925224922
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.3018527637
Short name T315
Test name
Test status
Simulation time 114989983 ps
CPU time 0.97 seconds
Started Aug 12 05:18:23 PM PDT 24
Finished Aug 12 05:18:24 PM PDT 24
Peak memory 200624 kb
Host smart-862de8a4-161d-4d27-b999-582eb3399e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018527637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3018527637
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3430398073
Short name T190
Test name
Test status
Simulation time 76114822 ps
CPU time 0.81 seconds
Started Aug 12 05:18:36 PM PDT 24
Finished Aug 12 05:18:37 PM PDT 24
Peak memory 200488 kb
Host smart-7d44e64b-b433-4288-a153-7fcbb0010716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430398073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3430398073
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1664179750
Short name T522
Test name
Test status
Simulation time 1221954957 ps
CPU time 5.52 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:43 PM PDT 24
Peak memory 217492 kb
Host smart-f5597545-3e5c-446d-9b5f-ef29b2483680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664179750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1664179750
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3355694283
Short name T365
Test name
Test status
Simulation time 244834105 ps
CPU time 1.03 seconds
Started Aug 12 05:18:31 PM PDT 24
Finished Aug 12 05:18:32 PM PDT 24
Peak memory 217852 kb
Host smart-e868e0fc-f42a-44b3-a578-49c8bb8ac905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355694283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3355694283
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1413188511
Short name T474
Test name
Test status
Simulation time 121815918 ps
CPU time 0.8 seconds
Started Aug 12 05:18:33 PM PDT 24
Finished Aug 12 05:18:34 PM PDT 24
Peak memory 200436 kb
Host smart-cc3e1bd9-5ca6-4170-9103-5302effa600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413188511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1413188511
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.4073093135
Short name T510
Test name
Test status
Simulation time 1569091764 ps
CPU time 5.94 seconds
Started Aug 12 05:18:29 PM PDT 24
Finished Aug 12 05:18:35 PM PDT 24
Peak memory 200792 kb
Host smart-0d8f8ae1-986a-4c0b-a171-6e3ffa15f382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073093135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4073093135
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2940177490
Short name T268
Test name
Test status
Simulation time 178536640 ps
CPU time 1.22 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:32 PM PDT 24
Peak memory 200644 kb
Host smart-d89a1a7f-4070-4a9b-add3-2d9f69bad122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940177490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2940177490
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.89545750
Short name T55
Test name
Test status
Simulation time 231786347 ps
CPU time 1.43 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:31 PM PDT 24
Peak memory 200664 kb
Host smart-dcb9a914-918d-4e0f-819a-c0ff45743b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89545750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.89545750
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.4143962808
Short name T258
Test name
Test status
Simulation time 4934481567 ps
CPU time 18.81 seconds
Started Aug 12 05:18:34 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 209944 kb
Host smart-b834caae-1ec9-4a8c-8ac7-f914b255ee0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143962808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.4143962808
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1509952276
Short name T81
Test name
Test status
Simulation time 125817355 ps
CPU time 1.64 seconds
Started Aug 12 05:18:35 PM PDT 24
Finished Aug 12 05:18:37 PM PDT 24
Peak memory 208712 kb
Host smart-b4e8deae-1ff4-41d2-a8e7-03ddadf74fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509952276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1509952276
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.653481168
Short name T294
Test name
Test status
Simulation time 92073855 ps
CPU time 0.83 seconds
Started Aug 12 05:18:29 PM PDT 24
Finished Aug 12 05:18:30 PM PDT 24
Peak memory 200636 kb
Host smart-da77630d-a4b7-4bb4-b300-8a69f3a7e475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653481168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.653481168
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2381121795
Short name T147
Test name
Test status
Simulation time 72869259 ps
CPU time 0.81 seconds
Started Aug 12 05:18:33 PM PDT 24
Finished Aug 12 05:18:34 PM PDT 24
Peak memory 200528 kb
Host smart-b5f5a71b-f819-4eda-8d43-16e3f6e39e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381121795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2381121795
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3040384873
Short name T63
Test name
Test status
Simulation time 2352335170 ps
CPU time 8.52 seconds
Started Aug 12 05:18:36 PM PDT 24
Finished Aug 12 05:18:44 PM PDT 24
Peak memory 218184 kb
Host smart-27ff4b9e-6c65-48c0-a06a-664c6e3a84a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040384873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3040384873
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1566674131
Short name T392
Test name
Test status
Simulation time 244912223 ps
CPU time 1.15 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:34 PM PDT 24
Peak memory 217936 kb
Host smart-94bd6ed1-ea19-4a1f-8cd4-825d1b2a1232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566674131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1566674131
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1838316700
Short name T304
Test name
Test status
Simulation time 207994712 ps
CPU time 0.98 seconds
Started Aug 12 05:18:34 PM PDT 24
Finished Aug 12 05:18:36 PM PDT 24
Peak memory 200448 kb
Host smart-8bd210b4-3a57-4b11-9067-0f6f58fd1745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838316700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1838316700
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.58651841
Short name T345
Test name
Test status
Simulation time 932665780 ps
CPU time 4.54 seconds
Started Aug 12 05:18:36 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200740 kb
Host smart-1fa1a9b9-4972-4596-9103-474ab94407db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58651841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.58651841
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1968865104
Short name T217
Test name
Test status
Simulation time 114566095 ps
CPU time 1.05 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:31 PM PDT 24
Peak memory 200612 kb
Host smart-6affc951-b6cb-460b-99aa-7354338d8a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968865104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1968865104
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2856135432
Short name T324
Test name
Test status
Simulation time 206329461 ps
CPU time 1.33 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:32 PM PDT 24
Peak memory 200712 kb
Host smart-34688782-0048-4dd8-87a4-e38a6a48f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856135432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2856135432
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.367937893
Short name T99
Test name
Test status
Simulation time 5420858700 ps
CPU time 24.62 seconds
Started Aug 12 05:18:31 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200884 kb
Host smart-cd504473-5d2e-4b0f-9cbe-f36c6cd34d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367937893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.367937893
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1081562797
Short name T43
Test name
Test status
Simulation time 130192968 ps
CPU time 1.62 seconds
Started Aug 12 05:18:28 PM PDT 24
Finished Aug 12 05:18:30 PM PDT 24
Peak memory 208724 kb
Host smart-e945a3a4-ae2c-4eb5-8913-702f65f7dd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081562797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1081562797
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3315036342
Short name T267
Test name
Test status
Simulation time 154522055 ps
CPU time 1.29 seconds
Started Aug 12 05:18:29 PM PDT 24
Finished Aug 12 05:18:31 PM PDT 24
Peak memory 200728 kb
Host smart-ed207fc7-00fb-4522-8aa6-6371fc88e5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315036342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3315036342
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.81278368
Short name T154
Test name
Test status
Simulation time 77662294 ps
CPU time 0.8 seconds
Started Aug 12 05:18:35 PM PDT 24
Finished Aug 12 05:18:36 PM PDT 24
Peak memory 200484 kb
Host smart-bfdfdcb9-9b70-436b-ba49-fb0a3699e57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81278368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.81278368
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3742053234
Short name T38
Test name
Test status
Simulation time 2354553946 ps
CPU time 8.15 seconds
Started Aug 12 05:18:33 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 218156 kb
Host smart-0ae48578-5337-41d6-8fb0-6ebc3b5d4760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742053234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3742053234
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4256052634
Short name T512
Test name
Test status
Simulation time 244375652 ps
CPU time 1.08 seconds
Started Aug 12 05:18:33 PM PDT 24
Finished Aug 12 05:18:34 PM PDT 24
Peak memory 217844 kb
Host smart-ca8f24f5-98f9-40a6-aa24-bcf2ad0e910b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256052634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4256052634
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3244574970
Short name T536
Test name
Test status
Simulation time 212538585 ps
CPU time 0.89 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 200440 kb
Host smart-9e2772dc-e7d0-45ce-b33f-129ff4953cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244574970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3244574970
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2712169339
Short name T95
Test name
Test status
Simulation time 922241245 ps
CPU time 4.41 seconds
Started Aug 12 05:18:31 PM PDT 24
Finished Aug 12 05:18:36 PM PDT 24
Peak memory 200768 kb
Host smart-eff1c00d-0455-41fd-944c-d75bc59a1b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712169339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2712169339
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1151494930
Short name T245
Test name
Test status
Simulation time 149108921 ps
CPU time 1.1 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:31 PM PDT 24
Peak memory 200560 kb
Host smart-1ee56196-b41e-4eee-b879-5807ac6a8adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151494930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1151494930
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2261849114
Short name T347
Test name
Test status
Simulation time 258958337 ps
CPU time 1.57 seconds
Started Aug 12 05:18:28 PM PDT 24
Finished Aug 12 05:18:30 PM PDT 24
Peak memory 200652 kb
Host smart-6a1a0aad-4d5e-4d2e-9821-bc0c0a42e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261849114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2261849114
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1994737411
Short name T540
Test name
Test status
Simulation time 5332317862 ps
CPU time 19.22 seconds
Started Aug 12 05:18:31 PM PDT 24
Finished Aug 12 05:18:51 PM PDT 24
Peak memory 209048 kb
Host smart-c25f27c3-1620-40f6-a861-2ae3bd610fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994737411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1994737411
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1346515644
Short name T239
Test name
Test status
Simulation time 446910121 ps
CPU time 2.45 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:34 PM PDT 24
Peak memory 200556 kb
Host smart-465999f5-9912-408f-ae32-2bb97be3e886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346515644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1346515644
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1286551675
Short name T137
Test name
Test status
Simulation time 96912292 ps
CPU time 0.92 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 200544 kb
Host smart-c0c9f51b-fc26-4e67-bf0f-14dd4e1f1619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286551675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1286551675
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3479466325
Short name T42
Test name
Test status
Simulation time 81327886 ps
CPU time 0.82 seconds
Started Aug 12 05:18:31 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 200504 kb
Host smart-71749d87-67a9-4538-9320-d767b17717e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479466325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3479466325
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2136414724
Short name T454
Test name
Test status
Simulation time 1223366269 ps
CPU time 5.49 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:36 PM PDT 24
Peak memory 217716 kb
Host smart-dfc5899a-7f1b-41e5-aea5-554b6d2b10c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136414724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2136414724
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3477425231
Short name T211
Test name
Test status
Simulation time 243494582 ps
CPU time 1.36 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 217752 kb
Host smart-cfc6001c-d0e0-4f3b-b017-f6cfd5deda98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477425231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3477425231
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2032769191
Short name T411
Test name
Test status
Simulation time 151696671 ps
CPU time 0.79 seconds
Started Aug 12 05:18:33 PM PDT 24
Finished Aug 12 05:18:34 PM PDT 24
Peak memory 200468 kb
Host smart-700285fc-fbcd-45e3-8bc3-eda0b29e76a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032769191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2032769191
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3383470924
Short name T488
Test name
Test status
Simulation time 807380289 ps
CPU time 4.39 seconds
Started Aug 12 05:18:34 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 200640 kb
Host smart-88ee5c83-4b26-4b26-86ec-9901f66839bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383470924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3383470924
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1881428025
Short name T333
Test name
Test status
Simulation time 178322920 ps
CPU time 1.14 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 200280 kb
Host smart-291fb617-ccc8-4ba2-a0aa-948cf75f0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881428025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1881428025
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3362263272
Short name T247
Test name
Test status
Simulation time 108287120 ps
CPU time 1.2 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 200648 kb
Host smart-82ea0669-8b12-4abc-b1e9-5b2e1574b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362263272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3362263272
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2375513626
Short name T259
Test name
Test status
Simulation time 2146379899 ps
CPU time 9.66 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 210568 kb
Host smart-9b6c10e3-8a77-4a34-b02e-7b5b5b7223f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375513626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2375513626
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2108098163
Short name T291
Test name
Test status
Simulation time 131569358 ps
CPU time 1.75 seconds
Started Aug 12 05:18:33 PM PDT 24
Finished Aug 12 05:18:35 PM PDT 24
Peak memory 200516 kb
Host smart-e416f719-34a3-4533-b7f4-28f018fec5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108098163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2108098163
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2588554449
Short name T300
Test name
Test status
Simulation time 161997625 ps
CPU time 1.28 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 200720 kb
Host smart-db7bf768-c002-4e17-aef5-ac1b363166da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588554449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2588554449
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.36475269
Short name T193
Test name
Test status
Simulation time 75081350 ps
CPU time 0.77 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 200516 kb
Host smart-bf9542b7-b57e-4da6-ab9d-72c175e9f746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36475269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.36475269
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1528532792
Short name T391
Test name
Test status
Simulation time 245066127 ps
CPU time 1.1 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 217868 kb
Host smart-d0325a14-faee-4df0-b4e1-94591f486eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528532792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1528532792
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3383358517
Short name T221
Test name
Test status
Simulation time 230732388 ps
CPU time 1.02 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 200392 kb
Host smart-3f5beaeb-0cde-43a0-b952-a6d414794827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383358517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3383358517
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2804030519
Short name T96
Test name
Test status
Simulation time 768368357 ps
CPU time 3.98 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:34 PM PDT 24
Peak memory 200700 kb
Host smart-f4889a00-fae5-4f99-b475-0e96ffa33efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804030519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2804030519
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2689940105
Short name T525
Test name
Test status
Simulation time 157688840 ps
CPU time 1.13 seconds
Started Aug 12 05:18:30 PM PDT 24
Finished Aug 12 05:18:32 PM PDT 24
Peak memory 200624 kb
Host smart-3e1fd97d-8b15-45f4-8eee-6a49c95623d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689940105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2689940105
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2264894367
Short name T375
Test name
Test status
Simulation time 206984734 ps
CPU time 1.38 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 200760 kb
Host smart-67c76ef9-7c23-4bf5-bcb5-71198ffd74e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264894367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2264894367
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1810567287
Short name T537
Test name
Test status
Simulation time 3077142305 ps
CPU time 10.97 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200848 kb
Host smart-9b374911-d4f3-4697-a085-0c657db2e615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810567287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1810567287
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1392775043
Short name T201
Test name
Test status
Simulation time 138278356 ps
CPU time 1.72 seconds
Started Aug 12 05:18:32 PM PDT 24
Finished Aug 12 05:18:33 PM PDT 24
Peak memory 200520 kb
Host smart-8b794b48-0336-4c4f-883e-cb32dea1a098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392775043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1392775043
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.1199592861
Short name T386
Test name
Test status
Simulation time 219779062 ps
CPU time 1.32 seconds
Started Aug 12 05:18:36 PM PDT 24
Finished Aug 12 05:18:37 PM PDT 24
Peak memory 200624 kb
Host smart-c8af2718-068b-4b1a-b4ec-d39faf7bb242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199592861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1199592861
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.1099130414
Short name T340
Test name
Test status
Simulation time 85244449 ps
CPU time 0.84 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:18:42 PM PDT 24
Peak memory 200508 kb
Host smart-266ed173-548a-4b8b-a050-8a8f546d4869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099130414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1099130414
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.2384214524
Short name T48
Test name
Test status
Simulation time 1219616931 ps
CPU time 6.08 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:18:47 PM PDT 24
Peak memory 221920 kb
Host smart-c9cb9738-0aab-488b-8873-87a7c4c18d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384214524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2384214524
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2240300149
Short name T298
Test name
Test status
Simulation time 249749333 ps
CPU time 0.99 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 209360 kb
Host smart-535928da-2c11-423b-8cbb-c3f9b7d83e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240300149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2240300149
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4210923814
Short name T197
Test name
Test status
Simulation time 162322351 ps
CPU time 0.9 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200456 kb
Host smart-ac52dfec-9257-46da-967b-43db06885e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210923814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4210923814
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.537760188
Short name T348
Test name
Test status
Simulation time 2010053086 ps
CPU time 7.77 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200756 kb
Host smart-30b14aa1-2273-4af0-b00f-cfa05393d17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537760188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.537760188
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1985474425
Short name T494
Test name
Test status
Simulation time 179115545 ps
CPU time 1.19 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200636 kb
Host smart-4bef59e1-fe34-469d-973b-83bad2d868e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985474425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1985474425
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.71876408
Short name T160
Test name
Test status
Simulation time 205661714 ps
CPU time 1.35 seconds
Started Aug 12 05:18:44 PM PDT 24
Finished Aug 12 05:18:45 PM PDT 24
Peak memory 200736 kb
Host smart-26e98aa1-e342-441c-9e26-fcfdff666036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71876408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.71876408
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.4043028656
Short name T128
Test name
Test status
Simulation time 10455410866 ps
CPU time 32.61 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:19:14 PM PDT 24
Peak memory 209048 kb
Host smart-30e04fa3-fc94-406b-bfe2-6bc559656be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043028656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4043028656
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1274340991
Short name T363
Test name
Test status
Simulation time 544371973 ps
CPU time 2.73 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200404 kb
Host smart-b2438158-5006-4043-a53b-c0f0cd2bc2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274340991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1274340991
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3628664081
Short name T181
Test name
Test status
Simulation time 201317416 ps
CPU time 1.32 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200612 kb
Host smart-29ef9e16-55ea-4082-9767-66d64c518536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628664081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3628664081
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1004588116
Short name T174
Test name
Test status
Simulation time 60023914 ps
CPU time 0.69 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200492 kb
Host smart-7d109ad2-ae9a-48ac-bcdf-8b73f96037ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004588116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1004588116
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2654521931
Short name T402
Test name
Test status
Simulation time 1216537255 ps
CPU time 5.99 seconds
Started Aug 12 05:18:40 PM PDT 24
Finished Aug 12 05:18:46 PM PDT 24
Peak memory 217252 kb
Host smart-46541b4e-8bef-4b86-a84d-59c1a8895b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654521931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2654521931
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1888417022
Short name T251
Test name
Test status
Simulation time 243872355 ps
CPU time 1.08 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 217864 kb
Host smart-e8e7558c-1519-4402-9862-1a525573219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888417022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1888417022
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.2194763191
Short name T418
Test name
Test status
Simulation time 173578751 ps
CPU time 0.92 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200424 kb
Host smart-898acbf5-005f-4a21-998d-7656d087d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194763191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2194763191
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2727374171
Short name T545
Test name
Test status
Simulation time 1421051208 ps
CPU time 5.72 seconds
Started Aug 12 05:18:42 PM PDT 24
Finished Aug 12 05:18:48 PM PDT 24
Peak memory 200840 kb
Host smart-f5209a15-b161-4613-9e13-5e245a2b4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727374171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2727374171
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2564701655
Short name T227
Test name
Test status
Simulation time 109571043 ps
CPU time 1 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200676 kb
Host smart-58f68178-14d9-41f6-b5f4-43933723640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564701655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2564701655
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1001243506
Short name T464
Test name
Test status
Simulation time 259490432 ps
CPU time 1.5 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 200744 kb
Host smart-91fb0a8d-a492-4bfd-8b1a-2d3ea177a7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001243506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1001243506
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3608538291
Short name T477
Test name
Test status
Simulation time 6722617976 ps
CPU time 23.72 seconds
Started Aug 12 05:18:43 PM PDT 24
Finished Aug 12 05:19:07 PM PDT 24
Peak memory 200916 kb
Host smart-3ee39020-fecd-4eac-a7c9-ad022ee981e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608538291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3608538291
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.503480923
Short name T177
Test name
Test status
Simulation time 145452937 ps
CPU time 1.84 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200568 kb
Host smart-5e30bcba-9734-4f91-84fb-b60a49ed2c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503480923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.503480923
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2864190180
Short name T202
Test name
Test status
Simulation time 77863707 ps
CPU time 0.78 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 200608 kb
Host smart-29111dac-2f03-43de-945f-25b5609cfa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864190180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2864190180
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.351265750
Short name T254
Test name
Test status
Simulation time 74282458 ps
CPU time 0.73 seconds
Started Aug 12 05:17:44 PM PDT 24
Finished Aug 12 05:17:45 PM PDT 24
Peak memory 200420 kb
Host smart-acf68d40-3836-4f87-9074-cfd8cbc15105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351265750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.351265750
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2228411154
Short name T234
Test name
Test status
Simulation time 1220838613 ps
CPU time 5.73 seconds
Started Aug 12 05:17:45 PM PDT 24
Finished Aug 12 05:17:51 PM PDT 24
Peak memory 222096 kb
Host smart-7e724c83-0c52-41c7-b25e-4077cae54fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228411154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2228411154
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2579812733
Short name T374
Test name
Test status
Simulation time 243289849 ps
CPU time 1.14 seconds
Started Aug 12 05:17:45 PM PDT 24
Finished Aug 12 05:17:47 PM PDT 24
Peak memory 217800 kb
Host smart-71d82462-626d-4307-b0c0-31ef0183f1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579812733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2579812733
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.753425336
Short name T24
Test name
Test status
Simulation time 205776328 ps
CPU time 0.91 seconds
Started Aug 12 05:17:47 PM PDT 24
Finished Aug 12 05:17:48 PM PDT 24
Peak memory 200392 kb
Host smart-c3bbaab4-0781-4085-8eee-79935bdf9228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753425336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.753425336
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3624733602
Short name T325
Test name
Test status
Simulation time 1925791070 ps
CPU time 7.59 seconds
Started Aug 12 05:17:49 PM PDT 24
Finished Aug 12 05:17:56 PM PDT 24
Peak memory 200772 kb
Host smart-3011b2e3-e8bd-4bf9-9be4-aae1796977a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624733602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3624733602
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.726565523
Short name T75
Test name
Test status
Simulation time 16646954784 ps
CPU time 27.23 seconds
Started Aug 12 05:17:47 PM PDT 24
Finished Aug 12 05:18:14 PM PDT 24
Peak memory 217436 kb
Host smart-0587819b-5727-42d1-9e00-a01a09d0ea12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726565523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.726565523
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2062251146
Short name T320
Test name
Test status
Simulation time 186076898 ps
CPU time 1.29 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:47 PM PDT 24
Peak memory 200612 kb
Host smart-4f25589f-d18a-455d-8ddd-0367870717b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062251146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2062251146
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2629883546
Short name T394
Test name
Test status
Simulation time 202362720 ps
CPU time 1.45 seconds
Started Aug 12 05:17:47 PM PDT 24
Finished Aug 12 05:17:49 PM PDT 24
Peak memory 200728 kb
Host smart-9585f91f-dff0-4d31-9f62-0de2e03a6963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629883546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2629883546
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1059398959
Short name T429
Test name
Test status
Simulation time 2140965533 ps
CPU time 10.01 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 208980 kb
Host smart-cbbef512-662c-4b75-86fb-08a2ac801802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059398959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1059398959
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2432251614
Short name T466
Test name
Test status
Simulation time 286359756 ps
CPU time 1.97 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:49 PM PDT 24
Peak memory 200512 kb
Host smart-25ed0375-8c10-46aa-81f0-3293a4ad1ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432251614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2432251614
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2135720277
Short name T498
Test name
Test status
Simulation time 79402953 ps
CPU time 0.89 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:47 PM PDT 24
Peak memory 200660 kb
Host smart-03c18ddd-4cb2-4cdb-aa8d-17ad032b3141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135720277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2135720277
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3887342892
Short name T225
Test name
Test status
Simulation time 86695680 ps
CPU time 0.81 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 200536 kb
Host smart-75dabdb3-70b5-4bd6-b855-a8decb8f0802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887342892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3887342892
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.3334793557
Short name T171
Test name
Test status
Simulation time 1228549813 ps
CPU time 5.66 seconds
Started Aug 12 05:18:40 PM PDT 24
Finished Aug 12 05:18:46 PM PDT 24
Peak memory 217904 kb
Host smart-b0697186-a574-4e49-b445-65fc029038b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334793557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3334793557
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1272837947
Short name T163
Test name
Test status
Simulation time 243374311 ps
CPU time 1.22 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 217760 kb
Host smart-744855a4-44cb-4cb6-b0b8-7ebe904bcdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272837947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1272837947
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1837753103
Short name T184
Test name
Test status
Simulation time 207787710 ps
CPU time 0.96 seconds
Started Aug 12 05:18:36 PM PDT 24
Finished Aug 12 05:18:37 PM PDT 24
Peak memory 200392 kb
Host smart-dc79cd1a-ae81-4a85-89b2-95ab538bc5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837753103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1837753103
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3622294266
Short name T189
Test name
Test status
Simulation time 1521452809 ps
CPU time 6.36 seconds
Started Aug 12 05:18:40 PM PDT 24
Finished Aug 12 05:18:47 PM PDT 24
Peak memory 200792 kb
Host smart-36f2c984-e896-4884-a817-9f5bc4fa7ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622294266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3622294266
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.891301699
Short name T264
Test name
Test status
Simulation time 147065098 ps
CPU time 1.09 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 200708 kb
Host smart-03486ad2-4da2-46c2-93ae-33cff09a30f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891301699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.891301699
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2847934332
Short name T455
Test name
Test status
Simulation time 193573449 ps
CPU time 1.43 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200740 kb
Host smart-7b84f7ea-459e-4ab7-bad6-65487972aef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847934332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2847934332
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2005601767
Short name T103
Test name
Test status
Simulation time 10959206785 ps
CPU time 38.43 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:19:17 PM PDT 24
Peak memory 209056 kb
Host smart-e17d7dd2-1ff3-4d61-bda5-7a6f124c5be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005601767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2005601767
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1010846586
Short name T465
Test name
Test status
Simulation time 403793636 ps
CPU time 2.35 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200556 kb
Host smart-a7f8406f-0e91-40d7-b386-b467ad313938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010846586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1010846586
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3876735047
Short name T284
Test name
Test status
Simulation time 101745251 ps
CPU time 0.86 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 200608 kb
Host smart-1caa02b2-71b6-4615-a527-3270f9e3b7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876735047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3876735047
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2938775385
Short name T469
Test name
Test status
Simulation time 136774271 ps
CPU time 0.95 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 200516 kb
Host smart-69d1f4b9-f291-4700-bfc8-d0daaeb82dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938775385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2938775385
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2003307161
Short name T50
Test name
Test status
Simulation time 2360471776 ps
CPU time 7.99 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:45 PM PDT 24
Peak memory 221992 kb
Host smart-34b4f42d-89d8-45ab-bd2e-5ef481468738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003307161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2003307161
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2959239296
Short name T224
Test name
Test status
Simulation time 244158160 ps
CPU time 1.19 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 217804 kb
Host smart-e85bcecb-0a9c-46a6-8bf5-85399ab5ac45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959239296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2959239296
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1998404543
Short name T21
Test name
Test status
Simulation time 121083084 ps
CPU time 0.84 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200448 kb
Host smart-e332bd5c-2cc9-4fd3-bcac-46522806bac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998404543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1998404543
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3327064029
Short name T495
Test name
Test status
Simulation time 1820009698 ps
CPU time 6.36 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:45 PM PDT 24
Peak memory 200776 kb
Host smart-efa2f04c-ed05-4291-80cc-8f4b499552d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327064029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3327064029
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.956477655
Short name T146
Test name
Test status
Simulation time 176411769 ps
CPU time 1.18 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 200652 kb
Host smart-61adf20d-6035-460b-b58f-d6ff56d241f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956477655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.956477655
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2553952338
Short name T413
Test name
Test status
Simulation time 124822636 ps
CPU time 1.23 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:18:48 PM PDT 24
Peak memory 200764 kb
Host smart-4c465cb6-8569-4265-890b-53bf171735f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553952338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2553952338
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3615051584
Short name T206
Test name
Test status
Simulation time 5279445581 ps
CPU time 21.53 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 200812 kb
Host smart-e34c6048-fce9-4661-8d66-67a0d957368e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615051584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3615051584
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.623712437
Short name T342
Test name
Test status
Simulation time 149731904 ps
CPU time 1.87 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200548 kb
Host smart-2957591f-fd67-4b3c-9ebf-b3c9ba40cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623712437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.623712437
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3698315759
Short name T223
Test name
Test status
Simulation time 165531540 ps
CPU time 1.42 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200712 kb
Host smart-9ad03431-bb83-4cca-95c3-9ae524c3292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698315759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3698315759
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2426729616
Short name T237
Test name
Test status
Simulation time 63356758 ps
CPU time 0.76 seconds
Started Aug 12 05:18:40 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200500 kb
Host smart-cf9a0851-0f36-41f7-bf03-60079663ac50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426729616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2426729616
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1467014793
Short name T49
Test name
Test status
Simulation time 1232923419 ps
CPU time 5.48 seconds
Started Aug 12 05:18:40 PM PDT 24
Finished Aug 12 05:18:45 PM PDT 24
Peak memory 221908 kb
Host smart-6f19b0f9-60cc-4b58-bae6-af30d711d016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467014793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1467014793
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1648879384
Short name T358
Test name
Test status
Simulation time 244825695 ps
CPU time 1.14 seconds
Started Aug 12 05:18:40 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 217892 kb
Host smart-5446c19e-a6d7-491e-8b37-70ee6c7bf263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648879384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1648879384
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3550509515
Short name T20
Test name
Test status
Simulation time 162784894 ps
CPU time 0.81 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 200452 kb
Host smart-f498340f-0734-4f63-a028-1697ab034906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550509515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3550509515
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2839551402
Short name T308
Test name
Test status
Simulation time 763280797 ps
CPU time 4.01 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:43 PM PDT 24
Peak memory 200756 kb
Host smart-7a5a5007-f2b7-42e1-b407-f30902d33e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839551402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2839551402
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1075075108
Short name T467
Test name
Test status
Simulation time 156742676 ps
CPU time 1.13 seconds
Started Aug 12 05:18:40 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200620 kb
Host smart-79e25a3b-78da-4932-8c34-3648c5e61fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075075108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1075075108
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1041231810
Short name T385
Test name
Test status
Simulation time 114746111 ps
CPU time 1.19 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:18:42 PM PDT 24
Peak memory 200716 kb
Host smart-96a9be6e-d520-4826-86d2-71e7f3ee6adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041231810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1041231810
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2122504686
Short name T519
Test name
Test status
Simulation time 4585231711 ps
CPU time 19.38 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:58 PM PDT 24
Peak memory 200856 kb
Host smart-e26776e4-b72b-4157-9bac-dbe6d181af70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122504686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2122504686
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1933845302
Short name T54
Test name
Test status
Simulation time 114410434 ps
CPU time 1.4 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:40 PM PDT 24
Peak memory 200488 kb
Host smart-bec0afd2-cbd1-46b8-9e11-51226fffecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933845302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1933845302
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1457008299
Short name T312
Test name
Test status
Simulation time 165074223 ps
CPU time 1.11 seconds
Started Aug 12 05:18:40 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200604 kb
Host smart-18a1caf6-1df2-4c4f-a4e1-e2e216d00385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457008299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1457008299
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.780975528
Short name T532
Test name
Test status
Simulation time 62402043 ps
CPU time 0.78 seconds
Started Aug 12 05:18:49 PM PDT 24
Finished Aug 12 05:18:50 PM PDT 24
Peak memory 200512 kb
Host smart-1a5ef043-ed6d-4f06-b474-92d7386acea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780975528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.780975528
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3930556028
Short name T3
Test name
Test status
Simulation time 1885248034 ps
CPU time 6.97 seconds
Started Aug 12 05:18:49 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 221900 kb
Host smart-febd2ac4-b0dc-4110-b500-936cb9eb40b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930556028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3930556028
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3209871941
Short name T15
Test name
Test status
Simulation time 243948056 ps
CPU time 1.14 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:50 PM PDT 24
Peak memory 217876 kb
Host smart-61e9d348-ae90-496a-aaa5-43cba0752045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209871941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3209871941
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2286438618
Short name T248
Test name
Test status
Simulation time 136249255 ps
CPU time 0.78 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:18:42 PM PDT 24
Peak memory 200412 kb
Host smart-9af78a25-bd64-40fd-ab52-011a31746295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286438618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2286438618
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.293301521
Short name T507
Test name
Test status
Simulation time 814495017 ps
CPU time 4.19 seconds
Started Aug 12 05:18:41 PM PDT 24
Finished Aug 12 05:18:45 PM PDT 24
Peak memory 200776 kb
Host smart-5e96f092-3002-4d48-9e2b-5a04f6bd901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293301521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.293301521
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3093990983
Short name T398
Test name
Test status
Simulation time 184064550 ps
CPU time 1.26 seconds
Started Aug 12 05:18:45 PM PDT 24
Finished Aug 12 05:18:47 PM PDT 24
Peak memory 200552 kb
Host smart-380d81df-1201-4db9-9eb4-34b7511b4875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093990983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3093990983
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1578765057
Short name T511
Test name
Test status
Simulation time 221817988 ps
CPU time 1.49 seconds
Started Aug 12 05:18:39 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200712 kb
Host smart-7ccdc332-09e9-4433-a4b2-25108c909525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578765057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1578765057
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1128237731
Short name T393
Test name
Test status
Simulation time 1954790087 ps
CPU time 8.63 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 209000 kb
Host smart-2b41c39c-8a0e-4b7b-9ee8-adb3a4c1f2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128237731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1128237731
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1280639489
Short name T486
Test name
Test status
Simulation time 391232467 ps
CPU time 2.13 seconds
Started Aug 12 05:18:38 PM PDT 24
Finished Aug 12 05:18:41 PM PDT 24
Peak memory 200496 kb
Host smart-23d94d36-c192-4f91-9fd5-a55e374c3bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280639489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1280639489
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.379117085
Short name T491
Test name
Test status
Simulation time 157123277 ps
CPU time 1.1 seconds
Started Aug 12 05:18:37 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 200532 kb
Host smart-c20ad783-fc93-4c8a-92f3-52e21081c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379117085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.379117085
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.4158416091
Short name T290
Test name
Test status
Simulation time 86248358 ps
CPU time 0.87 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200464 kb
Host smart-ee307b8e-ed10-4c63-8f3d-4d406c498424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158416091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.4158416091
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.693478972
Short name T287
Test name
Test status
Simulation time 1894712755 ps
CPU time 7.07 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 218152 kb
Host smart-a8736c44-6a79-41f8-a9ee-2e1813e157a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693478972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.693478972
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3954764942
Short name T208
Test name
Test status
Simulation time 245072276 ps
CPU time 1.08 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:50 PM PDT 24
Peak memory 217836 kb
Host smart-4a13060a-9c5d-4a81-b108-2526e295b7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954764942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3954764942
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2316837238
Short name T194
Test name
Test status
Simulation time 109496741 ps
CPU time 0.82 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200456 kb
Host smart-a07a2417-be30-4ff7-a207-26d717f97e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316837238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2316837238
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.133082302
Short name T332
Test name
Test status
Simulation time 817625968 ps
CPU time 4.55 seconds
Started Aug 12 05:18:49 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 200792 kb
Host smart-d2092392-9707-479d-83e8-ff75db202cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133082302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.133082302
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2791477809
Short name T165
Test name
Test status
Simulation time 184162354 ps
CPU time 1.15 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:50 PM PDT 24
Peak memory 200636 kb
Host smart-608eb104-0e97-4d5e-923a-dfc8b7325bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791477809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2791477809
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3322888961
Short name T236
Test name
Test status
Simulation time 5668455146 ps
CPU time 20.79 seconds
Started Aug 12 05:18:49 PM PDT 24
Finished Aug 12 05:19:10 PM PDT 24
Peak memory 209048 kb
Host smart-4d9856b7-ce04-4654-a3e1-3018159b5ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322888961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3322888961
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1020607901
Short name T344
Test name
Test status
Simulation time 348489891 ps
CPU time 2.22 seconds
Started Aug 12 05:18:49 PM PDT 24
Finished Aug 12 05:18:51 PM PDT 24
Peak memory 208712 kb
Host smart-63615ca2-19e7-42d8-bdec-86d28846c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020607901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1020607901
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2353832088
Short name T505
Test name
Test status
Simulation time 134280818 ps
CPU time 1.14 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:18:48 PM PDT 24
Peak memory 200624 kb
Host smart-2d798e88-6c57-4552-8ff3-065b85198b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353832088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2353832088
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.2029402072
Short name T155
Test name
Test status
Simulation time 77489560 ps
CPU time 0.79 seconds
Started Aug 12 05:18:50 PM PDT 24
Finished Aug 12 05:18:51 PM PDT 24
Peak memory 200480 kb
Host smart-02482220-c96e-4b4f-9c94-75e48e1ca442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029402072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2029402072
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3075424424
Short name T62
Test name
Test status
Simulation time 1975300143 ps
CPU time 7.07 seconds
Started Aug 12 05:18:44 PM PDT 24
Finished Aug 12 05:18:52 PM PDT 24
Peak memory 221936 kb
Host smart-4fdd090a-11d9-4676-a934-80b34f7df2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075424424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3075424424
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3139129548
Short name T161
Test name
Test status
Simulation time 246407101 ps
CPU time 1.05 seconds
Started Aug 12 05:18:45 PM PDT 24
Finished Aug 12 05:18:46 PM PDT 24
Peak memory 217860 kb
Host smart-a45127a5-83bd-4493-bb62-a1d7e17d3cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139129548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3139129548
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3034432924
Short name T250
Test name
Test status
Simulation time 156115636 ps
CPU time 0.81 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200420 kb
Host smart-87922d09-fdd0-4320-ada3-d27768ff6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034432924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3034432924
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1646397579
Short name T256
Test name
Test status
Simulation time 1082741460 ps
CPU time 5.17 seconds
Started Aug 12 05:18:50 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 200752 kb
Host smart-d0019d5d-3f0e-4058-81f9-ef3b8e3f27d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646397579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1646397579
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3328928488
Short name T240
Test name
Test status
Simulation time 107623838 ps
CPU time 1.07 seconds
Started Aug 12 05:18:47 PM PDT 24
Finished Aug 12 05:18:48 PM PDT 24
Peak memory 200668 kb
Host smart-6197f476-4530-4996-a501-1f30da4cb61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328928488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3328928488
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2201721616
Short name T272
Test name
Test status
Simulation time 122194981 ps
CPU time 1.22 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200672 kb
Host smart-087a71f8-4546-4551-ba17-b4649d072b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201721616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2201721616
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3476636375
Short name T288
Test name
Test status
Simulation time 3764401841 ps
CPU time 18.14 seconds
Started Aug 12 05:18:50 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 210928 kb
Host smart-04ff4f92-5126-4733-8849-ee5e0d24d35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476636375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3476636375
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2040436998
Short name T164
Test name
Test status
Simulation time 284654186 ps
CPU time 1.82 seconds
Started Aug 12 05:18:49 PM PDT 24
Finished Aug 12 05:18:51 PM PDT 24
Peak memory 200528 kb
Host smart-159feb7f-0263-4014-a198-ea663fa0702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040436998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2040436998
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1657527214
Short name T434
Test name
Test status
Simulation time 159369478 ps
CPU time 1.22 seconds
Started Aug 12 05:18:49 PM PDT 24
Finished Aug 12 05:18:51 PM PDT 24
Peak memory 200648 kb
Host smart-592cb826-142e-49c7-80b7-7db1f6bd0afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657527214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1657527214
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.2777758542
Short name T220
Test name
Test status
Simulation time 66621557 ps
CPU time 0.76 seconds
Started Aug 12 05:18:47 PM PDT 24
Finished Aug 12 05:18:48 PM PDT 24
Peak memory 200500 kb
Host smart-10d275d5-a444-4c23-9b5e-456672ff6320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777758542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2777758542
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.3212106025
Short name T35
Test name
Test status
Simulation time 1889255416 ps
CPU time 7.94 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 217056 kb
Host smart-dd9e19e0-348f-4208-a722-899edc50cf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212106025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3212106025
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.982004292
Short name T421
Test name
Test status
Simulation time 243914821 ps
CPU time 1.12 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:18:48 PM PDT 24
Peak memory 217748 kb
Host smart-4339b04b-4ede-422e-9434-b2f33a23faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982004292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.982004292
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.4065754022
Short name T280
Test name
Test status
Simulation time 97785157 ps
CPU time 0.75 seconds
Started Aug 12 05:18:44 PM PDT 24
Finished Aug 12 05:18:45 PM PDT 24
Peak memory 200392 kb
Host smart-d1ceb4e5-31de-49db-aaf0-b40ca0fa383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065754022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.4065754022
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2434448660
Short name T415
Test name
Test status
Simulation time 2150259384 ps
CPU time 7.55 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 200860 kb
Host smart-b24efaf9-d943-4c1f-b7cd-5f55d3bd9704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434448660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2434448660
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2921363770
Short name T4
Test name
Test status
Simulation time 175149184 ps
CPU time 1.18 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:18:47 PM PDT 24
Peak memory 200584 kb
Host smart-a7213aff-6993-410a-838d-3ff61a92b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921363770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2921363770
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2473208165
Short name T503
Test name
Test status
Simulation time 128738332 ps
CPU time 1.24 seconds
Started Aug 12 05:18:48 PM PDT 24
Finished Aug 12 05:18:50 PM PDT 24
Peak memory 200880 kb
Host smart-011ac9f0-2db3-43e7-9132-a06956a91bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473208165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2473208165
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3873838114
Short name T484
Test name
Test status
Simulation time 10138907774 ps
CPU time 36 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:19:23 PM PDT 24
Peak memory 209080 kb
Host smart-2e9a2627-d5bf-4058-9342-ebc5ef97e522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873838114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3873838114
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.716423818
Short name T82
Test name
Test status
Simulation time 150025013 ps
CPU time 1.81 seconds
Started Aug 12 05:18:47 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200496 kb
Host smart-5cfbc905-b3e6-43fc-9479-bfba6164098e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716423818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.716423818
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1909711020
Short name T263
Test name
Test status
Simulation time 64867212 ps
CPU time 0.78 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 200600 kb
Host smart-4dac7b40-2980-46ba-9bae-e9ca8bf343ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909711020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1909711020
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1796090214
Short name T44
Test name
Test status
Simulation time 94832165 ps
CPU time 0.92 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 200512 kb
Host smart-3a13ccc5-5c9d-4c7c-9198-e65ba4f6c4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796090214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1796090214
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2106795654
Short name T39
Test name
Test status
Simulation time 1913250054 ps
CPU time 6.91 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 218124 kb
Host smart-5c61dbf1-97fd-4bc4-8906-8d5884344619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106795654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2106795654
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3846031989
Short name T28
Test name
Test status
Simulation time 243904116 ps
CPU time 1.08 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 217784 kb
Host smart-c18285c3-4b9a-44a7-a870-40b4a95e82bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846031989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3846031989
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.636533924
Short name T19
Test name
Test status
Simulation time 119570282 ps
CPU time 0.77 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 200380 kb
Host smart-b385fb89-7424-46ea-9905-fb35f19193a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636533924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.636533924
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1349542745
Short name T132
Test name
Test status
Simulation time 809462537 ps
CPU time 3.67 seconds
Started Aug 12 05:18:46 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200808 kb
Host smart-59731828-7531-47c1-b8e3-c965ec3f8ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349542745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1349542745
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.925345355
Short name T179
Test name
Test status
Simulation time 173817428 ps
CPU time 1.27 seconds
Started Aug 12 05:18:47 PM PDT 24
Finished Aug 12 05:18:48 PM PDT 24
Peak memory 200668 kb
Host smart-675189f5-0e92-45c5-8236-fc1f3ba78a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925345355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.925345355
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1547552774
Short name T364
Test name
Test status
Simulation time 113860866 ps
CPU time 1.15 seconds
Started Aug 12 05:18:43 PM PDT 24
Finished Aug 12 05:18:45 PM PDT 24
Peak memory 200660 kb
Host smart-070e3e1e-9b89-402e-873c-638ba4b4e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547552774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1547552774
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2410715235
Short name T416
Test name
Test status
Simulation time 6580090000 ps
CPU time 25.05 seconds
Started Aug 12 05:18:52 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 209020 kb
Host smart-59fee056-a9c0-4d54-88fd-51ed4b04c1c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410715235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2410715235
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3393339617
Short name T544
Test name
Test status
Simulation time 129773744 ps
CPU time 1.6 seconds
Started Aug 12 05:18:47 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 200500 kb
Host smart-bf1eb16f-87f9-4128-a26b-bb01bbe209b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393339617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3393339617
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3892643554
Short name T369
Test name
Test status
Simulation time 109738679 ps
CPU time 0.94 seconds
Started Aug 12 05:18:47 PM PDT 24
Finished Aug 12 05:18:48 PM PDT 24
Peak memory 200632 kb
Host smart-59b2fd16-2ab7-4b1c-b240-cd6727bfddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892643554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3892643554
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2836179138
Short name T335
Test name
Test status
Simulation time 69238668 ps
CPU time 0.74 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200540 kb
Host smart-2f048a71-a9e4-41c6-83b7-e63279c5bc5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836179138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2836179138
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.1869032943
Short name T1
Test name
Test status
Simulation time 1901999743 ps
CPU time 7.2 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:19:00 PM PDT 24
Peak memory 217700 kb
Host smart-9bd65276-89e8-4e51-ab44-33a7a37a7708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869032943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1869032943
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.678555504
Short name T424
Test name
Test status
Simulation time 244774392 ps
CPU time 1.02 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 217824 kb
Host smart-c7845f6a-a6bb-45c4-8ef2-5927695b0fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678555504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.678555504
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3668990966
Short name T390
Test name
Test status
Simulation time 80360247 ps
CPU time 0.74 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200436 kb
Host smart-7c3a34fc-36aa-4b6b-ac54-68742b3cb095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668990966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3668990966
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2124674046
Short name T329
Test name
Test status
Simulation time 1793750334 ps
CPU time 6.82 seconds
Started Aug 12 05:18:50 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200764 kb
Host smart-c2f5eef1-a78e-404f-aa56-6fbe1c9f5bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124674046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2124674046
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1867261012
Short name T523
Test name
Test status
Simulation time 109657019 ps
CPU time 1.05 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 200612 kb
Host smart-c73f5aca-78eb-4b2c-aa89-fb9e4ff2ceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867261012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1867261012
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3246884186
Short name T129
Test name
Test status
Simulation time 259749389 ps
CPU time 1.47 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 200776 kb
Host smart-8693255c-c742-4e90-8d76-a29a1fbc7c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246884186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3246884186
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2601796202
Short name T303
Test name
Test status
Simulation time 3207061148 ps
CPU time 13.12 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 200804 kb
Host smart-ff6e01be-a5e7-4f6f-8687-164fd63b73f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601796202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2601796202
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.436610677
Short name T322
Test name
Test status
Simulation time 123985586 ps
CPU time 1.5 seconds
Started Aug 12 05:18:52 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 200516 kb
Host smart-475ce09f-bdb8-4d16-8d57-6e3f072bfd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436610677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.436610677
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2132851600
Short name T130
Test name
Test status
Simulation time 87615590 ps
CPU time 0.84 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 200556 kb
Host smart-41104dd0-3aa0-4b8a-950d-f29bc83ee6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132851600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2132851600
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.3339348697
Short name T192
Test name
Test status
Simulation time 83996491 ps
CPU time 0.92 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 200516 kb
Host smart-01759395-a198-4194-94f1-5550bf95f1db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339348697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3339348697
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1336831580
Short name T353
Test name
Test status
Simulation time 2336962061 ps
CPU time 8 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:19:04 PM PDT 24
Peak memory 218064 kb
Host smart-d4d809df-93a9-4f79-87ec-4b29cf746289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336831580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1336831580
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.276976677
Short name T330
Test name
Test status
Simulation time 244660001 ps
CPU time 1.04 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 217768 kb
Host smart-e0684180-dce9-431f-b7a5-ef2e1ceb1911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276976677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.276976677
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3379546019
Short name T249
Test name
Test status
Simulation time 223658624 ps
CPU time 0.92 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200436 kb
Host smart-4b1886fa-4e6a-49e5-9662-a4769e70082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379546019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3379546019
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.234253038
Short name T92
Test name
Test status
Simulation time 880040497 ps
CPU time 4.58 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:06 PM PDT 24
Peak memory 200808 kb
Host smart-b2b25191-be89-46a4-a082-2df1deb8d5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234253038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.234253038
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.4125002547
Short name T140
Test name
Test status
Simulation time 105116581 ps
CPU time 1.02 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 200624 kb
Host smart-5796f24a-aa49-4269-be42-abab5a27fcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125002547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.4125002547
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3493835035
Short name T533
Test name
Test status
Simulation time 253079729 ps
CPU time 1.49 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200764 kb
Host smart-a29da1dc-85e9-42e4-9e74-37701bea4d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493835035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3493835035
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3506893006
Short name T514
Test name
Test status
Simulation time 170991825 ps
CPU time 1.1 seconds
Started Aug 12 05:18:51 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 200432 kb
Host smart-02e3093b-6099-40f0-a04c-73d8d56009d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506893006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3506893006
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2312497130
Short name T169
Test name
Test status
Simulation time 278162292 ps
CPU time 1.89 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:18:58 PM PDT 24
Peak memory 200544 kb
Host smart-d745ef00-7780-475b-86cd-23bd34947493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312497130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2312497130
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.454220859
Short name T399
Test name
Test status
Simulation time 154076672 ps
CPU time 1.3 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200532 kb
Host smart-84118aec-f71b-4c34-a3bb-e121318e240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454220859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.454220859
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.79402962
Short name T175
Test name
Test status
Simulation time 61124309 ps
CPU time 0.73 seconds
Started Aug 12 05:17:58 PM PDT 24
Finished Aug 12 05:17:59 PM PDT 24
Peak memory 200492 kb
Host smart-360daf2f-c737-4452-ac07-9a6210c83ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79402962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.79402962
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1422507255
Short name T395
Test name
Test status
Simulation time 1899802679 ps
CPU time 7.26 seconds
Started Aug 12 05:17:48 PM PDT 24
Finished Aug 12 05:17:56 PM PDT 24
Peak memory 221828 kb
Host smart-6bcdbfe6-924d-4d50-aa24-2678cca02c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422507255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1422507255
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.758071690
Short name T277
Test name
Test status
Simulation time 244620271 ps
CPU time 1.1 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:47 PM PDT 24
Peak memory 217748 kb
Host smart-d1e0feeb-c6b8-408d-ba85-b8028f4452c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758071690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.758071690
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3838686488
Short name T534
Test name
Test status
Simulation time 77450628 ps
CPU time 0.72 seconds
Started Aug 12 05:17:45 PM PDT 24
Finished Aug 12 05:17:46 PM PDT 24
Peak memory 200240 kb
Host smart-46c640dd-8bd1-45eb-8c6e-5dd46f7a56e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838686488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3838686488
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3727250875
Short name T452
Test name
Test status
Simulation time 1624376999 ps
CPU time 6.87 seconds
Started Aug 12 05:17:48 PM PDT 24
Finished Aug 12 05:17:55 PM PDT 24
Peak memory 200740 kb
Host smart-1dbf1177-a6b6-4b45-bb58-f2d6e26e7313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727250875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3727250875
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3894932082
Short name T78
Test name
Test status
Simulation time 16813007033 ps
CPU time 24.36 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 218360 kb
Host smart-9d7d630b-5d3e-48ac-b183-10b9f4671bbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894932082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3894932082
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.174135704
Short name T26
Test name
Test status
Simulation time 184447744 ps
CPU time 1.21 seconds
Started Aug 12 05:17:47 PM PDT 24
Finished Aug 12 05:17:49 PM PDT 24
Peak memory 200612 kb
Host smart-0b5d6fe6-9fc1-4c8d-8323-195a017a41fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174135704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.174135704
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3139400933
Short name T131
Test name
Test status
Simulation time 248289913 ps
CPU time 1.48 seconds
Started Aug 12 05:17:46 PM PDT 24
Finished Aug 12 05:17:48 PM PDT 24
Peak memory 200728 kb
Host smart-bd116302-0ce9-4a3b-8d1a-204f6b91d78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139400933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3139400933
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1162186211
Short name T338
Test name
Test status
Simulation time 1789124786 ps
CPU time 6.38 seconds
Started Aug 12 05:17:47 PM PDT 24
Finished Aug 12 05:17:53 PM PDT 24
Peak memory 200812 kb
Host smart-02143ed6-9327-45cb-9d7f-6977f71b0997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162186211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1162186211
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3896727869
Short name T84
Test name
Test status
Simulation time 129149506 ps
CPU time 1.55 seconds
Started Aug 12 05:17:49 PM PDT 24
Finished Aug 12 05:17:51 PM PDT 24
Peak memory 200564 kb
Host smart-d0ad2a30-038a-4d31-a33b-b3b6636ec2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896727869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3896727869
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.49795715
Short name T356
Test name
Test status
Simulation time 67743315 ps
CPU time 0.76 seconds
Started Aug 12 05:17:48 PM PDT 24
Finished Aug 12 05:17:49 PM PDT 24
Peak memory 200656 kb
Host smart-200ef72d-84a5-406a-a655-f1a36d97c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49795715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.49795715
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3326717536
Short name T368
Test name
Test status
Simulation time 70705482 ps
CPU time 0.8 seconds
Started Aug 12 05:18:52 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 200516 kb
Host smart-3b8a4419-1bcb-43fc-bef8-a19a7f136445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326717536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3326717536
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3092510784
Short name T46
Test name
Test status
Simulation time 1225163830 ps
CPU time 6.06 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:06 PM PDT 24
Peak memory 221824 kb
Host smart-1a26dcac-bc20-4314-a3b9-74e4eb53f17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092510784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3092510784
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1870758874
Short name T183
Test name
Test status
Simulation time 244535454 ps
CPU time 1.07 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 217712 kb
Host smart-53eb6a2b-660b-4226-833b-efccd99cdf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870758874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1870758874
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.668435312
Short name T22
Test name
Test status
Simulation time 83064327 ps
CPU time 0.74 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 200360 kb
Host smart-234adbac-0d36-4f78-adf2-92ae0880eeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668435312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.668435312
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.4190909741
Short name T433
Test name
Test status
Simulation time 884195231 ps
CPU time 4.75 seconds
Started Aug 12 05:18:52 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200772 kb
Host smart-d33a3570-b028-4021-8ebc-b207860795e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190909741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4190909741
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.55175512
Short name T492
Test name
Test status
Simulation time 105024309 ps
CPU time 1.02 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200536 kb
Host smart-0e848852-d9ea-468a-ba1e-380d94d0f02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55175512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.55175512
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1742713564
Short name T341
Test name
Test status
Simulation time 122080738 ps
CPU time 1.19 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:18:58 PM PDT 24
Peak memory 200696 kb
Host smart-6ddb9817-a6ef-4507-94c3-38493dcb8896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742713564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1742713564
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2002536379
Short name T45
Test name
Test status
Simulation time 266742576 ps
CPU time 1.89 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200508 kb
Host smart-0bf98f9e-b474-4fe4-b8a0-508196be7740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002536379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2002536379
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3482571653
Short name T357
Test name
Test status
Simulation time 88698683 ps
CPU time 0.84 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 200612 kb
Host smart-d04c22c9-a056-4c78-9285-822b096fbf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482571653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3482571653
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3391877695
Short name T139
Test name
Test status
Simulation time 94649394 ps
CPU time 0.81 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200500 kb
Host smart-fb00f184-6394-40f0-8229-66186e1c4bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391877695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3391877695
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1825008792
Short name T47
Test name
Test status
Simulation time 2155709794 ps
CPU time 7.83 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 218012 kb
Host smart-2fdc4fe9-00b8-43a7-8da1-f776cb35e057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825008792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1825008792
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.877890041
Short name T142
Test name
Test status
Simulation time 244208807 ps
CPU time 1.08 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 217744 kb
Host smart-653df8f8-dfa5-4580-abf6-8ed91a0194ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877890041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.877890041
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.561230832
Short name T352
Test name
Test status
Simulation time 131697730 ps
CPU time 0.79 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 200412 kb
Host smart-de63480a-0527-4edf-9989-74e3ee8cf27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561230832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.561230832
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2750851260
Short name T535
Test name
Test status
Simulation time 1026754920 ps
CPU time 4.95 seconds
Started Aug 12 05:18:51 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200736 kb
Host smart-8f787e49-5c1f-4fab-9116-3ab02e2d95c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750851260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2750851260
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1390983509
Short name T354
Test name
Test status
Simulation time 145572808 ps
CPU time 1.07 seconds
Started Aug 12 05:18:51 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 200644 kb
Host smart-c2ecae63-d7ee-4c2d-91e9-2f8bbfa5fa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390983509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1390983509
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1511253689
Short name T520
Test name
Test status
Simulation time 112943530 ps
CPU time 1.14 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200676 kb
Host smart-43f25080-3e6b-4db5-9636-27c327f385e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511253689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1511253689
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3246598950
Short name T473
Test name
Test status
Simulation time 14164302102 ps
CPU time 46.05 seconds
Started Aug 12 05:18:52 PM PDT 24
Finished Aug 12 05:19:38 PM PDT 24
Peak memory 208992 kb
Host smart-4bebc90f-9465-454e-8b8c-e4780946ebec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246598950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3246598950
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3863500992
Short name T314
Test name
Test status
Simulation time 294242022 ps
CPU time 1.89 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:55 PM PDT 24
Peak memory 208696 kb
Host smart-b847f9ff-a679-4023-b537-e44d94058f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863500992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3863500992
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3136979003
Short name T198
Test name
Test status
Simulation time 240941748 ps
CPU time 1.47 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 200668 kb
Host smart-75ed8e0b-8e86-4755-b937-dc6edbc8eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136979003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3136979003
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.2871373973
Short name T8
Test name
Test status
Simulation time 79730758 ps
CPU time 0.8 seconds
Started Aug 12 05:18:52 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 200372 kb
Host smart-bb28d7fe-128d-43f5-8886-7d0d58299c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871373973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2871373973
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3585479086
Short name T34
Test name
Test status
Simulation time 1907753352 ps
CPU time 8.16 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 217368 kb
Host smart-2350ab20-f2f3-4575-af70-266eeb2f4edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585479086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3585479086
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1030538514
Short name T218
Test name
Test status
Simulation time 243790192 ps
CPU time 1.09 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 217756 kb
Host smart-1560f807-aa64-4f3a-bb1c-a9dcdd61fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030538514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1030538514
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.2694979693
Short name T339
Test name
Test status
Simulation time 114706172 ps
CPU time 0.78 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200404 kb
Host smart-553f149d-a311-4483-ba74-b1d7d61c09a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694979693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2694979693
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2890201258
Short name T405
Test name
Test status
Simulation time 1441453495 ps
CPU time 5.33 seconds
Started Aug 12 05:18:57 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 200740 kb
Host smart-001dda22-bd64-4fec-98fb-8ff6a695fe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890201258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2890201258
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2671975272
Short name T307
Test name
Test status
Simulation time 105563719 ps
CPU time 0.97 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200668 kb
Host smart-7bbb589a-3e53-46ba-b69b-fa74b1562f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671975272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2671975272
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.353890575
Short name T31
Test name
Test status
Simulation time 244038440 ps
CPU time 1.44 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:18:57 PM PDT 24
Peak memory 200688 kb
Host smart-0ad4c1f3-839c-47f6-84a4-8b0190d6bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353890575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.353890575
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2943764853
Short name T422
Test name
Test status
Simulation time 9618693284 ps
CPU time 30.61 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:19:27 PM PDT 24
Peak memory 200752 kb
Host smart-c4a170b6-92ff-4533-a89c-1665e971d803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943764853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2943764853
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2986995549
Short name T228
Test name
Test status
Simulation time 275982554 ps
CPU time 1.87 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200372 kb
Host smart-aa09cb93-6d65-4d67-b01c-cc2ecc97b029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986995549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2986995549
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.493921779
Short name T257
Test name
Test status
Simulation time 75825425 ps
CPU time 0.8 seconds
Started Aug 12 05:19:03 PM PDT 24
Finished Aug 12 05:19:04 PM PDT 24
Peak memory 200508 kb
Host smart-1cfab829-0313-43bd-a72b-977f5ac4ca81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493921779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.493921779
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2886116858
Short name T380
Test name
Test status
Simulation time 1222574715 ps
CPU time 5.38 seconds
Started Aug 12 05:18:55 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 217152 kb
Host smart-b61bcf30-3095-4014-99fc-6bbad7d5bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886116858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2886116858
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3229795068
Short name T542
Test name
Test status
Simulation time 244986912 ps
CPU time 1.15 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 217732 kb
Host smart-327342b7-9b31-4ceb-a557-b8d6dffe3351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229795068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3229795068
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3088043024
Short name T23
Test name
Test status
Simulation time 109492628 ps
CPU time 0.81 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200400 kb
Host smart-a9e2222b-ba24-4a19-8379-4ae7963a9ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088043024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3088043024
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.4086365665
Short name T439
Test name
Test status
Simulation time 956750118 ps
CPU time 4.7 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:59 PM PDT 24
Peak memory 200760 kb
Host smart-0780e0d9-06d4-4a99-8247-3950aa13742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086365665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4086365665
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1372464068
Short name T432
Test name
Test status
Simulation time 144154511 ps
CPU time 1.13 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 200628 kb
Host smart-a0cd4722-2ea0-492d-9522-a95a4afe53bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372464068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1372464068
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1885659358
Short name T306
Test name
Test status
Simulation time 192363927 ps
CPU time 1.34 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 200644 kb
Host smart-10b9da36-83b4-482e-9558-dbb29f6b98ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885659358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1885659358
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1632531548
Short name T127
Test name
Test status
Simulation time 6067377329 ps
CPU time 21.02 seconds
Started Aug 12 05:18:54 PM PDT 24
Finished Aug 12 05:19:16 PM PDT 24
Peak memory 208896 kb
Host smart-f56b9c64-410f-4471-9cc3-4a94eaeb6cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632531548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1632531548
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3209275208
Short name T156
Test name
Test status
Simulation time 368610288 ps
CPU time 2.07 seconds
Started Aug 12 05:18:56 PM PDT 24
Finished Aug 12 05:18:59 PM PDT 24
Peak memory 200676 kb
Host smart-9aa792e6-4599-44ca-a509-14a6fd5ec606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209275208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3209275208
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1715453606
Short name T463
Test name
Test status
Simulation time 153775752 ps
CPU time 1.12 seconds
Started Aug 12 05:18:53 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 200624 kb
Host smart-e9682df7-940b-4217-9048-e6460d28dd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715453606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1715453606
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2288292629
Short name T141
Test name
Test status
Simulation time 60829345 ps
CPU time 0.73 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200516 kb
Host smart-6db39b6f-7778-4169-8eb3-3cf488a89c37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288292629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2288292629
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3451590003
Short name T404
Test name
Test status
Simulation time 1891676076 ps
CPU time 7.3 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 217044 kb
Host smart-05b16829-3a27-457d-a569-8787d0eb72a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451590003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3451590003
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1008809059
Short name T440
Test name
Test status
Simulation time 244065455 ps
CPU time 1.09 seconds
Started Aug 12 05:19:03 PM PDT 24
Finished Aug 12 05:19:04 PM PDT 24
Peak memory 217812 kb
Host smart-b093d407-20e3-469b-a280-a2d4e09e2b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008809059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1008809059
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.1410942896
Short name T212
Test name
Test status
Simulation time 172414772 ps
CPU time 0.96 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200416 kb
Host smart-7019ed20-d461-4297-b5e6-c57af755b510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410942896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1410942896
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1933048351
Short name T445
Test name
Test status
Simulation time 1531508196 ps
CPU time 6.59 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 200772 kb
Host smart-204a01c1-7493-411f-964f-f154293af7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933048351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1933048351
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1177480056
Short name T196
Test name
Test status
Simulation time 175813892 ps
CPU time 1.22 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200620 kb
Host smart-53ccffe2-300a-474c-a78c-fd2bc353775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177480056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1177480056
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1210879180
Short name T447
Test name
Test status
Simulation time 196231502 ps
CPU time 1.43 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200740 kb
Host smart-4e00b7bf-7935-4e9a-a686-470d495e1f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210879180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1210879180
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1000147123
Short name T246
Test name
Test status
Simulation time 3429984190 ps
CPU time 15.77 seconds
Started Aug 12 05:19:05 PM PDT 24
Finished Aug 12 05:19:21 PM PDT 24
Peak memory 208952 kb
Host smart-3e9b57ab-5ef4-42cd-8b44-25dcb2721fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000147123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1000147123
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1266838756
Short name T262
Test name
Test status
Simulation time 125903563 ps
CPU time 1.53 seconds
Started Aug 12 05:19:05 PM PDT 24
Finished Aug 12 05:19:06 PM PDT 24
Peak memory 208616 kb
Host smart-cde44580-aa26-4ee4-a578-fc0adc3be27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266838756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1266838756
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.779040435
Short name T261
Test name
Test status
Simulation time 128317405 ps
CPU time 1.05 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200584 kb
Host smart-a499d01b-3ae7-4b4a-9339-0635e2f7ed4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779040435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.779040435
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.2430728581
Short name T57
Test name
Test status
Simulation time 71275096 ps
CPU time 0.76 seconds
Started Aug 12 05:19:03 PM PDT 24
Finished Aug 12 05:19:04 PM PDT 24
Peak memory 199916 kb
Host smart-64c89054-0459-4237-95f8-b3faa9508110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430728581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.2430728581
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1809218578
Short name T376
Test name
Test status
Simulation time 244250871 ps
CPU time 1.07 seconds
Started Aug 12 05:19:04 PM PDT 24
Finished Aug 12 05:19:05 PM PDT 24
Peak memory 217868 kb
Host smart-9ac43e46-42f6-481c-9903-fb4b6dea0c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809218578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1809218578
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1256960326
Short name T409
Test name
Test status
Simulation time 131996268 ps
CPU time 0.81 seconds
Started Aug 12 05:18:58 PM PDT 24
Finished Aug 12 05:18:59 PM PDT 24
Peak memory 200456 kb
Host smart-d26c9fe2-7175-4644-9588-26b1df361294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256960326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1256960326
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2940273587
Short name T504
Test name
Test status
Simulation time 1424124317 ps
CPU time 5.9 seconds
Started Aug 12 05:19:04 PM PDT 24
Finished Aug 12 05:19:11 PM PDT 24
Peak memory 200780 kb
Host smart-b2ec078f-54db-4bef-893b-2517c16a2340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940273587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2940273587
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2674000017
Short name T301
Test name
Test status
Simulation time 152116068 ps
CPU time 1.12 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200628 kb
Host smart-caeb0ec7-70c0-4099-9ba8-c3d977974d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674000017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2674000017
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4132268190
Short name T232
Test name
Test status
Simulation time 200743611 ps
CPU time 1.42 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200688 kb
Host smart-7c6404d8-9864-4a47-9c19-6ebce0ad2283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132268190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4132268190
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2635785958
Short name T281
Test name
Test status
Simulation time 4091772291 ps
CPU time 14.72 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:16 PM PDT 24
Peak memory 200844 kb
Host smart-f299ddfd-ad87-4588-88a6-7c6f146bc825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635785958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2635785958
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1440701515
Short name T397
Test name
Test status
Simulation time 390485515 ps
CPU time 2.39 seconds
Started Aug 12 05:19:03 PM PDT 24
Finished Aug 12 05:19:06 PM PDT 24
Peak memory 200520 kb
Host smart-28d664fc-41b0-4a03-8878-754e38248fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440701515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1440701515
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3793152358
Short name T180
Test name
Test status
Simulation time 231490481 ps
CPU time 1.31 seconds
Started Aug 12 05:19:05 PM PDT 24
Finished Aug 12 05:19:07 PM PDT 24
Peak memory 200620 kb
Host smart-602e2bd0-5892-44c4-b0cf-ef97ea817532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793152358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3793152358
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.4028459298
Short name T275
Test name
Test status
Simulation time 66773682 ps
CPU time 0.74 seconds
Started Aug 12 05:19:06 PM PDT 24
Finished Aug 12 05:19:07 PM PDT 24
Peak memory 200492 kb
Host smart-cbe6a90b-e425-4a18-954d-e8e9cca7a83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028459298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.4028459298
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.863793605
Short name T518
Test name
Test status
Simulation time 2343706439 ps
CPU time 7.98 seconds
Started Aug 12 05:18:57 PM PDT 24
Finished Aug 12 05:19:05 PM PDT 24
Peak memory 218144 kb
Host smart-0df9295c-5171-4b86-be88-dd68635d9e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863793605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.863793605
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1685351658
Short name T222
Test name
Test status
Simulation time 244417463 ps
CPU time 1.07 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 217796 kb
Host smart-77dd6be7-62e7-4eff-b775-4f98fb338194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685351658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1685351658
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3977185010
Short name T283
Test name
Test status
Simulation time 174901745 ps
CPU time 0.88 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 200448 kb
Host smart-23e9cbfd-d2b2-4bea-9c37-b1b7e7345c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977185010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3977185010
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1974086361
Short name T104
Test name
Test status
Simulation time 1632761429 ps
CPU time 6.18 seconds
Started Aug 12 05:19:03 PM PDT 24
Finished Aug 12 05:19:09 PM PDT 24
Peak memory 200680 kb
Host smart-c2fd7270-1a9b-4d32-ac21-bb0df3ad608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974086361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1974086361
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3316182575
Short name T244
Test name
Test status
Simulation time 178613114 ps
CPU time 1.23 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200608 kb
Host smart-dca9d4ae-db14-41ee-8884-1b53830dafb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316182575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3316182575
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1746674626
Short name T80
Test name
Test status
Simulation time 183581733 ps
CPU time 1.36 seconds
Started Aug 12 05:18:59 PM PDT 24
Finished Aug 12 05:19:00 PM PDT 24
Peak memory 200740 kb
Host smart-fd7d662e-f718-44d3-b015-c9357efd2fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746674626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1746674626
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1507102547
Short name T323
Test name
Test status
Simulation time 8723859601 ps
CPU time 31.84 seconds
Started Aug 12 05:19:03 PM PDT 24
Finished Aug 12 05:19:35 PM PDT 24
Peak memory 200264 kb
Host smart-e99938a7-6429-4f4a-98b0-3969bf030af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507102547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1507102547
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.4235604504
Short name T309
Test name
Test status
Simulation time 124164999 ps
CPU time 1.57 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:04 PM PDT 24
Peak memory 200508 kb
Host smart-8d5faff1-c45c-4c9f-a6a2-2fc164085199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235604504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.4235604504
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.296275712
Short name T209
Test name
Test status
Simulation time 69572094 ps
CPU time 0.83 seconds
Started Aug 12 05:19:02 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 200584 kb
Host smart-12e6afea-4f52-4d11-9f6c-3902487a13e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296275712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.296275712
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.4133958738
Short name T203
Test name
Test status
Simulation time 92652634 ps
CPU time 0.83 seconds
Started Aug 12 05:19:03 PM PDT 24
Finished Aug 12 05:19:04 PM PDT 24
Peak memory 200504 kb
Host smart-7f0ba101-1a3c-4907-9eb7-733402fedb07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133958738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4133958738
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4032558965
Short name T487
Test name
Test status
Simulation time 2361047022 ps
CPU time 8.69 seconds
Started Aug 12 05:18:59 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 218008 kb
Host smart-761086a9-3fc3-430b-832b-54fad0411da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032558965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4032558965
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1026462605
Short name T343
Test name
Test status
Simulation time 243989125 ps
CPU time 1.09 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 217736 kb
Host smart-29485c7b-682f-4ecd-b5dd-10196696e1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026462605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1026462605
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.139342426
Short name T401
Test name
Test status
Simulation time 130946696 ps
CPU time 0.84 seconds
Started Aug 12 05:18:59 PM PDT 24
Finished Aug 12 05:19:00 PM PDT 24
Peak memory 200224 kb
Host smart-303532a7-8996-459c-a8a3-77bb8d45fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139342426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.139342426
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1507464657
Short name T448
Test name
Test status
Simulation time 1112584184 ps
CPU time 4.53 seconds
Started Aug 12 05:18:59 PM PDT 24
Finished Aug 12 05:19:04 PM PDT 24
Peak memory 200864 kb
Host smart-8fb2731e-7001-4d61-a148-7f5678db80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507464657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1507464657
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2988942089
Short name T541
Test name
Test status
Simulation time 106747478 ps
CPU time 1 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 200668 kb
Host smart-e45e9687-d577-4bf7-8d47-c7efe0bf9f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988942089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2988942089
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.841829846
Short name T516
Test name
Test status
Simulation time 114826785 ps
CPU time 1.14 seconds
Started Aug 12 05:19:06 PM PDT 24
Finished Aug 12 05:19:07 PM PDT 24
Peak memory 200704 kb
Host smart-232bbc8a-4bf1-4561-aa1f-af60fc535c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841829846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.841829846
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.4049581831
Short name T490
Test name
Test status
Simulation time 5694658802 ps
CPU time 26.44 seconds
Started Aug 12 05:19:03 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 209076 kb
Host smart-26dba763-124e-4d6f-86dd-ffe03e9a0964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049581831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.4049581831
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.4256537959
Short name T389
Test name
Test status
Simulation time 300567968 ps
CPU time 1.99 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:03 PM PDT 24
Peak memory 208732 kb
Host smart-bf3e2f8b-a75e-4e26-b3b2-edf6f30e8ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256537959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4256537959
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.863083937
Short name T407
Test name
Test status
Simulation time 164239321 ps
CPU time 1.36 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 200748 kb
Host smart-9c40ea96-0a89-4712-8ee7-4665159a0d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863083937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.863083937
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2709937069
Short name T150
Test name
Test status
Simulation time 63915128 ps
CPU time 0.74 seconds
Started Aug 12 05:19:11 PM PDT 24
Finished Aug 12 05:19:12 PM PDT 24
Peak memory 200408 kb
Host smart-c0ced817-699a-4d41-a36e-044ac3424225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709937069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2709937069
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.4166228291
Short name T64
Test name
Test status
Simulation time 1233497578 ps
CPU time 5.72 seconds
Started Aug 12 05:19:07 PM PDT 24
Finished Aug 12 05:19:13 PM PDT 24
Peak memory 217624 kb
Host smart-f65d0e7e-0f57-44e4-a686-9c3a1725d58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166228291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.4166228291
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1058560630
Short name T187
Test name
Test status
Simulation time 243411192 ps
CPU time 1.06 seconds
Started Aug 12 05:19:09 PM PDT 24
Finished Aug 12 05:19:10 PM PDT 24
Peak memory 217780 kb
Host smart-57a4ab00-1238-478e-9366-36e842a34eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058560630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1058560630
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.3282870715
Short name T255
Test name
Test status
Simulation time 84909544 ps
CPU time 0.77 seconds
Started Aug 12 05:19:01 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 200456 kb
Host smart-9d655e55-b408-44a6-b838-c5a560879fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282870715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3282870715
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2162033943
Short name T278
Test name
Test status
Simulation time 1393786847 ps
CPU time 5.87 seconds
Started Aug 12 05:19:07 PM PDT 24
Finished Aug 12 05:19:13 PM PDT 24
Peak memory 200772 kb
Host smart-a1413408-6201-49ea-82b1-8d928f95ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162033943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2162033943
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3651911437
Short name T207
Test name
Test status
Simulation time 145372866 ps
CPU time 1.07 seconds
Started Aug 12 05:19:08 PM PDT 24
Finished Aug 12 05:19:10 PM PDT 24
Peak memory 200612 kb
Host smart-df2ec478-906a-4b96-85c5-ed9f924429b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651911437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3651911437
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3310024637
Short name T367
Test name
Test status
Simulation time 120569545 ps
CPU time 1.22 seconds
Started Aug 12 05:19:00 PM PDT 24
Finished Aug 12 05:19:01 PM PDT 24
Peak memory 200704 kb
Host smart-0739ef64-4e96-4921-aaf3-ea6270750fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310024637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3310024637
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.940350651
Short name T426
Test name
Test status
Simulation time 168696760 ps
CPU time 1.13 seconds
Started Aug 12 05:19:06 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 200640 kb
Host smart-eabb3028-5392-4ab2-97da-6c851e807557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940350651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.940350651
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3571647146
Short name T149
Test name
Test status
Simulation time 120106648 ps
CPU time 1.58 seconds
Started Aug 12 05:19:06 PM PDT 24
Finished Aug 12 05:19:12 PM PDT 24
Peak memory 208712 kb
Host smart-7952c184-5276-4c54-bb82-58c0de7b2c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571647146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3571647146
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2693481944
Short name T470
Test name
Test status
Simulation time 78740499 ps
CPU time 0.78 seconds
Started Aug 12 05:19:07 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 200640 kb
Host smart-b811ea95-ae85-45c3-932c-f51281f0048d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693481944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2693481944
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3071334169
Short name T388
Test name
Test status
Simulation time 78318925 ps
CPU time 0.77 seconds
Started Aug 12 05:19:08 PM PDT 24
Finished Aug 12 05:19:09 PM PDT 24
Peak memory 200472 kb
Host smart-da5e193d-ef15-4b49-af37-51662eecb5a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071334169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3071334169
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3856187696
Short name T483
Test name
Test status
Simulation time 1888374690 ps
CPU time 7.18 seconds
Started Aug 12 05:19:10 PM PDT 24
Finished Aug 12 05:19:18 PM PDT 24
Peak memory 217804 kb
Host smart-8397e859-e3df-4cb6-b115-a363163cc542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856187696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3856187696
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3495493049
Short name T289
Test name
Test status
Simulation time 244074840 ps
CPU time 1.03 seconds
Started Aug 12 05:19:07 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 217784 kb
Host smart-01dd90aa-222a-41e4-910e-cf1f4a9bba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495493049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3495493049
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3177292608
Short name T16
Test name
Test status
Simulation time 104997848 ps
CPU time 0.83 seconds
Started Aug 12 05:19:08 PM PDT 24
Finished Aug 12 05:19:09 PM PDT 24
Peak memory 200452 kb
Host smart-a4458e2a-d4a2-489d-b667-fd6478f3464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177292608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3177292608
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.877804111
Short name T186
Test name
Test status
Simulation time 1432216143 ps
CPU time 5.77 seconds
Started Aug 12 05:19:06 PM PDT 24
Finished Aug 12 05:19:12 PM PDT 24
Peak memory 200772 kb
Host smart-cce190b9-353a-4396-8d47-fe6abc41dccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877804111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.877804111
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3847836681
Short name T32
Test name
Test status
Simulation time 101232388 ps
CPU time 0.98 seconds
Started Aug 12 05:19:11 PM PDT 24
Finished Aug 12 05:19:12 PM PDT 24
Peak memory 200536 kb
Host smart-32b7f01a-e2af-4fb2-a2ae-d7150a4606d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847836681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3847836681
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.442037905
Short name T497
Test name
Test status
Simulation time 194788287 ps
CPU time 1.41 seconds
Started Aug 12 05:19:06 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 200584 kb
Host smart-f612bd0f-86a9-4dd3-b526-3e07b6b3edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442037905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.442037905
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.4014666228
Short name T271
Test name
Test status
Simulation time 5361368470 ps
CPU time 25.16 seconds
Started Aug 12 05:19:08 PM PDT 24
Finished Aug 12 05:19:34 PM PDT 24
Peak memory 200872 kb
Host smart-4b954892-a7ad-4b63-a5e5-14355de2d042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014666228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.4014666228
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2307675219
Short name T508
Test name
Test status
Simulation time 128317545 ps
CPU time 1.61 seconds
Started Aug 12 05:19:06 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 208724 kb
Host smart-ce469800-9e6b-4b32-95c3-6d397288274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307675219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2307675219
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1358751679
Short name T159
Test name
Test status
Simulation time 140856563 ps
CPU time 1.07 seconds
Started Aug 12 05:19:09 PM PDT 24
Finished Aug 12 05:19:10 PM PDT 24
Peak memory 200648 kb
Host smart-46101eb5-8dfe-416d-bbcf-e33d3f97efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358751679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1358751679
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.933230742
Short name T350
Test name
Test status
Simulation time 119785894 ps
CPU time 0.86 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 200412 kb
Host smart-93380cee-d41b-40d1-a43a-2a77a2b82b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933230742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.933230742
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2580514710
Short name T61
Test name
Test status
Simulation time 1902252484 ps
CPU time 7.78 seconds
Started Aug 12 05:17:52 PM PDT 24
Finished Aug 12 05:18:00 PM PDT 24
Peak memory 217984 kb
Host smart-39c2e2b9-2191-4687-885f-7feb20f938fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580514710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2580514710
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.739778223
Short name T359
Test name
Test status
Simulation time 245320785 ps
CPU time 1.18 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 217852 kb
Host smart-d55e6898-099a-441e-858c-086503e89758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739778223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.739778223
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.3916768528
Short name T295
Test name
Test status
Simulation time 115023489 ps
CPU time 0.78 seconds
Started Aug 12 05:17:55 PM PDT 24
Finished Aug 12 05:17:56 PM PDT 24
Peak memory 200416 kb
Host smart-89035547-225d-4076-839e-de6380957872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916768528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3916768528
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3893125399
Short name T210
Test name
Test status
Simulation time 1514038428 ps
CPU time 5.59 seconds
Started Aug 12 05:17:57 PM PDT 24
Finished Aug 12 05:18:03 PM PDT 24
Peak memory 200476 kb
Host smart-74798cbf-db0f-4a75-89ed-1a4f6ba95a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893125399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3893125399
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2309995071
Short name T355
Test name
Test status
Simulation time 181655793 ps
CPU time 1.25 seconds
Started Aug 12 05:17:55 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 200668 kb
Host smart-6e93617c-2581-4720-a447-3b5bd13a68bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309995071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2309995071
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.3002548720
Short name T538
Test name
Test status
Simulation time 191486213 ps
CPU time 1.34 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:55 PM PDT 24
Peak memory 200596 kb
Host smart-9124627b-619f-44a2-99aa-8ea475c3ee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002548720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3002548720
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3660743266
Short name T468
Test name
Test status
Simulation time 4351359207 ps
CPU time 14.03 seconds
Started Aug 12 05:17:52 PM PDT 24
Finished Aug 12 05:18:06 PM PDT 24
Peak memory 200796 kb
Host smart-24f5c5af-de56-4b53-9ea1-682c2da2d0e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660743266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3660743266
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3121831158
Short name T56
Test name
Test status
Simulation time 281905482 ps
CPU time 1.89 seconds
Started Aug 12 05:17:51 PM PDT 24
Finished Aug 12 05:17:53 PM PDT 24
Peak memory 200320 kb
Host smart-eaae4962-af31-4039-8a17-b0f0943feb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121831158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3121831158
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2082836582
Short name T199
Test name
Test status
Simulation time 74612926 ps
CPU time 0.78 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 200616 kb
Host smart-1246d739-c127-4cc6-8830-06d4c7a8b984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082836582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2082836582
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.893874562
Short name T166
Test name
Test status
Simulation time 61694491 ps
CPU time 0.74 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:54 PM PDT 24
Peak memory 200508 kb
Host smart-36ce92ad-015c-4926-957e-853c16074adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893874562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.893874562
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2237266908
Short name T530
Test name
Test status
Simulation time 1884256320 ps
CPU time 7.11 seconds
Started Aug 12 05:17:57 PM PDT 24
Finished Aug 12 05:18:04 PM PDT 24
Peak memory 221916 kb
Host smart-be9c03f7-40f9-4df1-b4bc-70f0b30cfac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237266908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2237266908
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2969389049
Short name T216
Test name
Test status
Simulation time 243488969 ps
CPU time 1.11 seconds
Started Aug 12 05:17:58 PM PDT 24
Finished Aug 12 05:17:59 PM PDT 24
Peak memory 217812 kb
Host smart-77b5e393-dec5-4b1b-a334-d775ce8e0503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969389049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2969389049
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.149825852
Short name T17
Test name
Test status
Simulation time 169784091 ps
CPU time 0.82 seconds
Started Aug 12 05:17:57 PM PDT 24
Finished Aug 12 05:17:58 PM PDT 24
Peak memory 200028 kb
Host smart-9a10c16e-2e7a-42e7-bb05-8e5b660df9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149825852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.149825852
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3031980552
Short name T93
Test name
Test status
Simulation time 1603658641 ps
CPU time 6.39 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:18:00 PM PDT 24
Peak memory 200800 kb
Host smart-fa179786-ef8d-4410-909b-4f8e5ef25719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031980552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3031980552
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3492298809
Short name T242
Test name
Test status
Simulation time 153859656 ps
CPU time 1.12 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:55 PM PDT 24
Peak memory 200540 kb
Host smart-cb853f65-ca56-43ed-ae6d-9f87eba3ab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492298809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3492298809
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1386257954
Short name T403
Test name
Test status
Simulation time 124856755 ps
CPU time 1.18 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 200704 kb
Host smart-a56d9e84-820f-44c4-aea5-07a59a3d1fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386257954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1386257954
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2313844483
Short name T313
Test name
Test status
Simulation time 7251715231 ps
CPU time 31.93 seconds
Started Aug 12 05:17:54 PM PDT 24
Finished Aug 12 05:18:26 PM PDT 24
Peak memory 217232 kb
Host smart-156abe83-4ae6-4aa4-9c77-7bcfd5f20be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313844483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2313844483
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3586852572
Short name T427
Test name
Test status
Simulation time 371502028 ps
CPU time 2.33 seconds
Started Aug 12 05:17:52 PM PDT 24
Finished Aug 12 05:17:54 PM PDT 24
Peak memory 200532 kb
Host smart-37d6aa28-8274-401d-bdc0-68749305c4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586852572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3586852572
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3120218619
Short name T162
Test name
Test status
Simulation time 167121854 ps
CPU time 1.08 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:55 PM PDT 24
Peak memory 200644 kb
Host smart-86100fa9-ab25-45c0-9832-393635679f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120218619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3120218619
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.638854829
Short name T351
Test name
Test status
Simulation time 81444018 ps
CPU time 0.79 seconds
Started Aug 12 05:17:51 PM PDT 24
Finished Aug 12 05:17:52 PM PDT 24
Peak memory 200516 kb
Host smart-fe4a3a8b-2638-4923-88cc-85271ca48b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638854829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.638854829
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.365194646
Short name T318
Test name
Test status
Simulation time 244191357 ps
CPU time 1.11 seconds
Started Aug 12 05:17:54 PM PDT 24
Finished Aug 12 05:17:55 PM PDT 24
Peak memory 217768 kb
Host smart-f8f70fd4-d51c-495b-aff5-94c7bc865ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365194646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.365194646
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.634151016
Short name T297
Test name
Test status
Simulation time 210166027 ps
CPU time 0.91 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:54 PM PDT 24
Peak memory 200436 kb
Host smart-3da13bc9-17a7-4c3d-9a9d-9fdbd607f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634151016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.634151016
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.435413842
Short name T274
Test name
Test status
Simulation time 929320598 ps
CPU time 5.08 seconds
Started Aug 12 05:17:54 PM PDT 24
Finished Aug 12 05:17:59 PM PDT 24
Peak memory 200836 kb
Host smart-ddbc70bf-b017-4fd5-9d60-d079a8d9fea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435413842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.435413842
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3822323831
Short name T456
Test name
Test status
Simulation time 104236358 ps
CPU time 0.99 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 200628 kb
Host smart-d3580795-3366-430e-a436-7ed332aff013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822323831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3822323831
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.1922941694
Short name T285
Test name
Test status
Simulation time 190071570 ps
CPU time 1.31 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:55 PM PDT 24
Peak memory 200720 kb
Host smart-e1694c5d-b239-4201-afe0-f043ecdc4138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922941694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.1922941694
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2578390139
Short name T101
Test name
Test status
Simulation time 8304130025 ps
CPU time 26.83 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:18:20 PM PDT 24
Peak memory 209864 kb
Host smart-8a16b43a-bfdc-470e-a049-559458cdc6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578390139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2578390139
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.3135738406
Short name T481
Test name
Test status
Simulation time 352113046 ps
CPU time 2.29 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:55 PM PDT 24
Peak memory 200528 kb
Host smart-998fd5ae-b679-4720-be8e-590d27af1277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135738406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3135738406
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.162095574
Short name T435
Test name
Test status
Simulation time 146029185 ps
CPU time 1.09 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:54 PM PDT 24
Peak memory 200608 kb
Host smart-64dc7458-3306-44d3-8c44-15f8a76f5c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162095574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.162095574
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.4285434036
Short name T191
Test name
Test status
Simulation time 76486967 ps
CPU time 0.79 seconds
Started Aug 12 05:17:52 PM PDT 24
Finished Aug 12 05:17:53 PM PDT 24
Peak memory 200432 kb
Host smart-3f355b6e-4527-4709-ab05-4d74c22434e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285434036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.4285434036
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3314516555
Short name T316
Test name
Test status
Simulation time 1885168071 ps
CPU time 6.85 seconds
Started Aug 12 05:17:52 PM PDT 24
Finished Aug 12 05:17:59 PM PDT 24
Peak memory 217192 kb
Host smart-2d8e1e0c-849c-4cdd-bd77-e1f33f21728e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314516555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3314516555
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1396531601
Short name T151
Test name
Test status
Simulation time 244699301 ps
CPU time 1.13 seconds
Started Aug 12 05:17:54 PM PDT 24
Finished Aug 12 05:17:56 PM PDT 24
Peak memory 217768 kb
Host smart-5950da1b-a473-42e8-88f2-803812bcef5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396531601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1396531601
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.2482028091
Short name T229
Test name
Test status
Simulation time 75153265 ps
CPU time 0.71 seconds
Started Aug 12 05:17:52 PM PDT 24
Finished Aug 12 05:17:52 PM PDT 24
Peak memory 200304 kb
Host smart-0a296c61-40a3-40c1-b2dd-a95f4441e744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482028091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.2482028091
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4238195279
Short name T431
Test name
Test status
Simulation time 1035698981 ps
CPU time 4.77 seconds
Started Aug 12 05:17:54 PM PDT 24
Finished Aug 12 05:17:59 PM PDT 24
Peak memory 200740 kb
Host smart-4ac15695-72c9-4302-a628-9999a5656e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238195279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4238195279
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.580752016
Short name T53
Test name
Test status
Simulation time 155910726 ps
CPU time 1.2 seconds
Started Aug 12 05:17:55 PM PDT 24
Finished Aug 12 05:17:56 PM PDT 24
Peak memory 200628 kb
Host smart-9ea20111-bbf1-4c03-86bb-e4cc2c864fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580752016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.580752016
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.805320328
Short name T458
Test name
Test status
Simulation time 128480209 ps
CPU time 1.17 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:54 PM PDT 24
Peak memory 200704 kb
Host smart-aa4507aa-4a87-4ebf-9cf4-71774d592a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805320328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.805320328
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.574686118
Short name T299
Test name
Test status
Simulation time 4328065127 ps
CPU time 18.93 seconds
Started Aug 12 05:17:54 PM PDT 24
Finished Aug 12 05:18:13 PM PDT 24
Peak memory 200636 kb
Host smart-27e9a62a-b402-4f84-9053-d7b6e94dc170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574686118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.574686118
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.4084436148
Short name T378
Test name
Test status
Simulation time 157815342 ps
CPU time 1.98 seconds
Started Aug 12 05:17:51 PM PDT 24
Finished Aug 12 05:17:53 PM PDT 24
Peak memory 200476 kb
Host smart-2c0ff216-4884-4f88-b372-60bc2614bb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084436148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.4084436148
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.4229656276
Short name T410
Test name
Test status
Simulation time 62650152 ps
CPU time 0.74 seconds
Started Aug 12 05:17:55 PM PDT 24
Finished Aug 12 05:17:56 PM PDT 24
Peak memory 200616 kb
Host smart-a2eb5e45-66bc-4fb2-813b-935657c04e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229656276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.4229656276
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2167583629
Short name T195
Test name
Test status
Simulation time 75075874 ps
CPU time 0.87 seconds
Started Aug 12 05:18:01 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 200508 kb
Host smart-88f00bbb-66b0-45b8-9006-897267931a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167583629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2167583629
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.1881419276
Short name T51
Test name
Test status
Simulation time 1229827958 ps
CPU time 5.68 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:59 PM PDT 24
Peak memory 221920 kb
Host smart-37025f89-455d-4299-8e41-c3b5f235a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881419276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.1881419276
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2229976455
Short name T235
Test name
Test status
Simulation time 245742241 ps
CPU time 1.06 seconds
Started Aug 12 05:17:57 PM PDT 24
Finished Aug 12 05:17:59 PM PDT 24
Peak memory 217816 kb
Host smart-c6a58002-857c-43ec-ba92-5a94e3883be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229976455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2229976455
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3781935576
Short name T437
Test name
Test status
Simulation time 201743638 ps
CPU time 0.86 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 200344 kb
Host smart-22e82ff4-227f-4644-8ba2-71093c6596c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781935576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3781935576
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.4140073654
Short name T408
Test name
Test status
Simulation time 861998109 ps
CPU time 4.91 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:18:01 PM PDT 24
Peak memory 200820 kb
Host smart-9dc37a0c-3bd3-4a07-8a17-a0656d654664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140073654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4140073654
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3595699458
Short name T178
Test name
Test status
Simulation time 150444215 ps
CPU time 1.15 seconds
Started Aug 12 05:17:53 PM PDT 24
Finished Aug 12 05:17:54 PM PDT 24
Peak memory 200668 kb
Host smart-9e1a0aad-3bf9-4413-8aea-bdef73108593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595699458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3595699458
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.707188416
Short name T233
Test name
Test status
Simulation time 124243549 ps
CPU time 1.21 seconds
Started Aug 12 05:17:56 PM PDT 24
Finished Aug 12 05:17:58 PM PDT 24
Peak memory 200688 kb
Host smart-d2d00aff-3b31-4935-9a75-c7632f0efb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707188416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.707188416
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2825165266
Short name T478
Test name
Test status
Simulation time 6897160106 ps
CPU time 23.86 seconds
Started Aug 12 05:17:54 PM PDT 24
Finished Aug 12 05:18:18 PM PDT 24
Peak memory 200612 kb
Host smart-06429245-9449-4811-84b9-1a4a60c3f7a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825165266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2825165266
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1413639993
Short name T59
Test name
Test status
Simulation time 373835213 ps
CPU time 2.38 seconds
Started Aug 12 05:17:55 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 200496 kb
Host smart-67ff3686-f05c-4733-bdd2-c0fc3d8f9e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413639993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1413639993
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1465971299
Short name T136
Test name
Test status
Simulation time 109032143 ps
CPU time 0.96 seconds
Started Aug 12 05:17:54 PM PDT 24
Finished Aug 12 05:17:55 PM PDT 24
Peak memory 200668 kb
Host smart-fb91d132-a2c4-4479-8e92-4ddb2346f2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465971299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1465971299
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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