Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8063

1

T3

98

T12

189

T13

1

auto[1]

10898

1

T1

4

T2

4

T3

120

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5880	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6363	1			T1	2		T2	2		T3	87
reset_info_cp[2]	2872	1			T1	1		T2	1		T3	33
reset_info_cp[4]	3889	1			T1	1		T2	1		T3	40
reset_info_cp[8]	116	1			T3	1		T12	3		T86	1
reset_info_cp[16]	126	1			T3	1		T12	2		T56	3
reset_info_cp[32]	112	1			T12	3		T57	1		T42	1
reset_info_cp[64]	119	1			T2	1		T3	3		T12	1
reset_info_cp[128]	104	1			T3	2		T12	1		T57	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3046	1			T3	40		T12	52		T13	1
reset_info_cp[1]	auto[1]	2697	1			T1	1		T2	1		T3	46
reset_info_cp[2]	auto[0]	898	1			T3	13		T12	28		T57	6
reset_info_cp[2]	auto[1]	1974	1			T1	1		T2	1		T3	20
reset_info_cp[4]	auto[0]	1382	1			T3	14		T12	42		T57	8
reset_info_cp[4]	auto[1]	2507	1			T1	1		T2	1		T3	26
reset_info_cp[8]	auto[0]	39	1			T3	1		T12	1		T87	1
reset_info_cp[8]	auto[1]	77	1			T12	2		T86	1		T25	1
reset_info_cp[16]	auto[0]	58	1			T3	1		T12	2		T56	2
reset_info_cp[16]	auto[1]	68	1			T56	1		T25	1		T99	1
reset_info_cp[32]	auto[0]	49	1			T12	2		T57	1		T86	1
reset_info_cp[32]	auto[1]	63	1			T12	1		T42	1		T50	1
reset_info_cp[64]	auto[0]	57	1			T3	1		T12	1		T56	1
reset_info_cp[64]	auto[1]	62	1			T2	1		T3	2		T42	1
reset_info_cp[128]	auto[0]	40	1			T57	1		T121	1		T87	1
reset_info_cp[128]	auto[1]	64	1			T3	2		T12	1		T87	1