Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T533 /workspace/coverage/default/47.rstmgr_sw_rst.2689682339 Aug 13 06:43:59 PM PDT 24 Aug 13 06:44:01 PM PDT 24 131704459 ps
T534 /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1311130615 Aug 13 06:43:17 PM PDT 24 Aug 13 06:43:18 PM PDT 24 162568877 ps
T535 /workspace/coverage/default/43.rstmgr_alert_test.850957541 Aug 13 06:43:38 PM PDT 24 Aug 13 06:43:39 PM PDT 24 65529678 ps
T536 /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2134963081 Aug 13 06:42:58 PM PDT 24 Aug 13 06:42:59 PM PDT 24 87565283 ps
T537 /workspace/coverage/default/4.rstmgr_stress_all.2859607385 Aug 13 06:42:49 PM PDT 24 Aug 13 06:43:09 PM PDT 24 5292189070 ps
T62 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2854707351 Aug 13 06:26:16 PM PDT 24 Aug 13 06:26:18 PM PDT 24 83065160 ps
T63 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1752769920 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:14 PM PDT 24 105070093 ps
T64 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2278163538 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:16 PM PDT 24 408905393 ps
T65 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.448664886 Aug 13 06:26:01 PM PDT 24 Aug 13 06:26:02 PM PDT 24 61457762 ps
T66 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.702406374 Aug 13 06:26:01 PM PDT 24 Aug 13 06:26:03 PM PDT 24 148193272 ps
T67 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3774037752 Aug 13 06:26:11 PM PDT 24 Aug 13 06:26:15 PM PDT 24 461909538 ps
T74 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1394661071 Aug 13 06:26:12 PM PDT 24 Aug 13 06:26:14 PM PDT 24 179989200 ps
T101 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.578954240 Aug 13 06:26:02 PM PDT 24 Aug 13 06:26:03 PM PDT 24 153361053 ps
T102 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.908391371 Aug 13 06:26:16 PM PDT 24 Aug 13 06:26:17 PM PDT 24 58189333 ps
T103 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3587029841 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:15 PM PDT 24 151149721 ps
T104 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3330928150 Aug 13 06:26:23 PM PDT 24 Aug 13 06:26:24 PM PDT 24 101450110 ps
T538 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3304014008 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:04 PM PDT 24 70396898 ps
T68 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2496116634 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:06 PM PDT 24 799987401 ps
T88 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.312814529 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:17 PM PDT 24 877794627 ps
T89 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1537509006 Aug 13 06:26:12 PM PDT 24 Aug 13 06:26:16 PM PDT 24 477495911 ps
T105 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2096148602 Aug 13 06:26:16 PM PDT 24 Aug 13 06:26:17 PM PDT 24 193814197 ps
T539 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1996402245 Aug 13 06:26:06 PM PDT 24 Aug 13 06:26:08 PM PDT 24 152621941 ps
T90 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1441306941 Aug 13 06:26:08 PM PDT 24 Aug 13 06:26:11 PM PDT 24 149614966 ps
T91 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3494858384 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:15 PM PDT 24 246663089 ps
T92 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2754004130 Aug 13 06:26:00 PM PDT 24 Aug 13 06:26:03 PM PDT 24 777368852 ps
T93 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3156819662 Aug 13 06:26:15 PM PDT 24 Aug 13 06:26:19 PM PDT 24 655249768 ps
T94 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3927744122 Aug 13 06:26:08 PM PDT 24 Aug 13 06:26:09 PM PDT 24 121152224 ps
T540 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4224957401 Aug 13 06:26:20 PM PDT 24 Aug 13 06:26:23 PM PDT 24 290993565 ps
T106 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2187427759 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:16 PM PDT 24 74907450 ps
T541 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3048851816 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:15 PM PDT 24 125409136 ps
T107 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3246341255 Aug 13 06:26:15 PM PDT 24 Aug 13 06:26:16 PM PDT 24 58442558 ps
T542 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1518310904 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:06 PM PDT 24 153456602 ps
T108 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3411957517 Aug 13 06:26:20 PM PDT 24 Aug 13 06:26:22 PM PDT 24 191739832 ps
T543 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.18231090 Aug 13 06:26:02 PM PDT 24 Aug 13 06:26:03 PM PDT 24 103243266 ps
T125 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1423397391 Aug 13 06:26:15 PM PDT 24 Aug 13 06:26:18 PM PDT 24 898503600 ps
T113 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.57645894 Aug 13 06:26:12 PM PDT 24 Aug 13 06:26:15 PM PDT 24 479495835 ps
T544 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1424230112 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:14 PM PDT 24 67898687 ps
T114 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3734838189 Aug 13 06:26:15 PM PDT 24 Aug 13 06:26:18 PM PDT 24 782992564 ps
T545 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3669629849 Aug 13 06:26:01 PM PDT 24 Aug 13 06:26:02 PM PDT 24 110274142 ps
T546 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2533109252 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:15 PM PDT 24 123242936 ps
T547 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1361032927 Aug 13 06:26:17 PM PDT 24 Aug 13 06:26:18 PM PDT 24 60229729 ps
T115 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.263436332 Aug 13 06:26:12 PM PDT 24 Aug 13 06:26:16 PM PDT 24 873374993 ps
T548 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1932725219 Aug 13 06:26:09 PM PDT 24 Aug 13 06:26:13 PM PDT 24 911213086 ps
T549 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3555356926 Aug 13 06:26:05 PM PDT 24 Aug 13 06:26:09 PM PDT 24 1221244480 ps
T550 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.276963763 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:05 PM PDT 24 187206703 ps
T551 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2289425895 Aug 13 06:26:20 PM PDT 24 Aug 13 06:26:22 PM PDT 24 78202338 ps
T552 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4189276343 Aug 13 06:26:08 PM PDT 24 Aug 13 06:26:09 PM PDT 24 153866537 ps
T553 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4290327053 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:05 PM PDT 24 86028555 ps
T554 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2560375406 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:14 PM PDT 24 120649112 ps
T555 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3919600793 Aug 13 06:26:12 PM PDT 24 Aug 13 06:26:13 PM PDT 24 214578004 ps
T556 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1288007793 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:07 PM PDT 24 179745545 ps
T557 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.965678536 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:15 PM PDT 24 98913157 ps
T558 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.238303016 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:15 PM PDT 24 259205061 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3785500966 Aug 13 06:26:02 PM PDT 24 Aug 13 06:26:04 PM PDT 24 128607047 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1987154668 Aug 13 06:26:01 PM PDT 24 Aug 13 06:26:06 PM PDT 24 814628241 ps
T561 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.884970994 Aug 13 06:26:00 PM PDT 24 Aug 13 06:26:01 PM PDT 24 75146449 ps
T562 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.632831375 Aug 13 06:26:17 PM PDT 24 Aug 13 06:26:18 PM PDT 24 72370577 ps
T563 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3354456571 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:08 PM PDT 24 803713317 ps
T564 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3722513189 Aug 13 06:26:16 PM PDT 24 Aug 13 06:26:17 PM PDT 24 62949705 ps
T565 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.560603756 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:14 PM PDT 24 60576390 ps
T566 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2282933654 Aug 13 06:26:12 PM PDT 24 Aug 13 06:26:15 PM PDT 24 194073374 ps
T567 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1567788153 Aug 13 06:26:05 PM PDT 24 Aug 13 06:26:06 PM PDT 24 74703668 ps
T568 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.322518986 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:16 PM PDT 24 96816743 ps
T569 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3312571949 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:04 PM PDT 24 106440458 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3473127976 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:05 PM PDT 24 200119730 ps
T110 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.856611483 Aug 13 06:26:16 PM PDT 24 Aug 13 06:26:18 PM PDT 24 432775640 ps
T571 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1135919006 Aug 13 06:26:15 PM PDT 24 Aug 13 06:26:18 PM PDT 24 880959393 ps
T572 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4048900684 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:05 PM PDT 24 364316223 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.489340253 Aug 13 06:26:01 PM PDT 24 Aug 13 06:26:02 PM PDT 24 100956999 ps
T574 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.429118716 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:05 PM PDT 24 122366056 ps
T575 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3502182268 Aug 13 06:26:02 PM PDT 24 Aug 13 06:26:07 PM PDT 24 484704651 ps
T576 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2097540696 Aug 13 06:26:02 PM PDT 24 Aug 13 06:26:04 PM PDT 24 147525091 ps
T577 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1650557527 Aug 13 06:26:16 PM PDT 24 Aug 13 06:26:17 PM PDT 24 133370457 ps
T578 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3134247095 Aug 13 06:26:02 PM PDT 24 Aug 13 06:26:04 PM PDT 24 117233736 ps
T579 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1336905559 Aug 13 06:26:20 PM PDT 24 Aug 13 06:26:22 PM PDT 24 174998192 ps
T580 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3507561722 Aug 13 06:26:05 PM PDT 24 Aug 13 06:26:14 PM PDT 24 1991389225 ps
T581 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2787746718 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:14 PM PDT 24 164322551 ps
T582 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1325313848 Aug 13 06:26:15 PM PDT 24 Aug 13 06:26:17 PM PDT 24 124480160 ps
T583 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1224173327 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:15 PM PDT 24 258331272 ps
T584 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1435314040 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:14 PM PDT 24 84896771 ps
T585 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3878042178 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:04 PM PDT 24 95622772 ps
T586 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2241913572 Aug 13 06:26:10 PM PDT 24 Aug 13 06:26:11 PM PDT 24 76028472 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1861974974 Aug 13 06:26:07 PM PDT 24 Aug 13 06:26:08 PM PDT 24 138398662 ps
T588 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.653998239 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:05 PM PDT 24 99160313 ps
T589 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3618115955 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:16 PM PDT 24 144870740 ps
T590 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1126011845 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:15 PM PDT 24 100498437 ps
T591 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.186915139 Aug 13 06:26:09 PM PDT 24 Aug 13 06:26:14 PM PDT 24 1177506272 ps
T592 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2879472515 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:05 PM PDT 24 166698517 ps
T593 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3422657651 Aug 13 06:26:11 PM PDT 24 Aug 13 06:26:12 PM PDT 24 68911265 ps
T594 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3875227704 Aug 13 06:26:20 PM PDT 24 Aug 13 06:26:22 PM PDT 24 189734893 ps
T111 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1152348832 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:06 PM PDT 24 530700419 ps
T126 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2982253496 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:06 PM PDT 24 967751813 ps
T595 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4052159243 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:15 PM PDT 24 312402380 ps
T596 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2796405373 Aug 13 06:26:01 PM PDT 24 Aug 13 06:26:04 PM PDT 24 884294652 ps
T597 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3049580571 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:15 PM PDT 24 72414858 ps
T598 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2829193956 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:14 PM PDT 24 60023253 ps
T599 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3504958943 Aug 13 06:26:10 PM PDT 24 Aug 13 06:26:12 PM PDT 24 485375725 ps
T600 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.788847288 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:07 PM PDT 24 186454260 ps
T601 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2103800913 Aug 13 06:26:16 PM PDT 24 Aug 13 06:26:18 PM PDT 24 79326664 ps
T602 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.197637573 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:14 PM PDT 24 144703243 ps
T603 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1688435649 Aug 13 06:26:06 PM PDT 24 Aug 13 06:26:07 PM PDT 24 112108946 ps
T604 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1068555861 Aug 13 06:26:17 PM PDT 24 Aug 13 06:26:20 PM PDT 24 940366217 ps
T109 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1632010635 Aug 13 06:26:11 PM PDT 24 Aug 13 06:26:14 PM PDT 24 931864255 ps
T605 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2507340838 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:15 PM PDT 24 76948113 ps
T606 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2627628447 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:05 PM PDT 24 249481469 ps
T607 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1321285880 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:06 PM PDT 24 420109090 ps
T608 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1265913902 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:05 PM PDT 24 155997862 ps
T609 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1116973813 Aug 13 06:26:16 PM PDT 24 Aug 13 06:26:18 PM PDT 24 144027343 ps
T610 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3124593179 Aug 13 06:26:25 PM PDT 24 Aug 13 06:26:26 PM PDT 24 113233919 ps
T611 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3680250467 Aug 13 06:26:06 PM PDT 24 Aug 13 06:26:07 PM PDT 24 113999078 ps
T612 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3432704707 Aug 13 06:26:01 PM PDT 24 Aug 13 06:26:02 PM PDT 24 86041045 ps
T613 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.135024110 Aug 13 06:26:04 PM PDT 24 Aug 13 06:26:06 PM PDT 24 202065399 ps
T614 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3038613363 Aug 13 06:26:11 PM PDT 24 Aug 13 06:26:14 PM PDT 24 183706616 ps
T615 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1551071302 Aug 13 06:26:03 PM PDT 24 Aug 13 06:26:04 PM PDT 24 96206187 ps
T616 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2589801737 Aug 13 06:26:17 PM PDT 24 Aug 13 06:26:18 PM PDT 24 136207837 ps
T617 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.524137952 Aug 13 06:26:10 PM PDT 24 Aug 13 06:26:12 PM PDT 24 188279611 ps
T618 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.346038854 Aug 13 06:26:14 PM PDT 24 Aug 13 06:26:18 PM PDT 24 1099159194 ps
T112 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3882802161 Aug 13 06:26:13 PM PDT 24 Aug 13 06:26:15 PM PDT 24 488037941 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.720785215 Aug 13 06:26:05 PM PDT 24 Aug 13 06:26:06 PM PDT 24 66152937 ps
T620 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.45690854 Aug 13 06:26:20 PM PDT 24 Aug 13 06:26:21 PM PDT 24 68570740 ps

Test location /workspace/coverage/default/26.rstmgr_stress_all.2115614793
Short name T3
Test name
Test status
Simulation time 4044723300 ps
CPU time 18.94 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:46 PM PDT 24
Peak memory 209096 kb
Host smart-fd1092c9-4b53-4a60-a0c3-382ea6c57ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115614793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2115614793
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2742874127
Short name T1
Test name
Test status
Simulation time 235957532 ps
CPU time 1.48 seconds
Started Aug 13 06:42:55 PM PDT 24
Finished Aug 13 06:42:57 PM PDT 24
Peak memory 200772 kb
Host smart-993858d8-be61-47a3-91ee-197fec6fb84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742874127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2742874127
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1752769920
Short name T63
Test name
Test status
Simulation time 105070093 ps
CPU time 0.92 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200920 kb
Host smart-0601002e-7f68-44e5-9728-88491649136e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752769920 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.1752769920
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.2018863545
Short name T71
Test name
Test status
Simulation time 16611616470 ps
CPU time 25.44 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 217700 kb
Host smart-55f9696b-9f87-44eb-a24f-9a17baaea64d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018863545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2018863545
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2541147540
Short name T42
Test name
Test status
Simulation time 2190590030 ps
CPU time 7.78 seconds
Started Aug 13 06:43:21 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 218048 kb
Host smart-de4b0bd9-83a8-4538-a4fc-62cd8b841dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541147540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2541147540
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.1252517093
Short name T61
Test name
Test status
Simulation time 388668461 ps
CPU time 2.13 seconds
Started Aug 13 06:43:07 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 200568 kb
Host smart-cb7f3966-5a8d-4cd0-88cc-d93e5a4b2cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252517093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1252517093
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.312814529
Short name T88
Test name
Test status
Simulation time 877794627 ps
CPU time 3.26 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:17 PM PDT 24
Peak memory 201068 kb
Host smart-f4b529ca-aa4c-4fef-a18d-5eb5b7fe440d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312814529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.312814529
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.29570635
Short name T131
Test name
Test status
Simulation time 75574329 ps
CPU time 0.82 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:18 PM PDT 24
Peak memory 200540 kb
Host smart-2edae85e-8611-4c3f-bdd8-da107bf7c5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29570635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.29570635
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2455497414
Short name T12
Test name
Test status
Simulation time 6097255664 ps
CPU time 26.78 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:44:06 PM PDT 24
Peak memory 200856 kb
Host smart-a6652885-552d-4e39-aac3-1f6eaa77a036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455497414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2455497414
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3494858384
Short name T91
Test name
Test status
Simulation time 246663089 ps
CPU time 1.91 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 217392 kb
Host smart-34eb31d3-5219-4a7c-a525-ac082996a9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494858384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3494858384
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3453444817
Short name T116
Test name
Test status
Simulation time 15554740351 ps
CPU time 50.96 seconds
Started Aug 13 06:45:17 PM PDT 24
Finished Aug 13 06:46:08 PM PDT 24
Peak memory 209120 kb
Host smart-ec16a59c-3527-4c19-a277-c61e8047e205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453444817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3453444817
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3898866552
Short name T24
Test name
Test status
Simulation time 104493260 ps
CPU time 0.96 seconds
Started Aug 13 06:43:06 PM PDT 24
Finished Aug 13 06:43:07 PM PDT 24
Peak memory 200676 kb
Host smart-33a01d0f-0f63-44de-9717-1d2df3f0f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898866552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3898866552
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2226738498
Short name T25
Test name
Test status
Simulation time 2355433460 ps
CPU time 9.43 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:23 PM PDT 24
Peak memory 218136 kb
Host smart-9b867f04-cd1b-4d88-8dbf-5efd796c0536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226738498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2226738498
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2956586086
Short name T43
Test name
Test status
Simulation time 2351837828 ps
CPU time 8.09 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:27 PM PDT 24
Peak memory 222048 kb
Host smart-7bbe9d54-0732-49dd-9acf-2aa40a8e6647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956586086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2956586086
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1423397391
Short name T125
Test name
Test status
Simulation time 898503600 ps
CPU time 2.91 seconds
Started Aug 13 06:26:15 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 201076 kb
Host smart-9a5bdc7c-62a3-4ea2-863b-203f1b225428
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423397391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.1423397391
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2853609923
Short name T120
Test name
Test status
Simulation time 116908862 ps
CPU time 0.93 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:16 PM PDT 24
Peak memory 200636 kb
Host smart-c2bda83f-95de-4393-ab19-a0626ce8fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853609923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2853609923
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3669629849
Short name T545
Test name
Test status
Simulation time 110274142 ps
CPU time 1.53 seconds
Started Aug 13 06:26:01 PM PDT 24
Finished Aug 13 06:26:02 PM PDT 24
Peak memory 209228 kb
Host smart-4bf07eea-216d-4781-8369-0abaf71cc70a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669629849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3669629849
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2096148602
Short name T105
Test name
Test status
Simulation time 193814197 ps
CPU time 1.48 seconds
Started Aug 13 06:26:16 PM PDT 24
Finished Aug 13 06:26:17 PM PDT 24
Peak memory 201084 kb
Host smart-35908817-0c60-4a10-b851-abe8e9b7216d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096148602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2096148602
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.459188528
Short name T4
Test name
Test status
Simulation time 85944731 ps
CPU time 0.75 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:52 PM PDT 24
Peak memory 200440 kb
Host smart-a3266f92-7296-492d-922a-b3eb1c618474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459188528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.459188528
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2754004130
Short name T92
Test name
Test status
Simulation time 777368852 ps
CPU time 3.19 seconds
Started Aug 13 06:26:00 PM PDT 24
Finished Aug 13 06:26:03 PM PDT 24
Peak memory 201144 kb
Host smart-e7d6ecd4-39d9-48a9-bb82-0592ccb0c10f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754004130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2754004130
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3882802161
Short name T112
Test name
Test status
Simulation time 488037941 ps
CPU time 1.87 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 201052 kb
Host smart-bfcf98ab-c6d7-402e-9196-bb94843a8b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882802161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3882802161
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4048900684
Short name T572
Test name
Test status
Simulation time 364316223 ps
CPU time 2.57 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 200924 kb
Host smart-dd72c62e-1e7c-48bc-8027-b53ae49de219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048900684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
048900684
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3354456571
Short name T563
Test name
Test status
Simulation time 803713317 ps
CPU time 4.29 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:08 PM PDT 24
Peak memory 200972 kb
Host smart-047ac496-fbfc-4214-a734-1d08e10eb389
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354456571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
354456571
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1551071302
Short name T615
Test name
Test status
Simulation time 96206187 ps
CPU time 0.86 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 200816 kb
Host smart-d94e6ae7-ad68-47df-94ea-cfa26c6eb8b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551071302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
551071302
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3473127976
Short name T570
Test name
Test status
Simulation time 200119730 ps
CPU time 1.34 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 209116 kb
Host smart-35ad42f4-25b8-4265-aa4a-868f3225545b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473127976 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3473127976
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.884970994
Short name T561
Test name
Test status
Simulation time 75146449 ps
CPU time 0.82 seconds
Started Aug 13 06:26:00 PM PDT 24
Finished Aug 13 06:26:01 PM PDT 24
Peak memory 200776 kb
Host smart-babbc9bd-9516-45df-a5b7-e3bc46ce5655
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884970994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.884970994
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3785500966
Short name T559
Test name
Test status
Simulation time 128607047 ps
CPU time 1.33 seconds
Started Aug 13 06:26:02 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 201040 kb
Host smart-b3cc7452-3e0a-4923-9ee7-3812cf37e881
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785500966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3785500966
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1321285880
Short name T607
Test name
Test status
Simulation time 420109090 ps
CPU time 1.93 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 201048 kb
Host smart-3d7a0e00-b9cf-4874-bdee-62e29970b462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321285880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1321285880
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.653998239
Short name T588
Test name
Test status
Simulation time 99160313 ps
CPU time 1.31 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 200984 kb
Host smart-05a4f3f6-507c-4a3e-b063-619713775cb4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653998239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.653998239
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1987154668
Short name T560
Test name
Test status
Simulation time 814628241 ps
CPU time 4.35 seconds
Started Aug 13 06:26:01 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 200956 kb
Host smart-ffdf62d4-5857-4c7d-a78a-a2b98f55f7c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987154668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
987154668
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.18231090
Short name T543
Test name
Test status
Simulation time 103243266 ps
CPU time 0.88 seconds
Started Aug 13 06:26:02 PM PDT 24
Finished Aug 13 06:26:03 PM PDT 24
Peak memory 200856 kb
Host smart-e01d220b-e80b-47f1-b16d-443bea004f76
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18231090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.18231090
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.276963763
Short name T550
Test name
Test status
Simulation time 187206703 ps
CPU time 1.27 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 209088 kb
Host smart-d5170b41-d2fb-468c-9460-a9a3e1f93852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276963763 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.276963763
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3432704707
Short name T612
Test name
Test status
Simulation time 86041045 ps
CPU time 0.93 seconds
Started Aug 13 06:26:01 PM PDT 24
Finished Aug 13 06:26:02 PM PDT 24
Peak memory 200832 kb
Host smart-4319ff44-1965-42c0-9601-58fe6a5e3985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432704707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3432704707
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1265913902
Short name T608
Test name
Test status
Simulation time 155997862 ps
CPU time 1.15 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 200784 kb
Host smart-b3d9621c-ec63-47fd-8a5b-f611afedfed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265913902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1265913902
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1288007793
Short name T556
Test name
Test status
Simulation time 179745545 ps
CPU time 2.45 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:07 PM PDT 24
Peak memory 212856 kb
Host smart-4c964d06-2dfe-4976-987e-585e0a3b42b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288007793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1288007793
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3048851816
Short name T541
Test name
Test status
Simulation time 125409136 ps
CPU time 0.98 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 200932 kb
Host smart-7f46c164-8e3a-4263-8d7d-6358842874c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048851816 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3048851816
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1424230112
Short name T544
Test name
Test status
Simulation time 67898687 ps
CPU time 0.79 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200684 kb
Host smart-f77cea99-dd87-4b67-8f52-1426f105ceaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424230112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1424230112
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3919600793
Short name T555
Test name
Test status
Simulation time 214578004 ps
CPU time 1.46 seconds
Started Aug 13 06:26:12 PM PDT 24
Finished Aug 13 06:26:13 PM PDT 24
Peak memory 201104 kb
Host smart-a16d90b4-0994-4ef5-a723-6a2fb7924577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919600793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3919600793
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3156819662
Short name T93
Test name
Test status
Simulation time 655249768 ps
CPU time 4.31 seconds
Started Aug 13 06:26:15 PM PDT 24
Finished Aug 13 06:26:19 PM PDT 24
Peak memory 209164 kb
Host smart-9b68d71c-fb2d-46a5-8bfe-725cc96c3aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156819662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3156819662
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1650557527
Short name T577
Test name
Test status
Simulation time 133370457 ps
CPU time 1.18 seconds
Started Aug 13 06:26:16 PM PDT 24
Finished Aug 13 06:26:17 PM PDT 24
Peak memory 209260 kb
Host smart-e06c324e-3581-4ae8-a253-6620b8d409f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650557527 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.1650557527
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2829193956
Short name T598
Test name
Test status
Simulation time 60023253 ps
CPU time 0.79 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200700 kb
Host smart-5b4f7b2d-92b4-4185-a97c-6e9d379c9557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829193956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2829193956
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1116973813
Short name T609
Test name
Test status
Simulation time 144027343 ps
CPU time 1.22 seconds
Started Aug 13 06:26:16 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 200864 kb
Host smart-3cdba13b-9e47-428a-81cc-cd7794236cf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116973813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1116973813
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3038613363
Short name T614
Test name
Test status
Simulation time 183706616 ps
CPU time 2.57 seconds
Started Aug 13 06:26:11 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 213032 kb
Host smart-2818ca94-946b-4809-abcb-d43a15d2b334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038613363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3038613363
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3504958943
Short name T599
Test name
Test status
Simulation time 485375725 ps
CPU time 1.98 seconds
Started Aug 13 06:26:10 PM PDT 24
Finished Aug 13 06:26:12 PM PDT 24
Peak memory 201068 kb
Host smart-b6c6bf24-90c2-409f-abff-787c82b4a610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504958943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3504958943
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2560375406
Short name T554
Test name
Test status
Simulation time 120649112 ps
CPU time 1.02 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200924 kb
Host smart-177dd0cd-e79b-4a70-98ad-9be36415c889
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560375406 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2560375406
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3422657651
Short name T593
Test name
Test status
Simulation time 68911265 ps
CPU time 0.79 seconds
Started Aug 13 06:26:11 PM PDT 24
Finished Aug 13 06:26:12 PM PDT 24
Peak memory 200700 kb
Host smart-49815530-888f-4829-a644-6919263e257a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422657651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3422657651
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1224173327
Short name T583
Test name
Test status
Simulation time 258331272 ps
CPU time 1.72 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 201060 kb
Host smart-6b1298d1-8438-4829-95e3-26abfd9a22a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224173327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1224173327
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1325313848
Short name T582
Test name
Test status
Simulation time 124480160 ps
CPU time 1.81 seconds
Started Aug 13 06:26:15 PM PDT 24
Finished Aug 13 06:26:17 PM PDT 24
Peak memory 212500 kb
Host smart-93e1e5eb-4f4a-4f40-9bdf-a5b9e63458d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325313848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1325313848
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1068555861
Short name T604
Test name
Test status
Simulation time 940366217 ps
CPU time 3.05 seconds
Started Aug 13 06:26:17 PM PDT 24
Finished Aug 13 06:26:20 PM PDT 24
Peak memory 201016 kb
Host smart-78dd9d49-b1bc-4ea1-acd1-7f59987bdc41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068555861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1068555861
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2787746718
Short name T581
Test name
Test status
Simulation time 164322551 ps
CPU time 1.22 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 209164 kb
Host smart-5e81b68d-df24-4824-848e-ad45b1182c44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787746718 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2787746718
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3722513189
Short name T564
Test name
Test status
Simulation time 62949705 ps
CPU time 0.86 seconds
Started Aug 13 06:26:16 PM PDT 24
Finished Aug 13 06:26:17 PM PDT 24
Peak memory 200816 kb
Host smart-93c8af15-b39f-4eb0-a417-ac329f56a5f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722513189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3722513189
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.238303016
Short name T558
Test name
Test status
Simulation time 259205061 ps
CPU time 2.25 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 211556 kb
Host smart-18a00c45-a9ad-4cdc-84f3-49b0774e8928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238303016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.238303016
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.45690854
Short name T620
Test name
Test status
Simulation time 68570740 ps
CPU time 0.8 seconds
Started Aug 13 06:26:20 PM PDT 24
Finished Aug 13 06:26:21 PM PDT 24
Peak memory 200824 kb
Host smart-688070b5-9c36-4922-9712-cf274cb4eab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45690854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.45690854
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3049580571
Short name T597
Test name
Test status
Simulation time 72414858 ps
CPU time 0.89 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 200716 kb
Host smart-c658eaca-362b-4cb2-8e34-95f246b2a215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049580571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3049580571
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3774037752
Short name T67
Test name
Test status
Simulation time 461909538 ps
CPU time 3.3 seconds
Started Aug 13 06:26:11 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 209248 kb
Host smart-959ce123-455f-4089-8fcd-0d29874e30eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774037752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3774037752
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1632010635
Short name T109
Test name
Test status
Simulation time 931864255 ps
CPU time 3.13 seconds
Started Aug 13 06:26:11 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 201040 kb
Host smart-91354ac6-2288-4b8b-b7ea-3b53c7dc8fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632010635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.1632010635
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2589801737
Short name T616
Test name
Test status
Simulation time 136207837 ps
CPU time 1 seconds
Started Aug 13 06:26:17 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 200876 kb
Host smart-dffe662c-869f-4d2b-bcf1-7f7521cbf06e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589801737 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2589801737
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.560603756
Short name T565
Test name
Test status
Simulation time 60576390 ps
CPU time 0.76 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200816 kb
Host smart-5f3795f0-72f8-4b48-8fe0-c87eb411015f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560603756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.560603756
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3587029841
Short name T103
Test name
Test status
Simulation time 151149721 ps
CPU time 1.24 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 200844 kb
Host smart-393c0b3e-0aa8-4d0a-9008-04f95c8c2e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587029841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3587029841
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2278163538
Short name T64
Test name
Test status
Simulation time 408905393 ps
CPU time 1.74 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:16 PM PDT 24
Peak memory 200948 kb
Host smart-f5c1bf48-6f7e-4e75-8ca1-8a2e8e18a22a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278163538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2278163538
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1394661071
Short name T74
Test name
Test status
Simulation time 179989200 ps
CPU time 1.33 seconds
Started Aug 13 06:26:12 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 209164 kb
Host smart-05f21ec9-a2e0-4005-8434-c7af66f843a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394661071 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1394661071
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2241913572
Short name T586
Test name
Test status
Simulation time 76028472 ps
CPU time 0.88 seconds
Started Aug 13 06:26:10 PM PDT 24
Finished Aug 13 06:26:11 PM PDT 24
Peak memory 200752 kb
Host smart-59388bc8-19b3-4902-b743-a98d68732875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241913572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2241913572
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2187427759
Short name T106
Test name
Test status
Simulation time 74907450 ps
CPU time 0.99 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:16 PM PDT 24
Peak memory 201008 kb
Host smart-e1b4433f-70fb-4a63-af6d-b39113e6c120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187427759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2187427759
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.57645894
Short name T113
Test name
Test status
Simulation time 479495835 ps
CPU time 3.23 seconds
Started Aug 13 06:26:12 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 217308 kb
Host smart-ff94a327-f2f9-4ebf-8016-39273fb5ba9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57645894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.57645894
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3734838189
Short name T114
Test name
Test status
Simulation time 782992564 ps
CPU time 2.72 seconds
Started Aug 13 06:26:15 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 201032 kb
Host smart-b9bca8f3-2403-4927-91e0-2194e0d9416f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734838189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3734838189
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.197637573
Short name T602
Test name
Test status
Simulation time 144703243 ps
CPU time 1.11 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200844 kb
Host smart-daa6871d-1642-4142-af68-c2a2d94a8a05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197637573 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.197637573
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.908391371
Short name T102
Test name
Test status
Simulation time 58189333 ps
CPU time 0.86 seconds
Started Aug 13 06:26:16 PM PDT 24
Finished Aug 13 06:26:17 PM PDT 24
Peak memory 200796 kb
Host smart-c22fd2df-d1bb-40c9-8bd3-d12c71df963f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908391371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.908391371
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.632831375
Short name T562
Test name
Test status
Simulation time 72370577 ps
CPU time 0.9 seconds
Started Aug 13 06:26:17 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 200864 kb
Host smart-4899200e-e6bd-4f21-b823-6ef17ccad01e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632831375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.632831375
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4052159243
Short name T595
Test name
Test status
Simulation time 312402380 ps
CPU time 2.68 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 209228 kb
Host smart-ec61a724-798c-4e1a-b8a0-62bbc7b881b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052159243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4052159243
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1336905559
Short name T579
Test name
Test status
Simulation time 174998192 ps
CPU time 1.17 seconds
Started Aug 13 06:26:20 PM PDT 24
Finished Aug 13 06:26:22 PM PDT 24
Peak memory 208504 kb
Host smart-282878ff-fee8-4df2-9c2f-edf2b3b6274e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336905559 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.1336905559
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2103800913
Short name T601
Test name
Test status
Simulation time 79326664 ps
CPU time 0.86 seconds
Started Aug 13 06:26:16 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 200820 kb
Host smart-dcb79d14-101c-4d84-8bfb-ea548503c42f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103800913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2103800913
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2289425895
Short name T551
Test name
Test status
Simulation time 78202338 ps
CPU time 1.02 seconds
Started Aug 13 06:26:20 PM PDT 24
Finished Aug 13 06:26:22 PM PDT 24
Peak memory 200640 kb
Host smart-c67de9fc-597e-40bd-962f-a2dba811ca6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289425895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2289425895
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3618115955
Short name T589
Test name
Test status
Simulation time 144870740 ps
CPU time 2.07 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:16 PM PDT 24
Peak memory 209252 kb
Host smart-bde950ef-2166-4fa8-bc56-d3010bc06f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618115955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3618115955
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.346038854
Short name T618
Test name
Test status
Simulation time 1099159194 ps
CPU time 3.25 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 200988 kb
Host smart-bd82a496-5d75-43a3-ba79-069c5a88a11d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346038854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err
.346038854
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3124593179
Short name T610
Test name
Test status
Simulation time 113233919 ps
CPU time 1 seconds
Started Aug 13 06:26:25 PM PDT 24
Finished Aug 13 06:26:26 PM PDT 24
Peak memory 200968 kb
Host smart-61daeb5c-221f-43a8-8ca6-27d167970ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124593179 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3124593179
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3246341255
Short name T107
Test name
Test status
Simulation time 58442558 ps
CPU time 0.78 seconds
Started Aug 13 06:26:15 PM PDT 24
Finished Aug 13 06:26:16 PM PDT 24
Peak memory 200796 kb
Host smart-0caf28ee-5059-4108-b3f7-af33ceb4e7c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246341255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3246341255
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.3330928150
Short name T104
Test name
Test status
Simulation time 101450110 ps
CPU time 1.29 seconds
Started Aug 13 06:26:23 PM PDT 24
Finished Aug 13 06:26:24 PM PDT 24
Peak memory 201116 kb
Host smart-f2fd9462-ea3f-49dd-90fa-bece6649613f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330928150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.3330928150
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4224957401
Short name T540
Test name
Test status
Simulation time 290993565 ps
CPU time 2.32 seconds
Started Aug 13 06:26:20 PM PDT 24
Finished Aug 13 06:26:23 PM PDT 24
Peak memory 208988 kb
Host smart-b7b2f954-6f3d-4811-9ea5-c5375b930f99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224957401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4224957401
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.856611483
Short name T110
Test name
Test status
Simulation time 432775640 ps
CPU time 1.93 seconds
Started Aug 13 06:26:16 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 201056 kb
Host smart-fe59a8bf-7f7a-4fcf-b40d-b8377ebf3159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856611483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.856611483
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1996402245
Short name T539
Test name
Test status
Simulation time 152621941 ps
CPU time 1.98 seconds
Started Aug 13 06:26:06 PM PDT 24
Finished Aug 13 06:26:08 PM PDT 24
Peak memory 200992 kb
Host smart-a4b02865-cd98-4e0b-9b86-14677cca9b7d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996402245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1
996402245
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3507561722
Short name T580
Test name
Test status
Simulation time 1991389225 ps
CPU time 8.63 seconds
Started Aug 13 06:26:05 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200996 kb
Host smart-4d978914-31ad-4f2c-9074-f1dea499bc22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507561722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
507561722
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3878042178
Short name T585
Test name
Test status
Simulation time 95622772 ps
CPU time 0.83 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 200832 kb
Host smart-47bb148c-9dc8-4eda-ba1e-dc3404c6add0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878042178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
878042178
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3927744122
Short name T94
Test name
Test status
Simulation time 121152224 ps
CPU time 0.96 seconds
Started Aug 13 06:26:08 PM PDT 24
Finished Aug 13 06:26:09 PM PDT 24
Peak memory 200936 kb
Host smart-0663f661-0a18-4b30-a29c-c263a8919fd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927744122 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3927744122
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1567788153
Short name T567
Test name
Test status
Simulation time 74703668 ps
CPU time 0.8 seconds
Started Aug 13 06:26:05 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 200744 kb
Host smart-8b29ccce-128e-4243-851f-c06ac5f1aab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567788153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1567788153
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.489340253
Short name T573
Test name
Test status
Simulation time 100956999 ps
CPU time 1.32 seconds
Started Aug 13 06:26:01 PM PDT 24
Finished Aug 13 06:26:02 PM PDT 24
Peak memory 201060 kb
Host smart-d0d7f1a7-aa0f-478c-925e-73b939523c4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489340253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sam
e_csr_outstanding.489340253
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.429118716
Short name T574
Test name
Test status
Simulation time 122366056 ps
CPU time 1.84 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 209312 kb
Host smart-f735161a-8005-4c66-bcd7-f72189ae7299
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429118716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.429118716
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2796405373
Short name T596
Test name
Test status
Simulation time 884294652 ps
CPU time 3.02 seconds
Started Aug 13 06:26:01 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 201028 kb
Host smart-7eeaff23-b8a5-411f-92c5-75d1be8913dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796405373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2796405373
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.135024110
Short name T613
Test name
Test status
Simulation time 202065399 ps
CPU time 1.5 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 200936 kb
Host smart-bb80eaf2-65b8-42a8-aeca-08712704b48a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135024110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.135024110
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.186915139
Short name T591
Test name
Test status
Simulation time 1177506272 ps
CPU time 5.05 seconds
Started Aug 13 06:26:09 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200960 kb
Host smart-6f678e08-90d8-4c61-9225-e43d68522192
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186915139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.186915139
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2097540696
Short name T576
Test name
Test status
Simulation time 147525091 ps
CPU time 0.97 seconds
Started Aug 13 06:26:02 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 200772 kb
Host smart-e7d7cf87-b4e3-42db-a8b8-698e958eab17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097540696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
097540696
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2879472515
Short name T592
Test name
Test status
Simulation time 166698517 ps
CPU time 1.18 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 200900 kb
Host smart-78e0af98-72a1-4871-b928-0ba17f8d33d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879472515 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2879472515
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.448664886
Short name T65
Test name
Test status
Simulation time 61457762 ps
CPU time 0.83 seconds
Started Aug 13 06:26:01 PM PDT 24
Finished Aug 13 06:26:02 PM PDT 24
Peak memory 200816 kb
Host smart-534d3836-82b3-47c5-90c5-2c5668f6fa3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448664886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.448664886
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1688435649
Short name T603
Test name
Test status
Simulation time 112108946 ps
CPU time 1.03 seconds
Started Aug 13 06:26:06 PM PDT 24
Finished Aug 13 06:26:07 PM PDT 24
Peak memory 200716 kb
Host smart-9adb9b48-590e-4c48-bd66-a2255514960f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688435649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1688435649
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1441306941
Short name T90
Test name
Test status
Simulation time 149614966 ps
CPU time 2.05 seconds
Started Aug 13 06:26:08 PM PDT 24
Finished Aug 13 06:26:11 PM PDT 24
Peak memory 209212 kb
Host smart-5b49e213-a6f9-4cbb-b0ca-d85a9efe83b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441306941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1441306941
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3555356926
Short name T549
Test name
Test status
Simulation time 1221244480 ps
CPU time 3.52 seconds
Started Aug 13 06:26:05 PM PDT 24
Finished Aug 13 06:26:09 PM PDT 24
Peak memory 201020 kb
Host smart-e6c076d7-f686-481a-a40e-cc861cc95480
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555356926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3555356926
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1518310904
Short name T542
Test name
Test status
Simulation time 153456602 ps
CPU time 1.95 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 200992 kb
Host smart-b54cadd7-4cba-463a-9f6c-9e4862cbf388
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518310904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
518310904
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3502182268
Short name T575
Test name
Test status
Simulation time 484704651 ps
CPU time 5.83 seconds
Started Aug 13 06:26:02 PM PDT 24
Finished Aug 13 06:26:07 PM PDT 24
Peak memory 201056 kb
Host smart-8e492008-1731-4d20-b750-ae6dd308fe2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502182268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
502182268
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1861974974
Short name T587
Test name
Test status
Simulation time 138398662 ps
CPU time 0.94 seconds
Started Aug 13 06:26:07 PM PDT 24
Finished Aug 13 06:26:08 PM PDT 24
Peak memory 200832 kb
Host smart-74985d9e-f0ae-458d-85ce-baaaf863b611
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861974974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
861974974
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3680250467
Short name T611
Test name
Test status
Simulation time 113999078 ps
CPU time 1.06 seconds
Started Aug 13 06:26:06 PM PDT 24
Finished Aug 13 06:26:07 PM PDT 24
Peak memory 209068 kb
Host smart-702210dc-2fe5-4e6f-a492-28b23089c2e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680250467 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.3680250467
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.720785215
Short name T619
Test name
Test status
Simulation time 66152937 ps
CPU time 0.8 seconds
Started Aug 13 06:26:05 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 200796 kb
Host smart-0e5b935c-5538-4304-995f-8675273b2de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720785215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.720785215
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.578954240
Short name T101
Test name
Test status
Simulation time 153361053 ps
CPU time 1.15 seconds
Started Aug 13 06:26:02 PM PDT 24
Finished Aug 13 06:26:03 PM PDT 24
Peak memory 200900 kb
Host smart-de5ceca7-d6c0-4d34-a512-b0d91356f522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578954240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.578954240
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.2627628447
Short name T606
Test name
Test status
Simulation time 249481469 ps
CPU time 1.86 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 209188 kb
Host smart-c0e11352-7867-4986-b307-9116438989ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627628447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2627628447
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2982253496
Short name T126
Test name
Test status
Simulation time 967751813 ps
CPU time 3.27 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 201056 kb
Host smart-949d88fd-50a7-4d34-b3ad-3fec42ef0443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982253496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2982253496
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3312571949
Short name T569
Test name
Test status
Simulation time 106440458 ps
CPU time 1.02 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 200912 kb
Host smart-e3c17c0d-2e07-4975-86b0-135d0e7b5e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312571949 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3312571949
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3304014008
Short name T538
Test name
Test status
Simulation time 70396898 ps
CPU time 0.8 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 200820 kb
Host smart-2df51fc9-71ea-497c-bc8c-98699392e098
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304014008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3304014008
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.4189276343
Short name T552
Test name
Test status
Simulation time 153866537 ps
CPU time 1.16 seconds
Started Aug 13 06:26:08 PM PDT 24
Finished Aug 13 06:26:09 PM PDT 24
Peak memory 200896 kb
Host smart-04afb1b6-b325-426d-9c4d-b6b71f5a831a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189276343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.4189276343
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.702406374
Short name T66
Test name
Test status
Simulation time 148193272 ps
CPU time 2.11 seconds
Started Aug 13 06:26:01 PM PDT 24
Finished Aug 13 06:26:03 PM PDT 24
Peak memory 209212 kb
Host smart-0b8aca56-d031-4f87-b85f-7790a21900e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702406374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.702406374
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2496116634
Short name T68
Test name
Test status
Simulation time 799987401 ps
CPU time 2.73 seconds
Started Aug 13 06:26:03 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 201104 kb
Host smart-e3882751-072b-46c8-9d98-83bc5aba1705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496116634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2496116634
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1126011845
Short name T590
Test name
Test status
Simulation time 100498437 ps
CPU time 0.86 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 200900 kb
Host smart-25f264b9-2461-47eb-a082-cc2cc6a99256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126011845 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1126011845
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4290327053
Short name T553
Test name
Test status
Simulation time 86028555 ps
CPU time 0.89 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:05 PM PDT 24
Peak memory 200780 kb
Host smart-9b543fa7-0c12-42c4-90d2-395909d62321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290327053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.4290327053
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3134247095
Short name T578
Test name
Test status
Simulation time 117233736 ps
CPU time 1.31 seconds
Started Aug 13 06:26:02 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 201048 kb
Host smart-b3e3cdfb-2f8e-41ff-837f-25559e5a0f5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134247095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.3134247095
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.788847288
Short name T600
Test name
Test status
Simulation time 186454260 ps
CPU time 2.76 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:07 PM PDT 24
Peak memory 209284 kb
Host smart-7bd4fc98-8ad0-42aa-8fd5-f0e257733d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788847288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.788847288
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1152348832
Short name T111
Test name
Test status
Simulation time 530700419 ps
CPU time 1.91 seconds
Started Aug 13 06:26:04 PM PDT 24
Finished Aug 13 06:26:06 PM PDT 24
Peak memory 201056 kb
Host smart-73311265-225d-4f74-88e8-c3cd21af4971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152348832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.1152348832
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.524137952
Short name T617
Test name
Test status
Simulation time 188279611 ps
CPU time 1.7 seconds
Started Aug 13 06:26:10 PM PDT 24
Finished Aug 13 06:26:12 PM PDT 24
Peak memory 209276 kb
Host smart-a67ad2f7-2c4d-4527-893f-5b9d74f875dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524137952 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.524137952
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2507340838
Short name T605
Test name
Test status
Simulation time 76948113 ps
CPU time 0.81 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 200804 kb
Host smart-5f7ef316-ba7a-4c54-b057-0b6a0b0e631f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507340838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2507340838
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3411957517
Short name T108
Test name
Test status
Simulation time 191739832 ps
CPU time 1.54 seconds
Started Aug 13 06:26:20 PM PDT 24
Finished Aug 13 06:26:22 PM PDT 24
Peak memory 200420 kb
Host smart-6b1cdcef-7bda-4696-bde8-030364b90012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411957517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.3411957517
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1537509006
Short name T89
Test name
Test status
Simulation time 477495911 ps
CPU time 3.14 seconds
Started Aug 13 06:26:12 PM PDT 24
Finished Aug 13 06:26:16 PM PDT 24
Peak memory 217296 kb
Host smart-6305b51c-d4c2-461c-b6e9-17f27a394cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537509006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1537509006
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.263436332
Short name T115
Test name
Test status
Simulation time 873374993 ps
CPU time 3.13 seconds
Started Aug 13 06:26:12 PM PDT 24
Finished Aug 13 06:26:16 PM PDT 24
Peak memory 201084 kb
Host smart-7974365a-bb57-4ff4-97b5-05e5d990d3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263436332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
263436332
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.965678536
Short name T557
Test name
Test status
Simulation time 98913157 ps
CPU time 0.91 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 200864 kb
Host smart-b849a160-e26d-4659-a613-f997942b8568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965678536 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.965678536
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.2854707351
Short name T62
Test name
Test status
Simulation time 83065160 ps
CPU time 0.83 seconds
Started Aug 13 06:26:16 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 200720 kb
Host smart-c6c830d7-d0e7-495d-a335-82c2ceced9b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854707351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2854707351
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1435314040
Short name T584
Test name
Test status
Simulation time 84896771 ps
CPU time 1 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:14 PM PDT 24
Peak memory 200904 kb
Host smart-63f26c6c-f16b-40a4-83a4-d2c171a8695b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435314040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.1435314040
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2282933654
Short name T566
Test name
Test status
Simulation time 194073374 ps
CPU time 2.46 seconds
Started Aug 13 06:26:12 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 209228 kb
Host smart-0200ebfe-8913-4c77-a091-6c8ba500f286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282933654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2282933654
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1932725219
Short name T548
Test name
Test status
Simulation time 911213086 ps
CPU time 3.21 seconds
Started Aug 13 06:26:09 PM PDT 24
Finished Aug 13 06:26:13 PM PDT 24
Peak memory 201064 kb
Host smart-3f750635-3278-47d6-8ebd-703a829abe3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932725219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1932725219
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2533109252
Short name T546
Test name
Test status
Simulation time 123242936 ps
CPU time 1.44 seconds
Started Aug 13 06:26:13 PM PDT 24
Finished Aug 13 06:26:15 PM PDT 24
Peak memory 209316 kb
Host smart-6c3f01f4-13a8-4999-81d6-1618c02f7445
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533109252 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2533109252
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1361032927
Short name T547
Test name
Test status
Simulation time 60229729 ps
CPU time 0.75 seconds
Started Aug 13 06:26:17 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 200788 kb
Host smart-6e37b4ab-9bc8-4c78-87ad-6df0a63bbc10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361032927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1361032927
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.322518986
Short name T568
Test name
Test status
Simulation time 96816743 ps
CPU time 1.19 seconds
Started Aug 13 06:26:14 PM PDT 24
Finished Aug 13 06:26:16 PM PDT 24
Peak memory 200956 kb
Host smart-80f0145a-b822-4b43-bff2-dbbb00481de3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322518986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.322518986
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3875227704
Short name T594
Test name
Test status
Simulation time 189734893 ps
CPU time 1.68 seconds
Started Aug 13 06:26:20 PM PDT 24
Finished Aug 13 06:26:22 PM PDT 24
Peak memory 209300 kb
Host smart-8748be1c-3a11-4d0e-8673-169eebddafc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875227704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3875227704
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1135919006
Short name T571
Test name
Test status
Simulation time 880959393 ps
CPU time 3.02 seconds
Started Aug 13 06:26:15 PM PDT 24
Finished Aug 13 06:26:18 PM PDT 24
Peak memory 201168 kb
Host smart-52d24e61-912d-40aa-adbd-15a5fa2b4d93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135919006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1135919006
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3918188034
Short name T242
Test name
Test status
Simulation time 68729978 ps
CPU time 0.78 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:48 PM PDT 24
Peak memory 200500 kb
Host smart-dfcd63f7-7941-4bca-8934-79a376e26dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918188034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3918188034
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.130688069
Short name T44
Test name
Test status
Simulation time 1878298853 ps
CPU time 7.31 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:53 PM PDT 24
Peak memory 218016 kb
Host smart-b6733247-1694-4299-af03-9b7da5baa0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130688069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.130688069
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4112668957
Short name T266
Test name
Test status
Simulation time 246367278 ps
CPU time 1.03 seconds
Started Aug 13 06:42:52 PM PDT 24
Finished Aug 13 06:42:53 PM PDT 24
Peak memory 217892 kb
Host smart-fc38b9ff-11dd-4467-96b3-7929e50a73fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112668957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4112668957
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3497478471
Short name T362
Test name
Test status
Simulation time 186916025 ps
CPU time 0.91 seconds
Started Aug 13 06:42:49 PM PDT 24
Finished Aug 13 06:42:50 PM PDT 24
Peak memory 200412 kb
Host smart-697bacb1-2704-4bae-b324-16dde5e5d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497478471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3497478471
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.2650912792
Short name T327
Test name
Test status
Simulation time 1379176583 ps
CPU time 5.47 seconds
Started Aug 13 06:43:05 PM PDT 24
Finished Aug 13 06:43:11 PM PDT 24
Peak memory 200824 kb
Host smart-22172f96-b1ca-48e4-adce-7e802e344d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650912792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2650912792
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3766644943
Short name T173
Test name
Test status
Simulation time 155326825 ps
CPU time 1.13 seconds
Started Aug 13 06:43:05 PM PDT 24
Finished Aug 13 06:43:07 PM PDT 24
Peak memory 200608 kb
Host smart-8b8b049c-ace3-45ef-9350-f5aa0610588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766644943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3766644943
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.3016366214
Short name T376
Test name
Test status
Simulation time 194540320 ps
CPU time 1.31 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 200772 kb
Host smart-bba21663-5b67-48a7-b86b-96b2c25e083c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016366214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3016366214
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.1758309630
Short name T513
Test name
Test status
Simulation time 3250425792 ps
CPU time 14.77 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:43:06 PM PDT 24
Peak memory 209112 kb
Host smart-8aa6f89a-0337-4bba-9cd0-68784ad9fe2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758309630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1758309630
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1415329892
Short name T510
Test name
Test status
Simulation time 115111624 ps
CPU time 1.44 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200568 kb
Host smart-50323e2e-a168-46fb-b00e-c5795c64f5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415329892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1415329892
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3688629988
Short name T134
Test name
Test status
Simulation time 65730370 ps
CPU time 0.8 seconds
Started Aug 13 06:43:16 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200672 kb
Host smart-72f98d44-7fc5-4d22-864c-f1b6aeb5f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688629988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3688629988
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1566599672
Short name T309
Test name
Test status
Simulation time 81331118 ps
CPU time 0.86 seconds
Started Aug 13 06:43:33 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 200536 kb
Host smart-23ebc663-0fef-46a0-9e13-37ffefb1f353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566599672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1566599672
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1594070823
Short name T529
Test name
Test status
Simulation time 1892254756 ps
CPU time 7.79 seconds
Started Aug 13 06:42:47 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 218012 kb
Host smart-9b6f279b-5c1e-4d07-828a-fdddc6dabb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594070823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1594070823
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.52140432
Short name T444
Test name
Test status
Simulation time 244439652 ps
CPU time 1.13 seconds
Started Aug 13 06:42:49 PM PDT 24
Finished Aug 13 06:42:50 PM PDT 24
Peak memory 217828 kb
Host smart-0e26b7a1-ed0e-4de3-84f8-4fdf9cb8e518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52140432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.52140432
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_reset.3161005663
Short name T428
Test name
Test status
Simulation time 814569513 ps
CPU time 3.86 seconds
Started Aug 13 06:42:57 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 200788 kb
Host smart-338a4bf1-14be-4b14-b5a5-56cb86f5cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161005663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3161005663
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.293584434
Short name T76
Test name
Test status
Simulation time 8321180059 ps
CPU time 12.73 seconds
Started Aug 13 06:42:48 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 217808 kb
Host smart-ad68a8ff-b134-47fa-a525-cfedbc7223ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293584434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.293584434
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.4041864761
Short name T221
Test name
Test status
Simulation time 154940958 ps
CPU time 1.1 seconds
Started Aug 13 06:42:46 PM PDT 24
Finished Aug 13 06:42:47 PM PDT 24
Peak memory 200628 kb
Host smart-0207643b-f325-4073-b407-1fcaa58f10a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041864761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.4041864761
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.953534371
Short name T508
Test name
Test status
Simulation time 207155343 ps
CPU time 1.43 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 200820 kb
Host smart-7ed7bc2b-0833-48e2-8a8c-52d3dbeb1d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953534371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.953534371
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.4283822792
Short name T408
Test name
Test status
Simulation time 2779504521 ps
CPU time 12.06 seconds
Started Aug 13 06:42:57 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 209096 kb
Host smart-dbacba9f-bb38-4fda-ad7e-8070bba1c637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283822792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4283822792
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3768815947
Short name T141
Test name
Test status
Simulation time 138569750 ps
CPU time 1.81 seconds
Started Aug 13 06:42:48 PM PDT 24
Finished Aug 13 06:42:50 PM PDT 24
Peak memory 200568 kb
Host smart-f56e96af-4643-4756-9592-ff0bd3519a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768815947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3768815947
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.7571818
Short name T450
Test name
Test status
Simulation time 99439678 ps
CPU time 0.96 seconds
Started Aug 13 06:42:45 PM PDT 24
Finished Aug 13 06:42:46 PM PDT 24
Peak memory 200692 kb
Host smart-2a33bd81-5020-48ad-ad74-0582428faca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7571818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.7571818
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.450602154
Short name T206
Test name
Test status
Simulation time 62021365 ps
CPU time 0.73 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 200540 kb
Host smart-dd298e31-1229-471b-bf63-28035a821f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450602154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.450602154
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3428737320
Short name T58
Test name
Test status
Simulation time 1233993201 ps
CPU time 5.39 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 221892 kb
Host smart-da71f260-6cd8-4d64-a1a8-ba93757e1d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428737320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3428737320
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1710531032
Short name T319
Test name
Test status
Simulation time 244522761 ps
CPU time 1.1 seconds
Started Aug 13 06:42:55 PM PDT 24
Finished Aug 13 06:42:56 PM PDT 24
Peak memory 217816 kb
Host smart-bfa5f5b2-e2e7-4d9a-a434-02274e5b9fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710531032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1710531032
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2635957661
Short name T21
Test name
Test status
Simulation time 85499403 ps
CPU time 0.76 seconds
Started Aug 13 06:42:50 PM PDT 24
Finished Aug 13 06:42:51 PM PDT 24
Peak memory 200456 kb
Host smart-6f495734-a9c8-4d8b-afa8-5b708927a288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635957661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2635957661
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2367294263
Short name T119
Test name
Test status
Simulation time 1754091300 ps
CPU time 6.31 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 200792 kb
Host smart-e35d32c7-438a-478a-8b0a-5ad7e9ad3a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367294263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2367294263
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1769022772
Short name T194
Test name
Test status
Simulation time 110072554 ps
CPU time 1.02 seconds
Started Aug 13 06:43:11 PM PDT 24
Finished Aug 13 06:43:12 PM PDT 24
Peak memory 200640 kb
Host smart-d494cb4d-362e-42b3-8800-e7ba80c73a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769022772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1769022772
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.678393037
Short name T317
Test name
Test status
Simulation time 190568590 ps
CPU time 1.34 seconds
Started Aug 13 06:43:04 PM PDT 24
Finished Aug 13 06:43:06 PM PDT 24
Peak memory 200808 kb
Host smart-eb1d83ef-240b-49e7-9430-9ff66fbdcd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678393037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.678393037
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1466879894
Short name T470
Test name
Test status
Simulation time 7747672471 ps
CPU time 26.16 seconds
Started Aug 13 06:43:11 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 209088 kb
Host smart-50af5b83-3700-466c-9e38-f0bfc6c72fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466879894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1466879894
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2231218236
Short name T161
Test name
Test status
Simulation time 116124477 ps
CPU time 0.99 seconds
Started Aug 13 06:42:59 PM PDT 24
Finished Aug 13 06:43:00 PM PDT 24
Peak memory 200628 kb
Host smart-c2e8cf63-ffde-4365-8563-45f3cac2c032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231218236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2231218236
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3167518727
Short name T153
Test name
Test status
Simulation time 75945645 ps
CPU time 0.81 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 200464 kb
Host smart-0603a004-7d27-4f59-a6ab-3fb854ed09e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167518727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3167518727
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3890799135
Short name T30
Test name
Test status
Simulation time 2188543062 ps
CPU time 7.8 seconds
Started Aug 13 06:43:01 PM PDT 24
Finished Aug 13 06:43:08 PM PDT 24
Peak memory 221984 kb
Host smart-991425aa-8d50-4f33-a602-ab4680032b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890799135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3890799135
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3235905650
Short name T288
Test name
Test status
Simulation time 243414701 ps
CPU time 1.27 seconds
Started Aug 13 06:43:04 PM PDT 24
Finished Aug 13 06:43:06 PM PDT 24
Peak memory 217832 kb
Host smart-ee0a857d-6ae5-489f-ac09-6d6874a20b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235905650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3235905650
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2277947361
Short name T236
Test name
Test status
Simulation time 121527096 ps
CPU time 0.8 seconds
Started Aug 13 06:43:11 PM PDT 24
Finished Aug 13 06:43:12 PM PDT 24
Peak memory 200460 kb
Host smart-247aff7b-cf41-4ccd-b04a-a3ce186bb381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277947361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2277947361
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.4195719003
Short name T179
Test name
Test status
Simulation time 1587967348 ps
CPU time 6.13 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 200852 kb
Host smart-4340bf5d-4349-4e28-b28b-9830fd429c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195719003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.4195719003
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1754895561
Short name T437
Test name
Test status
Simulation time 117396807 ps
CPU time 1.06 seconds
Started Aug 13 06:43:07 PM PDT 24
Finished Aug 13 06:43:08 PM PDT 24
Peak memory 200668 kb
Host smart-9cdc5601-fdab-47e0-94ec-4f6316448eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754895561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1754895561
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1059382135
Short name T51
Test name
Test status
Simulation time 195365344 ps
CPU time 1.32 seconds
Started Aug 13 06:43:03 PM PDT 24
Finished Aug 13 06:43:05 PM PDT 24
Peak memory 200804 kb
Host smart-7dd21f91-c80c-48c3-ad1c-00f57030b477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059382135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1059382135
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.2320386505
Short name T490
Test name
Test status
Simulation time 2671433122 ps
CPU time 13.84 seconds
Started Aug 13 06:43:00 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 200776 kb
Host smart-e04efcad-b766-43f7-b388-a498cba7a1d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320386505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2320386505
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.534146888
Short name T409
Test name
Test status
Simulation time 130443521 ps
CPU time 1.58 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 208752 kb
Host smart-c6d71973-d89f-44eb-ad0c-bf87f1cddd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534146888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.534146888
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.3132153539
Short name T174
Test name
Test status
Simulation time 227490846 ps
CPU time 1.33 seconds
Started Aug 13 06:43:00 PM PDT 24
Finished Aug 13 06:43:02 PM PDT 24
Peak memory 200664 kb
Host smart-62759f44-43a8-431e-bb33-21d18e60bceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132153539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3132153539
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3403435995
Short name T219
Test name
Test status
Simulation time 65780006 ps
CPU time 0.76 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 200540 kb
Host smart-7423c5a2-6449-4c57-9d2a-67ef2e4b8f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403435995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3403435995
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3967276788
Short name T77
Test name
Test status
Simulation time 244147937 ps
CPU time 1.14 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 217848 kb
Host smart-95ac4192-39ba-49fb-816f-9a1ecc697e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967276788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3967276788
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3513370748
Short name T299
Test name
Test status
Simulation time 158246983 ps
CPU time 0.89 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 200480 kb
Host smart-e070e8a0-5a36-43a4-b5b8-fc99c1116af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513370748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3513370748
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3356506543
Short name T338
Test name
Test status
Simulation time 1816462076 ps
CPU time 7.52 seconds
Started Aug 13 06:42:52 PM PDT 24
Finished Aug 13 06:42:59 PM PDT 24
Peak memory 200756 kb
Host smart-227a3600-af57-4b95-859f-e49fa7aaf4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356506543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3356506543
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.4048405396
Short name T449
Test name
Test status
Simulation time 100197769 ps
CPU time 0.99 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:52 PM PDT 24
Peak memory 200664 kb
Host smart-fb4b0d85-b1f2-4767-beb5-52ca1548058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048405396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.4048405396
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2908848445
Short name T250
Test name
Test status
Simulation time 7761213939 ps
CPU time 28.18 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 209060 kb
Host smart-2ffbe0d2-2adb-42ae-95d5-d5845c234c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908848445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2908848445
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.27801367
Short name T124
Test name
Test status
Simulation time 352570440 ps
CPU time 2.24 seconds
Started Aug 13 06:42:59 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 200536 kb
Host smart-304413c0-2c65-459e-a0c3-38f5f85ab1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27801367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.27801367
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2134963081
Short name T536
Test name
Test status
Simulation time 87565283 ps
CPU time 0.84 seconds
Started Aug 13 06:42:58 PM PDT 24
Finished Aug 13 06:42:59 PM PDT 24
Peak memory 200656 kb
Host smart-3ced4bc5-49a5-486b-a127-0980e1da5282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134963081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2134963081
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2460688879
Short name T310
Test name
Test status
Simulation time 68946365 ps
CPU time 0.84 seconds
Started Aug 13 06:43:11 PM PDT 24
Finished Aug 13 06:43:12 PM PDT 24
Peak memory 200500 kb
Host smart-dabb1619-dd67-4263-8ce7-860ffbe5118c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460688879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2460688879
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.822088243
Short name T84
Test name
Test status
Simulation time 244417261 ps
CPU time 1.02 seconds
Started Aug 13 06:42:56 PM PDT 24
Finished Aug 13 06:42:57 PM PDT 24
Peak memory 217860 kb
Host smart-b077c960-a9ee-45c9-a05d-058b2a574229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822088243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.822088243
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2522311881
Short name T164
Test name
Test status
Simulation time 189817878 ps
CPU time 0.87 seconds
Started Aug 13 06:43:21 PM PDT 24
Finished Aug 13 06:43:22 PM PDT 24
Peak memory 200476 kb
Host smart-ce56b800-594d-46e6-9426-af480214ac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522311881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2522311881
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2054378549
Short name T370
Test name
Test status
Simulation time 2145918315 ps
CPU time 7.26 seconds
Started Aug 13 06:43:11 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 200824 kb
Host smart-81d61672-c8a2-4982-8314-6888f931315b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054378549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2054378549
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.3859849264
Short name T494
Test name
Test status
Simulation time 191574005 ps
CPU time 1.29 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200808 kb
Host smart-d424d52c-0f6c-4270-89b7-6f11cff3223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859849264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3859849264
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3713953561
Short name T86
Test name
Test status
Simulation time 1088534239 ps
CPU time 5.54 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 200784 kb
Host smart-40cb8fd3-950d-4bd5-afb7-f2f20532e634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713953561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3713953561
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.2464816292
Short name T480
Test name
Test status
Simulation time 148487765 ps
CPU time 1.9 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:21 PM PDT 24
Peak memory 200540 kb
Host smart-f42960cb-b202-4d04-b778-ce38111e50b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464816292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2464816292
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3437282120
Short name T381
Test name
Test status
Simulation time 180872698 ps
CPU time 1.27 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:16 PM PDT 24
Peak memory 200632 kb
Host smart-28264a03-ebc2-433a-b3e1-c26e8ebcb610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437282120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3437282120
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2806558138
Short name T203
Test name
Test status
Simulation time 55528933 ps
CPU time 0.71 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:18 PM PDT 24
Peak memory 200540 kb
Host smart-2b4badfe-3a45-4651-9f2e-a3edea7fe5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806558138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2806558138
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.661019640
Short name T504
Test name
Test status
Simulation time 1223703399 ps
CPU time 5.75 seconds
Started Aug 13 06:43:00 PM PDT 24
Finished Aug 13 06:43:06 PM PDT 24
Peak memory 221928 kb
Host smart-073a0881-1efc-4a73-baef-d0670824f9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661019640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.661019640
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3427837194
Short name T422
Test name
Test status
Simulation time 244191271 ps
CPU time 1.12 seconds
Started Aug 13 06:43:05 PM PDT 24
Finished Aug 13 06:43:06 PM PDT 24
Peak memory 217796 kb
Host smart-242ede60-1d56-4049-a89c-6a6f709ed654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427837194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3427837194
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2847942769
Short name T168
Test name
Test status
Simulation time 164947142 ps
CPU time 0.83 seconds
Started Aug 13 06:42:55 PM PDT 24
Finished Aug 13 06:42:56 PM PDT 24
Peak memory 200440 kb
Host smart-aeec7a83-e395-432b-8bab-eace799f475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847942769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2847942769
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.4144055211
Short name T152
Test name
Test status
Simulation time 698071829 ps
CPU time 4.08 seconds
Started Aug 13 06:43:20 PM PDT 24
Finished Aug 13 06:43:24 PM PDT 24
Peak memory 200744 kb
Host smart-2c47270e-eed6-4739-85bd-63264d11ae6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144055211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.4144055211
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3401968470
Short name T229
Test name
Test status
Simulation time 103704545 ps
CPU time 0.99 seconds
Started Aug 13 06:42:56 PM PDT 24
Finished Aug 13 06:42:57 PM PDT 24
Peak memory 200600 kb
Host smart-fd1059f7-8920-4735-a0c2-5f915490f0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401968470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3401968470
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3626082659
Short name T166
Test name
Test status
Simulation time 122355781 ps
CPU time 1.24 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:20 PM PDT 24
Peak memory 200760 kb
Host smart-876b1b65-3209-4449-83b2-1215f4f14bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626082659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3626082659
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2330654666
Short name T212
Test name
Test status
Simulation time 908669426 ps
CPU time 4.23 seconds
Started Aug 13 06:43:06 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 200836 kb
Host smart-a8d55ead-b733-4544-9062-05bfba7f24c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330654666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2330654666
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2190794254
Short name T254
Test name
Test status
Simulation time 134372003 ps
CPU time 1.58 seconds
Started Aug 13 06:43:20 PM PDT 24
Finished Aug 13 06:43:22 PM PDT 24
Peak memory 200572 kb
Host smart-ef995134-0bd3-42ef-a17c-f3c976d9c479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190794254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2190794254
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3282919985
Short name T336
Test name
Test status
Simulation time 153072790 ps
CPU time 1.32 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 200764 kb
Host smart-5707842d-ed11-4de4-a2a5-7312f55be63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282919985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3282919985
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3384388396
Short name T186
Test name
Test status
Simulation time 53355852 ps
CPU time 0.78 seconds
Started Aug 13 06:43:06 PM PDT 24
Finished Aug 13 06:43:07 PM PDT 24
Peak memory 200516 kb
Host smart-215c7149-dfef-4977-9765-60d59b58295c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384388396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3384388396
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.682603604
Short name T527
Test name
Test status
Simulation time 1921205414 ps
CPU time 8 seconds
Started Aug 13 06:42:56 PM PDT 24
Finished Aug 13 06:43:04 PM PDT 24
Peak memory 217484 kb
Host smart-6d4fd341-c27e-4b2a-8eb3-83e0795dc618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682603604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.682603604
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3113287406
Short name T521
Test name
Test status
Simulation time 246608645 ps
CPU time 1.06 seconds
Started Aug 13 06:43:00 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 217896 kb
Host smart-17b7098e-34b6-47a4-9561-9b5d3c7e5f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113287406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3113287406
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2777679329
Short name T496
Test name
Test status
Simulation time 142659444 ps
CPU time 0.85 seconds
Started Aug 13 06:43:16 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200480 kb
Host smart-19582da6-57bb-48de-a2ac-f7d2be67627c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777679329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2777679329
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.243794626
Short name T118
Test name
Test status
Simulation time 1673543591 ps
CPU time 6.42 seconds
Started Aug 13 06:43:02 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 200836 kb
Host smart-ba32debb-e823-47b2-b319-9b941e91cd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243794626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.243794626
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2575848317
Short name T402
Test name
Test status
Simulation time 160122727 ps
CPU time 1.12 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:18 PM PDT 24
Peak memory 200616 kb
Host smart-12c4c441-d00f-487b-857f-3a703948a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575848317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2575848317
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.2639503175
Short name T180
Test name
Test status
Simulation time 112110199 ps
CPU time 1.19 seconds
Started Aug 13 06:43:09 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 200728 kb
Host smart-15d0a753-cb92-49a1-82ca-469cee5b7bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639503175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2639503175
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1206120543
Short name T252
Test name
Test status
Simulation time 2148585725 ps
CPU time 9.52 seconds
Started Aug 13 06:43:10 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 200844 kb
Host smart-0b7678fd-f660-4beb-934f-35218471d082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206120543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1206120543
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2095417629
Short name T358
Test name
Test status
Simulation time 371707259 ps
CPU time 2.02 seconds
Started Aug 13 06:43:03 PM PDT 24
Finished Aug 13 06:43:05 PM PDT 24
Peak memory 200564 kb
Host smart-2ea8f968-d7c7-48b7-b610-8a4f3011a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095417629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2095417629
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.99407624
Short name T235
Test name
Test status
Simulation time 72787372 ps
CPU time 0.76 seconds
Started Aug 13 06:43:01 PM PDT 24
Finished Aug 13 06:43:02 PM PDT 24
Peak memory 200652 kb
Host smart-37989886-904e-40c9-98ca-8c7ddbbdc21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99407624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.99407624
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2750739102
Short name T369
Test name
Test status
Simulation time 63832439 ps
CPU time 0.79 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 200444 kb
Host smart-bffd03bc-4c17-4860-97f5-7c2661682904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750739102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2750739102
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.2320146219
Short name T495
Test name
Test status
Simulation time 1225786146 ps
CPU time 6.05 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:24 PM PDT 24
Peak memory 217036 kb
Host smart-3ba99265-32c6-4c50-aac8-8c50fc099171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320146219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.2320146219
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.657317720
Short name T503
Test name
Test status
Simulation time 244497359 ps
CPU time 1.07 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 217868 kb
Host smart-0bae7c16-e8ca-440c-86ac-619e667e03b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657317720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.657317720
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.3385780279
Short name T321
Test name
Test status
Simulation time 200321497 ps
CPU time 0.91 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:18 PM PDT 24
Peak memory 200476 kb
Host smart-a210bf5d-18cc-4963-8ec9-206ece4ee383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385780279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.3385780279
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4134538859
Short name T260
Test name
Test status
Simulation time 1520343856 ps
CPU time 6.22 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200808 kb
Host smart-b2291d6c-850e-4adc-b214-e4a6622d2fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134538859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4134538859
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1098073970
Short name T128
Test name
Test status
Simulation time 148320548 ps
CPU time 1.12 seconds
Started Aug 13 06:43:33 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 200648 kb
Host smart-4ca84846-a37b-483c-b002-f43df06e4cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098073970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1098073970
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2204552552
Short name T488
Test name
Test status
Simulation time 253370479 ps
CPU time 1.46 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:20 PM PDT 24
Peak memory 200804 kb
Host smart-a6a35f86-d413-4485-9f23-d1596d651db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204552552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2204552552
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2062322305
Short name T210
Test name
Test status
Simulation time 7162420138 ps
CPU time 25.3 seconds
Started Aug 13 06:43:09 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 209048 kb
Host smart-7a983d87-92fc-4554-982c-a8219fa58bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062322305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2062322305
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3272432604
Short name T36
Test name
Test status
Simulation time 141322700 ps
CPU time 1.74 seconds
Started Aug 13 06:43:07 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 200540 kb
Host smart-08befbb6-743d-4e50-9446-db9aeea08b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272432604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3272432604
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.3435974457
Short name T357
Test name
Test status
Simulation time 263990974 ps
CPU time 1.39 seconds
Started Aug 13 06:43:12 PM PDT 24
Finished Aug 13 06:43:13 PM PDT 24
Peak memory 200692 kb
Host smart-7661abb9-08e8-4283-93dc-a30584e4bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435974457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3435974457
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.220148
Short name T502
Test name
Test status
Simulation time 74657384 ps
CPU time 0.75 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:18 PM PDT 24
Peak memory 200476 kb
Host smart-a6e3408c-4bf1-4993-a471-365b27d8d76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.220148
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.3906037895
Short name T26
Test name
Test status
Simulation time 1894500078 ps
CPU time 6.93 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:26 PM PDT 24
Peak memory 222012 kb
Host smart-8f7ead69-e1e5-4267-a82e-d58b0547dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906037895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3906037895
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2971699672
Short name T209
Test name
Test status
Simulation time 244080010 ps
CPU time 1.09 seconds
Started Aug 13 06:42:59 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 217836 kb
Host smart-d8b82eb0-67ca-47de-87fb-a1770793ffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971699672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2971699672
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.603793506
Short name T458
Test name
Test status
Simulation time 182526993 ps
CPU time 0.92 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:24 PM PDT 24
Peak memory 200460 kb
Host smart-44f6836c-0ed2-48e3-8385-a8d78baa4919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603793506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.603793506
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.876753858
Short name T162
Test name
Test status
Simulation time 1514286645 ps
CPU time 6.06 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:24 PM PDT 24
Peak memory 200860 kb
Host smart-bb399350-6439-499d-8c81-97cf89a7007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876753858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.876753858
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2547548914
Short name T178
Test name
Test status
Simulation time 137189075 ps
CPU time 1.05 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 200652 kb
Host smart-59228f6e-fab4-4f1d-84ec-a331352cbe85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547548914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2547548914
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2037998713
Short name T123
Test name
Test status
Simulation time 261361156 ps
CPU time 1.49 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200724 kb
Host smart-2e5129d8-6099-4eac-8b75-b16e629db2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037998713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2037998713
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.1221424926
Short name T339
Test name
Test status
Simulation time 5165406610 ps
CPU time 18.05 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 209856 kb
Host smart-07a14c42-1d59-4615-b10b-cda09be0cf8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221424926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1221424926
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1803272196
Short name T150
Test name
Test status
Simulation time 127332950 ps
CPU time 1.65 seconds
Started Aug 13 06:43:31 PM PDT 24
Finished Aug 13 06:43:32 PM PDT 24
Peak memory 208740 kb
Host smart-be600832-6b84-4e1c-b536-1ddb3575efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803272196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1803272196
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.1098033576
Short name T200
Test name
Test status
Simulation time 134108643 ps
CPU time 1.07 seconds
Started Aug 13 06:43:12 PM PDT 24
Finished Aug 13 06:43:13 PM PDT 24
Peak memory 200600 kb
Host smart-aa9fa37f-8327-4dbe-816f-1fd7ad957bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098033576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1098033576
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1360638712
Short name T135
Test name
Test status
Simulation time 57576570 ps
CPU time 0.73 seconds
Started Aug 13 06:43:05 PM PDT 24
Finished Aug 13 06:43:06 PM PDT 24
Peak memory 200500 kb
Host smart-87da6aae-3e6a-40de-a20e-a2b119bc0691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360638712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1360638712
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.4282180361
Short name T47
Test name
Test status
Simulation time 1233627844 ps
CPU time 6.24 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:23 PM PDT 24
Peak memory 217972 kb
Host smart-be3fc54a-107d-47ef-b52e-b18c6a8ffef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282180361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4282180361
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.907326843
Short name T78
Test name
Test status
Simulation time 243618176 ps
CPU time 1.1 seconds
Started Aug 13 06:43:11 PM PDT 24
Finished Aug 13 06:43:12 PM PDT 24
Peak memory 217820 kb
Host smart-b7823b36-2741-4a44-b8cd-7abcffb873be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907326843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.907326843
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2455249129
Short name T273
Test name
Test status
Simulation time 145815313 ps
CPU time 0.87 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 200488 kb
Host smart-359acf36-088f-4794-93c5-4947f3cfca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455249129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2455249129
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.825261456
Short name T224
Test name
Test status
Simulation time 1565121630 ps
CPU time 6.23 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 200848 kb
Host smart-d0c0080e-66ac-4ccc-9245-5c994207ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825261456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.825261456
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1571548620
Short name T531
Test name
Test status
Simulation time 104616829 ps
CPU time 0.95 seconds
Started Aug 13 06:43:20 PM PDT 24
Finished Aug 13 06:43:26 PM PDT 24
Peak memory 200672 kb
Host smart-b57cc2e3-cdd7-4088-b917-77c53adc9fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571548620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1571548620
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.300802247
Short name T523
Test name
Test status
Simulation time 199657526 ps
CPU time 1.42 seconds
Started Aug 13 06:43:25 PM PDT 24
Finished Aug 13 06:43:26 PM PDT 24
Peak memory 200764 kb
Host smart-031ef07c-6d53-4e3d-9367-673b1cf734dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300802247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.300802247
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1221701535
Short name T13
Test name
Test status
Simulation time 259610755 ps
CPU time 1.7 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:21 PM PDT 24
Peak memory 200676 kb
Host smart-1fd59360-3f6f-4d76-8eda-1379756dd35a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221701535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1221701535
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1677079368
Short name T394
Test name
Test status
Simulation time 136784423 ps
CPU time 1.65 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200616 kb
Host smart-6b5fd365-3707-4ef0-a615-17a7b304d295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677079368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1677079368
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2574444882
Short name T147
Test name
Test status
Simulation time 226857564 ps
CPU time 1.38 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 200672 kb
Host smart-e1e21609-1815-4cec-845d-7b5813291666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574444882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2574444882
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2884149437
Short name T382
Test name
Test status
Simulation time 67863942 ps
CPU time 0.79 seconds
Started Aug 13 06:43:01 PM PDT 24
Finished Aug 13 06:43:02 PM PDT 24
Peak memory 200540 kb
Host smart-11b07a6d-0942-4a4c-8b0b-639827bf533c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884149437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2884149437
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3701095912
Short name T355
Test name
Test status
Simulation time 1219331578 ps
CPU time 5.28 seconds
Started Aug 13 06:43:06 PM PDT 24
Finished Aug 13 06:43:11 PM PDT 24
Peak memory 218000 kb
Host smart-e7a34597-2f63-45d2-af0e-2b4b145c5b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701095912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3701095912
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1740125514
Short name T505
Test name
Test status
Simulation time 244608173 ps
CPU time 1.08 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 217760 kb
Host smart-d9640a44-a150-40d6-8775-27178a237c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740125514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1740125514
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3368059159
Short name T520
Test name
Test status
Simulation time 113456465 ps
CPU time 0.81 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:16 PM PDT 24
Peak memory 200484 kb
Host smart-ca2dbd84-95ca-4e88-94f3-1a7550d044de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368059159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3368059159
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2112714070
Short name T142
Test name
Test status
Simulation time 1255541069 ps
CPU time 4.72 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:35 PM PDT 24
Peak memory 200816 kb
Host smart-60dad0d0-25e1-4b52-b2b5-645683b48f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112714070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2112714070
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.1469078610
Short name T386
Test name
Test status
Simulation time 151069379 ps
CPU time 1.15 seconds
Started Aug 13 06:42:58 PM PDT 24
Finished Aug 13 06:43:00 PM PDT 24
Peak memory 200656 kb
Host smart-bccb7232-9832-4717-9b7f-1e3809887e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469078610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.1469078610
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2984265020
Short name T415
Test name
Test status
Simulation time 113157989 ps
CPU time 1.18 seconds
Started Aug 13 06:43:10 PM PDT 24
Finished Aug 13 06:43:11 PM PDT 24
Peak memory 200776 kb
Host smart-2f6a5a8f-d93b-46b4-bf1d-15066885d87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984265020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2984265020
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2783436697
Short name T404
Test name
Test status
Simulation time 13058682787 ps
CPU time 44.43 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:44:02 PM PDT 24
Peak memory 200876 kb
Host smart-8a9aa194-f961-422d-ac39-cd386c1f187d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783436697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2783436697
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2254155238
Short name T389
Test name
Test status
Simulation time 472034744 ps
CPU time 2.76 seconds
Started Aug 13 06:43:10 PM PDT 24
Finished Aug 13 06:43:13 PM PDT 24
Peak memory 200580 kb
Host smart-eaf4df36-7e81-402d-a909-d5676cd3c472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254155238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2254155238
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.972028747
Short name T170
Test name
Test status
Simulation time 91357536 ps
CPU time 0.85 seconds
Started Aug 13 06:43:16 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200552 kb
Host smart-3b11edb2-f647-4731-b2ea-49d67002db7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972028747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.972028747
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4290066705
Short name T365
Test name
Test status
Simulation time 2168373035 ps
CPU time 7.63 seconds
Started Aug 13 06:43:01 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 221920 kb
Host smart-ed7dcced-b075-49fc-8812-dff8231bf6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290066705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4290066705
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1411912761
Short name T226
Test name
Test status
Simulation time 244579351 ps
CPU time 1.18 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 217872 kb
Host smart-6e89a62e-ca7e-4b14-8005-5d7c4ea7e0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411912761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1411912761
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.2120126854
Short name T154
Test name
Test status
Simulation time 95244236 ps
CPU time 0.74 seconds
Started Aug 13 06:42:56 PM PDT 24
Finished Aug 13 06:42:57 PM PDT 24
Peak memory 200488 kb
Host smart-c4a0d00f-989a-48e2-a73e-631a2d089590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120126854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2120126854
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.4159597790
Short name T518
Test name
Test status
Simulation time 1165836070 ps
CPU time 5.08 seconds
Started Aug 13 06:42:50 PM PDT 24
Finished Aug 13 06:42:56 PM PDT 24
Peak memory 200792 kb
Host smart-ef08f342-e026-4035-a109-96f9c179ec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159597790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.4159597790
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2664063572
Short name T70
Test name
Test status
Simulation time 22674546651 ps
CPU time 34.26 seconds
Started Aug 13 06:43:22 PM PDT 24
Finished Aug 13 06:43:56 PM PDT 24
Peak memory 218452 kb
Host smart-3a05845c-00b5-4df7-9542-1e60827a66b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664063572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2664063572
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3488652521
Short name T7
Test name
Test status
Simulation time 175400036 ps
CPU time 1.15 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 200604 kb
Host smart-1bf89160-ee52-45d2-a56c-0faac1648408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488652521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3488652521
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3071839314
Short name T53
Test name
Test status
Simulation time 111914443 ps
CPU time 1.14 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 200720 kb
Host smart-d857a5c7-7c70-46d3-bbef-73f3c2b1da0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071839314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3071839314
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1515711134
Short name T191
Test name
Test status
Simulation time 346364264 ps
CPU time 1.89 seconds
Started Aug 13 06:42:58 PM PDT 24
Finished Aug 13 06:43:00 PM PDT 24
Peak memory 200772 kb
Host smart-f33cb1a9-aa0f-4d08-9de3-7bfdc57774e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515711134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1515711134
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2104059384
Short name T217
Test name
Test status
Simulation time 305233917 ps
CPU time 1.82 seconds
Started Aug 13 06:43:03 PM PDT 24
Finished Aug 13 06:43:05 PM PDT 24
Peak memory 200500 kb
Host smart-7c0f66b0-c82b-4a9a-b29c-fb1256d0e021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104059384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2104059384
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1979389746
Short name T322
Test name
Test status
Simulation time 121948065 ps
CPU time 1.11 seconds
Started Aug 13 06:43:00 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 200644 kb
Host smart-9e56f0f5-4fce-449d-8a65-d1044505204e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979389746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1979389746
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2608210338
Short name T264
Test name
Test status
Simulation time 65146765 ps
CPU time 0.75 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 200464 kb
Host smart-0db5bdaf-c61c-48d1-b11c-9c5ad5b31424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608210338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2608210338
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2910874080
Short name T298
Test name
Test status
Simulation time 1887671654 ps
CPU time 6.97 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:20 PM PDT 24
Peak memory 221644 kb
Host smart-35ec9cd9-5f56-4668-9770-98886d6ca2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910874080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2910874080
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.500176277
Short name T351
Test name
Test status
Simulation time 245417552 ps
CPU time 1.07 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:16 PM PDT 24
Peak memory 217804 kb
Host smart-9b38f4ad-bf64-407b-9cf9-9c1663075242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500176277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.500176277
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3288713836
Short name T397
Test name
Test status
Simulation time 119441173 ps
CPU time 0.81 seconds
Started Aug 13 06:43:20 PM PDT 24
Finished Aug 13 06:43:21 PM PDT 24
Peak memory 200416 kb
Host smart-f1331461-e0fc-44aa-9980-b77b7bbdbf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288713836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3288713836
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.298422425
Short name T223
Test name
Test status
Simulation time 922241955 ps
CPU time 4.69 seconds
Started Aug 13 06:42:57 PM PDT 24
Finished Aug 13 06:43:02 PM PDT 24
Peak memory 200816 kb
Host smart-e24b33b0-e3cf-4a20-8693-2ecd8fea9578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298422425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.298422425
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.776188446
Short name T157
Test name
Test status
Simulation time 184651050 ps
CPU time 1.28 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200632 kb
Host smart-9a85bd77-f9a3-496d-98bb-80af05b457a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776188446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.776188446
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.37590601
Short name T455
Test name
Test status
Simulation time 228748809 ps
CPU time 1.46 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:21 PM PDT 24
Peak memory 200744 kb
Host smart-f2d9024f-dc55-41c1-b588-a329e025a339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37590601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.37590601
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.862578270
Short name T99
Test name
Test status
Simulation time 6136173092 ps
CPU time 28.25 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 200948 kb
Host smart-cf6381c2-df09-4b08-9d70-03c59b9f476e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862578270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.862578270
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2834850799
Short name T60
Test name
Test status
Simulation time 372650829 ps
CPU time 2.03 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:32 PM PDT 24
Peak memory 200572 kb
Host smart-cd1178c7-4fed-4840-9513-6128b324506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834850799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2834850799
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3911028199
Short name T461
Test name
Test status
Simulation time 104248785 ps
CPU time 0.95 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:24 PM PDT 24
Peak memory 200648 kb
Host smart-76f14a3c-380b-445e-b9a3-8b6e3dc9a5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911028199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3911028199
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2735060020
Short name T406
Test name
Test status
Simulation time 79823721 ps
CPU time 0.79 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200524 kb
Host smart-2983adcb-dc05-4d8c-bbf5-3450d1ebf9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735060020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2735060020
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1341889062
Short name T497
Test name
Test status
Simulation time 1231170497 ps
CPU time 5.76 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 217972 kb
Host smart-c69f0d8d-d497-4e3e-a0f8-0b31b9756c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341889062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1341889062
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3831817484
Short name T280
Test name
Test status
Simulation time 244483256 ps
CPU time 1.05 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 217808 kb
Host smart-152adecc-de67-4280-b8ba-69430942a557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831817484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3831817484
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1842044402
Short name T256
Test name
Test status
Simulation time 94990140 ps
CPU time 0.75 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200488 kb
Host smart-24ca459a-89f5-445d-a641-e4930e169be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842044402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1842044402
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3838912003
Short name T501
Test name
Test status
Simulation time 1323467482 ps
CPU time 5.16 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:21 PM PDT 24
Peak memory 200844 kb
Host smart-07c34cb5-6d24-4d82-905d-b8ea08bfad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838912003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3838912003
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.902744876
Short name T530
Test name
Test status
Simulation time 177483820 ps
CPU time 1.17 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 200672 kb
Host smart-d9db75be-0940-4121-ac81-03a7d201bb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902744876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.902744876
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1855207850
Short name T169
Test name
Test status
Simulation time 194407936 ps
CPU time 1.37 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:43:42 PM PDT 24
Peak memory 200716 kb
Host smart-7c97e27a-5825-4a9b-b8ee-70c80f49d986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855207850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1855207850
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1405995372
Short name T295
Test name
Test status
Simulation time 6470326021 ps
CPU time 25.15 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:34 PM PDT 24
Peak memory 209156 kb
Host smart-bcfcaf28-797a-41aa-a008-8bf6893028de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405995372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1405995372
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2822972317
Short name T367
Test name
Test status
Simulation time 143568604 ps
CPU time 1.84 seconds
Started Aug 13 06:43:22 PM PDT 24
Finished Aug 13 06:43:24 PM PDT 24
Peak memory 200560 kb
Host smart-68537c42-7308-4f92-a72d-05a1eb87bed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822972317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2822972317
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3210315544
Short name T507
Test name
Test status
Simulation time 90453319 ps
CPU time 0.85 seconds
Started Aug 13 06:43:25 PM PDT 24
Finished Aug 13 06:43:26 PM PDT 24
Peak memory 200612 kb
Host smart-f3cdfca4-90b6-400d-bf47-6586a8e55e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210315544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3210315544
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.872077163
Short name T384
Test name
Test status
Simulation time 59368631 ps
CPU time 0.76 seconds
Started Aug 13 06:43:16 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200508 kb
Host smart-68b4c5da-6591-4771-b698-be3d6c3e3f60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872077163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.872077163
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2790751069
Short name T395
Test name
Test status
Simulation time 2170879831 ps
CPU time 8.77 seconds
Started Aug 13 06:43:33 PM PDT 24
Finished Aug 13 06:43:42 PM PDT 24
Peak memory 218116 kb
Host smart-4b2fdae3-8029-4f75-bda8-b62fa414a431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790751069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2790751069
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1921638395
Short name T282
Test name
Test status
Simulation time 244571717 ps
CPU time 1.04 seconds
Started Aug 13 06:43:26 PM PDT 24
Finished Aug 13 06:43:27 PM PDT 24
Peak memory 217840 kb
Host smart-6442404b-833a-4bfc-aa73-cd93c1b39f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921638395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1921638395
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.216176695
Short name T285
Test name
Test status
Simulation time 157832687 ps
CPU time 0.86 seconds
Started Aug 13 06:43:21 PM PDT 24
Finished Aug 13 06:43:22 PM PDT 24
Peak memory 200508 kb
Host smart-fca9c26f-1801-4b94-ab1a-b3e19f8eff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216176695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.216176695
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2497136619
Short name T332
Test name
Test status
Simulation time 1214340177 ps
CPU time 5.37 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:21 PM PDT 24
Peak memory 200832 kb
Host smart-b9ac4864-93df-42d0-b5f5-13e13e526352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497136619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2497136619
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1629497953
Short name T267
Test name
Test status
Simulation time 106832601 ps
CPU time 0.98 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200636 kb
Host smart-2c2dd514-e9ee-45ab-9afc-539c7288055c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629497953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1629497953
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1688720055
Short name T391
Test name
Test status
Simulation time 124441791 ps
CPU time 1.19 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200776 kb
Host smart-4bec9de4-0a72-48d8-829d-73f02b80778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688720055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1688720055
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1103793163
Short name T39
Test name
Test status
Simulation time 5805402339 ps
CPU time 26.71 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:44:07 PM PDT 24
Peak memory 209020 kb
Host smart-273aa2b7-fbc0-48c8-9f4d-80533d501557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103793163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1103793163
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.952858126
Short name T516
Test name
Test status
Simulation time 389832187 ps
CPU time 2.21 seconds
Started Aug 13 06:43:26 PM PDT 24
Finished Aug 13 06:43:28 PM PDT 24
Peak memory 200584 kb
Host smart-f835cd29-ef45-436b-a84c-610582464b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952858126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.952858126
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1434443186
Short name T40
Test name
Test status
Simulation time 146567200 ps
CPU time 1.09 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:31 PM PDT 24
Peak memory 200668 kb
Host smart-7b233008-f662-4365-9625-eb1a62b0f4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434443186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1434443186
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2534801716
Short name T421
Test name
Test status
Simulation time 74190088 ps
CPU time 0.74 seconds
Started Aug 13 06:43:33 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 200536 kb
Host smart-41c88ebb-da0c-4f76-b4de-2ad433413b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534801716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2534801716
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.358125868
Short name T459
Test name
Test status
Simulation time 1211627537 ps
CPU time 6.09 seconds
Started Aug 13 06:43:21 PM PDT 24
Finished Aug 13 06:43:27 PM PDT 24
Peak memory 217600 kb
Host smart-6efa56aa-e4fc-4917-9a5a-039b40562743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358125868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.358125868
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3310205780
Short name T515
Test name
Test status
Simulation time 244028886 ps
CPU time 1.13 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:28 PM PDT 24
Peak memory 217812 kb
Host smart-29fdd31e-e4e6-475f-bf96-205fb3158416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310205780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3310205780
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.1956910501
Short name T287
Test name
Test status
Simulation time 108828005 ps
CPU time 0.78 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:16 PM PDT 24
Peak memory 200444 kb
Host smart-15943e0a-d859-422c-9d0e-38d21f68420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956910501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1956910501
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.381797843
Short name T83
Test name
Test status
Simulation time 1585119886 ps
CPU time 5.77 seconds
Started Aug 13 06:43:31 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200820 kb
Host smart-fb172dca-2a59-4163-80a2-99887996bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381797843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.381797843
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2312612284
Short name T445
Test name
Test status
Simulation time 148910465 ps
CPU time 1.13 seconds
Started Aug 13 06:43:22 PM PDT 24
Finished Aug 13 06:43:23 PM PDT 24
Peak memory 200680 kb
Host smart-a299ceff-62fb-4f9c-8ab9-f66546673b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312612284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2312612284
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2663363488
Short name T360
Test name
Test status
Simulation time 117906195 ps
CPU time 1.1 seconds
Started Aug 13 06:43:26 PM PDT 24
Finished Aug 13 06:43:27 PM PDT 24
Peak memory 200728 kb
Host smart-3d1b9bbb-12c0-4308-9fac-3096cc0072a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663363488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2663363488
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3988932955
Short name T284
Test name
Test status
Simulation time 8258171100 ps
CPU time 26.88 seconds
Started Aug 13 06:43:16 PM PDT 24
Finished Aug 13 06:43:43 PM PDT 24
Peak memory 209060 kb
Host smart-509e22d8-cf35-4c0e-bba1-9dd19542f86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988932955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3988932955
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.471410003
Short name T432
Test name
Test status
Simulation time 310780980 ps
CPU time 2.07 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:20 PM PDT 24
Peak memory 208764 kb
Host smart-e2072f14-5195-4ab0-aa12-6667d6c4b010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471410003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.471410003
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.1867881193
Short name T506
Test name
Test status
Simulation time 171914387 ps
CPU time 1.21 seconds
Started Aug 13 06:43:29 PM PDT 24
Finished Aug 13 06:43:30 PM PDT 24
Peak memory 200620 kb
Host smart-d95ac0f0-827f-4590-a999-df84cea15d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867881193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1867881193
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.850102475
Short name T522
Test name
Test status
Simulation time 74485607 ps
CPU time 0.77 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200444 kb
Host smart-82031f75-44a2-4507-a558-c5dd4c0458d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850102475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.850102475
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2026205421
Short name T193
Test name
Test status
Simulation time 247499893 ps
CPU time 1.02 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:31 PM PDT 24
Peak memory 217832 kb
Host smart-02a28b80-d29b-4fee-b592-a54bafc5092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026205421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2026205421
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2034888735
Short name T197
Test name
Test status
Simulation time 95958184 ps
CPU time 0.78 seconds
Started Aug 13 06:43:22 PM PDT 24
Finished Aug 13 06:43:23 PM PDT 24
Peak memory 200484 kb
Host smart-8b7b0f2d-14c4-48fd-b914-f14a18f0c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034888735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2034888735
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2494849802
Short name T163
Test name
Test status
Simulation time 663333715 ps
CPU time 3.6 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 200844 kb
Host smart-1671e629-dd63-4963-8757-18aa190ef73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494849802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2494849802
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1311130615
Short name T534
Test name
Test status
Simulation time 162568877 ps
CPU time 1.15 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:18 PM PDT 24
Peak memory 200632 kb
Host smart-340cf579-2014-47be-b0c9-b651afa9e728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311130615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1311130615
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1343880314
Short name T296
Test name
Test status
Simulation time 223954008 ps
CPU time 1.4 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200784 kb
Host smart-c5f3109d-326b-47f7-9518-fd67d82ba479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343880314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1343880314
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3514249917
Short name T509
Test name
Test status
Simulation time 3287841472 ps
CPU time 15.03 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:54 PM PDT 24
Peak memory 200844 kb
Host smart-94ced788-02d4-42b4-8ab8-eb3dbb5b5a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514249917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3514249917
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.4189402070
Short name T452
Test name
Test status
Simulation time 373201770 ps
CPU time 2.28 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200572 kb
Host smart-09054cc8-0ed0-47b4-be1f-524f11174fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189402070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4189402070
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3331631279
Short name T189
Test name
Test status
Simulation time 133328031 ps
CPU time 1.13 seconds
Started Aug 13 06:43:22 PM PDT 24
Finished Aug 13 06:43:23 PM PDT 24
Peak memory 200624 kb
Host smart-0374448c-1b33-432c-9889-7bd401415e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331631279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3331631279
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.932946656
Short name T277
Test name
Test status
Simulation time 76114361 ps
CPU time 0.81 seconds
Started Aug 13 06:43:24 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200544 kb
Host smart-4db33a64-5ca5-4f3e-a1db-214d7c1d8018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932946656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.932946656
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.4088838036
Short name T33
Test name
Test status
Simulation time 1893926472 ps
CPU time 6.9 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:35 PM PDT 24
Peak memory 221924 kb
Host smart-12bb429b-56c4-463f-a684-cb5dff51a151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088838036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.4088838036
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3642372097
Short name T184
Test name
Test status
Simulation time 244030974 ps
CPU time 1.08 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:28 PM PDT 24
Peak memory 217820 kb
Host smart-a0c465e5-0af9-442d-a613-df906018893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642372097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3642372097
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1547125925
Short name T15
Test name
Test status
Simulation time 110372973 ps
CPU time 0.79 seconds
Started Aug 13 06:43:24 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200440 kb
Host smart-cc92b0e2-42dc-4916-8e96-9bd372a35f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547125925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1547125925
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2824624620
Short name T100
Test name
Test status
Simulation time 915213415 ps
CPU time 4.56 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:43 PM PDT 24
Peak memory 200760 kb
Host smart-9de30535-8a39-4acc-8e6b-bc5c40150c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824624620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2824624620
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.870665775
Short name T440
Test name
Test status
Simulation time 190272787 ps
CPU time 1.24 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200672 kb
Host smart-11c81f24-182a-421a-98c4-ccf77778f979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870665775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.870665775
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2338910926
Short name T348
Test name
Test status
Simulation time 125273420 ps
CPU time 1.2 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200832 kb
Host smart-a9d0a6a2-c51f-4796-8dd3-5caf4b2d3d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338910926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2338910926
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.387393100
Short name T320
Test name
Test status
Simulation time 3308635282 ps
CPU time 12.46 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:48 PM PDT 24
Peak memory 200944 kb
Host smart-e043c85e-b64b-4409-b4f6-41a7f9ee13fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387393100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.387393100
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1651622659
Short name T300
Test name
Test status
Simulation time 105489347 ps
CPU time 1.45 seconds
Started Aug 13 06:43:24 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200576 kb
Host smart-052241c0-69d5-464f-9226-4c468ef70cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651622659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1651622659
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.2847043983
Short name T138
Test name
Test status
Simulation time 99908753 ps
CPU time 0.87 seconds
Started Aug 13 06:43:29 PM PDT 24
Finished Aug 13 06:43:30 PM PDT 24
Peak memory 200680 kb
Host smart-98a5b30b-fa26-4c8f-90b7-e08bb1b942f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847043983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.2847043983
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.212696738
Short name T289
Test name
Test status
Simulation time 1892469847 ps
CPU time 7.53 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:44 PM PDT 24
Peak memory 218064 kb
Host smart-9a9f751d-4ad5-47c7-8008-329f620ffcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212696738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.212696738
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1735281723
Short name T442
Test name
Test status
Simulation time 244039155 ps
CPU time 1.2 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:36 PM PDT 24
Peak memory 217884 kb
Host smart-6d7097f5-76b8-4a0d-b0c2-a75ac10416f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735281723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1735281723
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.2197829882
Short name T20
Test name
Test status
Simulation time 126732030 ps
CPU time 0.79 seconds
Started Aug 13 06:43:31 PM PDT 24
Finished Aug 13 06:43:32 PM PDT 24
Peak memory 200456 kb
Host smart-f1d03471-74e3-43ad-acb4-327e6c0850aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197829882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2197829882
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.4176650783
Short name T399
Test name
Test status
Simulation time 1092196588 ps
CPU time 5.32 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:33 PM PDT 24
Peak memory 200792 kb
Host smart-2281b6b3-7073-4023-add5-9b6917be0f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176650783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4176650783
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3922541461
Short name T2
Test name
Test status
Simulation time 152698295 ps
CPU time 1.1 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:31 PM PDT 24
Peak memory 200692 kb
Host smart-08c4e385-5445-45ac-bfb3-231ccdea69aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922541461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3922541461
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3565088152
Short name T448
Test name
Test status
Simulation time 198333281 ps
CPU time 1.41 seconds
Started Aug 13 06:43:32 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 200768 kb
Host smart-ceccd276-d36d-4645-9f4f-f2ee9958efd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565088152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3565088152
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2076946151
Short name T427
Test name
Test status
Simulation time 278412145 ps
CPU time 1.79 seconds
Started Aug 13 06:43:25 PM PDT 24
Finished Aug 13 06:43:27 PM PDT 24
Peak memory 200588 kb
Host smart-a20a63be-7d56-4c1c-aa5e-0d9a9e95b35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076946151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2076946151
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.186000224
Short name T122
Test name
Test status
Simulation time 112369133 ps
CPU time 0.91 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:31 PM PDT 24
Peak memory 200688 kb
Host smart-6e306996-3bb3-469f-8e64-d4a4a076bb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186000224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.186000224
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.780745848
Short name T188
Test name
Test status
Simulation time 88453926 ps
CPU time 0.84 seconds
Started Aug 13 06:43:59 PM PDT 24
Finished Aug 13 06:44:00 PM PDT 24
Peak memory 200548 kb
Host smart-cf83ca48-29cd-4078-a80e-20afef82cc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780745848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.780745848
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.636761344
Short name T425
Test name
Test status
Simulation time 1231167701 ps
CPU time 5.49 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:43:54 PM PDT 24
Peak memory 221940 kb
Host smart-c295987d-7a81-422e-83b6-77c26fdf1e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636761344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.636761344
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.4205048340
Short name T202
Test name
Test status
Simulation time 250497202 ps
CPU time 1.03 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 217896 kb
Host smart-875d82fe-6974-437c-9779-177f486aaad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205048340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.4205048340
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1528916206
Short name T175
Test name
Test status
Simulation time 87870724 ps
CPU time 0.71 seconds
Started Aug 13 06:43:35 PM PDT 24
Finished Aug 13 06:43:36 PM PDT 24
Peak memory 200500 kb
Host smart-827caf0a-ff77-45ac-8c82-1ad83e09c90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528916206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1528916206
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1231936830
Short name T227
Test name
Test status
Simulation time 1780081822 ps
CPU time 6.24 seconds
Started Aug 13 06:43:46 PM PDT 24
Finished Aug 13 06:43:52 PM PDT 24
Peak memory 200800 kb
Host smart-02b92434-45da-4e47-91c3-0ab4feed393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231936830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1231936830
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.696612046
Short name T201
Test name
Test status
Simulation time 94114132 ps
CPU time 0.98 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200612 kb
Host smart-6a28149f-4326-4071-93cf-8ebda10036f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696612046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.696612046
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.4076946109
Short name T158
Test name
Test status
Simulation time 113199102 ps
CPU time 1.19 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 200724 kb
Host smart-9c3351a0-0ceb-49c7-9a2a-147ee42dd1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076946109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.4076946109
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.2834294904
Short name T483
Test name
Test status
Simulation time 8457398051 ps
CPU time 27.83 seconds
Started Aug 13 06:43:45 PM PDT 24
Finished Aug 13 06:44:13 PM PDT 24
Peak memory 209040 kb
Host smart-aab15199-ba5f-4cfb-8b31-b0d992f8da28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834294904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2834294904
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3335586567
Short name T460
Test name
Test status
Simulation time 159999756 ps
CPU time 1.9 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200564 kb
Host smart-e6326cd1-67c3-42c1-a80e-b1e1edb3933b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335586567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3335586567
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3610897529
Short name T414
Test name
Test status
Simulation time 178284298 ps
CPU time 1.29 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:43:42 PM PDT 24
Peak memory 200784 kb
Host smart-d6e2079d-961e-47ab-a04d-5e248187c07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610897529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3610897529
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4188511002
Short name T195
Test name
Test status
Simulation time 57946172 ps
CPU time 0.74 seconds
Started Aug 13 06:43:49 PM PDT 24
Finished Aug 13 06:43:49 PM PDT 24
Peak memory 200540 kb
Host smart-a554b689-da0d-4ed9-a865-812857034fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188511002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4188511002
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1877516300
Short name T34
Test name
Test status
Simulation time 2171597078 ps
CPU time 7.57 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 221944 kb
Host smart-40f2e223-b690-44bc-83cf-f7840779a739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877516300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1877516300
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2688972932
Short name T85
Test name
Test status
Simulation time 243868356 ps
CPU time 1.13 seconds
Started Aug 13 06:43:42 PM PDT 24
Finished Aug 13 06:43:43 PM PDT 24
Peak memory 217788 kb
Host smart-e537ef16-76cc-4ebd-94ad-d0a4a904c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688972932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2688972932
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3800300241
Short name T372
Test name
Test status
Simulation time 148564763 ps
CPU time 0.82 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:43:49 PM PDT 24
Peak memory 200480 kb
Host smart-7d3ee49c-11af-401c-8f89-e74c8354d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800300241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3800300241
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2915290079
Short name T484
Test name
Test status
Simulation time 1678671218 ps
CPU time 5.81 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:43:46 PM PDT 24
Peak memory 200876 kb
Host smart-0fc3cdf4-f600-4c9a-a74e-d15e532e374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915290079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2915290079
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3895153783
Short name T473
Test name
Test status
Simulation time 187191556 ps
CPU time 1.24 seconds
Started Aug 13 06:43:35 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200680 kb
Host smart-463ba1af-bd8b-4b05-94d8-52b47267e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895153783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3895153783
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2346509098
Short name T159
Test name
Test status
Simulation time 128441799 ps
CPU time 1.19 seconds
Started Aug 13 06:43:42 PM PDT 24
Finished Aug 13 06:43:43 PM PDT 24
Peak memory 200724 kb
Host smart-ec882bec-8d15-4c6d-8ff6-0f7c91338556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346509098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2346509098
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1923448639
Short name T478
Test name
Test status
Simulation time 7111122301 ps
CPU time 24.91 seconds
Started Aug 13 06:43:43 PM PDT 24
Finished Aug 13 06:44:08 PM PDT 24
Peak memory 200840 kb
Host smart-69940a80-4aa8-4df7-a67e-5cf633fa39ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923448639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1923448639
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.3222007771
Short name T366
Test name
Test status
Simulation time 125333345 ps
CPU time 1.46 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200568 kb
Host smart-cf020207-785a-4e9e-9461-5823dec4dd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222007771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3222007771
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.546846573
Short name T136
Test name
Test status
Simulation time 165397135 ps
CPU time 1.14 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 200676 kb
Host smart-9c61323f-3179-41aa-90d5-982ac55b7ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546846573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.546846573
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2888254006
Short name T185
Test name
Test status
Simulation time 60248735 ps
CPU time 0.74 seconds
Started Aug 13 06:43:35 PM PDT 24
Finished Aug 13 06:43:36 PM PDT 24
Peak memory 200532 kb
Host smart-50ec98f4-a67b-4ddf-a39a-208d248beb1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888254006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2888254006
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2451356833
Short name T305
Test name
Test status
Simulation time 2345641897 ps
CPU time 8.4 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 218052 kb
Host smart-f707f461-4ea7-4628-beba-1e054d828fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451356833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2451356833
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2895802915
Short name T308
Test name
Test status
Simulation time 244700925 ps
CPU time 1.04 seconds
Started Aug 13 06:43:32 PM PDT 24
Finished Aug 13 06:43:33 PM PDT 24
Peak memory 217864 kb
Host smart-5a580f07-03a5-4507-bc6a-ed32ac93cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895802915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2895802915
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.913383574
Short name T476
Test name
Test status
Simulation time 160869732 ps
CPU time 0.87 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200416 kb
Host smart-49df0326-bfce-4432-9df7-d1e7323d9197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913383574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.913383574
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.178980143
Short name T97
Test name
Test status
Simulation time 1624117379 ps
CPU time 6.65 seconds
Started Aug 13 06:43:45 PM PDT 24
Finished Aug 13 06:43:52 PM PDT 24
Peak memory 200780 kb
Host smart-35fff678-f9f9-4f48-8a9d-90103735f022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178980143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.178980143
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.166007399
Short name T418
Test name
Test status
Simulation time 102320702 ps
CPU time 0.99 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:35 PM PDT 24
Peak memory 200692 kb
Host smart-e8799ee2-3a6b-4de8-bf0a-b7271cbdb87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166007399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.166007399
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2389748116
Short name T204
Test name
Test status
Simulation time 115569024 ps
CPU time 1.27 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 200724 kb
Host smart-70546946-2d4c-4166-b7c7-5d7ee920e258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389748116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2389748116
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.716290926
Short name T187
Test name
Test status
Simulation time 5014146121 ps
CPU time 20.68 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:58 PM PDT 24
Peak memory 200840 kb
Host smart-dd62b956-0c02-4def-b2e4-898cfb480899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716290926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.716290926
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1823826606
Short name T172
Test name
Test status
Simulation time 119164554 ps
CPU time 1.48 seconds
Started Aug 13 06:43:35 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200588 kb
Host smart-007d0bb4-feea-423f-8180-f072770cefe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823826606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1823826606
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1722379041
Short name T80
Test name
Test status
Simulation time 92579814 ps
CPU time 0.93 seconds
Started Aug 13 06:43:47 PM PDT 24
Finished Aug 13 06:43:48 PM PDT 24
Peak memory 200640 kb
Host smart-5dbdb6c9-caa3-4242-8db0-4701cd6245ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722379041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1722379041
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3802463798
Short name T72
Test name
Test status
Simulation time 52656171 ps
CPU time 0.7 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:52 PM PDT 24
Peak memory 200500 kb
Host smart-6ecca139-10e4-4ef5-9cb5-0e8695d6b1d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802463798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3802463798
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3140183190
Short name T275
Test name
Test status
Simulation time 1899970432 ps
CPU time 7.25 seconds
Started Aug 13 06:42:52 PM PDT 24
Finished Aug 13 06:43:00 PM PDT 24
Peak memory 217808 kb
Host smart-4a602ef2-44c0-4af0-83c8-2b2c0b0b7550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140183190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3140183190
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1607283007
Short name T259
Test name
Test status
Simulation time 244319140 ps
CPU time 1.03 seconds
Started Aug 13 06:43:05 PM PDT 24
Finished Aug 13 06:43:06 PM PDT 24
Peak memory 217864 kb
Host smart-a8bb5b3b-f97b-4d77-8b5c-2234c8f90b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607283007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1607283007
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.54706784
Short name T19
Test name
Test status
Simulation time 110452125 ps
CPU time 0.78 seconds
Started Aug 13 06:42:49 PM PDT 24
Finished Aug 13 06:42:50 PM PDT 24
Peak memory 200476 kb
Host smart-c4510e3b-0500-46d9-829e-26fe035b97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54706784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.54706784
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3977277792
Short name T54
Test name
Test status
Simulation time 1018657398 ps
CPU time 4.7 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:20 PM PDT 24
Peak memory 200856 kb
Host smart-dec731ea-9273-4488-8e97-4d522596e05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977277792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3977277792
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2088009091
Short name T75
Test name
Test status
Simulation time 8292381375 ps
CPU time 13.8 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:44 PM PDT 24
Peak memory 217192 kb
Host smart-c39a989b-b9b7-4029-bdce-c03474a6d8bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088009091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2088009091
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1036743485
Short name T214
Test name
Test status
Simulation time 106164287 ps
CPU time 1.02 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200688 kb
Host smart-49fd196d-d4ad-4ff8-8a77-a768975edfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036743485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1036743485
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2432699141
Short name T81
Test name
Test status
Simulation time 197605965 ps
CPU time 1.34 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 200716 kb
Host smart-0be0fdb6-a68e-4b0c-9053-133236bc7c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432699141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2432699141
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2368763363
Short name T329
Test name
Test status
Simulation time 4329186240 ps
CPU time 18.89 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200836 kb
Host smart-202defef-96f6-4cc4-a6f9-e2ac73c20585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368763363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2368763363
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1583199260
Short name T482
Test name
Test status
Simulation time 244452088 ps
CPU time 1.7 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 200560 kb
Host smart-7827a0eb-b4e4-4fc2-b8a6-aed39d1ce255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583199260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1583199260
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.4035293206
Short name T133
Test name
Test status
Simulation time 146153796 ps
CPU time 1.13 seconds
Started Aug 13 06:42:52 PM PDT 24
Finished Aug 13 06:42:53 PM PDT 24
Peak memory 200672 kb
Host smart-f7969366-5d1b-4a11-ae8f-478ee3015704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035293206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.4035293206
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3963095635
Short name T532
Test name
Test status
Simulation time 70325665 ps
CPU time 0.81 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 200444 kb
Host smart-c77d38d2-1b14-424d-8b61-79857f400b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963095635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3963095635
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.51887537
Short name T353
Test name
Test status
Simulation time 1231334423 ps
CPU time 5.66 seconds
Started Aug 13 06:43:31 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 217996 kb
Host smart-0bca4e6c-0f54-4659-a74b-614edbe5020f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51887537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.51887537
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2520271772
Short name T379
Test name
Test status
Simulation time 244078164 ps
CPU time 1.12 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:43:50 PM PDT 24
Peak memory 217836 kb
Host smart-ab8c297d-5931-4dee-9454-b85de119e227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520271772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2520271772
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.3292081351
Short name T393
Test name
Test status
Simulation time 174038017 ps
CPU time 0.9 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 200324 kb
Host smart-8d471db9-56d0-41f9-bbfc-d53d82dc3dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292081351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3292081351
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.145318863
Short name T434
Test name
Test status
Simulation time 835585433 ps
CPU time 4.18 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:43:52 PM PDT 24
Peak memory 200800 kb
Host smart-e3c9a301-a8ba-4b44-9632-69fc33d7d43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145318863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.145318863
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1418486432
Short name T14
Test name
Test status
Simulation time 92290541 ps
CPU time 0.99 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 200608 kb
Host smart-b0cc6ae0-3397-4847-aa19-a69e5cc165ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418486432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1418486432
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4084123728
Short name T323
Test name
Test status
Simulation time 115204092 ps
CPU time 1.13 seconds
Started Aug 13 06:43:35 PM PDT 24
Finished Aug 13 06:43:36 PM PDT 24
Peak memory 200788 kb
Host smart-7631146c-5cea-49f7-9fc2-d20a29278dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084123728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4084123728
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1052528670
Short name T218
Test name
Test status
Simulation time 9721562562 ps
CPU time 33.97 seconds
Started Aug 13 06:43:33 PM PDT 24
Finished Aug 13 06:44:07 PM PDT 24
Peak memory 200888 kb
Host smart-9c0a1a1a-7e9a-453e-ba82-86cb0536105e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052528670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1052528670
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.476641968
Short name T306
Test name
Test status
Simulation time 491538821 ps
CPU time 2.65 seconds
Started Aug 13 06:44:00 PM PDT 24
Finished Aug 13 06:44:03 PM PDT 24
Peak memory 200520 kb
Host smart-a7f8b0f7-fa97-46cd-88f4-69fc9d7f01f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476641968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.476641968
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3778374850
Short name T38
Test name
Test status
Simulation time 78985144 ps
CPU time 0.83 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200648 kb
Host smart-21bc5fad-ebcf-48ff-801d-e3af27f00e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778374850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3778374850
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.726976568
Short name T263
Test name
Test status
Simulation time 86781758 ps
CPU time 0.79 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200484 kb
Host smart-7ba28a55-812e-4ec4-8c20-23625d0b382d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726976568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.726976568
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.51505044
Short name T493
Test name
Test status
Simulation time 1888756284 ps
CPU time 7.27 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:44 PM PDT 24
Peak memory 217908 kb
Host smart-cc22d479-deab-4619-8659-b15de18e1ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51505044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.51505044
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.4033468270
Short name T244
Test name
Test status
Simulation time 245648697 ps
CPU time 1.06 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:43:49 PM PDT 24
Peak memory 217752 kb
Host smart-e7c8fa04-94ea-4e8e-9378-e2d7a808e5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033468270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.4033468270
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.161996245
Short name T11
Test name
Test status
Simulation time 114574662 ps
CPU time 0.81 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 200452 kb
Host smart-4dd37a52-c666-4198-8ca3-ccb2729d33fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161996245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.161996245
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.721012428
Short name T176
Test name
Test status
Simulation time 950987131 ps
CPU time 4.67 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:43:44 PM PDT 24
Peak memory 200800 kb
Host smart-0b416328-3cd7-423a-8cc8-c4ee2ae31c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721012428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.721012428
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2580322422
Short name T485
Test name
Test status
Simulation time 110855368 ps
CPU time 1.02 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:35 PM PDT 24
Peak memory 200688 kb
Host smart-1565b2f5-e12c-418a-8238-9986ac1879b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580322422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2580322422
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.4237155673
Short name T198
Test name
Test status
Simulation time 203248597 ps
CPU time 1.46 seconds
Started Aug 13 06:43:50 PM PDT 24
Finished Aug 13 06:43:51 PM PDT 24
Peak memory 200780 kb
Host smart-3e600d97-d29f-45a0-9000-93ab883f917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237155673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.4237155673
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2959656424
Short name T347
Test name
Test status
Simulation time 490249315 ps
CPU time 2.53 seconds
Started Aug 13 06:43:35 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 208976 kb
Host smart-93e82d85-89bb-481c-9cd7-f34d1d555116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959656424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2959656424
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.162942897
Short name T517
Test name
Test status
Simulation time 376867411 ps
CPU time 2.19 seconds
Started Aug 13 06:43:46 PM PDT 24
Finished Aug 13 06:43:48 PM PDT 24
Peak memory 200528 kb
Host smart-0ba54322-dcec-40d0-84da-727f4cc3012a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162942897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.162942897
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2846861132
Short name T137
Test name
Test status
Simulation time 123440189 ps
CPU time 1.14 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200608 kb
Host smart-43ed5d9d-6911-45b3-b194-dc710176c0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846861132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2846861132
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2535326555
Short name T407
Test name
Test status
Simulation time 86357867 ps
CPU time 0.86 seconds
Started Aug 13 06:43:52 PM PDT 24
Finished Aug 13 06:43:53 PM PDT 24
Peak memory 200556 kb
Host smart-cc49818e-c260-4cfb-a135-2e1add5ca007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535326555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2535326555
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3509224986
Short name T32
Test name
Test status
Simulation time 1213208085 ps
CPU time 5.46 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 217988 kb
Host smart-7f814ce2-aee8-4418-a259-8e1b2687832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509224986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3509224986
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3361823844
Short name T240
Test name
Test status
Simulation time 244069108 ps
CPU time 1.07 seconds
Started Aug 13 06:43:33 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 217812 kb
Host smart-66aae440-cf80-49cb-b4bf-390aac6969db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361823844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3361823844
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.780047387
Short name T430
Test name
Test status
Simulation time 181749620 ps
CPU time 0.82 seconds
Started Aug 13 06:43:41 PM PDT 24
Finished Aug 13 06:43:42 PM PDT 24
Peak memory 200500 kb
Host smart-2f064414-d166-4cb4-9514-3b836307965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780047387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.780047387
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1497677628
Short name T225
Test name
Test status
Simulation time 1232408042 ps
CPU time 4.71 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:43:58 PM PDT 24
Peak memory 200840 kb
Host smart-9d447d0f-b4b5-4b58-be9e-b33184a3e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497677628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1497677628
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1120712096
Short name T238
Test name
Test status
Simulation time 98790054 ps
CPU time 1 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 200692 kb
Host smart-7e6dd964-f4d2-469a-9fb7-673fe028e197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120712096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1120712096
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2527450622
Short name T388
Test name
Test status
Simulation time 192578563 ps
CPU time 1.38 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 200776 kb
Host smart-94446a08-723f-4db8-95d7-fd13e53dd634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527450622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2527450622
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2336219211
Short name T464
Test name
Test status
Simulation time 4560064151 ps
CPU time 20.29 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:59 PM PDT 24
Peak memory 209136 kb
Host smart-1fac59d1-364e-42ed-9659-d0271f797703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336219211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2336219211
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3939586242
Short name T356
Test name
Test status
Simulation time 143660463 ps
CPU time 1.84 seconds
Started Aug 13 06:43:43 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 200508 kb
Host smart-85c47f43-5c11-4e17-b74b-46bc93b2861d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939586242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3939586242
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3391195973
Short name T121
Test name
Test status
Simulation time 291233595 ps
CPU time 1.44 seconds
Started Aug 13 06:43:41 PM PDT 24
Finished Aug 13 06:43:42 PM PDT 24
Peak memory 200748 kb
Host smart-a7197c06-cab4-4af7-9f4a-de9197bdd076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391195973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3391195973
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1285689687
Short name T73
Test name
Test status
Simulation time 62231500 ps
CPU time 0.72 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 200544 kb
Host smart-97663000-ec68-4c60-9d07-1badca9382cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285689687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1285689687
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2838277156
Short name T359
Test name
Test status
Simulation time 1905994492 ps
CPU time 7.87 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:12 PM PDT 24
Peak memory 217972 kb
Host smart-d0d60dbe-545a-4bd2-a094-aaf682df0e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838277156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2838277156
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2056272538
Short name T416
Test name
Test status
Simulation time 244458924 ps
CPU time 1.08 seconds
Started Aug 13 06:44:15 PM PDT 24
Finished Aug 13 06:44:16 PM PDT 24
Peak memory 217812 kb
Host smart-c70f7a23-d304-4760-b60b-e6c9e2d608ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056272538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2056272538
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.311425463
Short name T17
Test name
Test status
Simulation time 149696821 ps
CPU time 0.87 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 200364 kb
Host smart-00ccaf3b-8d91-4a08-8173-d863ac5acfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311425463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.311425463
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3686603081
Short name T413
Test name
Test status
Simulation time 1677826662 ps
CPU time 6.37 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:44 PM PDT 24
Peak memory 200804 kb
Host smart-3abfe454-82b9-4afb-81ac-d7c0a395b30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686603081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3686603081
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2996145068
Short name T151
Test name
Test status
Simulation time 97657287 ps
CPU time 0.93 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 200584 kb
Host smart-e72ccfdd-1ac7-4c9c-9495-01541e160336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996145068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2996145068
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.733471078
Short name T468
Test name
Test status
Simulation time 194165690 ps
CPU time 1.44 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 200780 kb
Host smart-8dc81ddd-1304-4ab8-849a-733b169519a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733471078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.733471078
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.250151882
Short name T257
Test name
Test status
Simulation time 10884943742 ps
CPU time 41.78 seconds
Started Aug 13 06:44:01 PM PDT 24
Finished Aug 13 06:44:43 PM PDT 24
Peak memory 200872 kb
Host smart-c408ce81-2690-4ed7-8654-0adb52d9b36e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250151882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.250151882
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.4030469699
Short name T255
Test name
Test status
Simulation time 130997751 ps
CPU time 1.71 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 200556 kb
Host smart-4296861d-5896-4991-ad5e-2fff1816f372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030469699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.4030469699
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3397756265
Short name T486
Test name
Test status
Simulation time 145067453 ps
CPU time 1.08 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 200680 kb
Host smart-079f9ee3-ab79-41fd-bda6-d4fad9f1aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397756265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3397756265
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.424003215
Short name T456
Test name
Test status
Simulation time 59653740 ps
CPU time 0.74 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 200532 kb
Host smart-189d8410-b242-4868-ae4b-62f542900848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424003215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.424003215
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.977556946
Short name T324
Test name
Test status
Simulation time 1225661737 ps
CPU time 5.41 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:50 PM PDT 24
Peak memory 217672 kb
Host smart-c7c8fca9-70cd-4908-9d37-e869890908fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977556946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.977556946
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2578871120
Short name T526
Test name
Test status
Simulation time 244199527 ps
CPU time 1.09 seconds
Started Aug 13 06:43:31 PM PDT 24
Finished Aug 13 06:43:32 PM PDT 24
Peak memory 217836 kb
Host smart-3969881d-938a-4eca-8211-1f0d357ddfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578871120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2578871120
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.660966191
Short name T512
Test name
Test status
Simulation time 95612080 ps
CPU time 0.74 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 200480 kb
Host smart-3433acc6-68dc-458e-9480-9d32457d38d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660966191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.660966191
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2923263351
Short name T330
Test name
Test status
Simulation time 1656122895 ps
CPU time 6.18 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:46 PM PDT 24
Peak memory 200848 kb
Host smart-5cf0e7b0-f5c4-49b1-b17a-6ab5a777afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923263351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2923263351
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1354328554
Short name T199
Test name
Test status
Simulation time 102283423 ps
CPU time 0.98 seconds
Started Aug 13 06:43:54 PM PDT 24
Finished Aug 13 06:43:55 PM PDT 24
Peak memory 200660 kb
Host smart-807777be-31c0-4996-b977-d3ba8e432aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354328554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1354328554
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1797288771
Short name T498
Test name
Test status
Simulation time 122483211 ps
CPU time 1.17 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 200760 kb
Host smart-2d88a528-6e98-4331-b097-d85b8b5ddc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797288771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1797288771
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2820499502
Short name T363
Test name
Test status
Simulation time 1739929567 ps
CPU time 7.8 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:44 PM PDT 24
Peak memory 200872 kb
Host smart-9c45a797-1ec8-42f2-9715-d22336e8a79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820499502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2820499502
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.980721891
Short name T146
Test name
Test status
Simulation time 282282926 ps
CPU time 1.83 seconds
Started Aug 13 06:43:45 PM PDT 24
Finished Aug 13 06:43:47 PM PDT 24
Peak memory 200564 kb
Host smart-fa6aadc0-6f6c-44e3-b846-52c3ab7b423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980721891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.980721891
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.2440060802
Short name T231
Test name
Test status
Simulation time 158000303 ps
CPU time 1.19 seconds
Started Aug 13 06:43:33 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 200764 kb
Host smart-3a375035-1b39-4ea9-906d-45e0e55ebadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440060802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2440060802
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1603571845
Short name T364
Test name
Test status
Simulation time 69194767 ps
CPU time 0.8 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200512 kb
Host smart-f32da802-e210-4f8e-bd5c-d048f4cff396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603571845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1603571845
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1574217375
Short name T439
Test name
Test status
Simulation time 2359837309 ps
CPU time 8.63 seconds
Started Aug 13 06:43:51 PM PDT 24
Finished Aug 13 06:44:00 PM PDT 24
Peak memory 218136 kb
Host smart-2d778230-de4e-44df-b1d1-ee1963fd5283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574217375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1574217375
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2055858147
Short name T334
Test name
Test status
Simulation time 244815588 ps
CPU time 1.02 seconds
Started Aug 13 06:43:32 PM PDT 24
Finished Aug 13 06:43:33 PM PDT 24
Peak memory 217812 kb
Host smart-7b8013e9-efaa-4c3f-8cf3-8e18fb61d3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055858147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2055858147
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.698221418
Short name T342
Test name
Test status
Simulation time 117656496 ps
CPU time 0.86 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:29 PM PDT 24
Peak memory 200488 kb
Host smart-cc096639-c02f-4621-99b8-56437caf9298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698221418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.698221418
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1385660928
Short name T281
Test name
Test status
Simulation time 1130964220 ps
CPU time 5.09 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:43 PM PDT 24
Peak memory 200880 kb
Host smart-a461d3e5-863f-4561-89f3-3f36445d497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385660928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1385660928
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2152843997
Short name T262
Test name
Test status
Simulation time 184939256 ps
CPU time 1.15 seconds
Started Aug 13 06:43:35 PM PDT 24
Finished Aug 13 06:43:36 PM PDT 24
Peak memory 200676 kb
Host smart-5f6ee3fc-d88c-4734-80cc-197706baa3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152843997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2152843997
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.2151023372
Short name T453
Test name
Test status
Simulation time 192189675 ps
CPU time 1.35 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:43:49 PM PDT 24
Peak memory 200824 kb
Host smart-b5b11a5f-2087-4181-8492-7c40699e5bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151023372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2151023372
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2547946631
Short name T237
Test name
Test status
Simulation time 1617469873 ps
CPU time 6.48 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:50 PM PDT 24
Peak memory 200840 kb
Host smart-34ac6d39-c06a-400d-904c-9a76d8a457eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547946631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2547946631
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2011983807
Short name T371
Test name
Test status
Simulation time 313782404 ps
CPU time 2.08 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:31 PM PDT 24
Peak memory 200576 kb
Host smart-609b62b7-44d5-42c0-9bf4-bd73d27287f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011983807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2011983807
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3449657568
Short name T492
Test name
Test status
Simulation time 239109826 ps
CPU time 1.35 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:46 PM PDT 24
Peak memory 200648 kb
Host smart-796dfab3-2226-433a-aba3-9f3bb640ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449657568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3449657568
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.209179122
Short name T9
Test name
Test status
Simulation time 58945612 ps
CPU time 0.73 seconds
Started Aug 13 06:43:45 PM PDT 24
Finished Aug 13 06:43:46 PM PDT 24
Peak memory 200532 kb
Host smart-b54c946b-c1c8-4c8a-87b0-cdfbd1cbcdc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209179122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.209179122
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.556190614
Short name T525
Test name
Test status
Simulation time 2349047051 ps
CPU time 8.18 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:53 PM PDT 24
Peak memory 221992 kb
Host smart-cf5f8fa1-c3f2-45c9-bb53-472f08c8ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556190614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.556190614
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2423545405
Short name T343
Test name
Test status
Simulation time 246036598 ps
CPU time 1.05 seconds
Started Aug 13 06:43:45 PM PDT 24
Finished Aug 13 06:43:47 PM PDT 24
Peak memory 217808 kb
Host smart-915499a9-2eda-48f5-98ea-1e2f9f0af7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423545405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2423545405
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.537980512
Short name T16
Test name
Test status
Simulation time 195740323 ps
CPU time 0.88 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200444 kb
Host smart-25fde030-f6b0-4b6e-a52f-19241ab3975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537980512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.537980512
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4185737260
Short name T269
Test name
Test status
Simulation time 1786388031 ps
CPU time 6.15 seconds
Started Aug 13 06:43:49 PM PDT 24
Finished Aug 13 06:43:55 PM PDT 24
Peak memory 200844 kb
Host smart-61410372-4c3b-4907-b444-762d4f090118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185737260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4185737260
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2864470702
Short name T307
Test name
Test status
Simulation time 108405643 ps
CPU time 1 seconds
Started Aug 13 06:44:06 PM PDT 24
Finished Aug 13 06:44:07 PM PDT 24
Peak memory 200672 kb
Host smart-89274ced-d990-42d9-a2a2-045b1f7a1c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864470702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2864470702
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2329917150
Short name T211
Test name
Test status
Simulation time 124703464 ps
CPU time 1.17 seconds
Started Aug 13 06:43:33 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 200768 kb
Host smart-8e067ec1-df8a-4e90-8e39-7c6c241197c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329917150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2329917150
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4034007439
Short name T477
Test name
Test status
Simulation time 408663655 ps
CPU time 2.37 seconds
Started Aug 13 06:43:59 PM PDT 24
Finished Aug 13 06:44:02 PM PDT 24
Peak memory 200556 kb
Host smart-c50f1983-cdbd-47c7-98c7-4ba98d7762f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034007439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4034007439
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1343985981
Short name T443
Test name
Test status
Simulation time 75188591 ps
CPU time 0.82 seconds
Started Aug 13 06:43:47 PM PDT 24
Finished Aug 13 06:43:48 PM PDT 24
Peak memory 200668 kb
Host smart-dc129828-4d34-4a6d-b8e6-e56ee6d5991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343985981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1343985981
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3718505168
Short name T438
Test name
Test status
Simulation time 76272018 ps
CPU time 0.84 seconds
Started Aug 13 06:43:43 PM PDT 24
Finished Aug 13 06:43:44 PM PDT 24
Peak memory 200536 kb
Host smart-eaabb81c-c7ce-4680-9085-458de1e05d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718505168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3718505168
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1047831011
Short name T491
Test name
Test status
Simulation time 1227715327 ps
CPU time 5.31 seconds
Started Aug 13 06:43:32 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 221992 kb
Host smart-dfe4f918-651e-47e2-9549-fa735bc57350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047831011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1047831011
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.541043269
Short name T286
Test name
Test status
Simulation time 244036363 ps
CPU time 1.09 seconds
Started Aug 13 06:43:45 PM PDT 24
Finished Aug 13 06:43:46 PM PDT 24
Peak memory 217736 kb
Host smart-d64fe696-57d9-46ab-a0d8-aa49fc9682e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541043269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.541043269
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1286234042
Short name T344
Test name
Test status
Simulation time 150575920 ps
CPU time 0.85 seconds
Started Aug 13 06:44:08 PM PDT 24
Finished Aug 13 06:44:09 PM PDT 24
Peak memory 200460 kb
Host smart-e0391f97-bea1-4d6d-a4b2-d32a5d6d5556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286234042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1286234042
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1385489573
Short name T398
Test name
Test status
Simulation time 1398375425 ps
CPU time 5.52 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:43 PM PDT 24
Peak memory 200832 kb
Host smart-5c6c5ac4-c5e7-4954-b220-b27e6bff7b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385489573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1385489573
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2935534913
Short name T132
Test name
Test status
Simulation time 178282222 ps
CPU time 1.12 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:15 PM PDT 24
Peak memory 200676 kb
Host smart-36c29d8b-0f8e-4110-82bc-45e43618b297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935534913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2935534913
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1028442949
Short name T222
Test name
Test status
Simulation time 114949618 ps
CPU time 1.16 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 200692 kb
Host smart-e6910ab0-b7ff-4803-9d12-e6e2c127933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028442949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1028442949
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4088791995
Short name T514
Test name
Test status
Simulation time 14717774187 ps
CPU time 47.98 seconds
Started Aug 13 06:43:57 PM PDT 24
Finished Aug 13 06:44:45 PM PDT 24
Peak memory 209092 kb
Host smart-d5712cf9-3e4d-4c57-92fc-e39541d08c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088791995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4088791995
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1113907503
Short name T272
Test name
Test status
Simulation time 287238824 ps
CPU time 1.96 seconds
Started Aug 13 06:43:47 PM PDT 24
Finished Aug 13 06:43:49 PM PDT 24
Peak memory 208756 kb
Host smart-5256a892-41f6-40e7-9c7d-3c2895848277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113907503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1113907503
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.66844403
Short name T56
Test name
Test status
Simulation time 196117664 ps
CPU time 1.3 seconds
Started Aug 13 06:43:55 PM PDT 24
Finished Aug 13 06:43:56 PM PDT 24
Peak memory 200784 kb
Host smart-18e1d5aa-6d87-4efb-9252-16223407ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66844403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.66844403
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3011511250
Short name T190
Test name
Test status
Simulation time 78194753 ps
CPU time 0.83 seconds
Started Aug 13 06:43:31 PM PDT 24
Finished Aug 13 06:43:32 PM PDT 24
Peak memory 200540 kb
Host smart-f54fa159-bea7-4c40-871f-a9ef4a5b5cbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011511250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3011511250
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.700346321
Short name T346
Test name
Test status
Simulation time 1890998183 ps
CPU time 7.36 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 218024 kb
Host smart-27f82e65-f6a0-4945-a786-2d3aae85c01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700346321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.700346321
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2622896453
Short name T423
Test name
Test status
Simulation time 245289537 ps
CPU time 1.06 seconds
Started Aug 13 06:43:45 PM PDT 24
Finished Aug 13 06:43:46 PM PDT 24
Peak memory 217804 kb
Host smart-46881262-4e5c-4906-a383-e148cb72aa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622896453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2622896453
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.168577401
Short name T345
Test name
Test status
Simulation time 122070220 ps
CPU time 0.79 seconds
Started Aug 13 06:43:27 PM PDT 24
Finished Aug 13 06:43:27 PM PDT 24
Peak memory 200504 kb
Host smart-5e32cb7d-12a0-45d1-ab45-c12eaa851c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168577401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.168577401
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.1547445668
Short name T313
Test name
Test status
Simulation time 1426716988 ps
CPU time 5.54 seconds
Started Aug 13 06:43:43 PM PDT 24
Finished Aug 13 06:43:49 PM PDT 24
Peak memory 200824 kb
Host smart-7106fcab-fa7c-4d93-8ffd-ff4b1d4ecf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547445668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.1547445668
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3400178955
Short name T23
Test name
Test status
Simulation time 160532985 ps
CPU time 1.14 seconds
Started Aug 13 06:43:35 PM PDT 24
Finished Aug 13 06:43:36 PM PDT 24
Peak memory 200668 kb
Host smart-508462a8-c91c-483e-b0c8-df92acf65b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400178955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3400178955
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.252552573
Short name T182
Test name
Test status
Simulation time 254083023 ps
CPU time 1.49 seconds
Started Aug 13 06:43:32 PM PDT 24
Finished Aug 13 06:43:33 PM PDT 24
Peak memory 200720 kb
Host smart-6bdfe518-2612-4d73-a7f1-b65d3ad56ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252552573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.252552573
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.117861422
Short name T279
Test name
Test status
Simulation time 5810455945 ps
CPU time 21.64 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:36 PM PDT 24
Peak memory 200900 kb
Host smart-1baa1d42-aa71-4612-8a77-088d25ea3b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117861422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.117861422
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.134712647
Short name T411
Test name
Test status
Simulation time 388332506 ps
CPU time 2.39 seconds
Started Aug 13 06:44:00 PM PDT 24
Finished Aug 13 06:44:03 PM PDT 24
Peak memory 200600 kb
Host smart-321bfbc3-bd71-4bd9-b70d-99443e80fd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134712647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.134712647
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1769829774
Short name T528
Test name
Test status
Simulation time 247819370 ps
CPU time 1.37 seconds
Started Aug 13 06:43:56 PM PDT 24
Finished Aug 13 06:43:57 PM PDT 24
Peak memory 200620 kb
Host smart-decbe8ba-e6f5-4ff0-9f9b-52deb5309bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769829774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1769829774
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2357258146
Short name T454
Test name
Test status
Simulation time 76898061 ps
CPU time 0.79 seconds
Started Aug 13 06:44:05 PM PDT 24
Finished Aug 13 06:44:05 PM PDT 24
Peak memory 200484 kb
Host smart-1d488387-740a-4981-8d14-2b44689e463f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357258146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2357258146
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1036888916
Short name T471
Test name
Test status
Simulation time 1225703157 ps
CPU time 5.78 seconds
Started Aug 13 06:43:42 PM PDT 24
Finished Aug 13 06:43:47 PM PDT 24
Peak memory 218016 kb
Host smart-5cdbf59b-8ba2-4a32-b831-104afa50d8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036888916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1036888916
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3474702659
Short name T233
Test name
Test status
Simulation time 245445163 ps
CPU time 1.05 seconds
Started Aug 13 06:45:13 PM PDT 24
Finished Aug 13 06:45:15 PM PDT 24
Peak memory 217820 kb
Host smart-dc3afca2-086a-47d0-9e3c-9c282a7ddd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474702659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3474702659
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2123732021
Short name T303
Test name
Test status
Simulation time 116082656 ps
CPU time 0.78 seconds
Started Aug 13 06:43:32 PM PDT 24
Finished Aug 13 06:43:33 PM PDT 24
Peak memory 200424 kb
Host smart-44840184-7c95-49ab-a7d8-a0292bf40457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123732021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2123732021
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2815119674
Short name T335
Test name
Test status
Simulation time 729151892 ps
CPU time 3.92 seconds
Started Aug 13 06:43:29 PM PDT 24
Finished Aug 13 06:43:33 PM PDT 24
Peak memory 200820 kb
Host smart-3714cdf9-b307-4512-b07c-1c9136c72538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815119674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2815119674
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.166932915
Short name T380
Test name
Test status
Simulation time 101116569 ps
CPU time 0.99 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 200620 kb
Host smart-c078f727-81aa-497e-b994-83c32fcf322b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166932915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.166932915
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.2327573228
Short name T55
Test name
Test status
Simulation time 195231999 ps
CPU time 1.38 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200736 kb
Host smart-e90b1bd2-8477-432d-b661-527b0fa9bae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327573228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.2327573228
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.54993590
Short name T50
Test name
Test status
Simulation time 725083776 ps
CPU time 3.59 seconds
Started Aug 13 06:43:51 PM PDT 24
Finished Aug 13 06:43:54 PM PDT 24
Peak memory 200876 kb
Host smart-70308451-8785-4808-b9fc-6bae6d0328ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54993590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.54993590
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2282682863
Short name T156
Test name
Test status
Simulation time 118075679 ps
CPU time 1.54 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 200556 kb
Host smart-9394f15f-9746-402e-9343-c4ed31d4a014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282682863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2282682863
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1411488660
Short name T129
Test name
Test status
Simulation time 95442399 ps
CPU time 0.92 seconds
Started Aug 13 06:43:51 PM PDT 24
Finished Aug 13 06:43:52 PM PDT 24
Peak memory 200668 kb
Host smart-bcaa7be1-f047-4a33-a7ea-00d9b098cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411488660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1411488660
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.4147704008
Short name T130
Test name
Test status
Simulation time 56898817 ps
CPU time 0.71 seconds
Started Aug 13 06:42:52 PM PDT 24
Finished Aug 13 06:42:53 PM PDT 24
Peak memory 200504 kb
Host smart-12844fe4-657f-4e4b-9b50-19d93bf8043d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147704008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4147704008
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2786850986
Short name T45
Test name
Test status
Simulation time 1886372709 ps
CPU time 7.26 seconds
Started Aug 13 06:43:28 PM PDT 24
Finished Aug 13 06:43:35 PM PDT 24
Peak memory 216968 kb
Host smart-ae4ac29c-b3a9-4ea9-bc5c-7960e881c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786850986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2786850986
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4100405325
Short name T143
Test name
Test status
Simulation time 244278980 ps
CPU time 1.09 seconds
Started Aug 13 06:43:02 PM PDT 24
Finished Aug 13 06:43:03 PM PDT 24
Peak memory 217816 kb
Host smart-dcb26187-5f09-4144-8a1d-9a621b13f448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100405325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4100405325
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.32906094
Short name T431
Test name
Test status
Simulation time 212278056 ps
CPU time 0.96 seconds
Started Aug 13 06:43:02 PM PDT 24
Finished Aug 13 06:43:08 PM PDT 24
Peak memory 200472 kb
Host smart-7a6f2486-feab-4ed6-bbbb-b707a1c791d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32906094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.32906094
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3988988039
Short name T412
Test name
Test status
Simulation time 793616978 ps
CPU time 4.32 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:28 PM PDT 24
Peak memory 200848 kb
Host smart-2a02a196-01b6-418f-b4d9-7e8372f0e8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988988039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3988988039
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2235726516
Short name T69
Test name
Test status
Simulation time 8415384714 ps
CPU time 12.57 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:43:06 PM PDT 24
Peak memory 217340 kb
Host smart-511435b9-5db2-4cd7-aded-74f66e10589f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235726516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2235726516
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3306828091
Short name T479
Test name
Test status
Simulation time 164829880 ps
CPU time 1.13 seconds
Started Aug 13 06:42:56 PM PDT 24
Finished Aug 13 06:42:57 PM PDT 24
Peak memory 200688 kb
Host smart-04e3b305-bf81-4d20-a2a1-c5f2aaa58de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306828091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3306828091
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2879762135
Short name T315
Test name
Test status
Simulation time 217750204 ps
CPU time 1.35 seconds
Started Aug 13 06:43:01 PM PDT 24
Finished Aug 13 06:43:02 PM PDT 24
Peak memory 200736 kb
Host smart-f5f53d63-cd1e-4cbe-a711-50c67652f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879762135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2879762135
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2859607385
Short name T537
Test name
Test status
Simulation time 5292189070 ps
CPU time 19.15 seconds
Started Aug 13 06:42:49 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 200952 kb
Host smart-953dd64c-8351-4885-9f1c-85e0f5f08a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859607385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2859607385
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3974984380
Short name T265
Test name
Test status
Simulation time 391070016 ps
CPU time 2.17 seconds
Started Aug 13 06:42:57 PM PDT 24
Finished Aug 13 06:43:00 PM PDT 24
Peak memory 208760 kb
Host smart-725fec79-f8e3-4881-85d6-0a7d961cadd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974984380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3974984380
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1094382683
Short name T140
Test name
Test status
Simulation time 83191647 ps
CPU time 0.94 seconds
Started Aug 13 06:43:12 PM PDT 24
Finished Aug 13 06:43:13 PM PDT 24
Peak memory 200676 kb
Host smart-752b17cd-37c3-4b27-bd69-6d0bbbc888de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094382683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1094382683
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2947299381
Short name T208
Test name
Test status
Simulation time 81990794 ps
CPU time 0.79 seconds
Started Aug 13 06:45:13 PM PDT 24
Finished Aug 13 06:45:14 PM PDT 24
Peak memory 200564 kb
Host smart-997e3cbf-e3cf-4d79-a923-c6f82d025a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947299381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2947299381
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.842080081
Short name T27
Test name
Test status
Simulation time 2356379685 ps
CPU time 8.67 seconds
Started Aug 13 06:43:51 PM PDT 24
Finished Aug 13 06:44:00 PM PDT 24
Peak memory 218200 kb
Host smart-1f1d12c0-ab0a-46bc-8fd9-4f4d7af155d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842080081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.842080081
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.730552589
Short name T475
Test name
Test status
Simulation time 244106113 ps
CPU time 1.17 seconds
Started Aug 13 06:43:47 PM PDT 24
Finished Aug 13 06:43:48 PM PDT 24
Peak memory 217896 kb
Host smart-a6e15a6e-0da3-49c8-89a3-d7d0bc9720b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730552589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.730552589
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1991197879
Short name T426
Test name
Test status
Simulation time 130447466 ps
CPU time 0.8 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200424 kb
Host smart-71f7ac41-d207-4772-9a13-157b1a81d9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991197879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1991197879
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3156670058
Short name T216
Test name
Test status
Simulation time 656782100 ps
CPU time 3.46 seconds
Started Aug 13 06:43:37 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 200856 kb
Host smart-67e03d41-10b9-41d8-9c18-26563562df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156670058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3156670058
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3517046540
Short name T160
Test name
Test status
Simulation time 106660313 ps
CPU time 1.08 seconds
Started Aug 13 06:44:14 PM PDT 24
Finished Aug 13 06:44:15 PM PDT 24
Peak memory 200644 kb
Host smart-3121f399-164a-4bc0-ac86-1798118317c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517046540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3517046540
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.218667088
Short name T183
Test name
Test status
Simulation time 266696907 ps
CPU time 1.59 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:38 PM PDT 24
Peak memory 200840 kb
Host smart-6a8c14a6-47e3-494a-aa53-54c277faf05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218667088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.218667088
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2016385423
Short name T261
Test name
Test status
Simulation time 500914889 ps
CPU time 2.37 seconds
Started Aug 13 06:44:10 PM PDT 24
Finished Aug 13 06:44:13 PM PDT 24
Peak memory 200516 kb
Host smart-97a34db5-6d84-4900-b2b9-b6caa1ce0231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016385423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2016385423
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2397696109
Short name T385
Test name
Test status
Simulation time 367444216 ps
CPU time 2.26 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:06 PM PDT 24
Peak memory 200516 kb
Host smart-47c5b2e5-153e-4038-93f4-d33d1d18d7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397696109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2397696109
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3400780186
Short name T82
Test name
Test status
Simulation time 89317940 ps
CPU time 0.79 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:35 PM PDT 24
Peak memory 200668 kb
Host smart-5b26fed0-4362-4680-8546-c41371c3f42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400780186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3400780186
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1935004991
Short name T474
Test name
Test status
Simulation time 68854797 ps
CPU time 0.75 seconds
Started Aug 13 06:45:11 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 200564 kb
Host smart-63de1fcc-01e0-4e0e-904b-97c3b05e73df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935004991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1935004991
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3315604949
Short name T374
Test name
Test status
Simulation time 2355133856 ps
CPU time 7.98 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:43:48 PM PDT 24
Peak memory 218116 kb
Host smart-481e2c5c-cae6-42a5-a993-9fac15e449f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315604949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3315604949
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.219077782
Short name T293
Test name
Test status
Simulation time 244241333 ps
CPU time 1.17 seconds
Started Aug 13 06:43:39 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 217760 kb
Host smart-cb7a474b-fdc1-4fc8-8a41-fb0c54b4f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219077782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.219077782
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2745186648
Short name T463
Test name
Test status
Simulation time 87575934 ps
CPU time 0.74 seconds
Started Aug 13 06:43:34 PM PDT 24
Finished Aug 13 06:43:34 PM PDT 24
Peak memory 200424 kb
Host smart-c5f77ef8-643f-4148-a8bc-912ee563ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745186648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2745186648
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.2858625772
Short name T419
Test name
Test status
Simulation time 1119672063 ps
CPU time 5.39 seconds
Started Aug 13 06:43:40 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 200856 kb
Host smart-57114be5-019c-4abb-823a-66d5089e103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858625772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2858625772
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.403661297
Short name T469
Test name
Test status
Simulation time 154122199 ps
CPU time 1.05 seconds
Started Aug 13 06:45:11 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 200692 kb
Host smart-048bf8c3-2b60-4818-bb12-d688e433b71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403661297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.403661297
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2325471723
Short name T297
Test name
Test status
Simulation time 118816696 ps
CPU time 1.23 seconds
Started Aug 13 06:43:55 PM PDT 24
Finished Aug 13 06:44:01 PM PDT 24
Peak memory 200784 kb
Host smart-cd404c0e-6455-458e-851e-d98ee3517a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325471723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2325471723
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1236426830
Short name T274
Test name
Test status
Simulation time 373205985 ps
CPU time 2.38 seconds
Started Aug 13 06:43:54 PM PDT 24
Finished Aug 13 06:44:01 PM PDT 24
Peak memory 200568 kb
Host smart-f32f49cf-b889-4960-8552-96bfb3e26c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236426830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1236426830
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2985670459
Short name T524
Test name
Test status
Simulation time 111863144 ps
CPU time 0.96 seconds
Started Aug 13 06:43:30 PM PDT 24
Finished Aug 13 06:43:31 PM PDT 24
Peak memory 200668 kb
Host smart-2c66eb19-301a-4804-8b61-9378cdab7d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985670459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2985670459
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.120069233
Short name T148
Test name
Test status
Simulation time 76276729 ps
CPU time 0.8 seconds
Started Aug 13 06:43:42 PM PDT 24
Finished Aug 13 06:43:42 PM PDT 24
Peak memory 200444 kb
Host smart-65d25731-7cd7-44dd-8470-707b30598ba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120069233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.120069233
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1543247583
Short name T424
Test name
Test status
Simulation time 2371420757 ps
CPU time 8.17 seconds
Started Aug 13 06:43:32 PM PDT 24
Finished Aug 13 06:43:40 PM PDT 24
Peak memory 218016 kb
Host smart-286f659e-d8cf-45de-be19-595f41fffbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543247583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1543247583
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1261780322
Short name T396
Test name
Test status
Simulation time 244749552 ps
CPU time 0.99 seconds
Started Aug 13 06:43:57 PM PDT 24
Finished Aug 13 06:43:58 PM PDT 24
Peak memory 217780 kb
Host smart-64ce24f4-28b1-4fd7-ab29-d32c412c8e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261780322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1261780322
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3898794589
Short name T387
Test name
Test status
Simulation time 158662092 ps
CPU time 0.86 seconds
Started Aug 13 06:45:11 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 200504 kb
Host smart-4d90c370-bcd2-43a0-9ce6-eb7918505269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898794589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3898794589
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.33862083
Short name T401
Test name
Test status
Simulation time 1020921419 ps
CPU time 5.12 seconds
Started Aug 13 06:45:25 PM PDT 24
Finished Aug 13 06:45:30 PM PDT 24
Peak memory 200856 kb
Host smart-9d40214a-a9b5-4cd3-9b1d-5ec89b7fccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33862083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.33862083
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.157716939
Short name T467
Test name
Test status
Simulation time 98495094 ps
CPU time 0.98 seconds
Started Aug 13 06:43:58 PM PDT 24
Finished Aug 13 06:43:59 PM PDT 24
Peak memory 200664 kb
Host smart-151bc839-e9be-4dde-8b22-9c7e79e2cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157716939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.157716939
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.3016192024
Short name T352
Test name
Test status
Simulation time 194539283 ps
CPU time 1.3 seconds
Started Aug 13 06:45:04 PM PDT 24
Finished Aug 13 06:45:05 PM PDT 24
Peak memory 200832 kb
Host smart-566521f6-7f3f-474a-8282-5c0ef4f49389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016192024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3016192024
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4126742259
Short name T35
Test name
Test status
Simulation time 2029830066 ps
CPU time 6.89 seconds
Started Aug 13 06:43:42 PM PDT 24
Finished Aug 13 06:43:49 PM PDT 24
Peak memory 200736 kb
Host smart-d75b91e7-33b6-4a2e-8da2-fccf22ecd8eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126742259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4126742259
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3253336833
Short name T457
Test name
Test status
Simulation time 321815694 ps
CPU time 1.96 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:46 PM PDT 24
Peak memory 200532 kb
Host smart-ed5c7f90-4e4a-4576-bfe8-157e52ced40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253336833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3253336833
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.223617468
Short name T220
Test name
Test status
Simulation time 167331012 ps
CPU time 1.08 seconds
Started Aug 13 06:45:11 PM PDT 24
Finished Aug 13 06:45:12 PM PDT 24
Peak memory 200688 kb
Host smart-cdabb9cd-cf72-46a8-b633-045043c85e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223617468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.223617468
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.850957541
Short name T535
Test name
Test status
Simulation time 65529678 ps
CPU time 0.73 seconds
Started Aug 13 06:43:38 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 200524 kb
Host smart-dfd470b9-a2ea-4d43-9009-d89d01557514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850957541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.850957541
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2524970119
Short name T46
Test name
Test status
Simulation time 2171538828 ps
CPU time 8.29 seconds
Started Aug 13 06:43:47 PM PDT 24
Finished Aug 13 06:43:55 PM PDT 24
Peak memory 217860 kb
Host smart-f6d8b60c-a2c3-4f3d-a31e-bd4877f8f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524970119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2524970119
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2297867622
Short name T165
Test name
Test status
Simulation time 244208102 ps
CPU time 1.02 seconds
Started Aug 13 06:43:31 PM PDT 24
Finished Aug 13 06:43:32 PM PDT 24
Peak memory 217880 kb
Host smart-751f0822-6384-47cb-ab23-d4f7f42a9c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297867622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2297867622
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.1713200933
Short name T230
Test name
Test status
Simulation time 209609144 ps
CPU time 0.96 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:44:12 PM PDT 24
Peak memory 200464 kb
Host smart-db550fe5-71f2-4732-9a8e-dd3eb764ca09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713200933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1713200933
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.3503233063
Short name T451
Test name
Test status
Simulation time 1434244309 ps
CPU time 5.13 seconds
Started Aug 13 06:43:52 PM PDT 24
Finished Aug 13 06:43:57 PM PDT 24
Peak memory 200828 kb
Host smart-a857be9a-9cc9-4fef-ad90-e1b8c789847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503233063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3503233063
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2016389370
Short name T441
Test name
Test status
Simulation time 150371926 ps
CPU time 1.12 seconds
Started Aug 13 06:43:49 PM PDT 24
Finished Aug 13 06:43:51 PM PDT 24
Peak memory 200684 kb
Host smart-0d34cc45-d539-4213-a1c8-23cf72e7eae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016389370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2016389370
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1268783527
Short name T149
Test name
Test status
Simulation time 200570388 ps
CPU time 1.34 seconds
Started Aug 13 06:43:46 PM PDT 24
Finished Aug 13 06:43:48 PM PDT 24
Peak memory 200740 kb
Host smart-9819f7e3-a1a0-4e7e-8da3-f12cf5b4c5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268783527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1268783527
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.799959072
Short name T207
Test name
Test status
Simulation time 6789535649 ps
CPU time 23.75 seconds
Started Aug 13 06:43:59 PM PDT 24
Finished Aug 13 06:44:23 PM PDT 24
Peak memory 200820 kb
Host smart-284f7cf6-13e3-4904-ba33-5303ab47d499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799959072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.799959072
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3060532497
Short name T373
Test name
Test status
Simulation time 336662610 ps
CPU time 2.36 seconds
Started Aug 13 06:43:53 PM PDT 24
Finished Aug 13 06:43:55 PM PDT 24
Peak memory 208752 kb
Host smart-46d37601-bae8-49f4-9999-c17f3533e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060532497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3060532497
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.212124303
Short name T278
Test name
Test status
Simulation time 93403053 ps
CPU time 0.87 seconds
Started Aug 13 06:43:54 PM PDT 24
Finished Aug 13 06:43:55 PM PDT 24
Peak memory 200652 kb
Host smart-8cfda000-0ebe-4a15-a607-aca757b49c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212124303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.212124303
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2328352818
Short name T465
Test name
Test status
Simulation time 68778387 ps
CPU time 0.8 seconds
Started Aug 13 06:44:07 PM PDT 24
Finished Aug 13 06:44:08 PM PDT 24
Peak memory 200488 kb
Host smart-c642feda-d3de-4b19-b986-ce656c6bd330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328352818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2328352818
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3575025577
Short name T276
Test name
Test status
Simulation time 1229535133 ps
CPU time 6.1 seconds
Started Aug 13 06:44:03 PM PDT 24
Finished Aug 13 06:44:09 PM PDT 24
Peak memory 221872 kb
Host smart-28d36bf0-eff5-463b-b7a9-2ca1642ed58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575025577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3575025577
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.882075878
Short name T52
Test name
Test status
Simulation time 243955039 ps
CPU time 1.05 seconds
Started Aug 13 06:44:20 PM PDT 24
Finished Aug 13 06:44:21 PM PDT 24
Peak memory 217900 kb
Host smart-26bb7950-6070-46ad-935d-3bf2c62535e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882075878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.882075878
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.4228561823
Short name T181
Test name
Test status
Simulation time 127579707 ps
CPU time 0.82 seconds
Started Aug 13 06:43:32 PM PDT 24
Finished Aug 13 06:43:32 PM PDT 24
Peak memory 200464 kb
Host smart-97babf74-f66e-4c7e-8d92-e05387fca303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228561823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4228561823
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.15837591
Short name T245
Test name
Test status
Simulation time 2259884042 ps
CPU time 8.02 seconds
Started Aug 13 06:43:31 PM PDT 24
Finished Aug 13 06:43:39 PM PDT 24
Peak memory 200916 kb
Host smart-9c64a7e8-61b8-45f1-8e84-842efea01a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15837591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.15837591
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3242397514
Short name T378
Test name
Test status
Simulation time 94774455 ps
CPU time 1.03 seconds
Started Aug 13 06:44:10 PM PDT 24
Finished Aug 13 06:44:11 PM PDT 24
Peak memory 200672 kb
Host smart-d879fd0d-a906-4129-8001-5466c5c38c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242397514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3242397514
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2141769164
Short name T10
Test name
Test status
Simulation time 248314712 ps
CPU time 1.35 seconds
Started Aug 13 06:43:57 PM PDT 24
Finished Aug 13 06:43:59 PM PDT 24
Peak memory 200744 kb
Host smart-80aa1257-60d6-4911-b241-431fba854af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141769164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2141769164
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3565649473
Short name T271
Test name
Test status
Simulation time 8002933099 ps
CPU time 33.19 seconds
Started Aug 13 06:43:50 PM PDT 24
Finished Aug 13 06:44:24 PM PDT 24
Peak memory 210776 kb
Host smart-0e72f227-6ba5-4c31-b187-f964a03c5019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565649473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3565649473
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2567038931
Short name T325
Test name
Test status
Simulation time 147653542 ps
CPU time 1.84 seconds
Started Aug 13 06:43:50 PM PDT 24
Finished Aug 13 06:43:52 PM PDT 24
Peak memory 200516 kb
Host smart-d58cae5e-0fc4-4557-8709-3a901c55c7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567038931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2567038931
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2670093339
Short name T155
Test name
Test status
Simulation time 68571151 ps
CPU time 0.75 seconds
Started Aug 13 06:43:36 PM PDT 24
Finished Aug 13 06:43:37 PM PDT 24
Peak memory 200620 kb
Host smart-c845e827-c0b1-46c9-ac68-b28443822b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670093339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2670093339
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.835558363
Short name T5
Test name
Test status
Simulation time 80439234 ps
CPU time 0.84 seconds
Started Aug 13 06:43:58 PM PDT 24
Finished Aug 13 06:43:59 PM PDT 24
Peak memory 200504 kb
Host smart-d9352ab1-8fdc-46f3-88e0-7832592eb210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835558363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.835558363
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3775864153
Short name T447
Test name
Test status
Simulation time 2353849315 ps
CPU time 8.3 seconds
Started Aug 13 06:43:57 PM PDT 24
Finished Aug 13 06:44:05 PM PDT 24
Peak memory 222076 kb
Host smart-c60179d9-2ff0-4e44-a9fe-bd8995dec7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775864153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3775864153
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.553794349
Short name T145
Test name
Test status
Simulation time 244943212 ps
CPU time 1.12 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:43:49 PM PDT 24
Peak memory 217836 kb
Host smart-1b36dda3-c46a-47c0-9109-2e999c9b2e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553794349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.553794349
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3704941215
Short name T243
Test name
Test status
Simulation time 141688623 ps
CPU time 0.79 seconds
Started Aug 13 06:43:57 PM PDT 24
Finished Aug 13 06:43:58 PM PDT 24
Peak memory 200460 kb
Host smart-011694b6-ad75-41ac-a24a-de129c7fb132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704941215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3704941215
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.289998204
Short name T144
Test name
Test status
Simulation time 1681506692 ps
CPU time 6.64 seconds
Started Aug 13 06:43:46 PM PDT 24
Finished Aug 13 06:43:53 PM PDT 24
Peak memory 200800 kb
Host smart-61ba7075-08d7-48c1-b2a6-9fded8582930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289998204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.289998204
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.635009254
Short name T326
Test name
Test status
Simulation time 176778467 ps
CPU time 1.23 seconds
Started Aug 13 06:43:58 PM PDT 24
Finished Aug 13 06:44:00 PM PDT 24
Peak memory 200636 kb
Host smart-6a108892-afbb-44b1-9d65-fa1d0dc2eff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635009254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.635009254
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.2818261661
Short name T466
Test name
Test status
Simulation time 119400917 ps
CPU time 1.18 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:10 PM PDT 24
Peak memory 200792 kb
Host smart-f4d56ca4-8e6d-44e9-b444-c12359c3ef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818261661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2818261661
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3523614022
Short name T87
Test name
Test status
Simulation time 5060400180 ps
CPU time 23.18 seconds
Started Aug 13 06:43:47 PM PDT 24
Finished Aug 13 06:44:10 PM PDT 24
Peak memory 200860 kb
Host smart-555e144f-84e0-461b-b6aa-f91ab65f63a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523614022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3523614022
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.381288555
Short name T270
Test name
Test status
Simulation time 116357846 ps
CPU time 1.46 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:11 PM PDT 24
Peak memory 200572 kb
Host smart-31c3d72d-aa1f-4737-9c50-2bf085e6a56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381288555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.381288555
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.4253496149
Short name T340
Test name
Test status
Simulation time 233625771 ps
CPU time 1.42 seconds
Started Aug 13 06:44:05 PM PDT 24
Finished Aug 13 06:44:06 PM PDT 24
Peak memory 200656 kb
Host smart-3096fb4a-ddc2-4687-ae8d-561e066c96c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253496149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4253496149
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1387771696
Short name T249
Test name
Test status
Simulation time 76284378 ps
CPU time 0.84 seconds
Started Aug 13 06:43:52 PM PDT 24
Finished Aug 13 06:43:53 PM PDT 24
Peak memory 200520 kb
Host smart-c71b84f0-a5bd-4a46-bf4d-3b9dc74bbf99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387771696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1387771696
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.128471080
Short name T29
Test name
Test status
Simulation time 1876678653 ps
CPU time 6.98 seconds
Started Aug 13 06:44:00 PM PDT 24
Finished Aug 13 06:44:07 PM PDT 24
Peak memory 218024 kb
Host smart-1cb68eab-9b43-421f-af6d-356ca02ec357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128471080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.128471080
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.343695318
Short name T291
Test name
Test status
Simulation time 244158463 ps
CPU time 1.13 seconds
Started Aug 13 06:44:24 PM PDT 24
Finished Aug 13 06:44:25 PM PDT 24
Peak memory 217860 kb
Host smart-fc49a1c9-5847-426c-a979-491eca7f0251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343695318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.343695318
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3595549183
Short name T22
Test name
Test status
Simulation time 141202984 ps
CPU time 0.79 seconds
Started Aug 13 06:43:52 PM PDT 24
Finished Aug 13 06:43:53 PM PDT 24
Peak memory 200476 kb
Host smart-d070839e-a2e3-453e-9ed4-f4be66a670de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595549183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3595549183
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3289104403
Short name T96
Test name
Test status
Simulation time 1629386746 ps
CPU time 6.08 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:50 PM PDT 24
Peak memory 200828 kb
Host smart-53ee54a4-f4a5-4057-834c-f1e6d4b327c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289104403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3289104403
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3518143426
Short name T48
Test name
Test status
Simulation time 113689287 ps
CPU time 1 seconds
Started Aug 13 06:44:20 PM PDT 24
Finished Aug 13 06:44:22 PM PDT 24
Peak memory 200616 kb
Host smart-b1a008fa-41ce-4479-9f78-22e33df572b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518143426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3518143426
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.787616451
Short name T290
Test name
Test status
Simulation time 202692824 ps
CPU time 1.42 seconds
Started Aug 13 06:44:22 PM PDT 24
Finished Aug 13 06:44:23 PM PDT 24
Peak memory 200796 kb
Host smart-2d452843-4b86-45cb-be3d-25c67fc7c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787616451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.787616451
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.57623632
Short name T253
Test name
Test status
Simulation time 897823589 ps
CPU time 4.95 seconds
Started Aug 13 06:43:46 PM PDT 24
Finished Aug 13 06:43:51 PM PDT 24
Peak memory 200836 kb
Host smart-c3d7feeb-4118-4c71-8eb9-7828ef773d88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57623632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.57623632
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.3370115091
Short name T377
Test name
Test status
Simulation time 325668354 ps
CPU time 1.99 seconds
Started Aug 13 06:44:02 PM PDT 24
Finished Aug 13 06:44:04 PM PDT 24
Peak memory 200544 kb
Host smart-09170caa-03f5-40e3-9ab7-a73111b406ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370115091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3370115091
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2478021779
Short name T283
Test name
Test status
Simulation time 107781033 ps
CPU time 0.98 seconds
Started Aug 13 06:43:49 PM PDT 24
Finished Aug 13 06:43:50 PM PDT 24
Peak memory 200672 kb
Host smart-758bcd89-d16a-4d30-bbaf-43f31a2469ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478021779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2478021779
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.758503897
Short name T127
Test name
Test status
Simulation time 61707584 ps
CPU time 0.74 seconds
Started Aug 13 06:43:53 PM PDT 24
Finished Aug 13 06:43:54 PM PDT 24
Peak memory 200540 kb
Host smart-21ba9f2d-5f50-4f8e-aa1f-bf8b1d1d8ff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758503897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.758503897
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.4233792129
Short name T59
Test name
Test status
Simulation time 1224824674 ps
CPU time 5.95 seconds
Started Aug 13 06:43:50 PM PDT 24
Finished Aug 13 06:43:56 PM PDT 24
Peak memory 217976 kb
Host smart-d861a9bb-89d2-4864-9a69-b830a85bbc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233792129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4233792129
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4161907507
Short name T246
Test name
Test status
Simulation time 243997266 ps
CPU time 1.03 seconds
Started Aug 13 06:44:10 PM PDT 24
Finished Aug 13 06:44:11 PM PDT 24
Peak memory 217760 kb
Host smart-24e623fe-465b-4b38-b562-e10b3e9f3155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161907507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4161907507
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.3474930722
Short name T472
Test name
Test status
Simulation time 169493933 ps
CPU time 0.87 seconds
Started Aug 13 06:44:01 PM PDT 24
Finished Aug 13 06:44:02 PM PDT 24
Peak memory 200484 kb
Host smart-8a8f00e4-70de-4100-a07e-50fd58e2720d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474930722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3474930722
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4105095611
Short name T410
Test name
Test status
Simulation time 1820578369 ps
CPU time 6.5 seconds
Started Aug 13 06:43:56 PM PDT 24
Finished Aug 13 06:44:03 PM PDT 24
Peak memory 200864 kb
Host smart-cada0f1e-7893-4d3a-b431-2dea5c44b7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105095611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4105095611
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3539200113
Short name T239
Test name
Test status
Simulation time 139747094 ps
CPU time 1.12 seconds
Started Aug 13 06:43:52 PM PDT 24
Finished Aug 13 06:43:53 PM PDT 24
Peak memory 200676 kb
Host smart-39fceae3-292f-4add-8404-5d0d899d7c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539200113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3539200113
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3191966320
Short name T314
Test name
Test status
Simulation time 121405421 ps
CPU time 1.19 seconds
Started Aug 13 06:43:50 PM PDT 24
Finished Aug 13 06:43:51 PM PDT 24
Peak memory 200768 kb
Host smart-2dcb1fed-f3c2-4c2f-b771-b7b3e892917d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191966320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3191966320
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.3297233518
Short name T435
Test name
Test status
Simulation time 2999007742 ps
CPU time 11.63 seconds
Started Aug 13 06:44:13 PM PDT 24
Finished Aug 13 06:44:25 PM PDT 24
Peak memory 209084 kb
Host smart-d77e817f-36cd-4d20-a2fa-111ee004f3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297233518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3297233518
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2689682339
Short name T533
Test name
Test status
Simulation time 131704459 ps
CPU time 1.65 seconds
Started Aug 13 06:43:59 PM PDT 24
Finished Aug 13 06:44:01 PM PDT 24
Peak memory 208808 kb
Host smart-35184ac3-1d4f-42dd-92c6-78418bb37c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689682339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2689682339
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.797577911
Short name T316
Test name
Test status
Simulation time 137980726 ps
CPU time 1.13 seconds
Started Aug 13 06:44:06 PM PDT 24
Finished Aug 13 06:44:07 PM PDT 24
Peak memory 200632 kb
Host smart-1aecacfa-9709-4457-8fae-a1166b5bcefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797577911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.797577911
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2553287767
Short name T328
Test name
Test status
Simulation time 64075205 ps
CPU time 0.73 seconds
Started Aug 13 06:43:54 PM PDT 24
Finished Aug 13 06:43:55 PM PDT 24
Peak memory 200560 kb
Host smart-c622a775-1671-485f-9a6b-e70d6c541e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553287767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2553287767
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3622900253
Short name T462
Test name
Test status
Simulation time 1221454576 ps
CPU time 6.54 seconds
Started Aug 13 06:43:53 PM PDT 24
Finished Aug 13 06:44:00 PM PDT 24
Peak memory 217244 kb
Host smart-b094c46f-10e9-4793-ada4-3de5286b237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622900253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3622900253
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1519361060
Short name T487
Test name
Test status
Simulation time 243905111 ps
CPU time 1.1 seconds
Started Aug 13 06:44:17 PM PDT 24
Finished Aug 13 06:44:18 PM PDT 24
Peak memory 217848 kb
Host smart-4d7fa741-35b6-4a8e-94b4-97f35ec8ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519361060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1519361060
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1480307736
Short name T294
Test name
Test status
Simulation time 207783509 ps
CPU time 0.9 seconds
Started Aug 13 06:43:42 PM PDT 24
Finished Aug 13 06:43:48 PM PDT 24
Peak memory 200440 kb
Host smart-dd03273d-5ccc-468e-81bd-b504af0c3b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480307736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1480307736
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3929064794
Short name T37
Test name
Test status
Simulation time 2209178661 ps
CPU time 7.76 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:44:19 PM PDT 24
Peak memory 200892 kb
Host smart-fcb0ceb2-bb18-45d1-976f-138ac17d7d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929064794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3929064794
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2095583070
Short name T248
Test name
Test status
Simulation time 115498854 ps
CPU time 1.03 seconds
Started Aug 13 06:43:46 PM PDT 24
Finished Aug 13 06:43:47 PM PDT 24
Peak memory 200640 kb
Host smart-29f286ad-32de-434d-9a35-419af85e003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095583070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2095583070
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3622638126
Short name T403
Test name
Test status
Simulation time 118362076 ps
CPU time 1.24 seconds
Started Aug 13 06:44:04 PM PDT 24
Finished Aug 13 06:44:05 PM PDT 24
Peak memory 200736 kb
Host smart-1078b927-33c8-43dc-a0f8-81362848d114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622638126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3622638126
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.927993301
Short name T511
Test name
Test status
Simulation time 4282823929 ps
CPU time 20 seconds
Started Aug 13 06:44:11 PM PDT 24
Finished Aug 13 06:44:31 PM PDT 24
Peak memory 209096 kb
Host smart-d568301a-2b7e-478c-af0f-6da4dbd2deeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927993301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.927993301
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.2329749043
Short name T361
Test name
Test status
Simulation time 264697556 ps
CPU time 1.8 seconds
Started Aug 13 06:43:54 PM PDT 24
Finished Aug 13 06:43:56 PM PDT 24
Peak memory 200568 kb
Host smart-40c20537-fab6-4ac5-bd23-690a3a4c5408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329749043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2329749043
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2292823913
Short name T312
Test name
Test status
Simulation time 285583704 ps
CPU time 1.49 seconds
Started Aug 13 06:43:59 PM PDT 24
Finished Aug 13 06:44:01 PM PDT 24
Peak memory 200752 kb
Host smart-d13aaf6a-e927-4abe-90a2-21eda78d9287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292823913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2292823913
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4047313636
Short name T41
Test name
Test status
Simulation time 65612576 ps
CPU time 0.76 seconds
Started Aug 13 06:43:44 PM PDT 24
Finished Aug 13 06:43:45 PM PDT 24
Peak memory 200552 kb
Host smart-340625f1-9e3f-46f6-8a0d-77a4de4677fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047313636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4047313636
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2598052419
Short name T499
Test name
Test status
Simulation time 2348637123 ps
CPU time 8.3 seconds
Started Aug 13 06:43:59 PM PDT 24
Finished Aug 13 06:44:08 PM PDT 24
Peak memory 222044 kb
Host smart-f2d48231-0d44-4ea9-824c-eb622b609230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598052419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2598052419
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3348358953
Short name T390
Test name
Test status
Simulation time 244782701 ps
CPU time 1.1 seconds
Started Aug 13 06:44:06 PM PDT 24
Finished Aug 13 06:44:07 PM PDT 24
Peak memory 217844 kb
Host smart-7b0a1268-65a3-425d-bc70-40b72baba2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348358953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3348358953
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.219743956
Short name T489
Test name
Test status
Simulation time 203192555 ps
CPU time 0.88 seconds
Started Aug 13 06:44:09 PM PDT 24
Finished Aug 13 06:44:10 PM PDT 24
Peak memory 200460 kb
Host smart-f3611431-4914-4384-9d6d-43171f259fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219743956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.219743956
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2863087123
Short name T95
Test name
Test status
Simulation time 1597135672 ps
CPU time 6.75 seconds
Started Aug 13 06:43:47 PM PDT 24
Finished Aug 13 06:43:54 PM PDT 24
Peak memory 200780 kb
Host smart-2cdb83ac-ddb0-4134-b199-e4635663e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863087123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2863087123
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1087717541
Short name T171
Test name
Test status
Simulation time 186151125 ps
CPU time 1.18 seconds
Started Aug 13 06:43:51 PM PDT 24
Finished Aug 13 06:43:52 PM PDT 24
Peak memory 200572 kb
Host smart-88b55111-cbef-4227-a499-1f0983bc69ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087717541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1087717541
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.464155053
Short name T337
Test name
Test status
Simulation time 193323055 ps
CPU time 1.44 seconds
Started Aug 13 06:43:50 PM PDT 24
Finished Aug 13 06:43:51 PM PDT 24
Peak memory 200776 kb
Host smart-45845349-5510-4169-a76a-a0c260fe5b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464155053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.464155053
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2069826554
Short name T196
Test name
Test status
Simulation time 4414442243 ps
CPU time 18.93 seconds
Started Aug 13 06:43:48 PM PDT 24
Finished Aug 13 06:44:07 PM PDT 24
Peak memory 208980 kb
Host smart-0e3af5ae-285b-41cc-a549-155699de1256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069826554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2069826554
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.603490372
Short name T420
Test name
Test status
Simulation time 373543652 ps
CPU time 2.49 seconds
Started Aug 13 06:43:53 PM PDT 24
Finished Aug 13 06:43:56 PM PDT 24
Peak memory 200532 kb
Host smart-7d5db1a6-9d91-407d-875d-253bc32fc46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603490372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.603490372
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2987387633
Short name T215
Test name
Test status
Simulation time 162566543 ps
CPU time 1.34 seconds
Started Aug 13 06:43:54 PM PDT 24
Finished Aug 13 06:43:55 PM PDT 24
Peak memory 200772 kb
Host smart-05356853-ad5f-4df9-ad45-b90ab9322b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987387633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2987387633
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1906765600
Short name T301
Test name
Test status
Simulation time 69367210 ps
CPU time 0.8 seconds
Started Aug 13 06:43:14 PM PDT 24
Finished Aug 13 06:43:15 PM PDT 24
Peak memory 200540 kb
Host smart-2f723cb7-666d-4c15-b6f7-d36b39cfe061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906765600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1906765600
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3300854921
Short name T28
Test name
Test status
Simulation time 1221959211 ps
CPU time 5.69 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 221984 kb
Host smart-c7adb3d5-bf34-4d44-a29e-f094e3f15e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300854921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3300854921
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1903961889
Short name T6
Test name
Test status
Simulation time 244368414 ps
CPU time 1 seconds
Started Aug 13 06:43:10 PM PDT 24
Finished Aug 13 06:43:11 PM PDT 24
Peak memory 217816 kb
Host smart-caa212d8-bf36-4359-bdbc-aee90d8566db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903961889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1903961889
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2268070749
Short name T268
Test name
Test status
Simulation time 203776438 ps
CPU time 0.94 seconds
Started Aug 13 06:42:59 PM PDT 24
Finished Aug 13 06:43:00 PM PDT 24
Peak memory 200472 kb
Host smart-f8bd42be-c1c3-4a26-a23b-aadf0a18cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268070749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2268070749
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3414641671
Short name T213
Test name
Test status
Simulation time 1006542622 ps
CPU time 4.94 seconds
Started Aug 13 06:43:12 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200776 kb
Host smart-52cd4ac4-4ae2-4a52-957e-1d407dd80fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414641671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3414641671
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.294284309
Short name T241
Test name
Test status
Simulation time 107774847 ps
CPU time 1.06 seconds
Started Aug 13 06:42:51 PM PDT 24
Finished Aug 13 06:42:53 PM PDT 24
Peak memory 200620 kb
Host smart-2fcb6435-e710-44e5-ab04-4d408302f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294284309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.294284309
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1879541973
Short name T139
Test name
Test status
Simulation time 190156628 ps
CPU time 1.29 seconds
Started Aug 13 06:43:14 PM PDT 24
Finished Aug 13 06:43:16 PM PDT 24
Peak memory 200748 kb
Host smart-cd61eeda-152d-4b36-be98-5f5055d48fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879541973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1879541973
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3342570560
Short name T333
Test name
Test status
Simulation time 1117211315 ps
CPU time 5.55 seconds
Started Aug 13 06:43:24 PM PDT 24
Finished Aug 13 06:43:30 PM PDT 24
Peak memory 200836 kb
Host smart-98310d03-daa3-4fcd-bd86-3bebd3f69378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342570560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3342570560
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.1559523212
Short name T8
Test name
Test status
Simulation time 392827647 ps
CPU time 2.28 seconds
Started Aug 13 06:43:22 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200576 kb
Host smart-de2a0cf8-570e-43f4-8e61-fc456d68e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559523212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1559523212
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.848158825
Short name T304
Test name
Test status
Simulation time 174451788 ps
CPU time 1.18 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:20 PM PDT 24
Peak memory 200652 kb
Host smart-101a78f4-dfab-49b8-8107-3b86279bf2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848158825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.848158825
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1100187532
Short name T205
Test name
Test status
Simulation time 60997550 ps
CPU time 0.74 seconds
Started Aug 13 06:43:15 PM PDT 24
Finished Aug 13 06:43:15 PM PDT 24
Peak memory 200544 kb
Host smart-4581af62-078c-4848-b601-ff9711f9993c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100187532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1100187532
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.11915570
Short name T31
Test name
Test status
Simulation time 1224375160 ps
CPU time 5.59 seconds
Started Aug 13 06:43:17 PM PDT 24
Finished Aug 13 06:43:22 PM PDT 24
Peak memory 217920 kb
Host smart-eecf4bca-e90d-4c62-9849-47d2dfc0123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11915570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.11915570
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2819722685
Short name T311
Test name
Test status
Simulation time 243983884 ps
CPU time 1.08 seconds
Started Aug 13 06:42:55 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 217780 kb
Host smart-da93f1a5-e3dd-4ec2-8794-30a3305501a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819722685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2819722685
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.433441437
Short name T228
Test name
Test status
Simulation time 175647963 ps
CPU time 0.88 seconds
Started Aug 13 06:43:04 PM PDT 24
Finished Aug 13 06:43:05 PM PDT 24
Peak memory 200476 kb
Host smart-061190eb-1556-4595-b883-0aefd1b71727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433441437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.433441437
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3627900472
Short name T57
Test name
Test status
Simulation time 1442045715 ps
CPU time 5.73 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200860 kb
Host smart-89cb841d-46fd-4099-a2b6-7b34b8d285d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627900472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3627900472
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2996794060
Short name T375
Test name
Test status
Simulation time 97449398 ps
CPU time 1.01 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 200676 kb
Host smart-fafe4ed8-cab8-42a9-b531-50d0bb240398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996794060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2996794060
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.4168210641
Short name T433
Test name
Test status
Simulation time 203667258 ps
CPU time 1.32 seconds
Started Aug 13 06:42:59 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 200784 kb
Host smart-3abe138c-39b0-4834-9545-57b7b3888f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168210641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4168210641
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.837096909
Short name T400
Test name
Test status
Simulation time 4458144688 ps
CPU time 15.4 seconds
Started Aug 13 06:42:49 PM PDT 24
Finished Aug 13 06:43:05 PM PDT 24
Peak memory 200888 kb
Host smart-cab1b393-b4f3-4633-80cf-ca5c59c9c015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837096909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.837096909
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.874942954
Short name T429
Test name
Test status
Simulation time 304942478 ps
CPU time 2.18 seconds
Started Aug 13 06:42:56 PM PDT 24
Finished Aug 13 06:42:58 PM PDT 24
Peak memory 208776 kb
Host smart-49b771e4-0cf8-4131-bd15-71dc8465815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874942954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.874942954
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4065905853
Short name T349
Test name
Test status
Simulation time 177397411 ps
CPU time 1.12 seconds
Started Aug 13 06:42:56 PM PDT 24
Finished Aug 13 06:42:57 PM PDT 24
Peak memory 200632 kb
Host smart-a9fffe59-6de3-46c2-a0a0-323d1c219011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065905853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4065905853
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.81662239
Short name T446
Test name
Test status
Simulation time 72871376 ps
CPU time 0.88 seconds
Started Aug 13 06:43:13 PM PDT 24
Finished Aug 13 06:43:14 PM PDT 24
Peak memory 200564 kb
Host smart-732af148-de22-4c69-ada4-0478de3530a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81662239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.81662239
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1379546188
Short name T436
Test name
Test status
Simulation time 2373414996 ps
CPU time 8.84 seconds
Started Aug 13 06:43:11 PM PDT 24
Finished Aug 13 06:43:20 PM PDT 24
Peak memory 218168 kb
Host smart-033c7b64-81c5-44a8-99dd-4869632f48f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379546188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1379546188
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3291273706
Short name T292
Test name
Test status
Simulation time 245906534 ps
CPU time 1.04 seconds
Started Aug 13 06:42:54 PM PDT 24
Finished Aug 13 06:42:55 PM PDT 24
Peak memory 217844 kb
Host smart-b0c0c407-030b-43b2-b7e6-4d658095ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291273706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3291273706
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.2918470178
Short name T18
Test name
Test status
Simulation time 130737006 ps
CPU time 0.82 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:08 PM PDT 24
Peak memory 200368 kb
Host smart-219eb614-9001-4e4c-a371-9d63485c646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918470178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2918470178
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.4256245827
Short name T500
Test name
Test status
Simulation time 1437423461 ps
CPU time 6.05 seconds
Started Aug 13 06:42:57 PM PDT 24
Finished Aug 13 06:43:03 PM PDT 24
Peak memory 200796 kb
Host smart-08f90805-4b62-41d5-87fc-e8c90bc7a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256245827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.4256245827
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2895391402
Short name T331
Test name
Test status
Simulation time 104491087 ps
CPU time 1.05 seconds
Started Aug 13 06:43:09 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 200620 kb
Host smart-9ce50c18-3da4-4492-8763-cced256b7130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895391402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2895391402
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.552868108
Short name T383
Test name
Test status
Simulation time 122821746 ps
CPU time 1.3 seconds
Started Aug 13 06:43:26 PM PDT 24
Finished Aug 13 06:43:28 PM PDT 24
Peak memory 200788 kb
Host smart-63585070-abca-49b1-8fac-d412b9205298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552868108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.552868108
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2906441931
Short name T392
Test name
Test status
Simulation time 4124431375 ps
CPU time 19.74 seconds
Started Aug 13 06:43:01 PM PDT 24
Finished Aug 13 06:43:21 PM PDT 24
Peak memory 209100 kb
Host smart-c6a63170-41f4-475b-8c22-ef8482a4d53a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906441931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2906441931
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.516740179
Short name T79
Test name
Test status
Simulation time 326949074 ps
CPU time 2.33 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:25 PM PDT 24
Peak memory 200600 kb
Host smart-f2a40fa7-07a7-43c4-a0a1-b18a0f129c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516740179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.516740179
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1558099640
Short name T234
Test name
Test status
Simulation time 234945600 ps
CPU time 1.45 seconds
Started Aug 13 06:43:00 PM PDT 24
Finished Aug 13 06:43:01 PM PDT 24
Peak memory 200768 kb
Host smart-966946d9-ffcd-43c2-94f3-811200a01b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558099640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1558099640
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.2620218249
Short name T417
Test name
Test status
Simulation time 80243854 ps
CPU time 0.79 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 200548 kb
Host smart-5c98f151-82a4-4f41-ace0-ebedc15b62b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620218249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2620218249
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2282929808
Short name T302
Test name
Test status
Simulation time 1899923104 ps
CPU time 7.05 seconds
Started Aug 13 06:43:02 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 221924 kb
Host smart-3ad12787-fc6f-4618-941a-76f3aa712e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282929808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2282929808
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3715395127
Short name T167
Test name
Test status
Simulation time 248583269 ps
CPU time 1.12 seconds
Started Aug 13 06:43:19 PM PDT 24
Finished Aug 13 06:43:20 PM PDT 24
Peak memory 217828 kb
Host smart-c1e0ce47-9e2c-40a2-b5e2-ccdb94b41176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715395127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3715395127
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3776561745
Short name T247
Test name
Test status
Simulation time 182113582 ps
CPU time 0.85 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:42:54 PM PDT 24
Peak memory 200480 kb
Host smart-26172f60-3fb4-417d-92e7-8aa52685901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776561745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3776561745
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.384047443
Short name T177
Test name
Test status
Simulation time 1653137029 ps
CPU time 7.18 seconds
Started Aug 13 06:43:26 PM PDT 24
Finished Aug 13 06:43:33 PM PDT 24
Peak memory 200832 kb
Host smart-c956882d-fae9-47bb-8d96-f7072fc1ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384047443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.384047443
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.286806463
Short name T341
Test name
Test status
Simulation time 95331272 ps
CPU time 1.03 seconds
Started Aug 13 06:43:16 PM PDT 24
Finished Aug 13 06:43:17 PM PDT 24
Peak memory 200680 kb
Host smart-4561593b-f3ba-4ebe-9a0e-82fc076b86c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286806463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.286806463
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.644186003
Short name T405
Test name
Test status
Simulation time 256958016 ps
CPU time 1.59 seconds
Started Aug 13 06:43:07 PM PDT 24
Finished Aug 13 06:43:09 PM PDT 24
Peak memory 200764 kb
Host smart-9d9d2f6b-731e-46af-9223-0363bd82af6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644186003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.644186003
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.1795559348
Short name T98
Test name
Test status
Simulation time 8934520795 ps
CPU time 35.19 seconds
Started Aug 13 06:43:09 PM PDT 24
Finished Aug 13 06:43:44 PM PDT 24
Peak memory 209044 kb
Host smart-551ae487-c7c2-4bf9-bbac-3b565f3266bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795559348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.1795559348
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.797490060
Short name T258
Test name
Test status
Simulation time 125021946 ps
CPU time 1.64 seconds
Started Aug 13 06:43:08 PM PDT 24
Finished Aug 13 06:43:10 PM PDT 24
Peak memory 208768 kb
Host smart-31c6ce3e-845f-4718-bf0b-6bd4f377236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797490060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.797490060
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2331909853
Short name T232
Test name
Test status
Simulation time 77164850 ps
CPU time 0.82 seconds
Started Aug 13 06:43:12 PM PDT 24
Finished Aug 13 06:43:13 PM PDT 24
Peak memory 200632 kb
Host smart-a1294668-72b3-46c8-ae18-ee7122cddc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331909853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2331909853
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.4293523252
Short name T481
Test name
Test status
Simulation time 75323994 ps
CPU time 0.78 seconds
Started Aug 13 06:43:20 PM PDT 24
Finished Aug 13 06:43:21 PM PDT 24
Peak memory 200540 kb
Host smart-77a82f2a-b0f0-47ee-bac7-62c014f8d5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293523252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4293523252
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3756658414
Short name T350
Test name
Test status
Simulation time 2354261388 ps
CPU time 9.25 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:32 PM PDT 24
Peak memory 221896 kb
Host smart-24303565-ee5d-4f58-96b6-3593e86bdd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756658414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3756658414
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1805510555
Short name T251
Test name
Test status
Simulation time 243524938 ps
CPU time 1.07 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 217808 kb
Host smart-b4f694ba-5a41-485e-9f90-ea51ac78eb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805510555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1805510555
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2502347158
Short name T519
Test name
Test status
Simulation time 194036358 ps
CPU time 0.94 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 200372 kb
Host smart-e9f04110-653a-46e0-bbd8-938978e716b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502347158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2502347158
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.2287371917
Short name T318
Test name
Test status
Simulation time 1706170689 ps
CPU time 6.53 seconds
Started Aug 13 06:43:21 PM PDT 24
Finished Aug 13 06:43:28 PM PDT 24
Peak memory 200828 kb
Host smart-5e66bc0e-38a4-4926-a025-49e4e90343f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287371917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2287371917
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.449721302
Short name T192
Test name
Test status
Simulation time 113078983 ps
CPU time 0.97 seconds
Started Aug 13 06:43:23 PM PDT 24
Finished Aug 13 06:43:24 PM PDT 24
Peak memory 200568 kb
Host smart-f5a29a02-1e38-4166-b4fb-2bf322603f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449721302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.449721302
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1512309526
Short name T368
Test name
Test status
Simulation time 206166030 ps
CPU time 1.46 seconds
Started Aug 13 06:43:14 PM PDT 24
Finished Aug 13 06:43:16 PM PDT 24
Peak memory 200828 kb
Host smart-05424ae0-ef0c-4cb4-abe4-323cb6c148b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512309526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1512309526
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2593981130
Short name T117
Test name
Test status
Simulation time 5367440450 ps
CPU time 18.36 seconds
Started Aug 13 06:42:53 PM PDT 24
Finished Aug 13 06:43:12 PM PDT 24
Peak memory 209020 kb
Host smart-40b7ddb2-a88c-4ebd-ade8-6983fc54acf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593981130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2593981130
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3395321548
Short name T49
Test name
Test status
Simulation time 135730669 ps
CPU time 1.69 seconds
Started Aug 13 06:43:03 PM PDT 24
Finished Aug 13 06:43:04 PM PDT 24
Peak memory 208724 kb
Host smart-eaca053b-4a94-4121-af15-6de175c45693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395321548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3395321548
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.4286657758
Short name T354
Test name
Test status
Simulation time 216357617 ps
CPU time 1.32 seconds
Started Aug 13 06:43:18 PM PDT 24
Finished Aug 13 06:43:19 PM PDT 24
Peak memory 200572 kb
Host smart-76ea6b66-2d0d-4ea5-969a-20c526e0e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286657758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.4286657758
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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