Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7868

1

T3

7

T5

111

T6

6

auto[1]

10953

1

T1

4

T2

4

T3

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5875	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6294	1			T1	2		T2	2		T3	1
reset_info_cp[2]	2934	1			T1	1		T2	1		T5	35
reset_info_cp[4]	3786	1			T1	1		T2	1		T5	51
reset_info_cp[8]	108	1			T5	1		T11	1		T24	1
reset_info_cp[16]	111	1			T3	1		T11	2		T69	1
reset_info_cp[32]	111	1			T5	1		T10	2		T11	1
reset_info_cp[64]	108	1			T5	1		T10	3		T24	1
reset_info_cp[128]	114	1			T5	1		T6	1		T10	4

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2949	1			T5	39		T10	58		T11	49
reset_info_cp[1]	auto[1]	2725	1			T1	1		T2	1		T5	42
reset_info_cp[2]	auto[0]	911	1			T5	15		T10	24		T11	19
reset_info_cp[2]	auto[1]	2023	1			T1	1		T2	1		T5	20
reset_info_cp[4]	auto[0]	1323	1			T5	24		T10	30		T11	28
reset_info_cp[4]	auto[1]	2463	1			T1	1		T2	1		T5	27
reset_info_cp[8]	auto[0]	38	1			T69	1		T85	1		T87	1
reset_info_cp[8]	auto[1]	70	1			T5	1		T11	1		T24	1
reset_info_cp[16]	auto[0]	47	1			T3	1		T48	1		T87	1
reset_info_cp[16]	auto[1]	64	1			T11	2		T69	1		T42	1
reset_info_cp[32]	auto[0]	43	1			T10	1		T69	2		T71	2
reset_info_cp[32]	auto[1]	68	1			T5	1		T10	1		T11	1
reset_info_cp[64]	auto[0]	33	1			T10	1		T69	1		T71	1
reset_info_cp[64]	auto[1]	75	1			T5	1		T10	2		T24	1
reset_info_cp[128]	auto[0]	41	1			T5	1		T6	1		T10	2
reset_info_cp[128]	auto[1]	73	1			T10	2		T124	1		T43	1