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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T536 /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1111730179 Aug 14 05:11:23 PM PDT 24 Aug 14 05:11:25 PM PDT 24 244409173 ps
T537 /workspace/coverage/default/23.rstmgr_smoke.1909834412 Aug 14 05:10:37 PM PDT 24 Aug 14 05:10:38 PM PDT 24 235454760 ps
T538 /workspace/coverage/default/29.rstmgr_sw_rst.2411468639 Aug 14 05:10:54 PM PDT 24 Aug 14 05:10:56 PM PDT 24 141454762 ps
T539 /workspace/coverage/default/21.rstmgr_sw_rst.2407123760 Aug 14 05:10:26 PM PDT 24 Aug 14 05:10:28 PM PDT 24 137947595 ps
T540 /workspace/coverage/default/45.rstmgr_smoke.3028899314 Aug 14 05:11:28 PM PDT 24 Aug 14 05:11:29 PM PDT 24 111572160 ps
T56 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2178541526 Aug 14 04:30:16 PM PDT 24 Aug 14 04:30:20 PM PDT 24 934989936 ps
T59 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2106017538 Aug 14 04:30:43 PM PDT 24 Aug 14 04:30:47 PM PDT 24 638834661 ps
T57 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1009995193 Aug 14 04:30:20 PM PDT 24 Aug 14 04:30:21 PM PDT 24 125284360 ps
T60 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4060966313 Aug 14 04:30:35 PM PDT 24 Aug 14 04:30:38 PM PDT 24 198650812 ps
T58 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.929079704 Aug 14 04:30:21 PM PDT 24 Aug 14 04:30:23 PM PDT 24 196112922 ps
T74 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2750955320 Aug 14 04:30:38 PM PDT 24 Aug 14 04:30:40 PM PDT 24 496746260 ps
T75 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2986296584 Aug 14 04:30:30 PM PDT 24 Aug 14 04:30:31 PM PDT 24 137773687 ps
T100 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.594349407 Aug 14 04:30:50 PM PDT 24 Aug 14 04:30:52 PM PDT 24 415777769 ps
T123 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3420892881 Aug 14 04:30:18 PM PDT 24 Aug 14 04:30:22 PM PDT 24 805112295 ps
T541 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1248193975 Aug 14 04:30:23 PM PDT 24 Aug 14 04:30:28 PM PDT 24 483908109 ps
T76 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.338001421 Aug 14 04:30:23 PM PDT 24 Aug 14 04:30:26 PM PDT 24 888295168 ps
T77 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3763148662 Aug 14 04:30:26 PM PDT 24 Aug 14 04:30:28 PM PDT 24 137249032 ps
T78 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3119113895 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:32 PM PDT 24 180236079 ps
T79 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2513188104 Aug 14 04:30:26 PM PDT 24 Aug 14 04:30:28 PM PDT 24 112079578 ps
T542 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3141913537 Aug 14 04:30:23 PM PDT 24 Aug 14 04:30:26 PM PDT 24 276455842 ps
T90 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1211955634 Aug 14 04:30:33 PM PDT 24 Aug 14 04:30:34 PM PDT 24 61355203 ps
T80 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2783630402 Aug 14 04:30:12 PM PDT 24 Aug 14 04:30:13 PM PDT 24 123541704 ps
T543 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.183603861 Aug 14 04:30:48 PM PDT 24 Aug 14 04:30:51 PM PDT 24 77696460 ps
T91 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3917431608 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:30 PM PDT 24 62275797 ps
T92 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1958298190 Aug 14 04:30:23 PM PDT 24 Aug 14 04:30:24 PM PDT 24 69289235 ps
T544 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.329676756 Aug 14 04:30:12 PM PDT 24 Aug 14 04:30:12 PM PDT 24 69194037 ps
T93 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.118157569 Aug 14 04:30:26 PM PDT 24 Aug 14 04:30:27 PM PDT 24 59531125 ps
T107 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3550881830 Aug 14 04:30:36 PM PDT 24 Aug 14 04:30:39 PM PDT 24 181816627 ps
T94 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3048219601 Aug 14 04:30:27 PM PDT 24 Aug 14 04:30:28 PM PDT 24 101649677 ps
T545 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2185575422 Aug 14 04:30:26 PM PDT 24 Aug 14 04:30:27 PM PDT 24 81664791 ps
T95 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2061178943 Aug 14 04:30:42 PM PDT 24 Aug 14 04:30:43 PM PDT 24 72707368 ps
T546 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2273431857 Aug 14 04:30:46 PM PDT 24 Aug 14 04:30:47 PM PDT 24 194616326 ps
T119 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.864522029 Aug 14 04:30:27 PM PDT 24 Aug 14 04:30:30 PM PDT 24 473537930 ps
T547 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2549489861 Aug 14 04:30:39 PM PDT 24 Aug 14 04:30:40 PM PDT 24 181039565 ps
T548 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.308846498 Aug 14 04:30:11 PM PDT 24 Aug 14 04:30:20 PM PDT 24 1991428680 ps
T101 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1529534633 Aug 14 04:30:17 PM PDT 24 Aug 14 04:30:20 PM PDT 24 793920364 ps
T549 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.54090974 Aug 14 04:30:33 PM PDT 24 Aug 14 04:30:35 PM PDT 24 474486501 ps
T96 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2619878596 Aug 14 04:30:15 PM PDT 24 Aug 14 04:30:16 PM PDT 24 86322932 ps
T97 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3016689776 Aug 14 04:30:22 PM PDT 24 Aug 14 04:30:23 PM PDT 24 64828312 ps
T550 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1323007326 Aug 14 04:30:26 PM PDT 24 Aug 14 04:30:27 PM PDT 24 88995470 ps
T551 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.659903317 Aug 14 04:30:25 PM PDT 24 Aug 14 04:30:28 PM PDT 24 183235260 ps
T98 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.362590420 Aug 14 04:30:14 PM PDT 24 Aug 14 04:30:15 PM PDT 24 143872653 ps
T552 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3797365593 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:30 PM PDT 24 181027218 ps
T99 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.885430686 Aug 14 04:30:43 PM PDT 24 Aug 14 04:30:45 PM PDT 24 136033428 ps
T553 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3958473405 Aug 14 04:30:28 PM PDT 24 Aug 14 04:30:29 PM PDT 24 106404559 ps
T554 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.221505691 Aug 14 04:30:13 PM PDT 24 Aug 14 04:30:15 PM PDT 24 84442811 ps
T555 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2456161943 Aug 14 04:30:42 PM PDT 24 Aug 14 04:30:43 PM PDT 24 57165608 ps
T556 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3174633702 Aug 14 04:30:19 PM PDT 24 Aug 14 04:30:20 PM PDT 24 125773553 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3802134303 Aug 14 04:30:27 PM PDT 24 Aug 14 04:30:30 PM PDT 24 428691485 ps
T558 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2412962590 Aug 14 04:30:35 PM PDT 24 Aug 14 04:30:37 PM PDT 24 151200125 ps
T559 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3805011955 Aug 14 04:30:37 PM PDT 24 Aug 14 04:30:38 PM PDT 24 62744069 ps
T560 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1694834892 Aug 14 04:30:49 PM PDT 24 Aug 14 04:30:50 PM PDT 24 103654473 ps
T561 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2432575798 Aug 14 04:30:21 PM PDT 24 Aug 14 04:30:24 PM PDT 24 948747843 ps
T562 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.118887539 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:45 PM PDT 24 118706701 ps
T563 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2499672823 Aug 14 04:30:28 PM PDT 24 Aug 14 04:30:32 PM PDT 24 577155526 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2264571119 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:45 PM PDT 24 125957362 ps
T565 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1838212210 Aug 14 04:30:27 PM PDT 24 Aug 14 04:30:28 PM PDT 24 80022359 ps
T566 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4268966705 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:33 PM PDT 24 599446742 ps
T567 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3889300487 Aug 14 04:30:21 PM PDT 24 Aug 14 04:30:22 PM PDT 24 136367111 ps
T568 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.986753713 Aug 14 04:30:23 PM PDT 24 Aug 14 04:30:24 PM PDT 24 88785595 ps
T569 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1730030334 Aug 14 04:30:17 PM PDT 24 Aug 14 04:30:20 PM PDT 24 414738149 ps
T102 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.980432266 Aug 14 04:30:33 PM PDT 24 Aug 14 04:30:36 PM PDT 24 901319819 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.184666623 Aug 14 04:30:21 PM PDT 24 Aug 14 04:30:21 PM PDT 24 60205524 ps
T571 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2263402929 Aug 14 04:30:19 PM PDT 24 Aug 14 04:30:21 PM PDT 24 107778190 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.296751872 Aug 14 04:30:36 PM PDT 24 Aug 14 04:30:37 PM PDT 24 187539279 ps
T573 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2126043878 Aug 14 04:30:40 PM PDT 24 Aug 14 04:30:41 PM PDT 24 166999997 ps
T574 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1346695904 Aug 14 04:30:25 PM PDT 24 Aug 14 04:30:27 PM PDT 24 194248661 ps
T575 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.215156293 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:31 PM PDT 24 224916930 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3002567267 Aug 14 04:30:38 PM PDT 24 Aug 14 04:30:40 PM PDT 24 247320602 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3354143212 Aug 14 04:30:24 PM PDT 24 Aug 14 04:30:25 PM PDT 24 103071300 ps
T578 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4130509315 Aug 14 04:30:34 PM PDT 24 Aug 14 04:30:36 PM PDT 24 176948363 ps
T579 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3725874413 Aug 14 04:30:20 PM PDT 24 Aug 14 04:30:22 PM PDT 24 232576481 ps
T580 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3117692815 Aug 14 04:30:19 PM PDT 24 Aug 14 04:30:21 PM PDT 24 226159786 ps
T581 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2150036929 Aug 14 04:30:35 PM PDT 24 Aug 14 04:30:36 PM PDT 24 116652053 ps
T582 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.100619290 Aug 14 04:30:25 PM PDT 24 Aug 14 04:30:29 PM PDT 24 577500900 ps
T583 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1602643068 Aug 14 04:30:27 PM PDT 24 Aug 14 04:30:28 PM PDT 24 132775195 ps
T584 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2136059799 Aug 14 04:30:35 PM PDT 24 Aug 14 04:30:35 PM PDT 24 72285400 ps
T585 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2246683937 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:36 PM PDT 24 103901643 ps
T586 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3513470955 Aug 14 04:30:24 PM PDT 24 Aug 14 04:30:26 PM PDT 24 128318204 ps
T587 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.19568195 Aug 14 04:30:34 PM PDT 24 Aug 14 04:30:43 PM PDT 24 603112618 ps
T588 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3896877854 Aug 14 04:30:11 PM PDT 24 Aug 14 04:30:14 PM PDT 24 394570562 ps
T589 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3574455804 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:30 PM PDT 24 68689585 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.672339407 Aug 14 04:30:28 PM PDT 24 Aug 14 04:30:31 PM PDT 24 277068695 ps
T591 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3195850847 Aug 14 04:30:25 PM PDT 24 Aug 14 04:30:26 PM PDT 24 97867938 ps
T592 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1134136771 Aug 14 04:30:31 PM PDT 24 Aug 14 04:30:33 PM PDT 24 164196085 ps
T593 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1677636920 Aug 14 04:30:30 PM PDT 24 Aug 14 04:30:31 PM PDT 24 80622491 ps
T594 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2026635227 Aug 14 04:30:28 PM PDT 24 Aug 14 04:30:30 PM PDT 24 488290319 ps
T595 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.346488152 Aug 14 04:30:21 PM PDT 24 Aug 14 04:30:24 PM PDT 24 370493825 ps
T104 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1296661749 Aug 14 04:30:28 PM PDT 24 Aug 14 04:30:30 PM PDT 24 431785502 ps
T596 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.852995206 Aug 14 04:30:30 PM PDT 24 Aug 14 04:30:31 PM PDT 24 137407300 ps
T597 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3495824356 Aug 14 04:30:19 PM PDT 24 Aug 14 04:30:20 PM PDT 24 136236957 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3743735094 Aug 14 04:30:18 PM PDT 24 Aug 14 04:30:19 PM PDT 24 91038959 ps
T599 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4155165131 Aug 14 04:30:23 PM PDT 24 Aug 14 04:30:25 PM PDT 24 180275151 ps
T600 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1783246139 Aug 14 04:30:19 PM PDT 24 Aug 14 04:30:21 PM PDT 24 185857605 ps
T601 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2482720497 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:30 PM PDT 24 85367403 ps
T120 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.282969453 Aug 14 04:30:21 PM PDT 24 Aug 14 04:30:23 PM PDT 24 435413900 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2951495324 Aug 14 04:30:38 PM PDT 24 Aug 14 04:30:41 PM PDT 24 393158254 ps
T603 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2629241415 Aug 14 04:30:15 PM PDT 24 Aug 14 04:30:17 PM PDT 24 141666838 ps
T604 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2190417971 Aug 14 04:30:48 PM PDT 24 Aug 14 04:30:50 PM PDT 24 122533837 ps
T103 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2270456799 Aug 14 04:30:20 PM PDT 24 Aug 14 04:30:24 PM PDT 24 792069475 ps
T605 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1790244695 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:44 PM PDT 24 84078767 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.177222284 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:46 PM PDT 24 234582384 ps
T121 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2296878807 Aug 14 04:30:20 PM PDT 24 Aug 14 04:30:23 PM PDT 24 865498945 ps
T607 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3919406712 Aug 14 04:30:29 PM PDT 24 Aug 14 04:30:30 PM PDT 24 96035790 ps
T608 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4222093055 Aug 14 04:30:17 PM PDT 24 Aug 14 04:30:24 PM PDT 24 110157204 ps
T105 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.940887378 Aug 14 04:30:15 PM PDT 24 Aug 14 04:30:17 PM PDT 24 459452234 ps
T609 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.625134532 Aug 14 04:30:35 PM PDT 24 Aug 14 04:30:36 PM PDT 24 219484167 ps
T610 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2492817692 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:46 PM PDT 24 473619866 ps
T611 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4158805089 Aug 14 04:30:21 PM PDT 24 Aug 14 04:30:22 PM PDT 24 107771831 ps
T612 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1189478638 Aug 14 04:30:37 PM PDT 24 Aug 14 04:30:43 PM PDT 24 96580016 ps
T122 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.213815543 Aug 14 04:30:22 PM PDT 24 Aug 14 04:30:24 PM PDT 24 489789962 ps
T613 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1900273310 Aug 14 04:30:42 PM PDT 24 Aug 14 04:30:43 PM PDT 24 132565753 ps
T614 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1507150328 Aug 14 04:30:17 PM PDT 24 Aug 14 04:30:19 PM PDT 24 154832282 ps
T615 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3031638425 Aug 14 04:30:37 PM PDT 24 Aug 14 04:30:38 PM PDT 24 155773741 ps
T616 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.129027179 Aug 14 04:30:44 PM PDT 24 Aug 14 04:30:46 PM PDT 24 91445368 ps
T617 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1864411963 Aug 14 04:30:45 PM PDT 24 Aug 14 04:30:45 PM PDT 24 63398251 ps
T618 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1280272362 Aug 14 04:30:22 PM PDT 24 Aug 14 04:30:24 PM PDT 24 418293142 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.820877344 Aug 14 04:30:22 PM PDT 24 Aug 14 04:30:24 PM PDT 24 174246375 ps
T106 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3272380861 Aug 14 04:30:24 PM PDT 24 Aug 14 04:30:27 PM PDT 24 793698698 ps
T620 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3215158588 Aug 14 04:30:31 PM PDT 24 Aug 14 04:30:34 PM PDT 24 922711217 ps

Test location /workspace/coverage/default/25.rstmgr_stress_all.1638441431
Short name T10
Test name
Test status
Simulation time 6207614674 ps
CPU time 27.31 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:11:17 PM PDT 24
Peak memory 209084 kb
Host smart-b5f214e4-3907-45a5-a78a-22636f7ebbce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638441431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1638441431
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1728975595
Short name T25
Test name
Test status
Simulation time 240481459 ps
CPU time 1.44 seconds
Started Aug 14 05:10:35 PM PDT 24
Finished Aug 14 05:10:37 PM PDT 24
Peak memory 200820 kb
Host smart-0cf2f41b-6933-4b54-8480-351b6fdfb529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728975595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1728975595
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1009995193
Short name T57
Test name
Test status
Simulation time 125284360 ps
CPU time 1.34 seconds
Started Aug 14 04:30:20 PM PDT 24
Finished Aug 14 04:30:21 PM PDT 24
Peak memory 209144 kb
Host smart-1cbfab9d-3dfc-41b1-aea4-b4747cf8e545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009995193 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1009995193
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.355288228
Short name T62
Test name
Test status
Simulation time 16494754810 ps
CPU time 30.64 seconds
Started Aug 14 05:09:15 PM PDT 24
Finished Aug 14 05:09:46 PM PDT 24
Peak memory 217304 kb
Host smart-d25c5fcd-d343-43c6-a7dd-cd91bfe0c85d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355288228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.355288228
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.1009676905
Short name T42
Test name
Test status
Simulation time 1220453481 ps
CPU time 5.75 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:56 PM PDT 24
Peak memory 218000 kb
Host smart-fccfef58-2707-4e98-aacc-e8d063082d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009676905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1009676905
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1009443699
Short name T49
Test name
Test status
Simulation time 408572745 ps
CPU time 2.44 seconds
Started Aug 14 05:09:23 PM PDT 24
Finished Aug 14 05:09:25 PM PDT 24
Peak memory 208932 kb
Host smart-4bf3d783-0162-4347-b90b-02f8ff68329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009443699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1009443699
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.338001421
Short name T76
Test name
Test status
Simulation time 888295168 ps
CPU time 2.98 seconds
Started Aug 14 04:30:23 PM PDT 24
Finished Aug 14 04:30:26 PM PDT 24
Peak memory 200888 kb
Host smart-d31a597f-af4a-4965-9544-bba43a17df61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338001421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
338001421
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3369052679
Short name T35
Test name
Test status
Simulation time 79029040 ps
CPU time 0.8 seconds
Started Aug 14 05:10:13 PM PDT 24
Finished Aug 14 05:10:14 PM PDT 24
Peak memory 200448 kb
Host smart-b63970e0-ee48-4703-8c01-b5ba927f3258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369052679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3369052679
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.1599170037
Short name T87
Test name
Test status
Simulation time 7096286972 ps
CPU time 24.17 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 209064 kb
Host smart-4637bf40-8d44-4549-9c3c-2428c5d9ebc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599170037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1599170037
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.726014397
Short name T118
Test name
Test status
Simulation time 187539303 ps
CPU time 1.23 seconds
Started Aug 14 05:09:16 PM PDT 24
Finished Aug 14 05:09:17 PM PDT 24
Peak memory 200620 kb
Host smart-1bdfa57a-2e96-407d-802b-3a16332e7074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726014397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.726014397
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2106017538
Short name T59
Test name
Test status
Simulation time 638834661 ps
CPU time 3.84 seconds
Started Aug 14 04:30:43 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 209100 kb
Host smart-4748fef4-3889-40c1-9a9e-e70d33717ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106017538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2106017538
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3067141575
Short name T29
Test name
Test status
Simulation time 2173096459 ps
CPU time 7.87 seconds
Started Aug 14 05:09:12 PM PDT 24
Finished Aug 14 05:09:20 PM PDT 24
Peak memory 217832 kb
Host smart-68823aed-204e-4c4c-85f9-b1050c500daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067141575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3067141575
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.3773513290
Short name T43
Test name
Test status
Simulation time 1223376502 ps
CPU time 5.75 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:11:43 PM PDT 24
Peak memory 221916 kb
Host smart-f94408b2-0e05-4646-9942-48ebe0533469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773513290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3773513290
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1529534633
Short name T101
Test name
Test status
Simulation time 793920364 ps
CPU time 2.8 seconds
Started Aug 14 04:30:17 PM PDT 24
Finished Aug 14 04:30:20 PM PDT 24
Peak memory 200960 kb
Host smart-b9dfafbd-9725-4c7e-be4f-46d2b3951adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529534633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1529534633
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3272380861
Short name T106
Test name
Test status
Simulation time 793698698 ps
CPU time 2.71 seconds
Started Aug 14 04:30:24 PM PDT 24
Finished Aug 14 04:30:27 PM PDT 24
Peak memory 201012 kb
Host smart-921777fe-04d7-4da2-9f45-10f929b2daf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272380861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3272380861
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2474384724
Short name T246
Test name
Test status
Simulation time 128904055 ps
CPU time 1.09 seconds
Started Aug 14 05:09:15 PM PDT 24
Finished Aug 14 05:09:16 PM PDT 24
Peak memory 200632 kb
Host smart-78d99626-2151-4f4e-9adf-e448a6ee40be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474384724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2474384724
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2619878596
Short name T96
Test name
Test status
Simulation time 86322932 ps
CPU time 0.95 seconds
Started Aug 14 04:30:15 PM PDT 24
Finished Aug 14 04:30:16 PM PDT 24
Peak memory 200704 kb
Host smart-d3dc4350-05f9-471b-8ce4-47f1e20127e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619878596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2619878596
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3033786132
Short name T14
Test name
Test status
Simulation time 131621952 ps
CPU time 0.84 seconds
Started Aug 14 05:10:01 PM PDT 24
Finished Aug 14 05:10:02 PM PDT 24
Peak memory 200468 kb
Host smart-78c7d978-9855-4999-93f1-bdd9412a7367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033786132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3033786132
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.391531100
Short name T200
Test name
Test status
Simulation time 1223329409 ps
CPU time 6.03 seconds
Started Aug 14 05:09:15 PM PDT 24
Finished Aug 14 05:09:21 PM PDT 24
Peak memory 221928 kb
Host smart-f98db7df-f774-4175-b767-20c39bcdca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391531100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.391531100
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1296661749
Short name T104
Test name
Test status
Simulation time 431785502 ps
CPU time 1.91 seconds
Started Aug 14 04:30:28 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 200876 kb
Host smart-ee319342-323b-4d40-919b-b593c83e8803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296661749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1296661749
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3217572468
Short name T37
Test name
Test status
Simulation time 149445554 ps
CPU time 1.82 seconds
Started Aug 14 05:10:10 PM PDT 24
Finished Aug 14 05:10:12 PM PDT 24
Peak memory 200552 kb
Host smart-5957b6c5-9f8d-490a-955d-1f254ea0e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217572468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3217572468
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.625134532
Short name T609
Test name
Test status
Simulation time 219484167 ps
CPU time 1.52 seconds
Started Aug 14 04:30:35 PM PDT 24
Finished Aug 14 04:30:36 PM PDT 24
Peak memory 200812 kb
Host smart-df75f79e-9446-4366-a412-c2b4ad8aaac6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625134532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.625134532
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1248193975
Short name T541
Test name
Test status
Simulation time 483908109 ps
CPU time 5.61 seconds
Started Aug 14 04:30:23 PM PDT 24
Finished Aug 14 04:30:28 PM PDT 24
Peak memory 200908 kb
Host smart-21f8f622-e2e7-4475-ab27-313610ed3e0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248193975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
248193975
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3743735094
Short name T598
Test name
Test status
Simulation time 91038959 ps
CPU time 0.8 seconds
Started Aug 14 04:30:18 PM PDT 24
Finished Aug 14 04:30:19 PM PDT 24
Peak memory 200572 kb
Host smart-8f0f2815-8cc4-461c-8af9-a24e1ff9c2b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743735094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
743735094
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1346695904
Short name T574
Test name
Test status
Simulation time 194248661 ps
CPU time 1.95 seconds
Started Aug 14 04:30:25 PM PDT 24
Finished Aug 14 04:30:27 PM PDT 24
Peak memory 209072 kb
Host smart-fe25a1a1-9577-424f-a5c2-0aeaa4b75639
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346695904 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1346695904
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1838212210
Short name T565
Test name
Test status
Simulation time 80022359 ps
CPU time 0.87 seconds
Started Aug 14 04:30:27 PM PDT 24
Finished Aug 14 04:30:28 PM PDT 24
Peak memory 200652 kb
Host smart-62c8eadf-e9bb-4cf4-943f-c7289a921b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838212210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1838212210
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2150036929
Short name T581
Test name
Test status
Simulation time 116652053 ps
CPU time 0.96 seconds
Started Aug 14 04:30:35 PM PDT 24
Finished Aug 14 04:30:36 PM PDT 24
Peak memory 200744 kb
Host smart-cf1078f1-b2f8-4a73-9e27-cc970fb78c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150036929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2150036929
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2783630402
Short name T80
Test name
Test status
Simulation time 123541704 ps
CPU time 1.76 seconds
Started Aug 14 04:30:12 PM PDT 24
Finished Aug 14 04:30:13 PM PDT 24
Peak memory 209032 kb
Host smart-89cbc604-5679-4236-b7d4-2d5ff597a73f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783630402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2783630402
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3002567267
Short name T576
Test name
Test status
Simulation time 247320602 ps
CPU time 1.67 seconds
Started Aug 14 04:30:38 PM PDT 24
Finished Aug 14 04:30:40 PM PDT 24
Peak memory 200756 kb
Host smart-00d0f6bb-698a-49ac-82e6-8459bdc78d62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002567267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
002567267
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.308846498
Short name T548
Test name
Test status
Simulation time 1991428680 ps
CPU time 9.04 seconds
Started Aug 14 04:30:11 PM PDT 24
Finished Aug 14 04:30:20 PM PDT 24
Peak memory 200844 kb
Host smart-575c7f83-a236-452b-b4c2-e95898d7bd2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308846498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.308846498
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3495824356
Short name T597
Test name
Test status
Simulation time 136236957 ps
CPU time 0.98 seconds
Started Aug 14 04:30:19 PM PDT 24
Finished Aug 14 04:30:20 PM PDT 24
Peak memory 200948 kb
Host smart-68e160bb-4e62-4a43-8b35-ac33577e6647
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495824356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
495824356
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.4155165131
Short name T599
Test name
Test status
Simulation time 180275151 ps
CPU time 1.67 seconds
Started Aug 14 04:30:23 PM PDT 24
Finished Aug 14 04:30:25 PM PDT 24
Peak memory 209200 kb
Host smart-83341f54-2e49-43fd-90ef-a8d2e5ef9fbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155165131 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.4155165131
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2136059799
Short name T584
Test name
Test status
Simulation time 72285400 ps
CPU time 0.75 seconds
Started Aug 14 04:30:35 PM PDT 24
Finished Aug 14 04:30:35 PM PDT 24
Peak memory 200636 kb
Host smart-ae73c685-6af1-4106-98cb-54f8169a7270
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136059799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2136059799
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3117692815
Short name T580
Test name
Test status
Simulation time 226159786 ps
CPU time 1.64 seconds
Started Aug 14 04:30:19 PM PDT 24
Finished Aug 14 04:30:21 PM PDT 24
Peak memory 209084 kb
Host smart-d6b29d9a-84c2-4d9e-91b8-bca74232e8d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117692815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3117692815
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2432575798
Short name T561
Test name
Test status
Simulation time 948747843 ps
CPU time 2.93 seconds
Started Aug 14 04:30:21 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 200976 kb
Host smart-61c10353-faa8-4b1c-8a45-f5384a4f527f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432575798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2432575798
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3889300487
Short name T567
Test name
Test status
Simulation time 136367111 ps
CPU time 0.98 seconds
Started Aug 14 04:30:21 PM PDT 24
Finished Aug 14 04:30:22 PM PDT 24
Peak memory 200796 kb
Host smart-2f3d3143-1c9a-4d9f-b927-b467fabc170c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889300487 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3889300487
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1677636920
Short name T593
Test name
Test status
Simulation time 80622491 ps
CPU time 0.75 seconds
Started Aug 14 04:30:30 PM PDT 24
Finished Aug 14 04:30:31 PM PDT 24
Peak memory 200636 kb
Host smart-bdafff42-b808-4b2b-b3c7-ee52843ab899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677636920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1677636920
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.986753713
Short name T568
Test name
Test status
Simulation time 88785595 ps
CPU time 1.01 seconds
Started Aug 14 04:30:23 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 200732 kb
Host smart-637992e2-1bb5-43b4-bed0-f17f7bddf961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986753713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_sa
me_csr_outstanding.986753713
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.659903317
Short name T551
Test name
Test status
Simulation time 183235260 ps
CPU time 2.68 seconds
Started Aug 14 04:30:25 PM PDT 24
Finished Aug 14 04:30:28 PM PDT 24
Peak memory 212532 kb
Host smart-15ce4938-4a37-4a7f-a86e-cc3ee3e00544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659903317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.659903317
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2178541526
Short name T56
Test name
Test status
Simulation time 934989936 ps
CPU time 2.94 seconds
Started Aug 14 04:30:16 PM PDT 24
Finished Aug 14 04:30:20 PM PDT 24
Peak memory 200860 kb
Host smart-6f3165db-930f-4103-a878-f1412223b4aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178541526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2178541526
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2412962590
Short name T558
Test name
Test status
Simulation time 151200125 ps
CPU time 1.41 seconds
Started Aug 14 04:30:35 PM PDT 24
Finished Aug 14 04:30:37 PM PDT 24
Peak memory 209116 kb
Host smart-ffeed024-0a23-42be-96ad-bebd07dd0872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412962590 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2412962590
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2456161943
Short name T555
Test name
Test status
Simulation time 57165608 ps
CPU time 0.73 seconds
Started Aug 14 04:30:42 PM PDT 24
Finished Aug 14 04:30:43 PM PDT 24
Peak memory 200528 kb
Host smart-0fb53243-c85f-4bd9-9f6f-6561c306b70f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456161943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2456161943
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.885430686
Short name T99
Test name
Test status
Simulation time 136033428 ps
CPU time 1.32 seconds
Started Aug 14 04:30:43 PM PDT 24
Finished Aug 14 04:30:45 PM PDT 24
Peak memory 200816 kb
Host smart-7a9fa139-be2d-414e-a896-63076aa5a6f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885430686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.885430686
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.864522029
Short name T119
Test name
Test status
Simulation time 473537930 ps
CPU time 2 seconds
Started Aug 14 04:30:27 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 200924 kb
Host smart-d9774329-c92f-467e-80c6-85b3d01f8578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864522029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.864522029
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3763148662
Short name T77
Test name
Test status
Simulation time 137249032 ps
CPU time 1.41 seconds
Started Aug 14 04:30:26 PM PDT 24
Finished Aug 14 04:30:28 PM PDT 24
Peak memory 209160 kb
Host smart-ecdf240b-3e78-47bb-b8a2-0331bde187b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763148662 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3763148662
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.183603861
Short name T543
Test name
Test status
Simulation time 77696460 ps
CPU time 0.84 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:30:51 PM PDT 24
Peak memory 200636 kb
Host smart-48510390-94f3-4ee5-8ab6-a2c99758733a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183603861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.183603861
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3031638425
Short name T615
Test name
Test status
Simulation time 155773741 ps
CPU time 1.16 seconds
Started Aug 14 04:30:37 PM PDT 24
Finished Aug 14 04:30:38 PM PDT 24
Peak memory 200724 kb
Host smart-7d76c563-ee4a-40e3-9ba4-11d6d1b22831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031638425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3031638425
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3119113895
Short name T78
Test name
Test status
Simulation time 180236079 ps
CPU time 2.47 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:32 PM PDT 24
Peak memory 209136 kb
Host smart-fe15c150-5000-4b1c-a4c9-b0a82cd039ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119113895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3119113895
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.282969453
Short name T120
Test name
Test status
Simulation time 435413900 ps
CPU time 1.73 seconds
Started Aug 14 04:30:21 PM PDT 24
Finished Aug 14 04:30:23 PM PDT 24
Peak memory 200860 kb
Host smart-edfbd9f1-cfcc-4f21-ac51-e7311831d856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282969453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.282969453
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3195850847
Short name T591
Test name
Test status
Simulation time 97867938 ps
CPU time 0.92 seconds
Started Aug 14 04:30:25 PM PDT 24
Finished Aug 14 04:30:26 PM PDT 24
Peak memory 200788 kb
Host smart-5ab6f3d4-f180-4a2e-9688-a7ba1db77fdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195850847 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3195850847
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.3016689776
Short name T97
Test name
Test status
Simulation time 64828312 ps
CPU time 0.73 seconds
Started Aug 14 04:30:22 PM PDT 24
Finished Aug 14 04:30:23 PM PDT 24
Peak memory 200592 kb
Host smart-95dd31b0-73dc-4d82-9adf-e2e110e67bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016689776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3016689776
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.215156293
Short name T575
Test name
Test status
Simulation time 224916930 ps
CPU time 1.5 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:31 PM PDT 24
Peak memory 200888 kb
Host smart-5d53de2d-11e8-4c8a-8150-46c25ca13657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215156293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.215156293
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1783246139
Short name T600
Test name
Test status
Simulation time 185857605 ps
CPU time 2.57 seconds
Started Aug 14 04:30:19 PM PDT 24
Finished Aug 14 04:30:21 PM PDT 24
Peak memory 209148 kb
Host smart-9026f751-c236-4976-9eb9-e4433ae5187c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783246139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1783246139
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.213815543
Short name T122
Test name
Test status
Simulation time 489789962 ps
CPU time 1.93 seconds
Started Aug 14 04:30:22 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 200880 kb
Host smart-30eca165-5681-49f8-b084-157e2ce40b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213815543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err
.213815543
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.929079704
Short name T58
Test name
Test status
Simulation time 196112922 ps
CPU time 1.38 seconds
Started Aug 14 04:30:21 PM PDT 24
Finished Aug 14 04:30:23 PM PDT 24
Peak memory 208948 kb
Host smart-7a402b2f-1736-404b-bde9-d0c5343bef6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929079704 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.929079704
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.118157569
Short name T93
Test name
Test status
Simulation time 59531125 ps
CPU time 0.82 seconds
Started Aug 14 04:30:26 PM PDT 24
Finished Aug 14 04:30:27 PM PDT 24
Peak memory 200560 kb
Host smart-efb314e3-7889-4795-8b23-1fc2b2ec4541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118157569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.118157569
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1507150328
Short name T614
Test name
Test status
Simulation time 154832282 ps
CPU time 1.14 seconds
Started Aug 14 04:30:17 PM PDT 24
Finished Aug 14 04:30:19 PM PDT 24
Peak memory 200688 kb
Host smart-f8180703-c6c3-461e-a1a8-97b7c6da642e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507150328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.1507150328
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.100619290
Short name T582
Test name
Test status
Simulation time 577500900 ps
CPU time 3.68 seconds
Started Aug 14 04:30:25 PM PDT 24
Finished Aug 14 04:30:29 PM PDT 24
Peak memory 217152 kb
Host smart-0563f639-22c9-428b-9ba9-370fabe13b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100619290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.100619290
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2492817692
Short name T610
Test name
Test status
Simulation time 473619866 ps
CPU time 1.84 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:46 PM PDT 24
Peak memory 200928 kb
Host smart-30cdc53f-0728-4ce5-b129-854e485766f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492817692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2492817692
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2126043878
Short name T573
Test name
Test status
Simulation time 166999997 ps
CPU time 1.15 seconds
Started Aug 14 04:30:40 PM PDT 24
Finished Aug 14 04:30:41 PM PDT 24
Peak memory 208984 kb
Host smart-b78255ab-5f28-4b03-bae9-0214b5ad53b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126043878 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2126043878
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1790244695
Short name T605
Test name
Test status
Simulation time 84078767 ps
CPU time 0.84 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:44 PM PDT 24
Peak memory 200640 kb
Host smart-a7c8c830-9f27-4075-9c32-02ddd9051e26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790244695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1790244695
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2190417971
Short name T604
Test name
Test status
Simulation time 122533837 ps
CPU time 1.15 seconds
Started Aug 14 04:30:48 PM PDT 24
Finished Aug 14 04:30:50 PM PDT 24
Peak memory 200828 kb
Host smart-cf4adb72-2eb0-4aee-8f19-265c0d82dd0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190417971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2190417971
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.2499672823
Short name T563
Test name
Test status
Simulation time 577155526 ps
CPU time 3.97 seconds
Started Aug 14 04:30:28 PM PDT 24
Finished Aug 14 04:30:32 PM PDT 24
Peak memory 209112 kb
Host smart-144d3c20-67ba-4006-9b84-2f2fd5783e81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499672823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2499672823
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2986296584
Short name T75
Test name
Test status
Simulation time 137773687 ps
CPU time 1.07 seconds
Started Aug 14 04:30:30 PM PDT 24
Finished Aug 14 04:30:31 PM PDT 24
Peak memory 200804 kb
Host smart-954ef87d-2fc2-4c6b-a2df-00baf22096b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986296584 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.2986296584
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.3574455804
Short name T589
Test name
Test status
Simulation time 68689585 ps
CPU time 0.76 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 200664 kb
Host smart-e52c10dc-1112-4ca3-9a12-b83875f45b46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574455804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3574455804
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.4158805089
Short name T611
Test name
Test status
Simulation time 107771831 ps
CPU time 1.27 seconds
Started Aug 14 04:30:21 PM PDT 24
Finished Aug 14 04:30:22 PM PDT 24
Peak memory 200840 kb
Host smart-0e9e77bf-82fc-43e3-acf8-9e2405295e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158805089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.4158805089
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4060966313
Short name T60
Test name
Test status
Simulation time 198650812 ps
CPU time 2.72 seconds
Started Aug 14 04:30:35 PM PDT 24
Finished Aug 14 04:30:38 PM PDT 24
Peak memory 209128 kb
Host smart-f06df989-ea69-4e7c-b409-8a2b51ed57d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060966313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4060966313
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2513188104
Short name T79
Test name
Test status
Simulation time 112079578 ps
CPU time 0.95 seconds
Started Aug 14 04:30:26 PM PDT 24
Finished Aug 14 04:30:28 PM PDT 24
Peak memory 200736 kb
Host smart-94dae6df-90d9-4c3c-9379-6b07cce158c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513188104 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.2513188104
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.1323007326
Short name T550
Test name
Test status
Simulation time 88995470 ps
CPU time 0.82 seconds
Started Aug 14 04:30:26 PM PDT 24
Finished Aug 14 04:30:27 PM PDT 24
Peak memory 200624 kb
Host smart-4d1a57c7-779d-49a2-ac78-be12df9df2a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323007326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1323007326
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1189478638
Short name T612
Test name
Test status
Simulation time 96580016 ps
CPU time 1.16 seconds
Started Aug 14 04:30:37 PM PDT 24
Finished Aug 14 04:30:43 PM PDT 24
Peak memory 200912 kb
Host smart-82223ccb-1503-4db1-a397-62335a5e6647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189478638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1189478638
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.19568195
Short name T587
Test name
Test status
Simulation time 603112618 ps
CPU time 3.54 seconds
Started Aug 14 04:30:34 PM PDT 24
Finished Aug 14 04:30:43 PM PDT 24
Peak memory 217148 kb
Host smart-db53fae3-15f8-48b7-a1df-36c90c83a88b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19568195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.19568195
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.594349407
Short name T100
Test name
Test status
Simulation time 415777769 ps
CPU time 1.76 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:30:52 PM PDT 24
Peak memory 200912 kb
Host smart-9c2ee41c-5f4b-4201-b08e-b97cd1b63f78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594349407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.594349407
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.296751872
Short name T572
Test name
Test status
Simulation time 187539279 ps
CPU time 1.24 seconds
Started Aug 14 04:30:36 PM PDT 24
Finished Aug 14 04:30:37 PM PDT 24
Peak memory 209012 kb
Host smart-58b9261f-607e-467c-b65e-b7a5c0d3ff2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296751872 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.296751872
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1864411963
Short name T617
Test name
Test status
Simulation time 63398251 ps
CPU time 0.75 seconds
Started Aug 14 04:30:45 PM PDT 24
Finished Aug 14 04:30:45 PM PDT 24
Peak memory 200664 kb
Host smart-0476ea7a-c89f-4617-aaf0-c98572fa412a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864411963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1864411963
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2482720497
Short name T601
Test name
Test status
Simulation time 85367403 ps
CPU time 0.95 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 200656 kb
Host smart-5bdcbbf1-704d-40e9-b014-2b60c81c81a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482720497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.2482720497
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.177222284
Short name T606
Test name
Test status
Simulation time 234582384 ps
CPU time 1.69 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:46 PM PDT 24
Peak memory 209060 kb
Host smart-6d280513-4cf7-49e3-9272-089da16ac9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177222284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.177222284
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3215158588
Short name T620
Test name
Test status
Simulation time 922711217 ps
CPU time 3.06 seconds
Started Aug 14 04:30:31 PM PDT 24
Finished Aug 14 04:30:34 PM PDT 24
Peak memory 200844 kb
Host smart-0ef88c04-ee57-4992-85ad-69a83254d93a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215158588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.3215158588
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4130509315
Short name T578
Test name
Test status
Simulation time 176948363 ps
CPU time 1.62 seconds
Started Aug 14 04:30:34 PM PDT 24
Finished Aug 14 04:30:36 PM PDT 24
Peak memory 209184 kb
Host smart-a1b5569e-ed9e-447f-a234-ef4b9deec807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130509315 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.4130509315
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3919406712
Short name T607
Test name
Test status
Simulation time 96035790 ps
CPU time 0.91 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 200648 kb
Host smart-74cb1fd0-4636-4615-9a42-8ad2f71de514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919406712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3919406712
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2246683937
Short name T585
Test name
Test status
Simulation time 103901643 ps
CPU time 1.28 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:36 PM PDT 24
Peak memory 201012 kb
Host smart-4b41024c-d39b-48f7-9ba4-c74215e42cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246683937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2246683937
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1134136771
Short name T592
Test name
Test status
Simulation time 164196085 ps
CPU time 2.31 seconds
Started Aug 14 04:30:31 PM PDT 24
Finished Aug 14 04:30:33 PM PDT 24
Peak memory 209088 kb
Host smart-32b4c7a1-ae62-41e8-93e6-d3ddf676ee81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134136771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1134136771
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.940887378
Short name T105
Test name
Test status
Simulation time 459452234 ps
CPU time 2.05 seconds
Started Aug 14 04:30:15 PM PDT 24
Finished Aug 14 04:30:17 PM PDT 24
Peak memory 200980 kb
Host smart-216142a9-b9e3-4f09-b470-94bb6edff86e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940887378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.940887378
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3725874413
Short name T579
Test name
Test status
Simulation time 232576481 ps
CPU time 1.58 seconds
Started Aug 14 04:30:20 PM PDT 24
Finished Aug 14 04:30:22 PM PDT 24
Peak memory 200788 kb
Host smart-4f3d8b59-5da3-43d0-b306-cc5b2969c373
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725874413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
725874413
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3141913537
Short name T542
Test name
Test status
Simulation time 276455842 ps
CPU time 3.18 seconds
Started Aug 14 04:30:23 PM PDT 24
Finished Aug 14 04:30:26 PM PDT 24
Peak memory 200896 kb
Host smart-8e9134bc-0d65-4a7f-b97b-e3a129b506fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141913537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
141913537
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2264571119
Short name T564
Test name
Test status
Simulation time 125957362 ps
CPU time 0.87 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:45 PM PDT 24
Peak memory 200660 kb
Host smart-653d1823-ff5e-496e-97fa-3c40872bf025
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264571119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
264571119
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3797365593
Short name T552
Test name
Test status
Simulation time 181027218 ps
CPU time 1.19 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 208984 kb
Host smart-05489cb2-fde7-41f7-abe5-deafdb0e5830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797365593 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3797365593
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.184666623
Short name T570
Test name
Test status
Simulation time 60205524 ps
CPU time 0.74 seconds
Started Aug 14 04:30:21 PM PDT 24
Finished Aug 14 04:30:21 PM PDT 24
Peak memory 200612 kb
Host smart-08374227-22dc-417f-99a5-1522dd903026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184666623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.184666623
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1900273310
Short name T613
Test name
Test status
Simulation time 132565753 ps
CPU time 1.11 seconds
Started Aug 14 04:30:42 PM PDT 24
Finished Aug 14 04:30:43 PM PDT 24
Peak memory 200732 kb
Host smart-559e6231-9969-42d3-854f-e4e1a3d0e82f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900273310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1900273310
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4222093055
Short name T608
Test name
Test status
Simulation time 110157204 ps
CPU time 1.49 seconds
Started Aug 14 04:30:17 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 210808 kb
Host smart-e620e696-a5ec-4a2e-889e-1989af519fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222093055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.4222093055
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2270456799
Short name T103
Test name
Test status
Simulation time 792069475 ps
CPU time 3.1 seconds
Started Aug 14 04:30:20 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 200876 kb
Host smart-0a3f250e-b6bc-4eee-b590-23b0646b231c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270456799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.2270456799
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3896877854
Short name T588
Test name
Test status
Simulation time 394570562 ps
CPU time 2.57 seconds
Started Aug 14 04:30:11 PM PDT 24
Finished Aug 14 04:30:14 PM PDT 24
Peak memory 209008 kb
Host smart-bac481ef-8c82-43a4-ae41-5b37d7fe7817
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896877854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
896877854
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.672339407
Short name T590
Test name
Test status
Simulation time 277068695 ps
CPU time 3.15 seconds
Started Aug 14 04:30:28 PM PDT 24
Finished Aug 14 04:30:31 PM PDT 24
Peak memory 200816 kb
Host smart-b4ea58b4-bf37-4776-9a8c-bcabc0320948
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672339407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.672339407
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.118887539
Short name T562
Test name
Test status
Simulation time 118706701 ps
CPU time 0.83 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:45 PM PDT 24
Peak memory 200604 kb
Host smart-2cf5d1b2-076b-4b61-bcee-d4169e8d9dbf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118887539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.118887539
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3513470955
Short name T586
Test name
Test status
Simulation time 128318204 ps
CPU time 1.01 seconds
Started Aug 14 04:30:24 PM PDT 24
Finished Aug 14 04:30:26 PM PDT 24
Peak memory 200764 kb
Host smart-28ecd1de-bbd4-41b1-9c7b-5e12045d8f63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513470955 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3513470955
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.221505691
Short name T554
Test name
Test status
Simulation time 84442811 ps
CPU time 0.86 seconds
Started Aug 14 04:30:13 PM PDT 24
Finished Aug 14 04:30:15 PM PDT 24
Peak memory 200628 kb
Host smart-6f05b9a0-f1d3-44fb-9053-e129c0a2721e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221505691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.221505691
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.362590420
Short name T98
Test name
Test status
Simulation time 143872653 ps
CPU time 1.16 seconds
Started Aug 14 04:30:14 PM PDT 24
Finished Aug 14 04:30:15 PM PDT 24
Peak memory 200684 kb
Host smart-3ae8ae34-df06-4880-ae47-70e4dd2a6045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362590420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.362590420
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3802134303
Short name T557
Test name
Test status
Simulation time 428691485 ps
CPU time 2.87 seconds
Started Aug 14 04:30:27 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 209076 kb
Host smart-4bffaf3f-9ac1-4934-bfd9-fca3250a63cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802134303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3802134303
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.980432266
Short name T102
Test name
Test status
Simulation time 901319819 ps
CPU time 3 seconds
Started Aug 14 04:30:33 PM PDT 24
Finished Aug 14 04:30:36 PM PDT 24
Peak memory 200912 kb
Host smart-391bd195-8c30-455e-896a-82a9763b7d73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980432266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
980432266
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2951495324
Short name T602
Test name
Test status
Simulation time 393158254 ps
CPU time 2.55 seconds
Started Aug 14 04:30:38 PM PDT 24
Finished Aug 14 04:30:41 PM PDT 24
Peak memory 200832 kb
Host smart-54abad61-8336-496c-b468-6cc88a792024
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951495324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
951495324
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3420892881
Short name T123
Test name
Test status
Simulation time 805112295 ps
CPU time 4.26 seconds
Started Aug 14 04:30:18 PM PDT 24
Finished Aug 14 04:30:22 PM PDT 24
Peak memory 200800 kb
Host smart-5f8483a0-fdb8-4de9-a6d9-a0bf4f2b7e96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420892881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3
420892881
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2263402929
Short name T571
Test name
Test status
Simulation time 107778190 ps
CPU time 0.9 seconds
Started Aug 14 04:30:19 PM PDT 24
Finished Aug 14 04:30:21 PM PDT 24
Peak memory 199784 kb
Host smart-d61fd21d-adf2-497e-a268-56906ab1768a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263402929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
263402929
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1211955634
Short name T90
Test name
Test status
Simulation time 61355203 ps
CPU time 0.79 seconds
Started Aug 14 04:30:33 PM PDT 24
Finished Aug 14 04:30:34 PM PDT 24
Peak memory 200612 kb
Host smart-9f3300e4-f3b2-45ce-a169-679e76a66dd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211955634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1211955634
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3958473405
Short name T553
Test name
Test status
Simulation time 106404559 ps
CPU time 1.18 seconds
Started Aug 14 04:30:28 PM PDT 24
Finished Aug 14 04:30:29 PM PDT 24
Peak memory 200832 kb
Host smart-c80085b4-dc64-4e92-91d7-9c7a31779054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958473405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3958473405
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.820877344
Short name T619
Test name
Test status
Simulation time 174246375 ps
CPU time 2.49 seconds
Started Aug 14 04:30:22 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 209084 kb
Host smart-e4a9d5dc-4fda-4d3f-9c38-2ed29e714b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820877344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.820877344
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.54090974
Short name T549
Test name
Test status
Simulation time 474486501 ps
CPU time 1.91 seconds
Started Aug 14 04:30:33 PM PDT 24
Finished Aug 14 04:30:35 PM PDT 24
Peak memory 200932 kb
Host smart-cf1b9d05-2fac-47c6-a963-6e2f18102f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54090974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.54090974
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2629241415
Short name T603
Test name
Test status
Simulation time 141666838 ps
CPU time 1.02 seconds
Started Aug 14 04:30:15 PM PDT 24
Finished Aug 14 04:30:17 PM PDT 24
Peak memory 200752 kb
Host smart-23a9d165-74ff-4e31-836d-bcf02027c0d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629241415 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.2629241415
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.329676756
Short name T544
Test name
Test status
Simulation time 69194037 ps
CPU time 0.77 seconds
Started Aug 14 04:30:12 PM PDT 24
Finished Aug 14 04:30:12 PM PDT 24
Peak memory 200576 kb
Host smart-0f41fb71-b51b-4d5c-96b0-46c367885e7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329676756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.329676756
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3174633702
Short name T556
Test name
Test status
Simulation time 125773553 ps
CPU time 1.08 seconds
Started Aug 14 04:30:19 PM PDT 24
Finished Aug 14 04:30:20 PM PDT 24
Peak memory 200620 kb
Host smart-7d35d7f2-8cf1-42bd-a8b7-912390806343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174633702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3174633702
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.346488152
Short name T595
Test name
Test status
Simulation time 370493825 ps
CPU time 2.55 seconds
Started Aug 14 04:30:21 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 209072 kb
Host smart-d178f300-d903-4b00-9121-7efd088df246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346488152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.346488152
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2296878807
Short name T121
Test name
Test status
Simulation time 865498945 ps
CPU time 2.97 seconds
Started Aug 14 04:30:20 PM PDT 24
Finished Aug 14 04:30:23 PM PDT 24
Peak memory 200876 kb
Host smart-a9cb36d7-1f67-44af-9dc3-5c7632f19437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296878807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2296878807
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3354143212
Short name T577
Test name
Test status
Simulation time 103071300 ps
CPU time 0.87 seconds
Started Aug 14 04:30:24 PM PDT 24
Finished Aug 14 04:30:25 PM PDT 24
Peak memory 200748 kb
Host smart-098cf33d-1419-4611-bd31-e1848f1eec5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354143212 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.3354143212
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1958298190
Short name T92
Test name
Test status
Simulation time 69289235 ps
CPU time 0.83 seconds
Started Aug 14 04:30:23 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 200636 kb
Host smart-da697579-ec7a-4a88-92fd-160e3d23b15e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958298190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1958298190
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2061178943
Short name T95
Test name
Test status
Simulation time 72707368 ps
CPU time 0.92 seconds
Started Aug 14 04:30:42 PM PDT 24
Finished Aug 14 04:30:43 PM PDT 24
Peak memory 200744 kb
Host smart-1f620012-9153-448f-9739-414c2b461afa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061178943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2061178943
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4268966705
Short name T566
Test name
Test status
Simulation time 599446742 ps
CPU time 3.79 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:33 PM PDT 24
Peak memory 209100 kb
Host smart-61b66fbf-81cb-4a02-86d5-4daf964faf21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268966705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4268966705
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2750955320
Short name T74
Test name
Test status
Simulation time 496746260 ps
CPU time 1.93 seconds
Started Aug 14 04:30:38 PM PDT 24
Finished Aug 14 04:30:40 PM PDT 24
Peak memory 200932 kb
Host smart-e417105e-7008-4b86-8b6d-e0471a4cdc8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750955320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2750955320
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1694834892
Short name T560
Test name
Test status
Simulation time 103654473 ps
CPU time 0.99 seconds
Started Aug 14 04:30:49 PM PDT 24
Finished Aug 14 04:30:50 PM PDT 24
Peak memory 200852 kb
Host smart-2670fdeb-9f66-433d-a5f7-0f95e7ba8317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694834892 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1694834892
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2185575422
Short name T545
Test name
Test status
Simulation time 81664791 ps
CPU time 0.82 seconds
Started Aug 14 04:30:26 PM PDT 24
Finished Aug 14 04:30:27 PM PDT 24
Peak memory 200620 kb
Host smart-c364117f-5a52-491b-8c95-b3b2cf5fe823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185575422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2185575422
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1602643068
Short name T583
Test name
Test status
Simulation time 132775195 ps
CPU time 1.21 seconds
Started Aug 14 04:30:27 PM PDT 24
Finished Aug 14 04:30:28 PM PDT 24
Peak memory 200964 kb
Host smart-c2e33a0d-0d82-49fd-9445-44ca584800cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602643068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1602643068
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1730030334
Short name T569
Test name
Test status
Simulation time 414738149 ps
CPU time 2.68 seconds
Started Aug 14 04:30:17 PM PDT 24
Finished Aug 14 04:30:20 PM PDT 24
Peak memory 209068 kb
Host smart-22649952-bc7d-402d-aefc-eee338978652
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730030334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1730030334
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1280272362
Short name T618
Test name
Test status
Simulation time 418293142 ps
CPU time 1.7 seconds
Started Aug 14 04:30:22 PM PDT 24
Finished Aug 14 04:30:24 PM PDT 24
Peak memory 200868 kb
Host smart-223e7277-49de-4d85-bb04-7e5eab2b5779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280272362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1280272362
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2549489861
Short name T547
Test name
Test status
Simulation time 181039565 ps
CPU time 1.19 seconds
Started Aug 14 04:30:39 PM PDT 24
Finished Aug 14 04:30:40 PM PDT 24
Peak memory 208968 kb
Host smart-7353c974-a86f-4d0c-a9b9-94f6298d75a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549489861 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2549489861
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3917431608
Short name T91
Test name
Test status
Simulation time 62275797 ps
CPU time 0.73 seconds
Started Aug 14 04:30:29 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 200660 kb
Host smart-edbc53fa-2e02-40ea-a020-5b6bbd3c1922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917431608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3917431608
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3048219601
Short name T94
Test name
Test status
Simulation time 101649677 ps
CPU time 1.11 seconds
Started Aug 14 04:30:27 PM PDT 24
Finished Aug 14 04:30:28 PM PDT 24
Peak memory 200960 kb
Host smart-facfc7d9-fc79-42e1-ad21-c15cf55030f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048219601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3048219601
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.129027179
Short name T616
Test name
Test status
Simulation time 91445368 ps
CPU time 1.17 seconds
Started Aug 14 04:30:44 PM PDT 24
Finished Aug 14 04:30:46 PM PDT 24
Peak memory 200732 kb
Host smart-05ed851e-a0b9-4a28-b244-192252d5ee3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129027179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.129027179
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2026635227
Short name T594
Test name
Test status
Simulation time 488290319 ps
CPU time 2.02 seconds
Started Aug 14 04:30:28 PM PDT 24
Finished Aug 14 04:30:30 PM PDT 24
Peak memory 200956 kb
Host smart-7dd4b361-2321-4ad8-ad72-5f45b41943a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026635227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2026635227
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2273431857
Short name T546
Test name
Test status
Simulation time 194616326 ps
CPU time 1.29 seconds
Started Aug 14 04:30:46 PM PDT 24
Finished Aug 14 04:30:47 PM PDT 24
Peak memory 208968 kb
Host smart-a4587068-e316-4f91-a492-3418b0c86013
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273431857 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2273431857
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3805011955
Short name T559
Test name
Test status
Simulation time 62744069 ps
CPU time 0.73 seconds
Started Aug 14 04:30:37 PM PDT 24
Finished Aug 14 04:30:38 PM PDT 24
Peak memory 200536 kb
Host smart-cbe0ad96-1579-46c9-ba2a-79bff1af7f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805011955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3805011955
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.852995206
Short name T596
Test name
Test status
Simulation time 137407300 ps
CPU time 1.25 seconds
Started Aug 14 04:30:30 PM PDT 24
Finished Aug 14 04:30:31 PM PDT 24
Peak memory 200872 kb
Host smart-6458e288-c99f-420a-8f86-4e3056759786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852995206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.852995206
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3550881830
Short name T107
Test name
Test status
Simulation time 181816627 ps
CPU time 2.51 seconds
Started Aug 14 04:30:36 PM PDT 24
Finished Aug 14 04:30:39 PM PDT 24
Peak memory 217192 kb
Host smart-55637bbc-ed55-4e5a-bf35-99692c9f16b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550881830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3550881830
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3396743760
Short name T339
Test name
Test status
Simulation time 66987274 ps
CPU time 0.78 seconds
Started Aug 14 05:09:15 PM PDT 24
Finished Aug 14 05:09:15 PM PDT 24
Peak memory 200524 kb
Host smart-4e17ee05-0423-4733-9d54-494cfcdf2ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396743760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3396743760
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2274609257
Short name T138
Test name
Test status
Simulation time 244287926 ps
CPU time 1.11 seconds
Started Aug 14 05:09:16 PM PDT 24
Finished Aug 14 05:09:17 PM PDT 24
Peak memory 217696 kb
Host smart-c9aa644d-8033-4cd9-bca4-213b2d40f85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274609257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2274609257
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3088238582
Short name T497
Test name
Test status
Simulation time 125291133 ps
CPU time 0.85 seconds
Started Aug 14 05:09:08 PM PDT 24
Finished Aug 14 05:09:09 PM PDT 24
Peak memory 200464 kb
Host smart-17a5204b-8faa-4661-ba8d-a02b4c1aaedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088238582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3088238582
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.134427850
Short name T293
Test name
Test status
Simulation time 2051870894 ps
CPU time 7.74 seconds
Started Aug 14 05:09:08 PM PDT 24
Finished Aug 14 05:09:15 PM PDT 24
Peak memory 200840 kb
Host smart-7a3f0eee-c9ba-4827-8c09-10a105fbb1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134427850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.134427850
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3142218436
Short name T237
Test name
Test status
Simulation time 103403027 ps
CPU time 1.02 seconds
Started Aug 14 05:09:14 PM PDT 24
Finished Aug 14 05:09:16 PM PDT 24
Peak memory 200520 kb
Host smart-3c16fd1b-d875-4759-9b9c-7f0f9dfe4835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142218436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3142218436
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.889742999
Short name T295
Test name
Test status
Simulation time 211318962 ps
CPU time 1.46 seconds
Started Aug 14 05:09:06 PM PDT 24
Finished Aug 14 05:09:08 PM PDT 24
Peak memory 200740 kb
Host smart-2af8a250-baab-4622-bd0c-9ee65b23a0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889742999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.889742999
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.2742680815
Short name T110
Test name
Test status
Simulation time 2689468466 ps
CPU time 10.34 seconds
Started Aug 14 05:09:16 PM PDT 24
Finished Aug 14 05:09:27 PM PDT 24
Peak memory 209040 kb
Host smart-8b998cdf-9926-4ac8-bf69-8f0d93ae84e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742680815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2742680815
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.4114190644
Short name T526
Test name
Test status
Simulation time 333984770 ps
CPU time 2.35 seconds
Started Aug 14 05:09:16 PM PDT 24
Finished Aug 14 05:09:18 PM PDT 24
Peak memory 208744 kb
Host smart-9b1f9adf-39a0-43da-afb9-ed0b9631c249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114190644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4114190644
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.3693200790
Short name T416
Test name
Test status
Simulation time 75871806 ps
CPU time 0.81 seconds
Started Aug 14 05:09:25 PM PDT 24
Finished Aug 14 05:09:26 PM PDT 24
Peak memory 200500 kb
Host smart-5b687121-f7e5-4e63-ac20-faac2dda1de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693200790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.3693200790
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3525286278
Short name T212
Test name
Test status
Simulation time 244231311 ps
CPU time 1.16 seconds
Started Aug 14 05:09:16 PM PDT 24
Finished Aug 14 05:09:17 PM PDT 24
Peak memory 217808 kb
Host smart-f30ff14e-8d9d-48d2-9c25-440a7b4e5b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525286278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3525286278
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.208934599
Short name T264
Test name
Test status
Simulation time 172902418 ps
CPU time 0.86 seconds
Started Aug 14 05:09:17 PM PDT 24
Finished Aug 14 05:09:18 PM PDT 24
Peak memory 200488 kb
Host smart-a5663a58-cc64-4442-bb80-756c43b2ed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208934599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.208934599
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.116348922
Short name T462
Test name
Test status
Simulation time 904129020 ps
CPU time 4.34 seconds
Started Aug 14 05:09:14 PM PDT 24
Finished Aug 14 05:09:19 PM PDT 24
Peak memory 200744 kb
Host smart-59287f12-6da4-4872-80ac-d7bf6b6903ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116348922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.116348922
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.3437357179
Short name T64
Test name
Test status
Simulation time 8733304621 ps
CPU time 13.4 seconds
Started Aug 14 05:09:17 PM PDT 24
Finished Aug 14 05:09:31 PM PDT 24
Peak memory 217852 kb
Host smart-fcedbf3d-a682-4915-81a8-dde87820e6ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437357179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3437357179
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1879922092
Short name T473
Test name
Test status
Simulation time 195249803 ps
CPU time 1.34 seconds
Started Aug 14 05:09:15 PM PDT 24
Finished Aug 14 05:09:16 PM PDT 24
Peak memory 200812 kb
Host smart-26f815cc-508d-4b1d-976a-fb22eea8ed5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879922092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1879922092
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.293922695
Short name T467
Test name
Test status
Simulation time 5230200749 ps
CPU time 20.38 seconds
Started Aug 14 05:09:14 PM PDT 24
Finished Aug 14 05:09:35 PM PDT 24
Peak memory 200892 kb
Host smart-a11ef295-90e9-4ee2-bf1f-f1701cf396fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293922695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.293922695
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2078101632
Short name T140
Test name
Test status
Simulation time 271457542 ps
CPU time 1.82 seconds
Started Aug 14 05:09:14 PM PDT 24
Finished Aug 14 05:09:16 PM PDT 24
Peak memory 200540 kb
Host smart-3e4250eb-dfee-4515-b443-e14f2b84f609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078101632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2078101632
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2053827501
Short name T372
Test name
Test status
Simulation time 128744088 ps
CPU time 1.07 seconds
Started Aug 14 05:09:14 PM PDT 24
Finished Aug 14 05:09:15 PM PDT 24
Peak memory 200572 kb
Host smart-31705a9d-83ca-4a27-a017-481a1e7b8bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053827501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2053827501
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1284210206
Short name T369
Test name
Test status
Simulation time 59163593 ps
CPU time 0.7 seconds
Started Aug 14 05:09:59 PM PDT 24
Finished Aug 14 05:10:00 PM PDT 24
Peak memory 200516 kb
Host smart-8efd0e4b-62ff-45d0-99a4-096dd19f0d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284210206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1284210206
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3245116259
Short name T54
Test name
Test status
Simulation time 1216921042 ps
CPU time 5.66 seconds
Started Aug 14 05:10:05 PM PDT 24
Finished Aug 14 05:10:10 PM PDT 24
Peak memory 221944 kb
Host smart-3c0e6760-6f67-4108-8b02-bde73d1032b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245116259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3245116259
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3322424544
Short name T190
Test name
Test status
Simulation time 243458007 ps
CPU time 1.15 seconds
Started Aug 14 05:09:59 PM PDT 24
Finished Aug 14 05:10:01 PM PDT 24
Peak memory 217800 kb
Host smart-076b8884-db57-45dd-97f5-76bacec3ed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322424544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3322424544
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.827254877
Short name T487
Test name
Test status
Simulation time 196245392 ps
CPU time 0.9 seconds
Started Aug 14 05:10:02 PM PDT 24
Finished Aug 14 05:10:03 PM PDT 24
Peak memory 200468 kb
Host smart-d4938401-07df-4608-811b-cf812d4d66b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827254877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.827254877
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.743713352
Short name T156
Test name
Test status
Simulation time 833071510 ps
CPU time 4.09 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:05 PM PDT 24
Peak memory 200808 kb
Host smart-1bf735c0-765a-4c22-a428-d413d769e44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743713352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.743713352
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.907912942
Short name T439
Test name
Test status
Simulation time 152992716 ps
CPU time 1.14 seconds
Started Aug 14 05:09:59 PM PDT 24
Finished Aug 14 05:10:01 PM PDT 24
Peak memory 200556 kb
Host smart-b898de57-b006-488b-93fa-344a98812830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907912942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.907912942
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.221463573
Short name T244
Test name
Test status
Simulation time 119909794 ps
CPU time 1.23 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:01 PM PDT 24
Peak memory 200760 kb
Host smart-75c20bae-63fd-46c7-aadb-ee9d9f771b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221463573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.221463573
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.4087009168
Short name T84
Test name
Test status
Simulation time 2194500578 ps
CPU time 8.91 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:09 PM PDT 24
Peak memory 200860 kb
Host smart-a2a1791b-0dbe-4992-a8f0-13ed735bdf66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087009168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.4087009168
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3244368011
Short name T177
Test name
Test status
Simulation time 369407597 ps
CPU time 2.61 seconds
Started Aug 14 05:10:01 PM PDT 24
Finished Aug 14 05:10:03 PM PDT 24
Peak memory 200536 kb
Host smart-925a2f50-a3ba-4617-96fc-126f0279b891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244368011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3244368011
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.398224901
Short name T233
Test name
Test status
Simulation time 67860538 ps
CPU time 0.77 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:01 PM PDT 24
Peak memory 200620 kb
Host smart-f7843b09-261e-4ccd-879b-f933f60e346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398224901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.398224901
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.2550805597
Short name T131
Test name
Test status
Simulation time 72123677 ps
CPU time 0.77 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:01 PM PDT 24
Peak memory 200384 kb
Host smart-7c25f078-9918-4361-a131-a36345714a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550805597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2550805597
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3679077635
Short name T379
Test name
Test status
Simulation time 1220580290 ps
CPU time 5.6 seconds
Started Aug 14 05:10:02 PM PDT 24
Finished Aug 14 05:10:08 PM PDT 24
Peak memory 221944 kb
Host smart-e999aea7-6826-4d9a-8c8a-98686130a42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679077635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3679077635
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.543655594
Short name T158
Test name
Test status
Simulation time 244493183 ps
CPU time 1.09 seconds
Started Aug 14 05:10:02 PM PDT 24
Finished Aug 14 05:10:03 PM PDT 24
Peak memory 217812 kb
Host smart-92657c04-5124-46fe-9b0f-cf66ccafc543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543655594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.543655594
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1236192259
Short name T438
Test name
Test status
Simulation time 1388170084 ps
CPU time 5.59 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:06 PM PDT 24
Peak memory 200848 kb
Host smart-858a623e-b1ed-48c9-bfb3-e61ed23bde48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236192259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1236192259
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1611313052
Short name T152
Test name
Test status
Simulation time 94860533 ps
CPU time 0.97 seconds
Started Aug 14 05:09:59 PM PDT 24
Finished Aug 14 05:10:00 PM PDT 24
Peak memory 200572 kb
Host smart-fc7e3d6d-5794-4651-a5d1-03b39129edc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611313052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1611313052
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.593900434
Short name T387
Test name
Test status
Simulation time 107995601 ps
CPU time 1.26 seconds
Started Aug 14 05:10:01 PM PDT 24
Finished Aug 14 05:10:03 PM PDT 24
Peak memory 200772 kb
Host smart-b8d76207-eead-4f78-a133-0a8026c78821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593900434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.593900434
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1738053528
Short name T291
Test name
Test status
Simulation time 10669234472 ps
CPU time 43.18 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:43 PM PDT 24
Peak memory 209068 kb
Host smart-a49e29b9-493a-4cb0-be04-104eca18357d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738053528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1738053528
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1489961114
Short name T197
Test name
Test status
Simulation time 134313932 ps
CPU time 1.7 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:01 PM PDT 24
Peak memory 200528 kb
Host smart-e7019fd5-d60c-444f-85ca-3124d21c1855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489961114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1489961114
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.4111550580
Short name T136
Test name
Test status
Simulation time 83194518 ps
CPU time 0.85 seconds
Started Aug 14 05:10:04 PM PDT 24
Finished Aug 14 05:10:05 PM PDT 24
Peak memory 200656 kb
Host smart-8696ef40-a5e4-420b-9b0f-2943e629cdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111550580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.4111550580
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3136484087
Short name T139
Test name
Test status
Simulation time 57079215 ps
CPU time 0.78 seconds
Started Aug 14 05:10:13 PM PDT 24
Finished Aug 14 05:10:14 PM PDT 24
Peak memory 200452 kb
Host smart-2b86614a-3fe1-4c92-b5d4-c8daf7a25af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136484087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3136484087
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.1541101134
Short name T523
Test name
Test status
Simulation time 1214872298 ps
CPU time 6.01 seconds
Started Aug 14 05:10:10 PM PDT 24
Finished Aug 14 05:10:16 PM PDT 24
Peak memory 221948 kb
Host smart-2ec9bca1-13b0-4502-ae7d-14f6119dcdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541101134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1541101134
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2658975445
Short name T495
Test name
Test status
Simulation time 244148543 ps
CPU time 1.14 seconds
Started Aug 14 05:10:10 PM PDT 24
Finished Aug 14 05:10:11 PM PDT 24
Peak memory 217804 kb
Host smart-d2d9cc19-0b4f-4af0-9100-2bc1ee2b57d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658975445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2658975445
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3656954530
Short name T249
Test name
Test status
Simulation time 168527072 ps
CPU time 0.93 seconds
Started Aug 14 05:10:05 PM PDT 24
Finished Aug 14 05:10:06 PM PDT 24
Peak memory 200464 kb
Host smart-96df0f4a-8e9e-4f0d-afdd-595d9143a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656954530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3656954530
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.3438442254
Short name T168
Test name
Test status
Simulation time 959047293 ps
CPU time 5.01 seconds
Started Aug 14 05:09:59 PM PDT 24
Finished Aug 14 05:10:04 PM PDT 24
Peak memory 200804 kb
Host smart-4e47554f-c22e-4cee-a29a-4938f6338d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438442254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3438442254
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.192226822
Short name T142
Test name
Test status
Simulation time 113733497 ps
CPU time 1.06 seconds
Started Aug 14 05:10:10 PM PDT 24
Finished Aug 14 05:10:11 PM PDT 24
Peak memory 200652 kb
Host smart-38aee668-47cc-4884-aad4-10d494432886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192226822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.192226822
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1410155284
Short name T308
Test name
Test status
Simulation time 195444842 ps
CPU time 1.39 seconds
Started Aug 14 05:10:04 PM PDT 24
Finished Aug 14 05:10:06 PM PDT 24
Peak memory 200740 kb
Host smart-6eef393e-f95e-4670-b34a-ffc3c10ded74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410155284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1410155284
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.2937848698
Short name T11
Test name
Test status
Simulation time 8619521846 ps
CPU time 30.17 seconds
Started Aug 14 05:10:14 PM PDT 24
Finished Aug 14 05:10:44 PM PDT 24
Peak memory 208968 kb
Host smart-63910938-94d5-48f8-9180-d97da3a8f17a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937848698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.2937848698
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.995802290
Short name T268
Test name
Test status
Simulation time 368994547 ps
CPU time 1.97 seconds
Started Aug 14 05:10:02 PM PDT 24
Finished Aug 14 05:10:04 PM PDT 24
Peak memory 200432 kb
Host smart-ae9647aa-e5f3-490a-bd66-1e6f707caacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995802290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.995802290
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.3545456156
Short name T297
Test name
Test status
Simulation time 106066831 ps
CPU time 0.91 seconds
Started Aug 14 05:10:00 PM PDT 24
Finished Aug 14 05:10:01 PM PDT 24
Peak memory 200652 kb
Host smart-1c9ddd1f-9a0d-4871-913b-4e8eb516b37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545456156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3545456156
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.802875974
Short name T326
Test name
Test status
Simulation time 73276775 ps
CPU time 0.78 seconds
Started Aug 14 05:10:10 PM PDT 24
Finished Aug 14 05:10:11 PM PDT 24
Peak memory 200412 kb
Host smart-0a11d4b4-c4b5-493e-a325-479b5978725c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802875974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.802875974
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2868915423
Short name T294
Test name
Test status
Simulation time 1883793812 ps
CPU time 7.92 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:17 PM PDT 24
Peak memory 221960 kb
Host smart-77149fc2-7397-402a-b90a-373034a45b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868915423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2868915423
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2846781035
Short name T362
Test name
Test status
Simulation time 244241168 ps
CPU time 1.2 seconds
Started Aug 14 05:10:13 PM PDT 24
Finished Aug 14 05:10:14 PM PDT 24
Peak memory 217820 kb
Host smart-7d2e454b-7f0a-4a1d-8cd8-cbf2cdf7ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846781035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2846781035
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1104840783
Short name T404
Test name
Test status
Simulation time 131656392 ps
CPU time 0.92 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:10 PM PDT 24
Peak memory 200476 kb
Host smart-63d1192a-367b-4b3f-84f9-63886b1b6c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104840783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1104840783
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.1220188599
Short name T327
Test name
Test status
Simulation time 876711711 ps
CPU time 4.52 seconds
Started Aug 14 05:10:10 PM PDT 24
Finished Aug 14 05:10:15 PM PDT 24
Peak memory 200804 kb
Host smart-9aa74076-def6-4c62-b645-36e3a831621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220188599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1220188599
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3561831274
Short name T229
Test name
Test status
Simulation time 103066626 ps
CPU time 1.1 seconds
Started Aug 14 05:10:12 PM PDT 24
Finished Aug 14 05:10:13 PM PDT 24
Peak memory 200624 kb
Host smart-ac030800-a5ae-4110-be3d-d10fac90075e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561831274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3561831274
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2159645938
Short name T476
Test name
Test status
Simulation time 255950289 ps
CPU time 1.46 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:11 PM PDT 24
Peak memory 200732 kb
Host smart-8214ad12-fb2f-45dd-a22b-21bc8b75680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159645938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2159645938
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2060807920
Short name T338
Test name
Test status
Simulation time 6543326481 ps
CPU time 25.83 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:35 PM PDT 24
Peak memory 209244 kb
Host smart-0f9dc463-bc16-4c3a-bb6c-7aa2d7aad121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060807920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2060807920
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.402757045
Short name T186
Test name
Test status
Simulation time 59580718 ps
CPU time 0.77 seconds
Started Aug 14 05:10:10 PM PDT 24
Finished Aug 14 05:10:11 PM PDT 24
Peak memory 200704 kb
Host smart-d8ec5bbb-8fe7-4f10-9201-62d69a8b49aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402757045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.402757045
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.107030541
Short name T420
Test name
Test status
Simulation time 1220208919 ps
CPU time 5.64 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:15 PM PDT 24
Peak memory 218008 kb
Host smart-8a420378-8695-49fc-9ff3-ea1cd09254b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107030541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.107030541
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.956728239
Short name T255
Test name
Test status
Simulation time 243904430 ps
CPU time 1.09 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:10 PM PDT 24
Peak memory 217780 kb
Host smart-110cd40c-f461-49a2-b9c9-a41110c438e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956728239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.956728239
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1059609246
Short name T490
Test name
Test status
Simulation time 141826161 ps
CPU time 0.84 seconds
Started Aug 14 05:10:11 PM PDT 24
Finished Aug 14 05:10:12 PM PDT 24
Peak memory 200460 kb
Host smart-c3573cb2-2b47-4b1e-8ffa-f929947e2a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059609246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1059609246
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3799199177
Short name T367
Test name
Test status
Simulation time 958089747 ps
CPU time 5.04 seconds
Started Aug 14 05:10:11 PM PDT 24
Finished Aug 14 05:10:16 PM PDT 24
Peak memory 200784 kb
Host smart-9f755105-d194-4a2f-b943-c8da848c0091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799199177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3799199177
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3691007088
Short name T179
Test name
Test status
Simulation time 172617300 ps
CPU time 1.2 seconds
Started Aug 14 05:10:12 PM PDT 24
Finished Aug 14 05:10:13 PM PDT 24
Peak memory 200624 kb
Host smart-fedd6869-2113-4333-9f9e-dcb2c76e254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691007088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3691007088
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.1110146324
Short name T144
Test name
Test status
Simulation time 122318336 ps
CPU time 1.34 seconds
Started Aug 14 05:10:13 PM PDT 24
Finished Aug 14 05:10:15 PM PDT 24
Peak memory 200744 kb
Host smart-0a8f930f-a73b-4466-b219-854ed8e925d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110146324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.1110146324
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3191919510
Short name T354
Test name
Test status
Simulation time 2342256346 ps
CPU time 10.45 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:20 PM PDT 24
Peak memory 209052 kb
Host smart-21e331d7-fbf6-4bfd-a1d6-667b12d3d4d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191919510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3191919510
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1305147432
Short name T453
Test name
Test status
Simulation time 121982249 ps
CPU time 1.44 seconds
Started Aug 14 05:10:14 PM PDT 24
Finished Aug 14 05:10:15 PM PDT 24
Peak memory 200472 kb
Host smart-0eccf164-4164-41ab-83fd-b272e618b2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305147432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1305147432
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.752102267
Short name T471
Test name
Test status
Simulation time 81621813 ps
CPU time 0.93 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:10 PM PDT 24
Peak memory 200616 kb
Host smart-4e3fa050-e601-4312-ad5d-a78f20f96558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752102267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.752102267
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1504913896
Short name T129
Test name
Test status
Simulation time 64151593 ps
CPU time 0.8 seconds
Started Aug 14 05:10:19 PM PDT 24
Finished Aug 14 05:10:20 PM PDT 24
Peak memory 200520 kb
Host smart-02b74817-96e1-45d1-aab2-4486750f96cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504913896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1504913896
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2913214816
Short name T238
Test name
Test status
Simulation time 2352095006 ps
CPU time 8.85 seconds
Started Aug 14 05:10:21 PM PDT 24
Finished Aug 14 05:10:30 PM PDT 24
Peak memory 218072 kb
Host smart-468acf4b-7085-4870-9fd8-9d7082ad9ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913214816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2913214816
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1717683625
Short name T132
Test name
Test status
Simulation time 244209050 ps
CPU time 1.16 seconds
Started Aug 14 05:10:19 PM PDT 24
Finished Aug 14 05:10:20 PM PDT 24
Peak memory 217808 kb
Host smart-56df2e00-47b8-4f20-bebb-2a87c437010a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717683625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1717683625
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.127648287
Short name T21
Test name
Test status
Simulation time 147249092 ps
CPU time 0.85 seconds
Started Aug 14 05:10:10 PM PDT 24
Finished Aug 14 05:10:11 PM PDT 24
Peak memory 200448 kb
Host smart-4597405b-ddf8-4452-8e6e-f9f964dca589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127648287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.127648287
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.3530098909
Short name T318
Test name
Test status
Simulation time 1470425092 ps
CPU time 6.52 seconds
Started Aug 14 05:10:12 PM PDT 24
Finished Aug 14 05:10:19 PM PDT 24
Peak memory 200784 kb
Host smart-f3f0483a-0b1e-4616-93e6-7c88e15f9c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530098909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3530098909
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2639950266
Short name T333
Test name
Test status
Simulation time 102820178 ps
CPU time 1.03 seconds
Started Aug 14 05:10:18 PM PDT 24
Finished Aug 14 05:10:19 PM PDT 24
Peak memory 200588 kb
Host smart-08ee6ebd-c0f8-46f8-af17-8109f07fa349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639950266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2639950266
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4285303033
Short name T12
Test name
Test status
Simulation time 115166063 ps
CPU time 1.2 seconds
Started Aug 14 05:10:09 PM PDT 24
Finished Aug 14 05:10:10 PM PDT 24
Peak memory 200768 kb
Host smart-0bd740a5-bf30-454b-b47a-93109c036052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285303033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4285303033
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2407548165
Short name T459
Test name
Test status
Simulation time 6950578307 ps
CPU time 27.43 seconds
Started Aug 14 05:10:19 PM PDT 24
Finished Aug 14 05:10:47 PM PDT 24
Peak memory 200868 kb
Host smart-a371f2d9-557d-4f3b-b837-f73e9493bd1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407548165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2407548165
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1793055187
Short name T207
Test name
Test status
Simulation time 124860433 ps
CPU time 1.61 seconds
Started Aug 14 05:10:21 PM PDT 24
Finished Aug 14 05:10:23 PM PDT 24
Peak memory 200572 kb
Host smart-8481b1da-0935-4690-8031-65063165d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793055187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1793055187
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3361479735
Short name T162
Test name
Test status
Simulation time 215860007 ps
CPU time 1.34 seconds
Started Aug 14 05:10:13 PM PDT 24
Finished Aug 14 05:10:15 PM PDT 24
Peak memory 200660 kb
Host smart-e7c7e66f-be3a-4796-81b4-8e165cb2981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361479735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3361479735
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.2137619845
Short name T189
Test name
Test status
Simulation time 76153523 ps
CPU time 0.78 seconds
Started Aug 14 05:10:18 PM PDT 24
Finished Aug 14 05:10:19 PM PDT 24
Peak memory 200444 kb
Host smart-e36f47e2-4bb2-421f-a750-ea428d94843b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137619845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2137619845
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1245131855
Short name T413
Test name
Test status
Simulation time 2347170187 ps
CPU time 8.85 seconds
Started Aug 14 05:10:22 PM PDT 24
Finished Aug 14 05:10:31 PM PDT 24
Peak memory 221928 kb
Host smart-d6bfd0ef-2ab2-4efa-be4b-6d9318ab4a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245131855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1245131855
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3479357497
Short name T323
Test name
Test status
Simulation time 243374736 ps
CPU time 1.09 seconds
Started Aug 14 05:10:18 PM PDT 24
Finished Aug 14 05:10:20 PM PDT 24
Peak memory 217832 kb
Host smart-00807e4d-4298-4de3-a178-f0bea01247b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479357497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3479357497
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1861218455
Short name T374
Test name
Test status
Simulation time 144280443 ps
CPU time 0.82 seconds
Started Aug 14 05:10:22 PM PDT 24
Finished Aug 14 05:10:22 PM PDT 24
Peak memory 200436 kb
Host smart-647d54dc-ffad-4d22-b323-e8094764f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861218455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1861218455
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.1566443174
Short name T322
Test name
Test status
Simulation time 743954045 ps
CPU time 3.85 seconds
Started Aug 14 05:10:24 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 200832 kb
Host smart-5b86fe77-0bbf-450f-b618-6b5eddb13c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566443174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1566443174
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3428767200
Short name T50
Test name
Test status
Simulation time 96693113 ps
CPU time 1.01 seconds
Started Aug 14 05:10:21 PM PDT 24
Finished Aug 14 05:10:22 PM PDT 24
Peak memory 200576 kb
Host smart-7dacb030-64ab-44c6-bb9f-a0c28fd8d079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428767200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3428767200
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3263119415
Short name T485
Test name
Test status
Simulation time 124614523 ps
CPU time 1.16 seconds
Started Aug 14 05:10:21 PM PDT 24
Finished Aug 14 05:10:22 PM PDT 24
Peak memory 200816 kb
Host smart-efd924ac-c529-4ff8-80d7-2b4e5a97255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263119415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3263119415
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.109302382
Short name T85
Test name
Test status
Simulation time 5136607748 ps
CPU time 24.46 seconds
Started Aug 14 05:10:19 PM PDT 24
Finished Aug 14 05:10:44 PM PDT 24
Peak memory 210112 kb
Host smart-f283b5a2-6fb0-4c21-b4e8-28f70e78a984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109302382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.109302382
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.758016932
Short name T147
Test name
Test status
Simulation time 142817760 ps
CPU time 1.78 seconds
Started Aug 14 05:10:19 PM PDT 24
Finished Aug 14 05:10:21 PM PDT 24
Peak memory 200472 kb
Host smart-cc52a6fc-3a32-47cb-87c5-be16a40112dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758016932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.758016932
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.11484652
Short name T48
Test name
Test status
Simulation time 171605585 ps
CPU time 1.11 seconds
Started Aug 14 05:10:18 PM PDT 24
Finished Aug 14 05:10:20 PM PDT 24
Peak memory 200668 kb
Host smart-abbbbee0-9046-4c77-9fc8-cbed2cbfab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11484652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.11484652
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.4101753994
Short name T256
Test name
Test status
Simulation time 52774504 ps
CPU time 0.73 seconds
Started Aug 14 05:10:18 PM PDT 24
Finished Aug 14 05:10:19 PM PDT 24
Peak memory 200528 kb
Host smart-13b85538-d44d-424f-b619-d4f437667a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101753994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.4101753994
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.2218358599
Short name T24
Test name
Test status
Simulation time 1234947375 ps
CPU time 5.47 seconds
Started Aug 14 05:10:24 PM PDT 24
Finished Aug 14 05:10:29 PM PDT 24
Peak memory 217040 kb
Host smart-6f2d363e-6a52-4fcd-a76b-2dd77eb021eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218358599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2218358599
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1071125139
Short name T225
Test name
Test status
Simulation time 244450075 ps
CPU time 1.18 seconds
Started Aug 14 05:10:20 PM PDT 24
Finished Aug 14 05:10:21 PM PDT 24
Peak memory 217820 kb
Host smart-4d0d6416-2793-499e-b5d3-2dd2cd21b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071125139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1071125139
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2488363351
Short name T507
Test name
Test status
Simulation time 202158834 ps
CPU time 0.92 seconds
Started Aug 14 05:10:18 PM PDT 24
Finished Aug 14 05:10:19 PM PDT 24
Peak memory 200452 kb
Host smart-2d2efcf9-615b-4df3-b7c6-ea229ed42c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488363351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2488363351
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2304825038
Short name T513
Test name
Test status
Simulation time 1751915985 ps
CPU time 6.62 seconds
Started Aug 14 05:10:22 PM PDT 24
Finished Aug 14 05:10:29 PM PDT 24
Peak memory 200716 kb
Host smart-411d577c-0876-4726-9587-37587d9ad609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304825038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2304825038
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3604736429
Short name T535
Test name
Test status
Simulation time 150236391 ps
CPU time 1.21 seconds
Started Aug 14 05:10:20 PM PDT 24
Finished Aug 14 05:10:21 PM PDT 24
Peak memory 200660 kb
Host smart-96adec48-b087-40fa-a874-4731e002e77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604736429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3604736429
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.922035077
Short name T185
Test name
Test status
Simulation time 194110267 ps
CPU time 1.37 seconds
Started Aug 14 05:10:24 PM PDT 24
Finished Aug 14 05:10:25 PM PDT 24
Peak memory 200772 kb
Host smart-351f18ca-0700-4cac-a984-b7789eb56a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922035077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.922035077
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.179158374
Short name T164
Test name
Test status
Simulation time 261238807 ps
CPU time 1.89 seconds
Started Aug 14 05:10:19 PM PDT 24
Finished Aug 14 05:10:21 PM PDT 24
Peak memory 200468 kb
Host smart-e1cb4398-b42d-42f8-b32b-737bc0cd364b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179158374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.179158374
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2994334527
Short name T529
Test name
Test status
Simulation time 295706724 ps
CPU time 1.98 seconds
Started Aug 14 05:10:20 PM PDT 24
Finished Aug 14 05:10:22 PM PDT 24
Peak memory 208692 kb
Host smart-4a338064-2a00-47ef-a7c3-40d2965fc464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994334527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2994334527
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.162973367
Short name T469
Test name
Test status
Simulation time 151570202 ps
CPU time 1.27 seconds
Started Aug 14 05:10:20 PM PDT 24
Finished Aug 14 05:10:21 PM PDT 24
Peak memory 200732 kb
Host smart-5fb20e47-a217-4b8d-be61-a64ddd1e5379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162973367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.162973367
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1062156106
Short name T198
Test name
Test status
Simulation time 72860474 ps
CPU time 0.77 seconds
Started Aug 14 05:10:29 PM PDT 24
Finished Aug 14 05:10:30 PM PDT 24
Peak memory 200516 kb
Host smart-e97de0e3-157f-49a5-bb03-c0870a341092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062156106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1062156106
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3343930379
Short name T27
Test name
Test status
Simulation time 1231756771 ps
CPU time 5.85 seconds
Started Aug 14 05:10:28 PM PDT 24
Finished Aug 14 05:10:34 PM PDT 24
Peak memory 217620 kb
Host smart-3ce1bab7-ecb6-4dec-9bf1-bb6db99984b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343930379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3343930379
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.611194965
Short name T303
Test name
Test status
Simulation time 244993810 ps
CPU time 1.14 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 217848 kb
Host smart-225057a7-7d3f-4e29-995d-e12a78514e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611194965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.611194965
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1813304399
Short name T426
Test name
Test status
Simulation time 85578858 ps
CPU time 0.79 seconds
Started Aug 14 05:10:22 PM PDT 24
Finished Aug 14 05:10:23 PM PDT 24
Peak memory 200436 kb
Host smart-9fbc349b-13a9-4edb-9e3e-183456143b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813304399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1813304399
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3161631146
Short name T292
Test name
Test status
Simulation time 1219921746 ps
CPU time 5.2 seconds
Started Aug 14 05:10:26 PM PDT 24
Finished Aug 14 05:10:31 PM PDT 24
Peak memory 200792 kb
Host smart-e9e69f77-5608-4f30-b67e-ddc904d12fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161631146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3161631146
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2430179216
Short name T196
Test name
Test status
Simulation time 144666356 ps
CPU time 1.23 seconds
Started Aug 14 05:10:26 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 200544 kb
Host smart-59c9b25f-d1f8-4b1b-ab78-59c2ffedeba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430179216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2430179216
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1571965098
Short name T250
Test name
Test status
Simulation time 258745356 ps
CPU time 1.61 seconds
Started Aug 14 05:10:22 PM PDT 24
Finished Aug 14 05:10:23 PM PDT 24
Peak memory 200700 kb
Host smart-8d0c7361-6bd4-4463-bd71-ef64430e017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571965098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1571965098
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3735170223
Short name T174
Test name
Test status
Simulation time 1720674234 ps
CPU time 7.32 seconds
Started Aug 14 05:10:30 PM PDT 24
Finished Aug 14 05:10:38 PM PDT 24
Peak memory 200760 kb
Host smart-cdbf9104-428d-4e10-8410-5b1ea6a24f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735170223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3735170223
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3054161092
Short name T193
Test name
Test status
Simulation time 414990559 ps
CPU time 2.58 seconds
Started Aug 14 05:10:28 PM PDT 24
Finished Aug 14 05:10:30 PM PDT 24
Peak memory 208740 kb
Host smart-15469ef2-6cec-48a3-905a-92d9617c4bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054161092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3054161092
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.3035532659
Short name T365
Test name
Test status
Simulation time 132941695 ps
CPU time 1.1 seconds
Started Aug 14 05:10:26 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 200656 kb
Host smart-1003052d-21a8-4e87-a2df-466d39187958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035532659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.3035532659
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1055205590
Short name T334
Test name
Test status
Simulation time 63659568 ps
CPU time 0.74 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 200544 kb
Host smart-f257b658-9eee-479c-b9a6-32a7c8a722d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055205590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1055205590
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.12571620
Short name T45
Test name
Test status
Simulation time 1886883184 ps
CPU time 6.99 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:34 PM PDT 24
Peak memory 217712 kb
Host smart-f2f059a3-c8fe-4c2d-ae64-2089f1e50467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12571620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.12571620
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1939964706
Short name T368
Test name
Test status
Simulation time 244365735 ps
CPU time 1.08 seconds
Started Aug 14 05:10:26 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 217840 kb
Host smart-d47706eb-9194-4b05-b146-528c6bdd64dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939964706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1939964706
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1097180262
Short name T171
Test name
Test status
Simulation time 244625199 ps
CPU time 0.97 seconds
Started Aug 14 05:10:32 PM PDT 24
Finished Aug 14 05:10:33 PM PDT 24
Peak memory 200436 kb
Host smart-b62a7867-7465-4182-a428-e896abf043a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097180262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1097180262
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.2993343342
Short name T317
Test name
Test status
Simulation time 783125107 ps
CPU time 4.47 seconds
Started Aug 14 05:10:26 PM PDT 24
Finished Aug 14 05:10:30 PM PDT 24
Peak memory 200748 kb
Host smart-bfa1de59-ab98-4008-899c-5483329292d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993343342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.2993343342
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2388073609
Short name T366
Test name
Test status
Simulation time 140779082 ps
CPU time 1.23 seconds
Started Aug 14 05:10:28 PM PDT 24
Finished Aug 14 05:10:29 PM PDT 24
Peak memory 200660 kb
Host smart-e78b0b30-3314-4ae7-8030-d3a95c6a2d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388073609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2388073609
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2455662300
Short name T116
Test name
Test status
Simulation time 224647891 ps
CPU time 1.58 seconds
Started Aug 14 05:10:29 PM PDT 24
Finished Aug 14 05:10:31 PM PDT 24
Peak memory 200816 kb
Host smart-94e649eb-72fe-42ea-bccc-edf50593c7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455662300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2455662300
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.2695649886
Short name T109
Test name
Test status
Simulation time 5705454195 ps
CPU time 20.99 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:48 PM PDT 24
Peak memory 210148 kb
Host smart-039bd356-52ca-4b47-a3cf-cdbc812d72f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695649886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2695649886
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1459265200
Short name T378
Test name
Test status
Simulation time 479238153 ps
CPU time 2.59 seconds
Started Aug 14 05:10:32 PM PDT 24
Finished Aug 14 05:10:35 PM PDT 24
Peak memory 200480 kb
Host smart-562b870b-b7ef-425c-9c74-ac1f107726da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459265200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1459265200
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.372491111
Short name T265
Test name
Test status
Simulation time 189374967 ps
CPU time 1.15 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 200656 kb
Host smart-9f6f9f73-76f4-4935-9be3-444d55fe7689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372491111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.372491111
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.4056602845
Short name T65
Test name
Test status
Simulation time 72862898 ps
CPU time 0.8 seconds
Started Aug 14 05:09:28 PM PDT 24
Finished Aug 14 05:09:29 PM PDT 24
Peak memory 200516 kb
Host smart-418572c6-0ba1-4d28-9d38-73707f40f60c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056602845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.4056602845
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3100624150
Short name T454
Test name
Test status
Simulation time 2366338962 ps
CPU time 7.78 seconds
Started Aug 14 05:09:23 PM PDT 24
Finished Aug 14 05:09:31 PM PDT 24
Peak memory 218040 kb
Host smart-dc47ca69-2a24-46d9-b590-3b6bb593daca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100624150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3100624150
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3672603649
Short name T433
Test name
Test status
Simulation time 244984176 ps
CPU time 1.09 seconds
Started Aug 14 05:09:24 PM PDT 24
Finished Aug 14 05:09:25 PM PDT 24
Peak memory 217736 kb
Host smart-265fbad7-cf8a-4f8f-afa0-a19133d72a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672603649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3672603649
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.358475538
Short name T406
Test name
Test status
Simulation time 205533372 ps
CPU time 0.92 seconds
Started Aug 14 05:09:23 PM PDT 24
Finished Aug 14 05:09:24 PM PDT 24
Peak memory 200508 kb
Host smart-652a4f8c-c306-487f-b5b6-5100b4a483e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358475538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.358475538
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3043163317
Short name T521
Test name
Test status
Simulation time 773708028 ps
CPU time 3.88 seconds
Started Aug 14 05:09:21 PM PDT 24
Finished Aug 14 05:09:25 PM PDT 24
Peak memory 200696 kb
Host smart-ada891ab-724a-489e-8141-51b556f96821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043163317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3043163317
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2701556377
Short name T67
Test name
Test status
Simulation time 8298259348 ps
CPU time 14.56 seconds
Started Aug 14 05:09:28 PM PDT 24
Finished Aug 14 05:09:43 PM PDT 24
Peak memory 217312 kb
Host smart-b616372d-4eb2-42d7-a392-c8e646f3f23c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701556377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2701556377
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4179809875
Short name T191
Test name
Test status
Simulation time 110823301 ps
CPU time 1.06 seconds
Started Aug 14 05:09:23 PM PDT 24
Finished Aug 14 05:09:24 PM PDT 24
Peak memory 200648 kb
Host smart-1e7504a2-927b-45d4-bb9b-6ec90432148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179809875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4179809875
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3205327296
Short name T279
Test name
Test status
Simulation time 211528330 ps
CPU time 1.49 seconds
Started Aug 14 05:09:22 PM PDT 24
Finished Aug 14 05:09:24 PM PDT 24
Peak memory 200760 kb
Host smart-8dd5e7f0-0afa-400b-911a-4f3dd88e7a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205327296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3205327296
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2360366682
Short name T206
Test name
Test status
Simulation time 4024110249 ps
CPU time 17.98 seconds
Started Aug 14 05:09:24 PM PDT 24
Finished Aug 14 05:09:42 PM PDT 24
Peak memory 200844 kb
Host smart-5ea1aa4d-ab1e-4544-b10b-f3cad24c413e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360366682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2360366682
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.1078983333
Short name T143
Test name
Test status
Simulation time 120535388 ps
CPU time 1.65 seconds
Started Aug 14 05:09:22 PM PDT 24
Finished Aug 14 05:09:24 PM PDT 24
Peak memory 208812 kb
Host smart-af388d1a-0e74-4eec-9a61-0ec306014946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078983333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1078983333
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3220685586
Short name T222
Test name
Test status
Simulation time 85908783 ps
CPU time 0.86 seconds
Started Aug 14 05:09:24 PM PDT 24
Finished Aug 14 05:09:25 PM PDT 24
Peak memory 200624 kb
Host smart-7694c787-8bd9-4fc0-8d7c-7fdfb628c8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220685586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3220685586
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.895317652
Short name T400
Test name
Test status
Simulation time 76740815 ps
CPU time 0.83 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 200524 kb
Host smart-137c2c38-1352-453b-82e7-92d1ecb1b280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895317652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.895317652
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.4109863324
Short name T55
Test name
Test status
Simulation time 1894131922 ps
CPU time 7.38 seconds
Started Aug 14 05:10:26 PM PDT 24
Finished Aug 14 05:10:33 PM PDT 24
Peak memory 218024 kb
Host smart-60567e23-2780-49d9-8e83-dff6595857eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109863324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.4109863324
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.26690647
Short name T277
Test name
Test status
Simulation time 244326425 ps
CPU time 1.04 seconds
Started Aug 14 05:10:28 PM PDT 24
Finished Aug 14 05:10:29 PM PDT 24
Peak memory 217820 kb
Host smart-7d358596-5998-4665-9617-b0fe3b2732b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26690647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.26690647
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.444967985
Short name T18
Test name
Test status
Simulation time 196208858 ps
CPU time 0.96 seconds
Started Aug 14 05:10:28 PM PDT 24
Finished Aug 14 05:10:29 PM PDT 24
Peak memory 200468 kb
Host smart-16e54c68-7d81-4ea0-8a97-9cb01fccd5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444967985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.444967985
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1488168968
Short name T13
Test name
Test status
Simulation time 1583219875 ps
CPU time 5.98 seconds
Started Aug 14 05:10:25 PM PDT 24
Finished Aug 14 05:10:31 PM PDT 24
Peak memory 200804 kb
Host smart-7b48dcb0-3f24-4726-97b7-34003fd2d95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488168968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1488168968
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3886077697
Short name T298
Test name
Test status
Simulation time 182774099 ps
CPU time 1.15 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 200668 kb
Host smart-149b6655-55da-4929-85a7-d34cec564b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886077697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3886077697
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2573406392
Short name T449
Test name
Test status
Simulation time 124198165 ps
CPU time 1.28 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:29 PM PDT 24
Peak memory 200744 kb
Host smart-c9af906f-b071-4bda-8f26-8ba02d780b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573406392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2573406392
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3358019955
Short name T307
Test name
Test status
Simulation time 8388975202 ps
CPU time 35.9 seconds
Started Aug 14 05:10:28 PM PDT 24
Finished Aug 14 05:11:05 PM PDT 24
Peak memory 209124 kb
Host smart-9cef4d4a-afe0-4084-a1de-286e823aa452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358019955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3358019955
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2549415889
Short name T510
Test name
Test status
Simulation time 342197572 ps
CPU time 2.21 seconds
Started Aug 14 05:10:28 PM PDT 24
Finished Aug 14 05:10:30 PM PDT 24
Peak memory 200520 kb
Host smart-e95d4c04-1790-4437-89cc-663147c3cae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549415889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2549415889
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1949809233
Short name T287
Test name
Test status
Simulation time 201318318 ps
CPU time 1.31 seconds
Started Aug 14 05:10:32 PM PDT 24
Finished Aug 14 05:10:34 PM PDT 24
Peak memory 200628 kb
Host smart-374ff716-e483-4f8a-86ae-70227ebddf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949809233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1949809233
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2532958059
Short name T211
Test name
Test status
Simulation time 64980738 ps
CPU time 0.8 seconds
Started Aug 14 05:10:36 PM PDT 24
Finished Aug 14 05:10:37 PM PDT 24
Peak memory 200508 kb
Host smart-1c6efc8f-7fed-4928-9b26-0b956b91c3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532958059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2532958059
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.2704613260
Short name T52
Test name
Test status
Simulation time 2339720777 ps
CPU time 8.31 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:35 PM PDT 24
Peak memory 222040 kb
Host smart-693a973e-e54d-47a2-8342-be6c94a9b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704613260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2704613260
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3587241150
Short name T347
Test name
Test status
Simulation time 245399524 ps
CPU time 1.03 seconds
Started Aug 14 05:10:30 PM PDT 24
Finished Aug 14 05:10:31 PM PDT 24
Peak memory 217824 kb
Host smart-b16762a5-991f-4f80-9e3a-2ca9894c5271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587241150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3587241150
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2225550229
Short name T511
Test name
Test status
Simulation time 218368856 ps
CPU time 1.01 seconds
Started Aug 14 05:10:28 PM PDT 24
Finished Aug 14 05:10:29 PM PDT 24
Peak memory 200460 kb
Host smart-dd6d5bca-4f80-47d5-836d-81963903bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225550229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2225550229
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.440908729
Short name T112
Test name
Test status
Simulation time 1987162571 ps
CPU time 8.39 seconds
Started Aug 14 05:10:27 PM PDT 24
Finished Aug 14 05:10:36 PM PDT 24
Peak memory 200772 kb
Host smart-07111adf-5b41-4983-8f9e-4c4a94523fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440908729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.440908729
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1687088562
Short name T36
Test name
Test status
Simulation time 177496658 ps
CPU time 1.27 seconds
Started Aug 14 05:10:29 PM PDT 24
Finished Aug 14 05:10:30 PM PDT 24
Peak memory 200624 kb
Host smart-c08bbac2-52ca-49a2-a6fe-3632dd66d2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687088562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1687088562
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2971483992
Short name T363
Test name
Test status
Simulation time 258856263 ps
CPU time 1.53 seconds
Started Aug 14 05:10:31 PM PDT 24
Finished Aug 14 05:10:33 PM PDT 24
Peak memory 200744 kb
Host smart-037bc9dc-156f-40e4-90f8-e86c05c6943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971483992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2971483992
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.209704237
Short name T289
Test name
Test status
Simulation time 7913336251 ps
CPU time 29.68 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:11:07 PM PDT 24
Peak memory 209052 kb
Host smart-f900fb27-28a6-47b4-8f8d-da96535497a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209704237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.209704237
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2407123760
Short name T539
Test name
Test status
Simulation time 137947595 ps
CPU time 1.8 seconds
Started Aug 14 05:10:26 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 200556 kb
Host smart-d61dc34f-c51f-4961-acba-dbbea8c88a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407123760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2407123760
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.755698382
Short name T301
Test name
Test status
Simulation time 196324583 ps
CPU time 1.46 seconds
Started Aug 14 05:10:30 PM PDT 24
Finished Aug 14 05:10:32 PM PDT 24
Peak memory 200600 kb
Host smart-2d500c10-b41a-4dd4-b0fb-b5c6254d6bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755698382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.755698382
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.2065147866
Short name T251
Test name
Test status
Simulation time 76830987 ps
CPU time 0.85 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:10:38 PM PDT 24
Peak memory 200528 kb
Host smart-0115c9bb-e305-4dee-99dc-a481b42fd706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065147866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2065147866
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2091817340
Short name T411
Test name
Test status
Simulation time 1227617888 ps
CPU time 5.55 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:10:43 PM PDT 24
Peak memory 218008 kb
Host smart-1bbc5340-4dca-4877-ae3c-bd0c69c53e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091817340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2091817340
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.723737511
Short name T127
Test name
Test status
Simulation time 245701965 ps
CPU time 1.15 seconds
Started Aug 14 05:10:36 PM PDT 24
Finished Aug 14 05:10:37 PM PDT 24
Peak memory 217884 kb
Host smart-9255ed7d-0626-468b-a6c7-258684200c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723737511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.723737511
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3913311711
Short name T169
Test name
Test status
Simulation time 118940333 ps
CPU time 0.78 seconds
Started Aug 14 05:10:38 PM PDT 24
Finished Aug 14 05:10:39 PM PDT 24
Peak memory 200468 kb
Host smart-6b1d74b5-9958-4959-81b3-70bfc40d769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913311711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3913311711
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2748838123
Short name T484
Test name
Test status
Simulation time 1315087832 ps
CPU time 5.64 seconds
Started Aug 14 05:10:42 PM PDT 24
Finished Aug 14 05:10:48 PM PDT 24
Peak memory 200876 kb
Host smart-223ad2b2-a090-42c4-8336-9117d3a257bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748838123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2748838123
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1630676951
Short name T1
Test name
Test status
Simulation time 145492145 ps
CPU time 1.21 seconds
Started Aug 14 05:10:36 PM PDT 24
Finished Aug 14 05:10:37 PM PDT 24
Peak memory 200652 kb
Host smart-500faec8-97ad-4d62-80bb-6f72f2b92a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630676951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1630676951
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1375605657
Short name T124
Test name
Test status
Simulation time 200818124 ps
CPU time 1.43 seconds
Started Aug 14 05:10:40 PM PDT 24
Finished Aug 14 05:10:42 PM PDT 24
Peak memory 200768 kb
Host smart-91375125-3df1-4088-bb7f-f453ed049d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375605657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1375605657
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1632953486
Short name T380
Test name
Test status
Simulation time 2121129113 ps
CPU time 7.78 seconds
Started Aug 14 05:10:41 PM PDT 24
Finished Aug 14 05:10:49 PM PDT 24
Peak memory 200812 kb
Host smart-c285941a-f9b1-4966-8a5c-26770d74d29b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632953486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1632953486
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2977437210
Short name T23
Test name
Test status
Simulation time 134164434 ps
CPU time 1.6 seconds
Started Aug 14 05:10:42 PM PDT 24
Finished Aug 14 05:10:44 PM PDT 24
Peak memory 208744 kb
Host smart-b81ceaf2-589a-4dd0-8a9e-b4a1a9a1d0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977437210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2977437210
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2234880466
Short name T130
Test name
Test status
Simulation time 61411768 ps
CPU time 0.77 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:10:38 PM PDT 24
Peak memory 200660 kb
Host smart-6dbb8b57-0776-41f5-ad13-5fbb12a036a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234880466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2234880466
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3499213461
Short name T310
Test name
Test status
Simulation time 65326571 ps
CPU time 0.82 seconds
Started Aug 14 05:10:38 PM PDT 24
Finished Aug 14 05:10:39 PM PDT 24
Peak memory 200516 kb
Host smart-22a6ece0-b1d9-47df-a98e-fdc519c5a908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499213461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3499213461
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.1996963493
Short name T296
Test name
Test status
Simulation time 1889712892 ps
CPU time 8.1 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:10:45 PM PDT 24
Peak memory 218012 kb
Host smart-18b65be3-3d2a-4847-b072-9a8366355e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996963493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1996963493
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3784280434
Short name T515
Test name
Test status
Simulation time 243654132 ps
CPU time 1.06 seconds
Started Aug 14 05:10:36 PM PDT 24
Finished Aug 14 05:10:37 PM PDT 24
Peak memory 217824 kb
Host smart-0a11908e-c2ba-4c31-913e-fba4aa6b9316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784280434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3784280434
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.94797647
Short name T228
Test name
Test status
Simulation time 165401339 ps
CPU time 0.88 seconds
Started Aug 14 05:10:35 PM PDT 24
Finished Aug 14 05:10:36 PM PDT 24
Peak memory 200508 kb
Host smart-d8b0ff31-b918-4983-9c00-424618123ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94797647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.94797647
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.939754123
Short name T376
Test name
Test status
Simulation time 775070262 ps
CPU time 4.07 seconds
Started Aug 14 05:10:36 PM PDT 24
Finished Aug 14 05:10:41 PM PDT 24
Peak memory 200756 kb
Host smart-b7ad214e-f7c9-4711-99a7-d023694d253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939754123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.939754123
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1361995094
Short name T39
Test name
Test status
Simulation time 107946935 ps
CPU time 1.03 seconds
Started Aug 14 05:10:36 PM PDT 24
Finished Aug 14 05:10:37 PM PDT 24
Peak memory 200604 kb
Host smart-7acae35b-06ee-401b-b23b-6e8e12100f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361995094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1361995094
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1909834412
Short name T537
Test name
Test status
Simulation time 235454760 ps
CPU time 1.49 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:10:38 PM PDT 24
Peak memory 200760 kb
Host smart-98d68a2f-7095-4f0c-8193-597fd44ea819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909834412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1909834412
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1659680917
Short name T299
Test name
Test status
Simulation time 11636756120 ps
CPU time 43.31 seconds
Started Aug 14 05:10:34 PM PDT 24
Finished Aug 14 05:11:18 PM PDT 24
Peak memory 209080 kb
Host smart-7733f3c2-f556-43d3-9c24-0fd2e74645bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659680917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1659680917
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3416437372
Short name T496
Test name
Test status
Simulation time 469873205 ps
CPU time 2.71 seconds
Started Aug 14 05:10:36 PM PDT 24
Finished Aug 14 05:10:39 PM PDT 24
Peak memory 200544 kb
Host smart-829edecc-d454-4d62-9100-ee2edab9d671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416437372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3416437372
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3257165843
Short name T425
Test name
Test status
Simulation time 242083662 ps
CPU time 1.4 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:10:39 PM PDT 24
Peak memory 200536 kb
Host smart-fab3f77f-bcbf-4dff-8c4b-76ebe0ebce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257165843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3257165843
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3732360328
Short name T4
Test name
Test status
Simulation time 74732434 ps
CPU time 0.77 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200496 kb
Host smart-b457a8cb-c4c4-411d-bb79-190158f3dea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732360328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3732360328
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.2991136103
Short name T418
Test name
Test status
Simulation time 1225211165 ps
CPU time 6.51 seconds
Started Aug 14 05:10:41 PM PDT 24
Finished Aug 14 05:10:47 PM PDT 24
Peak memory 217812 kb
Host smart-556b308f-7b56-4622-bb41-fd47e0d1bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991136103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2991136103
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4226934328
Short name T434
Test name
Test status
Simulation time 244566326 ps
CPU time 1.07 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 217832 kb
Host smart-93ef1417-7f39-48f4-96f5-2a252d01c5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226934328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4226934328
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.66941789
Short name T19
Test name
Test status
Simulation time 84862444 ps
CPU time 0.74 seconds
Started Aug 14 05:10:42 PM PDT 24
Finished Aug 14 05:10:43 PM PDT 24
Peak memory 200488 kb
Host smart-e5ddfdae-3416-45b1-9bd6-3ebddb97fa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66941789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.66941789
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.3370308908
Short name T234
Test name
Test status
Simulation time 1739951827 ps
CPU time 6.66 seconds
Started Aug 14 05:10:39 PM PDT 24
Finished Aug 14 05:10:46 PM PDT 24
Peak memory 200888 kb
Host smart-72e84320-dcec-4086-a67b-9c5ecd9b22d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370308908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3370308908
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.92656623
Short name T336
Test name
Test status
Simulation time 163358674 ps
CPU time 1.17 seconds
Started Aug 14 05:10:36 PM PDT 24
Finished Aug 14 05:10:38 PM PDT 24
Peak memory 200668 kb
Host smart-0c0c9b6b-cd36-4e58-a82b-df228346be25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92656623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.92656623
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3016004570
Short name T153
Test name
Test status
Simulation time 3101175183 ps
CPU time 10.95 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:11:02 PM PDT 24
Peak memory 210556 kb
Host smart-c8ab7088-96d5-4eda-8e69-9c2368391f95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016004570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3016004570
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.1619067875
Short name T361
Test name
Test status
Simulation time 150416537 ps
CPU time 1.8 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:10:39 PM PDT 24
Peak memory 200520 kb
Host smart-6452b872-b691-4d97-8487-4e0dd8aafce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619067875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1619067875
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2644993355
Short name T401
Test name
Test status
Simulation time 106705710 ps
CPU time 1.02 seconds
Started Aug 14 05:10:37 PM PDT 24
Finished Aug 14 05:10:38 PM PDT 24
Peak memory 200636 kb
Host smart-b4d7371e-bfa7-47ae-a27d-73adde6ffa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644993355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2644993355
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2512370778
Short name T218
Test name
Test status
Simulation time 74036367 ps
CPU time 0.77 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200508 kb
Host smart-61fbed25-6150-42a4-b6c2-194f88dcd08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512370778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2512370778
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.2478569429
Short name T448
Test name
Test status
Simulation time 1890676049 ps
CPU time 7.5 seconds
Started Aug 14 05:10:53 PM PDT 24
Finished Aug 14 05:11:00 PM PDT 24
Peak memory 217328 kb
Host smart-19cc1724-2ee6-44f4-b66f-8720e1b886b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478569429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2478569429
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1187771774
Short name T61
Test name
Test status
Simulation time 244955011 ps
CPU time 1.07 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:50 PM PDT 24
Peak memory 217816 kb
Host smart-81ccd079-72d0-4e07-b87e-aa40280dc9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187771774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1187771774
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.840055063
Short name T457
Test name
Test status
Simulation time 144733022 ps
CPU time 0.85 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200496 kb
Host smart-82b24419-67b0-406d-baa3-a880fe749d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840055063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.840055063
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3106760215
Short name T405
Test name
Test status
Simulation time 1478010275 ps
CPU time 5.19 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:54 PM PDT 24
Peak memory 200844 kb
Host smart-f0c3acfd-ee00-4ffe-ad81-2ddbbb9d2ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106760215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3106760215
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2276294297
Short name T407
Test name
Test status
Simulation time 145247292 ps
CPU time 1.17 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200640 kb
Host smart-43aafc37-9fb6-4b11-a6f6-335236074690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276294297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2276294297
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3886892744
Short name T514
Test name
Test status
Simulation time 261701722 ps
CPU time 1.68 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200752 kb
Host smart-a4aed025-243c-4e04-be95-fa3539d26010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886892744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3886892744
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3557461517
Short name T261
Test name
Test status
Simulation time 264609882 ps
CPU time 1.73 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200512 kb
Host smart-48d731a5-631c-422b-ace7-2db9c8b3717d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557461517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3557461517
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.4216944972
Short name T430
Test name
Test status
Simulation time 81113272 ps
CPU time 0.81 seconds
Started Aug 14 05:10:52 PM PDT 24
Finished Aug 14 05:10:53 PM PDT 24
Peak memory 200624 kb
Host smart-14df1a73-aa74-4062-adf0-e5318cdf0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216944972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4216944972
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2138768035
Short name T392
Test name
Test status
Simulation time 79374368 ps
CPU time 0.81 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200536 kb
Host smart-4f8af61c-1135-4a52-a34b-f8b711149ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138768035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2138768035
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.3436938974
Short name T274
Test name
Test status
Simulation time 1218381833 ps
CPU time 6.18 seconds
Started Aug 14 05:10:56 PM PDT 24
Finished Aug 14 05:11:02 PM PDT 24
Peak memory 218020 kb
Host smart-5a376104-9857-4380-99da-448475e7b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436938974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3436938974
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3109763351
Short name T284
Test name
Test status
Simulation time 246147939 ps
CPU time 1.07 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 217880 kb
Host smart-616a5db5-179c-40a2-9b80-f4838c3bc028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109763351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3109763351
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.459331656
Short name T286
Test name
Test status
Simulation time 240951677 ps
CPU time 0.93 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200444 kb
Host smart-89738aaa-4455-4ced-a142-e4cd4d07a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459331656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.459331656
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2601094558
Short name T415
Test name
Test status
Simulation time 1580914074 ps
CPU time 6.45 seconds
Started Aug 14 05:10:48 PM PDT 24
Finished Aug 14 05:10:54 PM PDT 24
Peak memory 200744 kb
Host smart-b01b3a4c-f418-47a9-b498-c416f5df9133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601094558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2601094558
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.682736082
Short name T178
Test name
Test status
Simulation time 111694599 ps
CPU time 1.04 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200652 kb
Host smart-cc7e88d9-8aef-4b9e-87f0-bba868005139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682736082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.682736082
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.2804240436
Short name T422
Test name
Test status
Simulation time 221950780 ps
CPU time 1.55 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200636 kb
Host smart-7c615bd0-acc5-4f72-a477-bf1c9f77da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804240436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2804240436
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.3326157363
Short name T108
Test name
Test status
Simulation time 4715768547 ps
CPU time 16.23 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:11:08 PM PDT 24
Peak memory 200760 kb
Host smart-f80c5e1b-2ef0-4cb3-b396-5bb3994e89c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326157363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.3326157363
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2279388466
Short name T170
Test name
Test status
Simulation time 382251789 ps
CPU time 2.41 seconds
Started Aug 14 05:10:53 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 200544 kb
Host smart-396946a6-c708-4834-bf1b-8778b84e6dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279388466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2279388466
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2661712124
Short name T71
Test name
Test status
Simulation time 158286622 ps
CPU time 1.26 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200712 kb
Host smart-ced27faa-dec5-41cf-b034-260bbb341dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661712124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2661712124
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2227886453
Short name T149
Test name
Test status
Simulation time 78283268 ps
CPU time 0.8 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:50 PM PDT 24
Peak memory 200532 kb
Host smart-d4928506-4e89-4474-aca5-5d4908f282b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227886453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2227886453
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2880623919
Short name T203
Test name
Test status
Simulation time 243400839 ps
CPU time 1.19 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 217688 kb
Host smart-14234a21-cd27-40f0-be75-09c48eab4d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880623919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2880623919
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.1823996530
Short name T396
Test name
Test status
Simulation time 103486334 ps
CPU time 0.79 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200472 kb
Host smart-5eec1a47-ff23-4a0f-9db9-4d27b2edb565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823996530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1823996530
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.1153957265
Short name T283
Test name
Test status
Simulation time 1540883672 ps
CPU time 6.34 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:56 PM PDT 24
Peak memory 200820 kb
Host smart-5e5b76a8-0fbc-4d62-9609-287535091284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153957265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1153957265
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2757424078
Short name T463
Test name
Test status
Simulation time 158333396 ps
CPU time 1.2 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200644 kb
Host smart-c27b673b-33ad-4075-a1ce-6da6260ea00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757424078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2757424078
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2237710789
Short name T330
Test name
Test status
Simulation time 113291352 ps
CPU time 1.17 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200756 kb
Host smart-03d13e2e-997c-4bf2-8c66-bf8431a158cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237710789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2237710789
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.133647339
Short name T240
Test name
Test status
Simulation time 365653454 ps
CPU time 2.31 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200552 kb
Host smart-3dbc3655-5f5a-4a6f-9a15-1ac9277ce03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133647339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.133647339
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4054407880
Short name T518
Test name
Test status
Simulation time 74659886 ps
CPU time 0.81 seconds
Started Aug 14 05:10:50 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200664 kb
Host smart-4fa2ffd2-4f2b-4d4c-8205-df58a77a765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054407880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4054407880
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2148056005
Short name T357
Test name
Test status
Simulation time 60946182 ps
CPU time 0.74 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 200516 kb
Host smart-d5d2dada-5d2e-452d-8b24-32b5556b908e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148056005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2148056005
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1086398475
Short name T461
Test name
Test status
Simulation time 1223621870 ps
CPU time 6.25 seconds
Started Aug 14 05:10:52 PM PDT 24
Finished Aug 14 05:10:58 PM PDT 24
Peak memory 217660 kb
Host smart-81c514a7-9df6-41c8-8dbe-8090e009e32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086398475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1086398475
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1425128507
Short name T341
Test name
Test status
Simulation time 244290171 ps
CPU time 1.13 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 217700 kb
Host smart-45a4d19b-6930-45cb-b59b-3534afdb3f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425128507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1425128507
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.3907777299
Short name T492
Test name
Test status
Simulation time 201165830 ps
CPU time 0.93 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:50 PM PDT 24
Peak memory 200432 kb
Host smart-bbd17ad1-b45d-4a99-a007-a4766046efdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907777299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3907777299
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.2556737658
Short name T254
Test name
Test status
Simulation time 2146425050 ps
CPU time 7.94 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:57 PM PDT 24
Peak memory 200820 kb
Host smart-18c3859b-de0e-4371-9b10-cdab95e78a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556737658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2556737658
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.2666826633
Short name T506
Test name
Test status
Simulation time 157040094 ps
CPU time 1.22 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:52 PM PDT 24
Peak memory 200548 kb
Host smart-bdd7fe38-164d-4b50-8068-94081f2a56d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666826633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.2666826633
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.3479942662
Short name T428
Test name
Test status
Simulation time 196071480 ps
CPU time 1.47 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200804 kb
Host smart-029ef2fb-c27d-4ee9-af1d-0b49b999a6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479942662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3479942662
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.3364024080
Short name T531
Test name
Test status
Simulation time 7679761495 ps
CPU time 26.31 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:11:21 PM PDT 24
Peak memory 200848 kb
Host smart-a2b4236a-ed87-4162-a66d-022acef2a70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364024080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3364024080
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.4280471535
Short name T224
Test name
Test status
Simulation time 268279840 ps
CPU time 1.87 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:51 PM PDT 24
Peak memory 200504 kb
Host smart-d9ff1bcf-cfea-4903-b353-5dcd8c6189aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280471535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.4280471535
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.765947010
Short name T262
Test name
Test status
Simulation time 249996918 ps
CPU time 1.31 seconds
Started Aug 14 05:10:49 PM PDT 24
Finished Aug 14 05:10:50 PM PDT 24
Peak memory 200560 kb
Host smart-bfa16020-d71d-40bc-8298-7303d1c003de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765947010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.765947010
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2006386237
Short name T410
Test name
Test status
Simulation time 68570205 ps
CPU time 0.79 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 200516 kb
Host smart-e430cdc6-8606-4da8-8aed-90404363a375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006386237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2006386237
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.687899348
Short name T504
Test name
Test status
Simulation time 1230824299 ps
CPU time 5.75 seconds
Started Aug 14 05:10:52 PM PDT 24
Finished Aug 14 05:10:58 PM PDT 24
Peak memory 217068 kb
Host smart-5725b0df-05f0-4137-9a3d-604d4b5255b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687899348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.687899348
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.255783675
Short name T8
Test name
Test status
Simulation time 244112676 ps
CPU time 1.16 seconds
Started Aug 14 05:10:58 PM PDT 24
Finished Aug 14 05:10:59 PM PDT 24
Peak memory 217880 kb
Host smart-f798f5b3-7de3-4e37-8e7b-b4ea816f5e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255783675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.255783675
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3528054766
Short name T344
Test name
Test status
Simulation time 231110652 ps
CPU time 1.02 seconds
Started Aug 14 05:10:53 PM PDT 24
Finished Aug 14 05:10:54 PM PDT 24
Peak memory 200384 kb
Host smart-0f8a7aaf-89bf-46cb-bc13-7d50fdb1fcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528054766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3528054766
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3246334710
Short name T498
Test name
Test status
Simulation time 971791240 ps
CPU time 4.6 seconds
Started Aug 14 05:10:58 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 200880 kb
Host smart-8fbb1647-0e6c-4018-9b88-2f20fddf3ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246334710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3246334710
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2964899866
Short name T445
Test name
Test status
Simulation time 108163850 ps
CPU time 1.1 seconds
Started Aug 14 05:10:56 PM PDT 24
Finished Aug 14 05:10:57 PM PDT 24
Peak memory 200660 kb
Host smart-77512150-7e75-446c-99cf-7c1d05454d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964899866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2964899866
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3032754994
Short name T494
Test name
Test status
Simulation time 123416739 ps
CPU time 1.25 seconds
Started Aug 14 05:10:51 PM PDT 24
Finished Aug 14 05:10:53 PM PDT 24
Peak memory 200716 kb
Host smart-bcfc9a66-5ee1-4651-931f-ab16b8280bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032754994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3032754994
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1968962936
Short name T468
Test name
Test status
Simulation time 5153568406 ps
CPU time 17.3 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:11:12 PM PDT 24
Peak memory 200900 kb
Host smart-7c84af2b-aa5a-4c21-8b2a-05577a8f0556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968962936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1968962936
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2411468639
Short name T538
Test name
Test status
Simulation time 141454762 ps
CPU time 1.65 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:56 PM PDT 24
Peak memory 200516 kb
Host smart-a5fad36a-53f4-4894-a9cf-4ce6b40a2886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411468639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2411468639
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1799057516
Short name T419
Test name
Test status
Simulation time 159748447 ps
CPU time 1.21 seconds
Started Aug 14 05:10:56 PM PDT 24
Finished Aug 14 05:10:57 PM PDT 24
Peak memory 200652 kb
Host smart-fecb3279-82d2-431c-aacb-a04fa4f9837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799057516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1799057516
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1989221312
Short name T402
Test name
Test status
Simulation time 91480173 ps
CPU time 0.84 seconds
Started Aug 14 05:09:27 PM PDT 24
Finished Aug 14 05:09:28 PM PDT 24
Peak memory 200524 kb
Host smart-98254db0-055b-41d2-92e2-688a048d4bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989221312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1989221312
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.993292446
Short name T464
Test name
Test status
Simulation time 1881953373 ps
CPU time 7.92 seconds
Started Aug 14 05:09:24 PM PDT 24
Finished Aug 14 05:09:32 PM PDT 24
Peak memory 218012 kb
Host smart-ea3e349d-160a-4806-8a58-06328240bfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993292446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.993292446
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3811257105
Short name T412
Test name
Test status
Simulation time 245735148 ps
CPU time 1.03 seconds
Started Aug 14 05:09:22 PM PDT 24
Finished Aug 14 05:09:23 PM PDT 24
Peak memory 217728 kb
Host smart-8e93ddfa-e568-443f-acfe-9fd7ba832b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811257105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3811257105
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2796833826
Short name T271
Test name
Test status
Simulation time 91617128 ps
CPU time 0.78 seconds
Started Aug 14 05:09:23 PM PDT 24
Finished Aug 14 05:09:24 PM PDT 24
Peak memory 200344 kb
Host smart-1ba699dc-8326-4616-a492-7d87f87251e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796833826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2796833826
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3955018938
Short name T517
Test name
Test status
Simulation time 912463459 ps
CPU time 4.75 seconds
Started Aug 14 05:09:23 PM PDT 24
Finished Aug 14 05:09:27 PM PDT 24
Peak memory 200784 kb
Host smart-1662fcff-07d8-4abd-9182-7242a837a665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955018938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3955018938
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.858925978
Short name T63
Test name
Test status
Simulation time 8280550082 ps
CPU time 14.94 seconds
Started Aug 14 05:09:24 PM PDT 24
Finished Aug 14 05:09:39 PM PDT 24
Peak memory 217560 kb
Host smart-e51c7b7c-f4aa-402c-ba70-d6e33464ef74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858925978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.858925978
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1336066091
Short name T532
Test name
Test status
Simulation time 101277312 ps
CPU time 1.01 seconds
Started Aug 14 05:09:22 PM PDT 24
Finished Aug 14 05:09:23 PM PDT 24
Peak memory 200648 kb
Host smart-71b38f73-a379-4580-a2dd-3531dbf53265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336066091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1336066091
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4000818701
Short name T38
Test name
Test status
Simulation time 112029224 ps
CPU time 1.23 seconds
Started Aug 14 05:09:23 PM PDT 24
Finished Aug 14 05:09:25 PM PDT 24
Peak memory 200720 kb
Host smart-fb8aa4cd-7ff7-45bc-940c-96b1253bc21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000818701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4000818701
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3498060563
Short name T5
Test name
Test status
Simulation time 4106025206 ps
CPU time 18.99 seconds
Started Aug 14 05:09:22 PM PDT 24
Finished Aug 14 05:09:41 PM PDT 24
Peak memory 200880 kb
Host smart-03cb4eb7-fef4-49bc-9787-e23cc9d29d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498060563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3498060563
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3437877784
Short name T474
Test name
Test status
Simulation time 55359424 ps
CPU time 0.74 seconds
Started Aug 14 05:09:28 PM PDT 24
Finished Aug 14 05:09:29 PM PDT 24
Peak memory 200656 kb
Host smart-559e597f-eb2c-454e-b0f5-ae87140b98eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437877784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3437877784
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3357060997
Short name T184
Test name
Test status
Simulation time 85332089 ps
CPU time 0.81 seconds
Started Aug 14 05:10:55 PM PDT 24
Finished Aug 14 05:10:56 PM PDT 24
Peak memory 200524 kb
Host smart-6c2a6333-9bf9-4277-92eb-321f81ac2a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357060997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3357060997
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1499624256
Short name T26
Test name
Test status
Simulation time 2360594927 ps
CPU time 9.5 seconds
Started Aug 14 05:10:55 PM PDT 24
Finished Aug 14 05:11:05 PM PDT 24
Peak memory 217824 kb
Host smart-ec511aec-19d4-428b-b170-04925dd8f33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499624256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1499624256
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.747616053
Short name T444
Test name
Test status
Simulation time 243456769 ps
CPU time 1.09 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 216296 kb
Host smart-2536b10a-0c5f-4f2a-8d34-3c1586847900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747616053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.747616053
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1535375812
Short name T163
Test name
Test status
Simulation time 92732800 ps
CPU time 0.73 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:54 PM PDT 24
Peak memory 199068 kb
Host smart-27e2e678-e7c5-4914-93ed-317ef667bf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535375812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1535375812
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3674003606
Short name T81
Test name
Test status
Simulation time 2062091586 ps
CPU time 7.69 seconds
Started Aug 14 05:10:52 PM PDT 24
Finished Aug 14 05:11:00 PM PDT 24
Peak memory 200808 kb
Host smart-6cb35574-0f3e-4cd3-9b0b-e3c8375cf3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674003606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3674003606
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1745940326
Short name T154
Test name
Test status
Simulation time 157651883 ps
CPU time 1.21 seconds
Started Aug 14 05:10:53 PM PDT 24
Finished Aug 14 05:10:54 PM PDT 24
Peak memory 200692 kb
Host smart-fa3ce333-01fa-4c39-9ad7-3fbcf8ab96b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745940326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1745940326
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3601403255
Short name T335
Test name
Test status
Simulation time 110034049 ps
CPU time 1.24 seconds
Started Aug 14 05:10:53 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 200660 kb
Host smart-0c4f3abb-019f-4589-a538-4da640f74b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601403255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3601403255
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3279992239
Short name T311
Test name
Test status
Simulation time 6460581599 ps
CPU time 23.26 seconds
Started Aug 14 05:10:58 PM PDT 24
Finished Aug 14 05:11:22 PM PDT 24
Peak memory 200912 kb
Host smart-6dbba1f7-1451-4a04-87c4-7ea303f99481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279992239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3279992239
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.923328062
Short name T183
Test name
Test status
Simulation time 278375426 ps
CPU time 2.03 seconds
Started Aug 14 05:10:56 PM PDT 24
Finished Aug 14 05:10:58 PM PDT 24
Peak memory 200552 kb
Host smart-8453df1f-54d7-4130-9520-cff69d2286e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923328062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.923328062
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3021274788
Short name T382
Test name
Test status
Simulation time 217699981 ps
CPU time 1.36 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 200576 kb
Host smart-ec7726e3-c568-4d3e-8bd3-543219ebd8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021274788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3021274788
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2821905351
Short name T456
Test name
Test status
Simulation time 68822563 ps
CPU time 0.82 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 200528 kb
Host smart-3ebc5c21-402b-4380-bfdd-38b6434df98f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821905351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2821905351
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.635438259
Short name T30
Test name
Test status
Simulation time 1222088991 ps
CPU time 5.73 seconds
Started Aug 14 05:10:58 PM PDT 24
Finished Aug 14 05:11:04 PM PDT 24
Peak memory 218012 kb
Host smart-97874185-955e-4710-9fe6-ab2afcf5cae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635438259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.635438259
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.127523883
Short name T176
Test name
Test status
Simulation time 244949277 ps
CPU time 1.07 seconds
Started Aug 14 05:10:56 PM PDT 24
Finished Aug 14 05:10:57 PM PDT 24
Peak memory 217884 kb
Host smart-ea2d9ba2-adf9-42bd-a1e4-6b447ff3e856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127523883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.127523883
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.4215634966
Short name T346
Test name
Test status
Simulation time 251372457 ps
CPU time 1 seconds
Started Aug 14 05:10:53 PM PDT 24
Finished Aug 14 05:10:54 PM PDT 24
Peak memory 200384 kb
Host smart-53f19b1e-fd4b-4731-8b11-1a266efb03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215634966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.4215634966
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.774099280
Short name T230
Test name
Test status
Simulation time 793501394 ps
CPU time 4.46 seconds
Started Aug 14 05:10:58 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 200832 kb
Host smart-8b690e0f-3d9a-4d38-986e-74c77a7bdc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774099280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.774099280
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.550047492
Short name T260
Test name
Test status
Simulation time 155565439 ps
CPU time 1.19 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 200668 kb
Host smart-e861e7bc-6c19-48e7-be17-d4ab631c7641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550047492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.550047492
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.139868318
Short name T331
Test name
Test status
Simulation time 124493703 ps
CPU time 1.21 seconds
Started Aug 14 05:10:58 PM PDT 24
Finished Aug 14 05:11:00 PM PDT 24
Peak memory 200764 kb
Host smart-a23058b1-aa88-499f-9083-9cfa04d9495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139868318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.139868318
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2262203245
Short name T213
Test name
Test status
Simulation time 5165993691 ps
CPU time 21.48 seconds
Started Aug 14 05:10:58 PM PDT 24
Finished Aug 14 05:11:20 PM PDT 24
Peak memory 210092 kb
Host smart-ed1e929a-f563-4ed2-8cf6-9de4c3069f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262203245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2262203245
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1699973276
Short name T427
Test name
Test status
Simulation time 126943286 ps
CPU time 1.59 seconds
Started Aug 14 05:10:53 PM PDT 24
Finished Aug 14 05:10:55 PM PDT 24
Peak memory 208756 kb
Host smart-4e785c8e-0223-4913-b76c-8a0301a4389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699973276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1699973276
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2317846090
Short name T324
Test name
Test status
Simulation time 200041224 ps
CPU time 1.29 seconds
Started Aug 14 05:10:54 PM PDT 24
Finished Aug 14 05:10:56 PM PDT 24
Peak memory 200652 kb
Host smart-9d383999-c5ba-43a0-bb85-1846aa2b7a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317846090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2317846090
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2052592585
Short name T340
Test name
Test status
Simulation time 70773985 ps
CPU time 0.81 seconds
Started Aug 14 05:11:14 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 200520 kb
Host smart-71052c2a-4070-417e-96b2-9e3b64b6135d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052592585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2052592585
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.4246056462
Short name T223
Test name
Test status
Simulation time 1894457154 ps
CPU time 6.83 seconds
Started Aug 14 05:11:01 PM PDT 24
Finished Aug 14 05:11:08 PM PDT 24
Peak memory 221948 kb
Host smart-f6ef1f85-7ac2-4c6e-a86e-f5cbcf50a8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246056462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4246056462
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3903731936
Short name T519
Test name
Test status
Simulation time 243779266 ps
CPU time 1.1 seconds
Started Aug 14 05:11:01 PM PDT 24
Finished Aug 14 05:11:02 PM PDT 24
Peak memory 217884 kb
Host smart-7c88466b-f8e4-422d-86bc-f88ce3ef8b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903731936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3903731936
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1941587726
Short name T391
Test name
Test status
Simulation time 86998781 ps
CPU time 0.79 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:14 PM PDT 24
Peak memory 200464 kb
Host smart-fb71cac9-8340-4cae-a912-15a1e7d1de4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941587726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1941587726
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.17857310
Short name T161
Test name
Test status
Simulation time 1053121383 ps
CPU time 5.58 seconds
Started Aug 14 05:11:00 PM PDT 24
Finished Aug 14 05:11:06 PM PDT 24
Peak memory 200844 kb
Host smart-249faec4-0779-492c-a3ad-f80842bf2b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17857310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.17857310
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.917086614
Short name T320
Test name
Test status
Simulation time 153374164 ps
CPU time 1.14 seconds
Started Aug 14 05:11:01 PM PDT 24
Finished Aug 14 05:11:02 PM PDT 24
Peak memory 200628 kb
Host smart-ecd25080-bd3b-44b3-a947-f9a307fa284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917086614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.917086614
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.893144481
Short name T41
Test name
Test status
Simulation time 114150166 ps
CPU time 1.24 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 200768 kb
Host smart-19afc005-a9af-40a5-b148-b0091e528e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893144481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.893144481
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3827831816
Short name T72
Test name
Test status
Simulation time 1518674950 ps
CPU time 6.81 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:09 PM PDT 24
Peak memory 209108 kb
Host smart-51795626-61bb-4e7c-97a1-968041c119e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827831816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3827831816
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.3034741255
Short name T533
Test name
Test status
Simulation time 140651638 ps
CPU time 1.89 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:04 PM PDT 24
Peak memory 200548 kb
Host smart-a67d529f-112f-4b43-bf9f-2a5cb2bab777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034741255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3034741255
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.1939095209
Short name T414
Test name
Test status
Simulation time 162529935 ps
CPU time 1.38 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:04 PM PDT 24
Peak memory 200716 kb
Host smart-c8f8de68-82df-4f89-9e2a-3254a5f55fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939095209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1939095209
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1688547648
Short name T128
Test name
Test status
Simulation time 53860389 ps
CPU time 0.76 seconds
Started Aug 14 05:11:03 PM PDT 24
Finished Aug 14 05:11:04 PM PDT 24
Peak memory 200536 kb
Host smart-ad6ea876-edb6-438c-abb2-a77fe107c618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688547648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1688547648
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3880304047
Short name T44
Test name
Test status
Simulation time 1894166587 ps
CPU time 7.11 seconds
Started Aug 14 05:11:03 PM PDT 24
Finished Aug 14 05:11:10 PM PDT 24
Peak memory 217300 kb
Host smart-833faa80-7bbf-449a-a375-3c5d06db3a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880304047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3880304047
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3255290283
Short name T509
Test name
Test status
Simulation time 243249114 ps
CPU time 1.07 seconds
Started Aug 14 05:11:14 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 217824 kb
Host smart-cd952dcb-3b05-4c34-b0d6-ce4410220b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255290283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3255290283
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1876516724
Short name T20
Test name
Test status
Simulation time 188408120 ps
CPU time 0.85 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 200464 kb
Host smart-2fda11e6-d6d5-4059-a3d0-6dcd904f625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876516724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1876516724
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3044371861
Short name T432
Test name
Test status
Simulation time 1726964392 ps
CPU time 7.26 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:10 PM PDT 24
Peak memory 200824 kb
Host smart-08d456e0-b59e-4e80-9e15-a42106ba6f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044371861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3044371861
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2404671992
Short name T313
Test name
Test status
Simulation time 102695329 ps
CPU time 1.02 seconds
Started Aug 14 05:11:01 PM PDT 24
Finished Aug 14 05:11:02 PM PDT 24
Peak memory 200668 kb
Host smart-32d2666c-2be9-437a-8cf0-f8567b301a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404671992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2404671992
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.3362029102
Short name T125
Test name
Test status
Simulation time 189403502 ps
CPU time 1.42 seconds
Started Aug 14 05:11:01 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 200744 kb
Host smart-de67b199-7c1c-4aef-982d-a25f74261a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362029102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3362029102
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1917840973
Short name T247
Test name
Test status
Simulation time 1800259990 ps
CPU time 7.61 seconds
Started Aug 14 05:11:03 PM PDT 24
Finished Aug 14 05:11:10 PM PDT 24
Peak memory 200788 kb
Host smart-38120ea6-208d-46c7-945b-b7edaf4a891f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917840973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1917840973
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1026560397
Short name T479
Test name
Test status
Simulation time 123736698 ps
CPU time 1.62 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 208792 kb
Host smart-e481d3c2-3f22-409c-ab6c-9ca6f225810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026560397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1026560397
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3855311163
Short name T332
Test name
Test status
Simulation time 115813970 ps
CPU time 1.05 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 200600 kb
Host smart-65d910e9-32a0-4ed4-ad72-d0b6aedb2702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855311163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3855311163
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3992518848
Short name T167
Test name
Test status
Simulation time 66150744 ps
CPU time 0.79 seconds
Started Aug 14 05:11:03 PM PDT 24
Finished Aug 14 05:11:04 PM PDT 24
Peak memory 200504 kb
Host smart-d3cf9a9b-ca44-4c14-b949-22491f5cae66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992518848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3992518848
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1566344776
Short name T34
Test name
Test status
Simulation time 1889623586 ps
CPU time 7.17 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:09 PM PDT 24
Peak memory 221984 kb
Host smart-053da19c-9791-4b37-801a-88313baa4e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566344776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1566344776
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2121013934
Short name T442
Test name
Test status
Simulation time 245125556 ps
CPU time 1.14 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:04 PM PDT 24
Peak memory 217864 kb
Host smart-8fe69ff1-0d80-45aa-a70c-74907260f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121013934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2121013934
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.1881927141
Short name T383
Test name
Test status
Simulation time 154321814 ps
CPU time 0.85 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 200460 kb
Host smart-725db1a9-aaae-47c2-b36d-932715d7dcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881927141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1881927141
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.499924994
Short name T305
Test name
Test status
Simulation time 1905634793 ps
CPU time 7.08 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:09 PM PDT 24
Peak memory 200812 kb
Host smart-d4ff34f6-bf30-4f29-8fdc-fed78bf81edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499924994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.499924994
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1987691457
Short name T148
Test name
Test status
Simulation time 141317970 ps
CPU time 1.21 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 200668 kb
Host smart-457c41cc-2b43-4575-99b0-0f74bad058f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987691457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1987691457
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.4203727050
Short name T472
Test name
Test status
Simulation time 205317507 ps
CPU time 1.5 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 200772 kb
Host smart-aa74f57c-4b9a-421f-b044-4c5b05be1d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203727050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.4203727050
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3238188157
Short name T88
Test name
Test status
Simulation time 6471086918 ps
CPU time 24.14 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:26 PM PDT 24
Peak memory 209060 kb
Host smart-e8f04378-4bee-474d-bead-9b47e636759d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238188157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3238188157
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.8285618
Short name T360
Test name
Test status
Simulation time 492693753 ps
CPU time 2.59 seconds
Started Aug 14 05:11:03 PM PDT 24
Finished Aug 14 05:11:06 PM PDT 24
Peak memory 200544 kb
Host smart-3ec975f4-55db-45e0-9e20-e11c951faab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8285618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.8285618
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.78151765
Short name T451
Test name
Test status
Simulation time 106191029 ps
CPU time 0.88 seconds
Started Aug 14 05:11:01 PM PDT 24
Finished Aug 14 05:11:02 PM PDT 24
Peak memory 200672 kb
Host smart-f7d2e7f7-d5ca-4c9c-8591-3d0b5a05a639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78151765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.78151765
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3166325536
Short name T424
Test name
Test status
Simulation time 69248945 ps
CPU time 0.79 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:14 PM PDT 24
Peak memory 200520 kb
Host smart-8666b104-edfa-42d4-9f0f-fdfe822507e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166325536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3166325536
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.316117013
Short name T417
Test name
Test status
Simulation time 1231491847 ps
CPU time 5.43 seconds
Started Aug 14 05:11:15 PM PDT 24
Finished Aug 14 05:11:21 PM PDT 24
Peak memory 217904 kb
Host smart-de88ee20-ae77-4084-8370-ac77ee09bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316117013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.316117013
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.594787321
Short name T352
Test name
Test status
Simulation time 243917617 ps
CPU time 1.1 seconds
Started Aug 14 05:11:10 PM PDT 24
Finished Aug 14 05:11:11 PM PDT 24
Peak memory 217848 kb
Host smart-1dabbf87-c95b-410e-b88e-c9464267323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594787321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.594787321
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.733394213
Short name T393
Test name
Test status
Simulation time 180108132 ps
CPU time 0.81 seconds
Started Aug 14 05:11:00 PM PDT 24
Finished Aug 14 05:11:01 PM PDT 24
Peak memory 200472 kb
Host smart-2c22981b-e198-4a5e-bbb2-fe63ec7dd6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733394213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.733394213
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3380968585
Short name T491
Test name
Test status
Simulation time 1900210532 ps
CPU time 6.66 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:08 PM PDT 24
Peak memory 200832 kb
Host smart-d5853904-6fe6-440e-84dc-41b9e8467740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380968585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3380968585
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1146069117
Short name T145
Test name
Test status
Simulation time 157746408 ps
CPU time 1.27 seconds
Started Aug 14 05:11:04 PM PDT 24
Finished Aug 14 05:11:06 PM PDT 24
Peak memory 200660 kb
Host smart-b3fb352e-c71f-48a5-826f-444e83fd83ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146069117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1146069117
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.388232765
Short name T2
Test name
Test status
Simulation time 205822902 ps
CPU time 1.44 seconds
Started Aug 14 05:11:04 PM PDT 24
Finished Aug 14 05:11:05 PM PDT 24
Peak memory 200752 kb
Host smart-2c648518-e581-4bf1-8213-dce83a2d424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388232765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.388232765
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1573384763
Short name T386
Test name
Test status
Simulation time 4929617508 ps
CPU time 18.87 seconds
Started Aug 14 05:11:10 PM PDT 24
Finished Aug 14 05:11:29 PM PDT 24
Peak memory 208972 kb
Host smart-0e408b10-cffc-4986-8f4d-f5903389cf9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573384763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1573384763
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.1293240419
Short name T483
Test name
Test status
Simulation time 125621187 ps
CPU time 1.67 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 208672 kb
Host smart-c9a9eac4-7e48-4fe7-b9d3-68457bc424c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293240419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.1293240419
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2007724839
Short name T3
Test name
Test status
Simulation time 157666080 ps
CPU time 1.06 seconds
Started Aug 14 05:11:02 PM PDT 24
Finished Aug 14 05:11:03 PM PDT 24
Peak memory 200588 kb
Host smart-19d5ba57-62e9-4678-b428-e5463ce85a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007724839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2007724839
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3865738725
Short name T151
Test name
Test status
Simulation time 70524969 ps
CPU time 0.77 seconds
Started Aug 14 05:11:09 PM PDT 24
Finished Aug 14 05:11:11 PM PDT 24
Peak memory 200512 kb
Host smart-f76c18eb-4eb2-4408-8478-1509c0f25389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865738725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3865738725
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2409808654
Short name T534
Test name
Test status
Simulation time 1877927732 ps
CPU time 7.32 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:19 PM PDT 24
Peak memory 221892 kb
Host smart-dcf4d580-df04-41e6-a0d1-dc60ddeae283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409808654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2409808654
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3206129052
Short name T188
Test name
Test status
Simulation time 244152837 ps
CPU time 1.06 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:13 PM PDT 24
Peak memory 217828 kb
Host smart-f1f0640a-1eb2-44d8-9f9f-ac6c452851dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206129052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3206129052
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.78679337
Short name T22
Test name
Test status
Simulation time 200040381 ps
CPU time 0.91 seconds
Started Aug 14 05:11:10 PM PDT 24
Finished Aug 14 05:11:12 PM PDT 24
Peak memory 200464 kb
Host smart-d9ff2f97-82e8-43d3-8fe9-ba89e58ec5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78679337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.78679337
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4176029611
Short name T377
Test name
Test status
Simulation time 1961994983 ps
CPU time 7.96 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:21 PM PDT 24
Peak memory 200812 kb
Host smart-56f947fc-49e2-444e-8bff-48d9b3dadaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176029611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4176029611
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1328638350
Short name T160
Test name
Test status
Simulation time 187612933 ps
CPU time 1.24 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:14 PM PDT 24
Peak memory 200640 kb
Host smart-1d0281f9-2bb7-4578-97f1-25ccb8b3054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328638350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1328638350
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3689728725
Short name T231
Test name
Test status
Simulation time 201522706 ps
CPU time 1.65 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:14 PM PDT 24
Peak memory 200764 kb
Host smart-e08c1203-3359-4b24-bfd5-7b434d14076e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689728725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3689728725
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.299940596
Short name T159
Test name
Test status
Simulation time 3055962137 ps
CPU time 11.8 seconds
Started Aug 14 05:11:14 PM PDT 24
Finished Aug 14 05:11:26 PM PDT 24
Peak memory 210640 kb
Host smart-649d77c6-b7f7-4ee5-a8cc-e999584c7d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299940596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.299940596
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.4111827173
Short name T530
Test name
Test status
Simulation time 387069238 ps
CPU time 2.4 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 208740 kb
Host smart-db04d23f-ab2f-4599-a8be-81f04b211e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111827173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.4111827173
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2285090448
Short name T465
Test name
Test status
Simulation time 143113812 ps
CPU time 1.36 seconds
Started Aug 14 05:11:11 PM PDT 24
Finished Aug 14 05:11:13 PM PDT 24
Peak memory 200672 kb
Host smart-a79ee67e-e6d3-4a7c-b461-0964ca415838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285090448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2285090448
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.316887809
Short name T501
Test name
Test status
Simulation time 92609870 ps
CPU time 0.83 seconds
Started Aug 14 05:11:10 PM PDT 24
Finished Aug 14 05:11:11 PM PDT 24
Peak memory 200500 kb
Host smart-857a99d9-7cb7-44b9-b9a5-a0a005539a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316887809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.316887809
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.4244213914
Short name T458
Test name
Test status
Simulation time 1233084250 ps
CPU time 5.25 seconds
Started Aug 14 05:11:14 PM PDT 24
Finished Aug 14 05:11:19 PM PDT 24
Peak memory 221908 kb
Host smart-2575a078-0f59-4a6b-b9cd-d4e206d735e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244213914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.4244213914
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3509996208
Short name T315
Test name
Test status
Simulation time 244607733 ps
CPU time 1.13 seconds
Started Aug 14 05:11:14 PM PDT 24
Finished Aug 14 05:11:16 PM PDT 24
Peak memory 217756 kb
Host smart-c0a33895-0eaf-4805-bc67-e6027a195848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509996208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3509996208
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2993837180
Short name T280
Test name
Test status
Simulation time 123451537 ps
CPU time 0.83 seconds
Started Aug 14 05:11:11 PM PDT 24
Finished Aug 14 05:11:12 PM PDT 24
Peak memory 200460 kb
Host smart-13abf1a1-6305-4daf-989e-92185ac83024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993837180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2993837180
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.508301281
Short name T82
Test name
Test status
Simulation time 821621387 ps
CPU time 4.34 seconds
Started Aug 14 05:11:10 PM PDT 24
Finished Aug 14 05:11:14 PM PDT 24
Peak memory 200764 kb
Host smart-a4d5c7a0-5e2e-43f1-b3ab-fe53eddb2c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508301281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.508301281
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2435435549
Short name T520
Test name
Test status
Simulation time 154447537 ps
CPU time 1.15 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 200628 kb
Host smart-e3cc235e-a536-44b2-a304-520a8823858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435435549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2435435549
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3660767460
Short name T113
Test name
Test status
Simulation time 246865178 ps
CPU time 1.45 seconds
Started Aug 14 05:11:11 PM PDT 24
Finished Aug 14 05:11:13 PM PDT 24
Peak memory 200768 kb
Host smart-aaa32601-7fb3-41ee-b391-3fa8412a2976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660767460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3660767460
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2282867825
Short name T394
Test name
Test status
Simulation time 9993774022 ps
CPU time 34.48 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:47 PM PDT 24
Peak memory 200828 kb
Host smart-e2eceff0-1a61-4bcb-8202-6da91bbf3d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282867825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2282867825
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3540645174
Short name T70
Test name
Test status
Simulation time 120909473 ps
CPU time 1.52 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:14 PM PDT 24
Peak memory 200556 kb
Host smart-14b471de-222d-4245-90fb-1c0d6f25c0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540645174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3540645174
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.903569212
Short name T499
Test name
Test status
Simulation time 107155908 ps
CPU time 1.07 seconds
Started Aug 14 05:11:11 PM PDT 24
Finished Aug 14 05:11:13 PM PDT 24
Peak memory 200664 kb
Host smart-137281d6-8048-4aef-9da9-093e30a20566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903569212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.903569212
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.2282164505
Short name T216
Test name
Test status
Simulation time 59986679 ps
CPU time 0.73 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:13 PM PDT 24
Peak memory 200528 kb
Host smart-3f4866b5-c415-40ac-b089-a89051b7394d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282164505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2282164505
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.149883436
Short name T437
Test name
Test status
Simulation time 1896711561 ps
CPU time 7.4 seconds
Started Aug 14 05:11:14 PM PDT 24
Finished Aug 14 05:11:22 PM PDT 24
Peak memory 217956 kb
Host smart-16b8b617-cd5f-4990-94a6-0fe7e1d6d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149883436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.149883436
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.430847613
Short name T505
Test name
Test status
Simulation time 244942508 ps
CPU time 1.13 seconds
Started Aug 14 05:11:11 PM PDT 24
Finished Aug 14 05:11:12 PM PDT 24
Peak memory 217872 kb
Host smart-04a784de-63cb-4544-a1e2-6d581e2d1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430847613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.430847613
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2390764942
Short name T16
Test name
Test status
Simulation time 107151189 ps
CPU time 0.84 seconds
Started Aug 14 05:11:10 PM PDT 24
Finished Aug 14 05:11:11 PM PDT 24
Peak memory 200460 kb
Host smart-bca9e131-b152-469c-8794-255e574a547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390764942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2390764942
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2907579097
Short name T345
Test name
Test status
Simulation time 2065788796 ps
CPU time 7.98 seconds
Started Aug 14 05:11:10 PM PDT 24
Finished Aug 14 05:11:18 PM PDT 24
Peak memory 200748 kb
Host smart-b61d8764-efcf-4142-95ab-0ea7c7751e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907579097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2907579097
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3999835933
Short name T450
Test name
Test status
Simulation time 154106505 ps
CPU time 1.14 seconds
Started Aug 14 05:11:11 PM PDT 24
Finished Aug 14 05:11:12 PM PDT 24
Peak memory 200652 kb
Host smart-cf907b93-25c1-4cf7-8f00-72d0cacd04f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999835933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3999835933
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3801329713
Short name T314
Test name
Test status
Simulation time 200363919 ps
CPU time 1.42 seconds
Started Aug 14 05:11:11 PM PDT 24
Finished Aug 14 05:11:13 PM PDT 24
Peak memory 200788 kb
Host smart-a8a0bac9-0c8d-4ab1-a8f6-54f4c3caeaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801329713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3801329713
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1937000524
Short name T157
Test name
Test status
Simulation time 3736184664 ps
CPU time 16.08 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:28 PM PDT 24
Peak memory 200796 kb
Host smart-d87d20f7-59a9-46cf-910d-df1cd7786887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937000524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1937000524
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.852483428
Short name T441
Test name
Test status
Simulation time 349026807 ps
CPU time 2.46 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:16 PM PDT 24
Peak memory 200552 kb
Host smart-c22f9dc2-e176-4037-b321-2da407eadf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852483428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.852483428
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3128788496
Short name T403
Test name
Test status
Simulation time 139531827 ps
CPU time 1.21 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 200664 kb
Host smart-6bc030f8-21e7-4de4-a87a-422508526b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128788496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3128788496
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.4049034318
Short name T385
Test name
Test status
Simulation time 58116684 ps
CPU time 0.8 seconds
Started Aug 14 05:11:23 PM PDT 24
Finished Aug 14 05:11:24 PM PDT 24
Peak memory 200528 kb
Host smart-14293413-cfaf-4ed8-b23d-04c3882ff153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049034318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4049034318
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.333525980
Short name T399
Test name
Test status
Simulation time 2367679871 ps
CPU time 8.26 seconds
Started Aug 14 05:11:22 PM PDT 24
Finished Aug 14 05:11:30 PM PDT 24
Peak memory 218148 kb
Host smart-dbd3e8d5-5d81-4dcc-812c-fbe8db26e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333525980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.333525980
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1111730179
Short name T536
Test name
Test status
Simulation time 244409173 ps
CPU time 1.15 seconds
Started Aug 14 05:11:23 PM PDT 24
Finished Aug 14 05:11:25 PM PDT 24
Peak memory 217820 kb
Host smart-fae124a1-c546-47a9-8152-aa01ebe71b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111730179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1111730179
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1922392244
Short name T312
Test name
Test status
Simulation time 232324738 ps
CPU time 0.99 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:15 PM PDT 24
Peak memory 200436 kb
Host smart-fcb3df79-81da-40dc-8ae1-2acd05e0ba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922392244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1922392244
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3161038723
Short name T155
Test name
Test status
Simulation time 898790582 ps
CPU time 4.76 seconds
Started Aug 14 05:11:13 PM PDT 24
Finished Aug 14 05:11:18 PM PDT 24
Peak memory 200840 kb
Host smart-e67a5126-f481-477d-acef-f9a5823b5d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161038723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3161038723
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1761625748
Short name T133
Test name
Test status
Simulation time 99939115 ps
CPU time 1.01 seconds
Started Aug 14 05:11:19 PM PDT 24
Finished Aug 14 05:11:20 PM PDT 24
Peak memory 200660 kb
Host smart-f4ea3945-d302-47a3-94bf-312c871e779d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761625748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1761625748
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3751350603
Short name T226
Test name
Test status
Simulation time 193527510 ps
CPU time 1.39 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:14 PM PDT 24
Peak memory 200776 kb
Host smart-0ae85f93-d6f6-4ad8-b920-eafe66283b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751350603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3751350603
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1342717670
Short name T111
Test name
Test status
Simulation time 3657179825 ps
CPU time 13.31 seconds
Started Aug 14 05:11:17 PM PDT 24
Finished Aug 14 05:11:31 PM PDT 24
Peak memory 200920 kb
Host smart-d98ecdfb-4176-4620-8476-bae44a436814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342717670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1342717670
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3093270109
Short name T9
Test name
Test status
Simulation time 131791717 ps
CPU time 1.67 seconds
Started Aug 14 05:11:15 PM PDT 24
Finished Aug 14 05:11:17 PM PDT 24
Peak memory 208628 kb
Host smart-366fcce2-20c9-4f81-ab47-d82525e13aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093270109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3093270109
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2615825946
Short name T219
Test name
Test status
Simulation time 93689296 ps
CPU time 0.86 seconds
Started Aug 14 05:11:12 PM PDT 24
Finished Aug 14 05:11:12 PM PDT 24
Peak memory 200628 kb
Host smart-02d019de-543c-494d-8cc9-478ee695b2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615825946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2615825946
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1941326336
Short name T502
Test name
Test status
Simulation time 76037369 ps
CPU time 0.81 seconds
Started Aug 14 05:09:39 PM PDT 24
Finished Aug 14 05:09:40 PM PDT 24
Peak memory 200516 kb
Host smart-0e9f1d73-9e2a-4eb4-b685-1d20b65abc7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941326336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1941326336
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2528611088
Short name T351
Test name
Test status
Simulation time 2359883107 ps
CPU time 8.27 seconds
Started Aug 14 05:09:34 PM PDT 24
Finished Aug 14 05:09:43 PM PDT 24
Peak memory 221972 kb
Host smart-8bf85773-cbc4-43fc-85cf-a3b3c553387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528611088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2528611088
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.55027776
Short name T370
Test name
Test status
Simulation time 245237269 ps
CPU time 1.13 seconds
Started Aug 14 05:09:33 PM PDT 24
Finished Aug 14 05:09:34 PM PDT 24
Peak memory 217880 kb
Host smart-d5d62643-f27c-45f6-9838-0ec4af744a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55027776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.55027776
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.664503902
Short name T166
Test name
Test status
Simulation time 129455100 ps
CPU time 0.88 seconds
Started Aug 14 05:09:39 PM PDT 24
Finished Aug 14 05:09:40 PM PDT 24
Peak memory 200488 kb
Host smart-99117636-f227-456a-993e-a4f5761217a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664503902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.664503902
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.227107262
Short name T89
Test name
Test status
Simulation time 1015339897 ps
CPU time 5.21 seconds
Started Aug 14 05:09:33 PM PDT 24
Finished Aug 14 05:09:38 PM PDT 24
Peak memory 200724 kb
Host smart-15e89043-9b92-4112-bd4a-f88fb40c4b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227107262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.227107262
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1002757407
Short name T66
Test name
Test status
Simulation time 16506405397 ps
CPU time 31.57 seconds
Started Aug 14 05:09:39 PM PDT 24
Finished Aug 14 05:10:11 PM PDT 24
Peak memory 217424 kb
Host smart-4b9754aa-ca3f-4464-9679-0ef5494283b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002757407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1002757407
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2795102266
Short name T141
Test name
Test status
Simulation time 101276061 ps
CPU time 1.04 seconds
Started Aug 14 05:09:33 PM PDT 24
Finished Aug 14 05:09:34 PM PDT 24
Peak memory 200652 kb
Host smart-f8753e32-fd63-4cc3-8021-a7864c16898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795102266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2795102266
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.3075474924
Short name T288
Test name
Test status
Simulation time 227447428 ps
CPU time 1.47 seconds
Started Aug 14 05:09:33 PM PDT 24
Finished Aug 14 05:09:35 PM PDT 24
Peak memory 200812 kb
Host smart-9fb78586-7a6a-4b93-9e30-6a5fee207195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075474924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3075474924
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1358510432
Short name T68
Test name
Test status
Simulation time 201413607 ps
CPU time 1.19 seconds
Started Aug 14 05:09:34 PM PDT 24
Finished Aug 14 05:09:36 PM PDT 24
Peak memory 200536 kb
Host smart-918e7bb8-b935-4fa7-a065-2636c9f81b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358510432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1358510432
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.142811319
Short name T270
Test name
Test status
Simulation time 153857879 ps
CPU time 1.88 seconds
Started Aug 14 05:09:36 PM PDT 24
Finished Aug 14 05:09:38 PM PDT 24
Peak memory 200576 kb
Host smart-dbb7d35a-cf73-4cf4-9645-e23306a88f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142811319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.142811319
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.479550074
Short name T6
Test name
Test status
Simulation time 119496358 ps
CPU time 1.07 seconds
Started Aug 14 05:09:33 PM PDT 24
Finished Aug 14 05:09:34 PM PDT 24
Peak memory 200600 kb
Host smart-602cf2ab-2cf2-4225-a2e3-2e65fb0b5cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479550074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.479550074
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1994210802
Short name T470
Test name
Test status
Simulation time 62444486 ps
CPU time 0.78 seconds
Started Aug 14 05:11:26 PM PDT 24
Finished Aug 14 05:11:27 PM PDT 24
Peak memory 200500 kb
Host smart-bf04bddd-bbbb-4c80-8c2e-63f6f49e69c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994210802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1994210802
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2678345059
Short name T28
Test name
Test status
Simulation time 1231371881 ps
CPU time 5.93 seconds
Started Aug 14 05:11:20 PM PDT 24
Finished Aug 14 05:11:26 PM PDT 24
Peak memory 218072 kb
Host smart-8df143d0-48f1-4016-8cad-1e512485e80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678345059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2678345059
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.711612878
Short name T325
Test name
Test status
Simulation time 243988001 ps
CPU time 1.14 seconds
Started Aug 14 05:11:22 PM PDT 24
Finished Aug 14 05:11:23 PM PDT 24
Peak memory 217796 kb
Host smart-ef9c7108-4a2c-497d-8ff9-203b315f278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711612878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.711612878
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.2899414832
Short name T17
Test name
Test status
Simulation time 151161745 ps
CPU time 0.83 seconds
Started Aug 14 05:11:18 PM PDT 24
Finished Aug 14 05:11:19 PM PDT 24
Peak memory 200480 kb
Host smart-d44155aa-11bf-484c-9fff-1289fc2a58fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899414832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2899414832
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.334141877
Short name T302
Test name
Test status
Simulation time 1701999812 ps
CPU time 6.71 seconds
Started Aug 14 05:11:18 PM PDT 24
Finished Aug 14 05:11:25 PM PDT 24
Peak memory 200820 kb
Host smart-b44cfcec-d697-4621-8565-bc62f36e6f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334141877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.334141877
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3226093148
Short name T435
Test name
Test status
Simulation time 103998071 ps
CPU time 1.07 seconds
Started Aug 14 05:11:22 PM PDT 24
Finished Aug 14 05:11:23 PM PDT 24
Peak memory 200668 kb
Host smart-9176f7fe-ca1f-4887-847a-27143d143a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226093148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3226093148
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3792712130
Short name T337
Test name
Test status
Simulation time 129443350 ps
CPU time 1.25 seconds
Started Aug 14 05:11:21 PM PDT 24
Finished Aug 14 05:11:23 PM PDT 24
Peak memory 200720 kb
Host smart-0e2619ef-12db-43a1-881b-4c6d4140d343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792712130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3792712130
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1804948303
Short name T69
Test name
Test status
Simulation time 9805276245 ps
CPU time 35.41 seconds
Started Aug 14 05:11:20 PM PDT 24
Finished Aug 14 05:11:55 PM PDT 24
Peak memory 200828 kb
Host smart-b735a5e7-262a-487d-9edb-3c602c5f116d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804948303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1804948303
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.3913034719
Short name T423
Test name
Test status
Simulation time 142817133 ps
CPU time 1.83 seconds
Started Aug 14 05:11:21 PM PDT 24
Finished Aug 14 05:11:23 PM PDT 24
Peak memory 200552 kb
Host smart-7c2c7bb1-f09b-4b35-a5db-39428af3a831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913034719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3913034719
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.2177327122
Short name T350
Test name
Test status
Simulation time 67105321 ps
CPU time 0.77 seconds
Started Aug 14 05:11:20 PM PDT 24
Finished Aug 14 05:11:20 PM PDT 24
Peak memory 200636 kb
Host smart-4b21c2b9-0346-4e00-a825-52c0f3129770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177327122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2177327122
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3366841286
Short name T241
Test name
Test status
Simulation time 52734866 ps
CPU time 0.7 seconds
Started Aug 14 05:11:17 PM PDT 24
Finished Aug 14 05:11:18 PM PDT 24
Peak memory 200528 kb
Host smart-12da33ec-9213-44ee-aff5-f1365188fe47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366841286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3366841286
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.2161354266
Short name T172
Test name
Test status
Simulation time 1894430729 ps
CPU time 6.98 seconds
Started Aug 14 05:11:23 PM PDT 24
Finished Aug 14 05:11:30 PM PDT 24
Peak memory 217964 kb
Host smart-81a9db73-8e11-49c5-a75e-0815bfc332a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161354266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2161354266
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3517349503
Short name T512
Test name
Test status
Simulation time 243538643 ps
CPU time 1.07 seconds
Started Aug 14 05:11:21 PM PDT 24
Finished Aug 14 05:11:22 PM PDT 24
Peak memory 217756 kb
Host smart-6c673d8d-a4c7-4e5c-9ebe-25eee4e4b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517349503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3517349503
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.901834441
Short name T192
Test name
Test status
Simulation time 195907714 ps
CPU time 0.93 seconds
Started Aug 14 05:11:20 PM PDT 24
Finished Aug 14 05:11:21 PM PDT 24
Peak memory 200444 kb
Host smart-6aff2120-caeb-4f93-a8ab-4e1e513c060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901834441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.901834441
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3752806169
Short name T180
Test name
Test status
Simulation time 963536699 ps
CPU time 4.95 seconds
Started Aug 14 05:11:19 PM PDT 24
Finished Aug 14 05:11:24 PM PDT 24
Peak memory 200836 kb
Host smart-d4044bde-3d3b-4da9-8778-cf9aaec2ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752806169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3752806169
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3089178768
Short name T348
Test name
Test status
Simulation time 140866401 ps
CPU time 1.04 seconds
Started Aug 14 05:11:18 PM PDT 24
Finished Aug 14 05:11:20 PM PDT 24
Peak memory 200656 kb
Host smart-1804c30a-9d44-48f5-af77-669cba67387f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089178768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3089178768
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2777433110
Short name T408
Test name
Test status
Simulation time 199332377 ps
CPU time 1.37 seconds
Started Aug 14 05:11:17 PM PDT 24
Finished Aug 14 05:11:19 PM PDT 24
Peak memory 200692 kb
Host smart-a3218881-bdaf-4389-a1d4-3f3c04d30759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777433110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2777433110
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3477230973
Short name T187
Test name
Test status
Simulation time 189457004 ps
CPU time 1.31 seconds
Started Aug 14 05:11:18 PM PDT 24
Finished Aug 14 05:11:20 PM PDT 24
Peak memory 200796 kb
Host smart-6beb68f8-ff2f-4053-99b5-f4c86172cb9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477230973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3477230973
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1492111127
Short name T452
Test name
Test status
Simulation time 133782624 ps
CPU time 1.72 seconds
Started Aug 14 05:11:23 PM PDT 24
Finished Aug 14 05:11:25 PM PDT 24
Peak memory 200472 kb
Host smart-f68a051b-dc09-4367-a24a-20f3eba9c2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492111127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1492111127
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.369073022
Short name T508
Test name
Test status
Simulation time 132155131 ps
CPU time 1.03 seconds
Started Aug 14 05:11:22 PM PDT 24
Finished Aug 14 05:11:23 PM PDT 24
Peak memory 200624 kb
Host smart-28d90898-19de-45c9-8b53-0458e7d77937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369073022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.369073022
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1923860217
Short name T204
Test name
Test status
Simulation time 60571321 ps
CPU time 0.79 seconds
Started Aug 14 05:11:18 PM PDT 24
Finished Aug 14 05:11:19 PM PDT 24
Peak memory 200696 kb
Host smart-18ec4239-6352-49ae-aa4e-d154571afccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923860217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1923860217
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.3060284775
Short name T398
Test name
Test status
Simulation time 1236125465 ps
CPU time 5.62 seconds
Started Aug 14 05:11:20 PM PDT 24
Finished Aug 14 05:11:26 PM PDT 24
Peak memory 221940 kb
Host smart-3e1d19d9-9917-44e4-97a7-f102fde7b799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060284775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3060284775
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3447948189
Short name T281
Test name
Test status
Simulation time 244690875 ps
CPU time 1.21 seconds
Started Aug 14 05:11:21 PM PDT 24
Finished Aug 14 05:11:22 PM PDT 24
Peak memory 217880 kb
Host smart-0cfded3b-151f-4e74-ba7f-5b0d975b9e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447948189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3447948189
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1179860867
Short name T236
Test name
Test status
Simulation time 157828518 ps
CPU time 0.84 seconds
Started Aug 14 05:11:20 PM PDT 24
Finished Aug 14 05:11:21 PM PDT 24
Peak memory 200476 kb
Host smart-1d9e2fe6-487f-4d9a-ba86-2162d719133a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179860867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1179860867
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1316175282
Short name T389
Test name
Test status
Simulation time 778987493 ps
CPU time 4.33 seconds
Started Aug 14 05:11:19 PM PDT 24
Finished Aug 14 05:11:24 PM PDT 24
Peak memory 200808 kb
Host smart-3e5e4115-c02e-4bdf-a116-0e50fef25a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316175282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1316175282
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1591076583
Short name T390
Test name
Test status
Simulation time 143457494 ps
CPU time 1.13 seconds
Started Aug 14 05:11:18 PM PDT 24
Finished Aug 14 05:11:20 PM PDT 24
Peak memory 200652 kb
Host smart-2da0b150-7de9-4668-9e33-86acfb72b3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591076583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1591076583
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.4076140119
Short name T275
Test name
Test status
Simulation time 116412141 ps
CPU time 1.17 seconds
Started Aug 14 05:11:23 PM PDT 24
Finished Aug 14 05:11:24 PM PDT 24
Peak memory 200628 kb
Host smart-24247755-f26e-4f85-9bff-afdec84b5522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076140119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.4076140119
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.472588919
Short name T269
Test name
Test status
Simulation time 4628234803 ps
CPU time 16.79 seconds
Started Aug 14 05:11:19 PM PDT 24
Finished Aug 14 05:11:36 PM PDT 24
Peak memory 200888 kb
Host smart-17c9cdde-8cd9-4f40-bb6e-343f2fd34074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472588919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.472588919
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.570107732
Short name T137
Test name
Test status
Simulation time 377667162 ps
CPU time 2.71 seconds
Started Aug 14 05:11:19 PM PDT 24
Finished Aug 14 05:11:21 PM PDT 24
Peak memory 200516 kb
Host smart-7e579884-205a-4d15-a404-8f6ccab49a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570107732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.570107732
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1410066566
Short name T175
Test name
Test status
Simulation time 174950114 ps
CPU time 1.25 seconds
Started Aug 14 05:11:19 PM PDT 24
Finished Aug 14 05:11:20 PM PDT 24
Peak memory 200672 kb
Host smart-dd271bc4-1138-44ca-950e-87d3eca9b15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410066566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1410066566
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.673352847
Short name T215
Test name
Test status
Simulation time 81530105 ps
CPU time 0.79 seconds
Started Aug 14 05:11:29 PM PDT 24
Finished Aug 14 05:11:30 PM PDT 24
Peak memory 200496 kb
Host smart-e867a85f-aac5-4c13-a9ba-60127eb87e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673352847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.673352847
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3657701350
Short name T31
Test name
Test status
Simulation time 2350917218 ps
CPU time 8.66 seconds
Started Aug 14 05:11:29 PM PDT 24
Finished Aug 14 05:11:38 PM PDT 24
Peak memory 218112 kb
Host smart-42143961-6ccc-45db-b7e8-c071ca49a45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657701350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3657701350
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.764026956
Short name T253
Test name
Test status
Simulation time 244907677 ps
CPU time 1.07 seconds
Started Aug 14 05:11:27 PM PDT 24
Finished Aug 14 05:11:28 PM PDT 24
Peak memory 217788 kb
Host smart-0c7437b7-3466-4324-b8c7-d3a2edf9dbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764026956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.764026956
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2805036209
Short name T356
Test name
Test status
Simulation time 94575392 ps
CPU time 0.75 seconds
Started Aug 14 05:11:32 PM PDT 24
Finished Aug 14 05:11:33 PM PDT 24
Peak memory 200344 kb
Host smart-56f81069-d1e7-4a2e-9094-0c15dd2061bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805036209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2805036209
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1613529558
Short name T329
Test name
Test status
Simulation time 1942637852 ps
CPU time 7.62 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:36 PM PDT 24
Peak memory 200708 kb
Host smart-a1da815b-e2a1-49b4-a724-c05572750ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613529558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1613529558
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1977758538
Short name T272
Test name
Test status
Simulation time 168082670 ps
CPU time 1.18 seconds
Started Aug 14 05:11:32 PM PDT 24
Finished Aug 14 05:11:33 PM PDT 24
Peak memory 200652 kb
Host smart-c955205a-d8d7-4572-983f-7b3afe85daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977758538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1977758538
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1983779096
Short name T522
Test name
Test status
Simulation time 194204675 ps
CPU time 1.44 seconds
Started Aug 14 05:11:24 PM PDT 24
Finished Aug 14 05:11:25 PM PDT 24
Peak memory 200792 kb
Host smart-1e2747e9-5659-4cff-96a2-ce57e580af3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983779096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1983779096
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1518837638
Short name T227
Test name
Test status
Simulation time 5712150597 ps
CPU time 25.46 seconds
Started Aug 14 05:11:32 PM PDT 24
Finished Aug 14 05:11:58 PM PDT 24
Peak memory 209044 kb
Host smart-761db6f8-5b9a-4a63-bce0-6ebb4aef67b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518837638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1518837638
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3885397751
Short name T440
Test name
Test status
Simulation time 109108294 ps
CPU time 1.46 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:29 PM PDT 24
Peak memory 200560 kb
Host smart-20e30acc-ecdb-47d3-9c73-cd0f27cc0c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885397751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3885397751
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.2784337043
Short name T466
Test name
Test status
Simulation time 68707852 ps
CPU time 0.76 seconds
Started Aug 14 05:11:27 PM PDT 24
Finished Aug 14 05:11:28 PM PDT 24
Peak memory 200652 kb
Host smart-fa82a30b-d015-49e7-b04f-253bd5329c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784337043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2784337043
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1003827121
Short name T126
Test name
Test status
Simulation time 61406275 ps
CPU time 0.74 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:29 PM PDT 24
Peak memory 200508 kb
Host smart-2adc4d90-796f-45ca-9f28-700a4025d80a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003827121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1003827121
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3079364589
Short name T429
Test name
Test status
Simulation time 2353756798 ps
CPU time 8.36 seconds
Started Aug 14 05:11:26 PM PDT 24
Finished Aug 14 05:11:35 PM PDT 24
Peak memory 221928 kb
Host smart-45477224-4586-4abd-bbb3-e3fa79b0067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079364589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3079364589
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2691811796
Short name T46
Test name
Test status
Simulation time 244036224 ps
CPU time 1.07 seconds
Started Aug 14 05:11:32 PM PDT 24
Finished Aug 14 05:11:33 PM PDT 24
Peak memory 217800 kb
Host smart-f6cdad60-a8ef-4151-b83a-e2a4db299af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691811796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2691811796
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.3992331375
Short name T397
Test name
Test status
Simulation time 222606288 ps
CPU time 0.92 seconds
Started Aug 14 05:11:29 PM PDT 24
Finished Aug 14 05:11:30 PM PDT 24
Peak memory 200356 kb
Host smart-396fc0e2-ce6e-4b7d-b3cf-28dec1fb4195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992331375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3992331375
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1031133263
Short name T257
Test name
Test status
Simulation time 1355659244 ps
CPU time 5.67 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:34 PM PDT 24
Peak memory 200856 kb
Host smart-a7cecd8b-9958-4bd4-8a14-a197665c83e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031133263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1031133263
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2072147596
Short name T181
Test name
Test status
Simulation time 136206840 ps
CPU time 1.09 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:29 PM PDT 24
Peak memory 200624 kb
Host smart-0d6a8571-3848-4f51-87d5-d319f57c2b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072147596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2072147596
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2064098534
Short name T114
Test name
Test status
Simulation time 250358236 ps
CPU time 1.51 seconds
Started Aug 14 05:11:29 PM PDT 24
Finished Aug 14 05:11:30 PM PDT 24
Peak memory 200772 kb
Host smart-7f5421ba-b504-459a-9a3c-1e92ff6ce94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064098534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2064098534
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2807336390
Short name T86
Test name
Test status
Simulation time 2651797620 ps
CPU time 11.66 seconds
Started Aug 14 05:11:32 PM PDT 24
Finished Aug 14 05:11:44 PM PDT 24
Peak memory 200852 kb
Host smart-a6b69633-583c-43aa-bc30-8abb4a1fa7bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807336390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2807336390
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4228024792
Short name T258
Test name
Test status
Simulation time 137067092 ps
CPU time 1.71 seconds
Started Aug 14 05:11:29 PM PDT 24
Finished Aug 14 05:11:31 PM PDT 24
Peak memory 200524 kb
Host smart-59ddf51f-2ea7-4c13-9694-7e60582e3ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228024792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4228024792
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3647699552
Short name T342
Test name
Test status
Simulation time 136980847 ps
CPU time 1.18 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:29 PM PDT 24
Peak memory 200664 kb
Host smart-1e2b027b-5b5d-44a5-a426-eb821cdce767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647699552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3647699552
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1046769139
Short name T436
Test name
Test status
Simulation time 77564210 ps
CPU time 0.82 seconds
Started Aug 14 05:11:35 PM PDT 24
Finished Aug 14 05:11:36 PM PDT 24
Peak memory 200484 kb
Host smart-bcd69f9c-3c1f-42d4-acae-f8fbdc6c1b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046769139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1046769139
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1106012673
Short name T33
Test name
Test status
Simulation time 1230542401 ps
CPU time 5.75 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:45 PM PDT 24
Peak memory 218008 kb
Host smart-c1ecfdc2-2c9d-48b4-9fad-c8c92883e422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106012673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1106012673
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.13809777
Short name T527
Test name
Test status
Simulation time 243829280 ps
CPU time 1.06 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:40 PM PDT 24
Peak memory 217788 kb
Host smart-62e303c5-b1eb-4c4e-816d-6583aa464758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13809777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.13809777
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.360577158
Short name T15
Test name
Test status
Simulation time 134326864 ps
CPU time 0.9 seconds
Started Aug 14 05:11:29 PM PDT 24
Finished Aug 14 05:11:30 PM PDT 24
Peak memory 200504 kb
Host smart-22c9c8af-a897-48ec-b5d0-ffd8edcd47ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360577158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.360577158
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.2285612167
Short name T525
Test name
Test status
Simulation time 1084282704 ps
CPU time 5.14 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:33 PM PDT 24
Peak memory 200892 kb
Host smart-b13f0984-c557-436b-91e8-83cfdad9c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285612167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2285612167
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3856124574
Short name T373
Test name
Test status
Simulation time 113456985 ps
CPU time 1.04 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:29 PM PDT 24
Peak memory 200604 kb
Host smart-cdf7dd42-edc4-43c1-b3ba-1ebe7934eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856124574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3856124574
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3028899314
Short name T540
Test name
Test status
Simulation time 111572160 ps
CPU time 1.17 seconds
Started Aug 14 05:11:28 PM PDT 24
Finished Aug 14 05:11:29 PM PDT 24
Peak memory 200808 kb
Host smart-6dcec030-4088-41ac-bfbd-e1ed9b429828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028899314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3028899314
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3133242419
Short name T232
Test name
Test status
Simulation time 7446808257 ps
CPU time 28.52 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:12:06 PM PDT 24
Peak memory 209116 kb
Host smart-77ba189c-7a77-44d9-ad1a-f43fce986ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133242419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3133242419
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1514226813
Short name T235
Test name
Test status
Simulation time 141856119 ps
CPU time 1.65 seconds
Started Aug 14 05:11:29 PM PDT 24
Finished Aug 14 05:11:30 PM PDT 24
Peak memory 200444 kb
Host smart-89a7737d-47fd-43ea-b504-2fc4d70f7578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514226813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1514226813
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.684217551
Short name T267
Test name
Test status
Simulation time 162657732 ps
CPU time 1.34 seconds
Started Aug 14 05:11:31 PM PDT 24
Finished Aug 14 05:11:33 PM PDT 24
Peak memory 200716 kb
Host smart-99e9d096-d2f1-4bfd-901c-b4a0ac92edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684217551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.684217551
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.4220127691
Short name T252
Test name
Test status
Simulation time 74236871 ps
CPU time 0.81 seconds
Started Aug 14 05:11:38 PM PDT 24
Finished Aug 14 05:11:39 PM PDT 24
Peak memory 200516 kb
Host smart-d1de0677-5ce5-4772-bd52-cc55f3f8a3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220127691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.4220127691
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2372360492
Short name T195
Test name
Test status
Simulation time 1895342142 ps
CPU time 7.17 seconds
Started Aug 14 05:11:40 PM PDT 24
Finished Aug 14 05:11:47 PM PDT 24
Peak memory 221988 kb
Host smart-6cbf911a-521a-48a9-b1af-fe5428717b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372360492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2372360492
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.4020646105
Short name T364
Test name
Test status
Simulation time 244315850 ps
CPU time 1.06 seconds
Started Aug 14 05:11:38 PM PDT 24
Finished Aug 14 05:11:39 PM PDT 24
Peak memory 217820 kb
Host smart-3bd1a742-36a8-4535-8ac1-65c571680850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020646105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.4020646105
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.2548936385
Short name T259
Test name
Test status
Simulation time 92242801 ps
CPU time 0.76 seconds
Started Aug 14 05:11:38 PM PDT 24
Finished Aug 14 05:11:39 PM PDT 24
Peak memory 200380 kb
Host smart-c2b5c794-d3b6-4b9f-aa6b-2db37e179bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548936385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2548936385
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.980970129
Short name T375
Test name
Test status
Simulation time 1570997601 ps
CPU time 5.98 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:45 PM PDT 24
Peak memory 200812 kb
Host smart-a1a39274-3032-4710-ae70-00b2aad6b8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980970129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.980970129
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3292155958
Short name T446
Test name
Test status
Simulation time 102956500 ps
CPU time 1.07 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:40 PM PDT 24
Peak memory 200668 kb
Host smart-524ccc0f-dbf7-4ffb-ace6-ceebc3ca0ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292155958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3292155958
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.622183805
Short name T276
Test name
Test status
Simulation time 118248726 ps
CPU time 1.2 seconds
Started Aug 14 05:11:38 PM PDT 24
Finished Aug 14 05:11:39 PM PDT 24
Peak memory 200744 kb
Host smart-c83a5c43-b342-4d90-abd4-16fed4333c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622183805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.622183805
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1079062649
Short name T480
Test name
Test status
Simulation time 5066580136 ps
CPU time 19.09 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:59 PM PDT 24
Peak memory 208912 kb
Host smart-40da5410-4ac5-4e78-bd56-3361522c7265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079062649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1079062649
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1507512634
Short name T194
Test name
Test status
Simulation time 142830849 ps
CPU time 1.89 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:38 PM PDT 24
Peak memory 200484 kb
Host smart-c52995e4-75cd-4b15-9c67-d18888ef20e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507512634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1507512634
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.298943909
Short name T115
Test name
Test status
Simulation time 66902308 ps
CPU time 0.79 seconds
Started Aug 14 05:11:35 PM PDT 24
Finished Aug 14 05:11:36 PM PDT 24
Peak memory 200828 kb
Host smart-2c622efd-1ea4-4a21-bc2b-438da1fb9308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298943909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.298943909
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1063869353
Short name T285
Test name
Test status
Simulation time 65618654 ps
CPU time 0.81 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:37 PM PDT 24
Peak memory 200520 kb
Host smart-6e125833-4adb-4dc5-b00f-7590b9f1e69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063869353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1063869353
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.2726545416
Short name T208
Test name
Test status
Simulation time 1233739801 ps
CPU time 6.04 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:11:43 PM PDT 24
Peak memory 217988 kb
Host smart-aa1fc516-7189-4ae0-bf00-bd00a2a09367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726545416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2726545416
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.4119034129
Short name T182
Test name
Test status
Simulation time 244939721 ps
CPU time 1.07 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:11:38 PM PDT 24
Peak memory 217824 kb
Host smart-8fb63841-523b-48e3-959b-e99fb3536e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119034129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.4119034129
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2946840006
Short name T353
Test name
Test status
Simulation time 203871818 ps
CPU time 0.97 seconds
Started Aug 14 05:11:41 PM PDT 24
Finished Aug 14 05:11:42 PM PDT 24
Peak memory 200480 kb
Host smart-27f476ac-ac05-41ad-80d7-656cd8354c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946840006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2946840006
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.203133863
Short name T83
Test name
Test status
Simulation time 1242992183 ps
CPU time 5.2 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:41 PM PDT 24
Peak memory 200792 kb
Host smart-0568f572-6430-4cd3-86e9-cc9dbf24de08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203133863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.203133863
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.287760017
Short name T524
Test name
Test status
Simulation time 115491416 ps
CPU time 1.05 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:11:38 PM PDT 24
Peak memory 200668 kb
Host smart-fac6f9b6-726e-4c6c-9765-210df312a71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287760017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.287760017
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.325787019
Short name T47
Test name
Test status
Simulation time 114665797 ps
CPU time 1.25 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:40 PM PDT 24
Peak memory 200804 kb
Host smart-6e72f3f2-2768-4a34-aa2f-a3f6ebc8447e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325787019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.325787019
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1898102281
Short name T201
Test name
Test status
Simulation time 3603067954 ps
CPU time 14.35 seconds
Started Aug 14 05:11:38 PM PDT 24
Finished Aug 14 05:11:52 PM PDT 24
Peak memory 200848 kb
Host smart-d6c40311-0456-41de-8334-59f371958dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898102281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1898102281
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3504809590
Short name T489
Test name
Test status
Simulation time 384278340 ps
CPU time 2.65 seconds
Started Aug 14 05:11:40 PM PDT 24
Finished Aug 14 05:11:43 PM PDT 24
Peak memory 200548 kb
Host smart-62b3362f-3eb8-477e-b8fa-8245fece4cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504809590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3504809590
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.125127712
Short name T455
Test name
Test status
Simulation time 134192066 ps
CPU time 1.09 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:11:38 PM PDT 24
Peak memory 200572 kb
Host smart-fd760760-bc1c-44ef-9d75-1a293cc7a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125127712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.125127712
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.149814653
Short name T199
Test name
Test status
Simulation time 81443222 ps
CPU time 0.76 seconds
Started Aug 14 05:11:34 PM PDT 24
Finished Aug 14 05:11:35 PM PDT 24
Peak memory 200404 kb
Host smart-4e4558c8-a193-4f20-bfe8-85363edf219f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149814653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.149814653
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2909411323
Short name T217
Test name
Test status
Simulation time 243744420 ps
CPU time 1.09 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:11:38 PM PDT 24
Peak memory 217884 kb
Host smart-d74e7c21-d726-4bd5-8132-7616e7c24a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909411323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2909411323
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.344890058
Short name T359
Test name
Test status
Simulation time 145364514 ps
CPU time 0.85 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:40 PM PDT 24
Peak memory 200480 kb
Host smart-126f449c-42eb-4080-98ac-84415dd4ab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344890058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.344890058
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.2702758464
Short name T146
Test name
Test status
Simulation time 860705548 ps
CPU time 4.13 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:40 PM PDT 24
Peak memory 200800 kb
Host smart-ca7f9253-81cf-4a21-b05c-d38f5d69b5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702758464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2702758464
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.300022309
Short name T447
Test name
Test status
Simulation time 156700898 ps
CPU time 1.26 seconds
Started Aug 14 05:11:40 PM PDT 24
Finished Aug 14 05:11:41 PM PDT 24
Peak memory 200608 kb
Host smart-bacce1d0-6d4a-41ae-87a0-3db3925a8e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300022309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.300022309
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2013410952
Short name T278
Test name
Test status
Simulation time 106402830 ps
CPU time 1.16 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:37 PM PDT 24
Peak memory 200744 kb
Host smart-1c11b9e9-c292-4f51-aa87-f5e052aa4bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013410952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2013410952
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.1407475416
Short name T220
Test name
Test status
Simulation time 7638432450 ps
CPU time 29.79 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:12:07 PM PDT 24
Peak memory 200864 kb
Host smart-7b6de152-20e5-4bab-9ae4-6f5ddede33f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407475416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.1407475416
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.545154097
Short name T443
Test name
Test status
Simulation time 354823063 ps
CPU time 2.27 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:42 PM PDT 24
Peak memory 200524 kb
Host smart-6f51a5ac-e63d-4c44-8054-e9973aaecc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545154097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.545154097
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.3692462328
Short name T388
Test name
Test status
Simulation time 88902502 ps
CPU time 0.88 seconds
Started Aug 14 05:11:41 PM PDT 24
Finished Aug 14 05:11:42 PM PDT 24
Peak memory 200672 kb
Host smart-bfc7af55-7724-41c4-a797-d56acfced758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692462328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3692462328
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2383175555
Short name T263
Test name
Test status
Simulation time 79400565 ps
CPU time 0.78 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:37 PM PDT 24
Peak memory 200528 kb
Host smart-839b1ec6-0209-453f-8f0b-06270cf7474d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383175555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2383175555
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.1078502457
Short name T460
Test name
Test status
Simulation time 1208497501 ps
CPU time 5.81 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:42 PM PDT 24
Peak memory 217956 kb
Host smart-f3caa88b-190a-4f05-baa5-f45653a0e3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078502457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1078502457
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.599861932
Short name T482
Test name
Test status
Simulation time 244065856 ps
CPU time 1.1 seconds
Started Aug 14 05:11:35 PM PDT 24
Finished Aug 14 05:11:36 PM PDT 24
Peak memory 217828 kb
Host smart-a335f03a-dcae-4c22-963e-76bd5274fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599861932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.599861932
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3564118609
Short name T205
Test name
Test status
Simulation time 243487202 ps
CPU time 1.08 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:11:38 PM PDT 24
Peak memory 200452 kb
Host smart-916baadb-4499-4e39-a517-6066f9ee8b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564118609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3564118609
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.4231644654
Short name T242
Test name
Test status
Simulation time 1985835259 ps
CPU time 7.2 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:43 PM PDT 24
Peak memory 200696 kb
Host smart-0ad8dfa8-bc22-42b9-ac19-b172d2e9c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231644654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.4231644654
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2728824034
Short name T493
Test name
Test status
Simulation time 186649339 ps
CPU time 1.29 seconds
Started Aug 14 05:11:36 PM PDT 24
Finished Aug 14 05:11:37 PM PDT 24
Peak memory 200632 kb
Host smart-02b310dd-00fe-4333-9cd9-cd57f3bf505f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728824034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2728824034
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.2559709936
Short name T209
Test name
Test status
Simulation time 110984820 ps
CPU time 1.21 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:41 PM PDT 24
Peak memory 200604 kb
Host smart-6346ce64-085b-4c5f-9003-187ad92269ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559709936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2559709936
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2850558849
Short name T300
Test name
Test status
Simulation time 9959187606 ps
CPU time 35.19 seconds
Started Aug 14 05:11:38 PM PDT 24
Finished Aug 14 05:12:14 PM PDT 24
Peak memory 200892 kb
Host smart-f61a5ba3-3bbf-4402-a19d-18dad08ec940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850558849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2850558849
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3707445304
Short name T316
Test name
Test status
Simulation time 400752086 ps
CPU time 2.41 seconds
Started Aug 14 05:11:39 PM PDT 24
Finished Aug 14 05:11:42 PM PDT 24
Peak memory 200504 kb
Host smart-3381d5fd-e6a3-44c2-9557-e6c872a28d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707445304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3707445304
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2052824076
Short name T290
Test name
Test status
Simulation time 118997277 ps
CPU time 1.11 seconds
Started Aug 14 05:11:37 PM PDT 24
Finished Aug 14 05:11:38 PM PDT 24
Peak memory 200664 kb
Host smart-ee97446a-6c86-4b5b-8aec-2fdd8d6c5b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052824076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2052824076
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.1954630673
Short name T371
Test name
Test status
Simulation time 67028046 ps
CPU time 0.71 seconds
Started Aug 14 05:09:46 PM PDT 24
Finished Aug 14 05:09:47 PM PDT 24
Peak memory 200448 kb
Host smart-eeae5bb1-b70f-4221-8fce-75b7f41b8ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954630673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1954630673
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4010771684
Short name T32
Test name
Test status
Simulation time 1909170984 ps
CPU time 7.06 seconds
Started Aug 14 05:09:42 PM PDT 24
Finished Aug 14 05:09:50 PM PDT 24
Peak memory 221936 kb
Host smart-f131b8ea-5098-4407-8214-18b9b07b7203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010771684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4010771684
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1622442957
Short name T51
Test name
Test status
Simulation time 247274528 ps
CPU time 1.06 seconds
Started Aug 14 05:09:44 PM PDT 24
Finished Aug 14 05:09:45 PM PDT 24
Peak memory 217852 kb
Host smart-059c092c-6e2f-4d2b-b84d-d06ce43e0f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622442957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1622442957
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2561516527
Short name T395
Test name
Test status
Simulation time 153897727 ps
CPU time 0.87 seconds
Started Aug 14 05:09:40 PM PDT 24
Finished Aug 14 05:09:41 PM PDT 24
Peak memory 200460 kb
Host smart-d5192a2f-57fe-4f58-9764-1e24e837df88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561516527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2561516527
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3478522237
Short name T202
Test name
Test status
Simulation time 1192240710 ps
CPU time 4.87 seconds
Started Aug 14 05:09:33 PM PDT 24
Finished Aug 14 05:09:38 PM PDT 24
Peak memory 200780 kb
Host smart-997f3e9f-6794-44f7-9811-1db6ee69736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478522237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3478522237
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1518239691
Short name T134
Test name
Test status
Simulation time 155705123 ps
CPU time 1.22 seconds
Started Aug 14 05:09:33 PM PDT 24
Finished Aug 14 05:09:35 PM PDT 24
Peak memory 200620 kb
Host smart-77f1e72f-2068-405b-b6dc-c7acb1a16370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518239691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.1518239691
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1248861999
Short name T73
Test name
Test status
Simulation time 187950858 ps
CPU time 1.31 seconds
Started Aug 14 05:09:36 PM PDT 24
Finished Aug 14 05:09:37 PM PDT 24
Peak memory 200768 kb
Host smart-e7253e41-3885-4df2-aa21-ec0419f0f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248861999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1248861999
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1502180625
Short name T248
Test name
Test status
Simulation time 11920620720 ps
CPU time 43.56 seconds
Started Aug 14 05:09:44 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 209096 kb
Host smart-88f8234f-4324-412c-b564-5ce3957837f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502180625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1502180625
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3065714683
Short name T384
Test name
Test status
Simulation time 392526503 ps
CPU time 2.52 seconds
Started Aug 14 05:09:33 PM PDT 24
Finished Aug 14 05:09:36 PM PDT 24
Peak memory 200492 kb
Host smart-fef8f306-3d34-4751-b331-70af7bd5786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065714683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3065714683
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.204739904
Short name T266
Test name
Test status
Simulation time 111658362 ps
CPU time 0.93 seconds
Started Aug 14 05:09:34 PM PDT 24
Finished Aug 14 05:09:35 PM PDT 24
Peak memory 200668 kb
Host smart-95299e07-393d-4c42-a6c2-d3f996db7124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204739904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.204739904
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.60099544
Short name T488
Test name
Test status
Simulation time 65777439 ps
CPU time 0.78 seconds
Started Aug 14 05:09:44 PM PDT 24
Finished Aug 14 05:09:44 PM PDT 24
Peak memory 200532 kb
Host smart-fea8f5b2-54a9-4fc4-bf57-149bf0a0c462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60099544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.60099544
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2272362581
Short name T409
Test name
Test status
Simulation time 2206130213 ps
CPU time 9.2 seconds
Started Aug 14 05:09:43 PM PDT 24
Finished Aug 14 05:09:53 PM PDT 24
Peak memory 222012 kb
Host smart-108faeab-f21c-47d3-a46d-b93efb9140ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272362581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2272362581
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1275272609
Short name T309
Test name
Test status
Simulation time 243832725 ps
CPU time 1.09 seconds
Started Aug 14 05:09:54 PM PDT 24
Finished Aug 14 05:09:55 PM PDT 24
Peak memory 217840 kb
Host smart-6666f7d5-cceb-4238-9e3f-d32e14d53258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275272609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1275272609
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2598211029
Short name T7
Test name
Test status
Simulation time 182741137 ps
CPU time 0.93 seconds
Started Aug 14 05:09:42 PM PDT 24
Finished Aug 14 05:09:44 PM PDT 24
Peak memory 200384 kb
Host smart-66121c34-77f8-49e4-9367-76c47a6cc099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598211029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2598211029
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.94813171
Short name T306
Test name
Test status
Simulation time 690085085 ps
CPU time 3.58 seconds
Started Aug 14 05:09:42 PM PDT 24
Finished Aug 14 05:09:46 PM PDT 24
Peak memory 200820 kb
Host smart-cdc896dc-8f8f-4706-aa85-a6bfa38be2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94813171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.94813171
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1203773720
Short name T173
Test name
Test status
Simulation time 176573347 ps
CPU time 1.18 seconds
Started Aug 14 05:09:44 PM PDT 24
Finished Aug 14 05:09:45 PM PDT 24
Peak memory 200644 kb
Host smart-6b27add1-408d-4636-8a04-3551e16f6a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203773720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1203773720
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3983288385
Short name T117
Test name
Test status
Simulation time 194614862 ps
CPU time 1.43 seconds
Started Aug 14 05:09:43 PM PDT 24
Finished Aug 14 05:09:45 PM PDT 24
Peak memory 200768 kb
Host smart-0134c4bd-d13a-4b56-a6e6-ad37c448fe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983288385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3983288385
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1083799858
Short name T421
Test name
Test status
Simulation time 4511564430 ps
CPU time 15.85 seconds
Started Aug 14 05:09:45 PM PDT 24
Finished Aug 14 05:10:01 PM PDT 24
Peak memory 209072 kb
Host smart-760b725d-a350-45d1-8cf5-0546e19ed4f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083799858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1083799858
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.3802266072
Short name T516
Test name
Test status
Simulation time 132457802 ps
CPU time 1.8 seconds
Started Aug 14 05:09:44 PM PDT 24
Finished Aug 14 05:09:46 PM PDT 24
Peak memory 200564 kb
Host smart-1a7cf12a-c006-4e80-a32c-bb4f3b818075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802266072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3802266072
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2510227833
Short name T349
Test name
Test status
Simulation time 160495319 ps
CPU time 1.13 seconds
Started Aug 14 05:09:43 PM PDT 24
Finished Aug 14 05:09:44 PM PDT 24
Peak memory 200544 kb
Host smart-4b1a2aaa-9f5c-4398-a076-23b5e4ffabd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510227833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2510227833
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3819129095
Short name T321
Test name
Test status
Simulation time 66153551 ps
CPU time 0.74 seconds
Started Aug 14 05:09:51 PM PDT 24
Finished Aug 14 05:09:52 PM PDT 24
Peak memory 200540 kb
Host smart-d7bfc5e0-e6bf-42fe-8551-e17cd94fd039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819129095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3819129095
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2398264827
Short name T431
Test name
Test status
Simulation time 1901345473 ps
CPU time 7.06 seconds
Started Aug 14 05:09:42 PM PDT 24
Finished Aug 14 05:09:49 PM PDT 24
Peak memory 221916 kb
Host smart-63619bd4-20b7-4472-aa7e-43d31956ebde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398264827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2398264827
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2426182423
Short name T150
Test name
Test status
Simulation time 243781476 ps
CPU time 1.1 seconds
Started Aug 14 05:09:45 PM PDT 24
Finished Aug 14 05:09:46 PM PDT 24
Peak memory 217872 kb
Host smart-f8e51ee9-372f-421f-97f9-039d4f8240dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426182423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2426182423
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3433015957
Short name T214
Test name
Test status
Simulation time 228201999 ps
CPU time 0.95 seconds
Started Aug 14 05:09:43 PM PDT 24
Finished Aug 14 05:09:44 PM PDT 24
Peak memory 200376 kb
Host smart-07badacb-75c1-4174-8285-32992ec5497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433015957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3433015957
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1330758422
Short name T40
Test name
Test status
Simulation time 1430957711 ps
CPU time 6.05 seconds
Started Aug 14 05:09:45 PM PDT 24
Finished Aug 14 05:09:51 PM PDT 24
Peak memory 200848 kb
Host smart-3be9802e-f4c7-44c7-a038-ad4a2da8e312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330758422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1330758422
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2806831920
Short name T243
Test name
Test status
Simulation time 150069988 ps
CPU time 1.17 seconds
Started Aug 14 05:09:45 PM PDT 24
Finished Aug 14 05:09:46 PM PDT 24
Peak memory 200596 kb
Host smart-10e2aa58-9a54-4af9-96c7-a672da894236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806831920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2806831920
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4166540459
Short name T239
Test name
Test status
Simulation time 252406673 ps
CPU time 1.51 seconds
Started Aug 14 05:09:44 PM PDT 24
Finished Aug 14 05:09:46 PM PDT 24
Peak memory 200748 kb
Host smart-6387bf24-4fac-496c-9943-a69a81a47382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166540459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4166540459
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2365678814
Short name T477
Test name
Test status
Simulation time 2419172211 ps
CPU time 11.08 seconds
Started Aug 14 05:09:52 PM PDT 24
Finished Aug 14 05:10:03 PM PDT 24
Peak memory 200896 kb
Host smart-f3127c41-158d-467f-981b-d60978ad1be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365678814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2365678814
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.866193525
Short name T500
Test name
Test status
Simulation time 249203884 ps
CPU time 1.87 seconds
Started Aug 14 05:09:44 PM PDT 24
Finished Aug 14 05:09:46 PM PDT 24
Peak memory 200552 kb
Host smart-2f3c7392-73e8-41e2-9e6c-ca36964545f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866193525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.866193525
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.751444060
Short name T273
Test name
Test status
Simulation time 109704482 ps
CPU time 1.02 seconds
Started Aug 14 05:09:43 PM PDT 24
Finished Aug 14 05:09:44 PM PDT 24
Peak memory 200668 kb
Host smart-0a6669f1-5ab1-495e-bf8a-50128a4a791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751444060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.751444060
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3308313661
Short name T210
Test name
Test status
Simulation time 80732489 ps
CPU time 0.79 seconds
Started Aug 14 05:09:56 PM PDT 24
Finished Aug 14 05:09:57 PM PDT 24
Peak memory 200516 kb
Host smart-e53091f6-8c76-40db-94bf-46f7a1697c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308313661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3308313661
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2738428013
Short name T475
Test name
Test status
Simulation time 2352835449 ps
CPU time 7.88 seconds
Started Aug 14 05:09:52 PM PDT 24
Finished Aug 14 05:10:00 PM PDT 24
Peak memory 218136 kb
Host smart-ad685043-1f79-4a8f-a213-aa8103e2ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738428013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2738428013
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3855895642
Short name T135
Test name
Test status
Simulation time 243875270 ps
CPU time 1.08 seconds
Started Aug 14 05:09:53 PM PDT 24
Finished Aug 14 05:09:55 PM PDT 24
Peak memory 217824 kb
Host smart-91c79468-9b2a-4ff6-8796-e923e6c677b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855895642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3855895642
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.161449733
Short name T503
Test name
Test status
Simulation time 140237763 ps
CPU time 0.82 seconds
Started Aug 14 05:09:51 PM PDT 24
Finished Aug 14 05:09:52 PM PDT 24
Peak memory 200496 kb
Host smart-7c6b18f5-5494-465d-b306-b520f0a490c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161449733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.161449733
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1738050754
Short name T478
Test name
Test status
Simulation time 1491006514 ps
CPU time 6.89 seconds
Started Aug 14 05:09:56 PM PDT 24
Finished Aug 14 05:10:03 PM PDT 24
Peak memory 200800 kb
Host smart-e93c8f6a-1ba9-4b8e-becd-df12ee03512e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738050754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1738050754
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3612908666
Short name T343
Test name
Test status
Simulation time 175998396 ps
CPU time 1.2 seconds
Started Aug 14 05:09:53 PM PDT 24
Finished Aug 14 05:09:54 PM PDT 24
Peak memory 200660 kb
Host smart-a59b8479-47cc-4a09-8d87-e17d4172c53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612908666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3612908666
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3777430152
Short name T528
Test name
Test status
Simulation time 250576807 ps
CPU time 1.46 seconds
Started Aug 14 05:09:52 PM PDT 24
Finished Aug 14 05:09:53 PM PDT 24
Peak memory 200792 kb
Host smart-9bdee245-930d-4024-be75-948f262d8a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777430152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3777430152
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.2039434950
Short name T221
Test name
Test status
Simulation time 3051759738 ps
CPU time 12.24 seconds
Started Aug 14 05:09:53 PM PDT 24
Finished Aug 14 05:10:05 PM PDT 24
Peak memory 200880 kb
Host smart-d2bec035-3c28-4d09-bc65-820103bb872f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039434950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2039434950
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3383681825
Short name T245
Test name
Test status
Simulation time 459488103 ps
CPU time 2.72 seconds
Started Aug 14 05:09:52 PM PDT 24
Finished Aug 14 05:09:55 PM PDT 24
Peak memory 200472 kb
Host smart-3181ab7b-e945-44ca-911a-eff3c2ad8574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383681825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3383681825
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.4193187621
Short name T486
Test name
Test status
Simulation time 206697530 ps
CPU time 1.22 seconds
Started Aug 14 05:09:51 PM PDT 24
Finished Aug 14 05:09:53 PM PDT 24
Peak memory 200656 kb
Host smart-ec845811-f75d-4829-b966-f9cb1f7cf0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193187621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.4193187621
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3675872397
Short name T358
Test name
Test status
Simulation time 75398910 ps
CPU time 0.79 seconds
Started Aug 14 05:09:53 PM PDT 24
Finished Aug 14 05:09:54 PM PDT 24
Peak memory 200516 kb
Host smart-bcd764d6-e52e-492b-948f-8c9a8b0a5fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675872397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3675872397
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3638887702
Short name T53
Test name
Test status
Simulation time 1903762924 ps
CPU time 7.36 seconds
Started Aug 14 05:09:51 PM PDT 24
Finished Aug 14 05:09:58 PM PDT 24
Peak memory 218024 kb
Host smart-ba361fdb-3463-4fc0-b604-0929a4241a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638887702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3638887702
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.371640846
Short name T328
Test name
Test status
Simulation time 244607832 ps
CPU time 1.05 seconds
Started Aug 14 05:09:51 PM PDT 24
Finished Aug 14 05:09:52 PM PDT 24
Peak memory 217812 kb
Host smart-6c6ac140-6f15-4e85-9f61-ffb06e6f490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371640846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.371640846
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2205315122
Short name T355
Test name
Test status
Simulation time 217241364 ps
CPU time 0.96 seconds
Started Aug 14 05:09:52 PM PDT 24
Finished Aug 14 05:09:53 PM PDT 24
Peak memory 200412 kb
Host smart-ff006f4e-5a2a-4e08-9c04-9345e5e99350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205315122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2205315122
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1745675680
Short name T282
Test name
Test status
Simulation time 851452996 ps
CPU time 3.92 seconds
Started Aug 14 05:09:53 PM PDT 24
Finished Aug 14 05:09:57 PM PDT 24
Peak memory 200820 kb
Host smart-52036b39-a234-41f4-b1fd-2a546690feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745675680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1745675680
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.891903958
Short name T304
Test name
Test status
Simulation time 149908367 ps
CPU time 1.16 seconds
Started Aug 14 05:09:51 PM PDT 24
Finished Aug 14 05:09:52 PM PDT 24
Peak memory 200632 kb
Host smart-5af49e45-346f-4370-b1ab-8c054c01d5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891903958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.891903958
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1937107485
Short name T165
Test name
Test status
Simulation time 118274646 ps
CPU time 1.27 seconds
Started Aug 14 05:09:52 PM PDT 24
Finished Aug 14 05:09:53 PM PDT 24
Peak memory 200800 kb
Host smart-8c217c62-38cb-42d9-a54d-fbf3459930ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937107485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1937107485
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2829782706
Short name T381
Test name
Test status
Simulation time 11726796294 ps
CPU time 40.31 seconds
Started Aug 14 05:09:53 PM PDT 24
Finished Aug 14 05:10:33 PM PDT 24
Peak memory 209076 kb
Host smart-2bbf9fe3-9a36-4910-a0a6-341fadc7bd2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829782706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2829782706
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2081919980
Short name T481
Test name
Test status
Simulation time 547914399 ps
CPU time 3.16 seconds
Started Aug 14 05:09:50 PM PDT 24
Finished Aug 14 05:09:54 PM PDT 24
Peak memory 200432 kb
Host smart-a16b66a9-f633-4952-a591-394c101b9064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081919980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2081919980
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.4040025239
Short name T319
Test name
Test status
Simulation time 79984136 ps
CPU time 0.85 seconds
Started Aug 14 05:09:52 PM PDT 24
Finished Aug 14 05:09:53 PM PDT 24
Peak memory 200664 kb
Host smart-87764fa5-be5b-4e65-94ca-9ad817b1cfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040025239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.4040025239
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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