Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7778

1

T5

16

T6

19

T8

26

auto[1]

10533

1

T1

4

T3

4

T5

85

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5786	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6140	1			T1	2		T2	1		T3	2
reset_info_cp[2]	2801	1			T1	1		T3	1		T5	19
reset_info_cp[4]	3693	1			T1	1		T3	1		T5	16
reset_info_cp[8]	92	1			T1	1		T6	1		T11	2
reset_info_cp[16]	108	1			T3	1		T5	2		T10	1
reset_info_cp[32]	91	1			T5	1		T10	1		T26	1
reset_info_cp[64]	103	1			T24	1		T26	1		T83	1
reset_info_cp[128]	117	1			T5	1		T8	1		T24	2

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2934	1			T5	16		T6	19		T8	7
reset_info_cp[1]	auto[1]	2586	1			T1	1		T3	1		T5	10
reset_info_cp[2]	auto[0]	842	1			T8	2		T10	11		T23	6
reset_info_cp[2]	auto[1]	1959	1			T1	1		T3	1		T5	19
reset_info_cp[4]	auto[0]	1307	1			T8	7		T10	13		T23	14
reset_info_cp[4]	auto[1]	2386	1			T1	1		T3	1		T5	16
reset_info_cp[8]	auto[0]	44	1			T11	2		T24	1		T26	1
reset_info_cp[8]	auto[1]	48	1			T1	1		T6	1		T24	1
reset_info_cp[16]	auto[0]	43	1			T11	1		T24	1		T26	1
reset_info_cp[16]	auto[1]	65	1			T3	1		T5	2		T10	1
reset_info_cp[32]	auto[0]	39	1			T26	1		T135	1		T136	1
reset_info_cp[32]	auto[1]	52	1			T5	1		T10	1		T93	1
reset_info_cp[64]	auto[0]	39	1			T26	1		T137	1		T138	1
reset_info_cp[64]	auto[1]	64	1			T24	1		T83	1		T128	1
reset_info_cp[128]	auto[0]	56	1			T8	1		T26	1		T43	1
reset_info_cp[128]	auto[1]	61	1			T5	1		T24	2		T29	1