Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T540 /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.539664925 Aug 15 04:49:46 PM PDT 24 Aug 15 04:49:48 PM PDT 24 180747960 ps
T541 /workspace/coverage/default/19.rstmgr_stress_all.3526151993 Aug 15 04:49:39 PM PDT 24 Aug 15 04:49:48 PM PDT 24 2576590287 ps
T542 /workspace/coverage/default/30.rstmgr_por_stretcher.1710058531 Aug 15 04:49:54 PM PDT 24 Aug 15 04:49:56 PM PDT 24 146614335 ps
T543 /workspace/coverage/default/12.rstmgr_alert_test.3295712627 Aug 15 04:49:19 PM PDT 24 Aug 15 04:49:20 PM PDT 24 74360700 ps
T544 /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1706825049 Aug 15 04:49:04 PM PDT 24 Aug 15 04:49:05 PM PDT 24 244233805 ps
T53 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1866617553 Aug 15 05:50:19 PM PDT 24 Aug 15 05:50:23 PM PDT 24 867041825 ps
T54 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3748949053 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:07 PM PDT 24 122605384 ps
T55 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1413574616 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:08 PM PDT 24 101692261 ps
T56 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.540241972 Aug 15 05:50:15 PM PDT 24 Aug 15 05:50:17 PM PDT 24 137406509 ps
T57 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1417920551 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:17 PM PDT 24 105772011 ps
T112 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1558203392 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:07 PM PDT 24 147488544 ps
T103 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1709333972 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:08 PM PDT 24 213159555 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3437184217 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:09 PM PDT 24 200147908 ps
T104 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.247184992 Aug 15 05:50:12 PM PDT 24 Aug 15 05:50:13 PM PDT 24 67443580 ps
T59 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.819572761 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:20 PM PDT 24 690948109 ps
T65 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1642102422 Aug 15 05:50:19 PM PDT 24 Aug 15 05:50:21 PM PDT 24 413495572 ps
T86 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.4153544283 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:16 PM PDT 24 193282182 ps
T87 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3359470364 Aug 15 05:50:21 PM PDT 24 Aug 15 05:50:22 PM PDT 24 197692299 ps
T88 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3346020380 Aug 15 05:50:31 PM PDT 24 Aug 15 05:50:34 PM PDT 24 320868289 ps
T89 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.861930375 Aug 15 05:50:23 PM PDT 24 Aug 15 05:50:24 PM PDT 24 124362844 ps
T105 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2846821202 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:15 PM PDT 24 76195614 ps
T545 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4259954316 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:17 PM PDT 24 73363907 ps
T106 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1640457418 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:18 PM PDT 24 214075419 ps
T92 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.123841141 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:16 PM PDT 24 468698556 ps
T90 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3473962924 Aug 15 05:50:09 PM PDT 24 Aug 15 05:50:11 PM PDT 24 124897695 ps
T107 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1545242431 Aug 15 05:50:17 PM PDT 24 Aug 15 05:50:18 PM PDT 24 257983141 ps
T134 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2309407595 Aug 15 05:50:04 PM PDT 24 Aug 15 05:50:07 PM PDT 24 466362401 ps
T91 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.143812397 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:09 PM PDT 24 130023985 ps
T546 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1152842806 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:17 PM PDT 24 163858042 ps
T119 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1256434667 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:12 PM PDT 24 872240331 ps
T547 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3209727189 Aug 15 05:50:27 PM PDT 24 Aug 15 05:50:29 PM PDT 24 216164327 ps
T548 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1359536714 Aug 15 05:50:15 PM PDT 24 Aug 15 05:50:18 PM PDT 24 309737882 ps
T113 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2524602799 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:20 PM PDT 24 505080261 ps
T114 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4265881213 Aug 15 05:50:15 PM PDT 24 Aug 15 05:50:16 PM PDT 24 94153252 ps
T108 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2560722257 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:15 PM PDT 24 96202512 ps
T549 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1504765543 Aug 15 05:50:13 PM PDT 24 Aug 15 05:50:16 PM PDT 24 185195646 ps
T550 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2828059560 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:11 PM PDT 24 392860922 ps
T109 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2102407009 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:17 PM PDT 24 151790561 ps
T121 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.166455975 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:19 PM PDT 24 924035645 ps
T110 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.672736049 Aug 15 05:50:18 PM PDT 24 Aug 15 05:50:19 PM PDT 24 126784220 ps
T111 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3740718039 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:07 PM PDT 24 112946073 ps
T132 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.749551474 Aug 15 05:50:23 PM PDT 24 Aug 15 05:50:26 PM PDT 24 787735561 ps
T551 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2215706570 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:08 PM PDT 24 265779325 ps
T552 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1681765330 Aug 15 05:50:27 PM PDT 24 Aug 15 05:50:28 PM PDT 24 120696964 ps
T553 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2143476618 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:17 PM PDT 24 88955902 ps
T554 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4229002907 Aug 15 05:50:15 PM PDT 24 Aug 15 05:50:16 PM PDT 24 109940006 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2534130519 Aug 15 05:50:11 PM PDT 24 Aug 15 05:50:17 PM PDT 24 483650812 ps
T556 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1673293258 Aug 15 05:50:20 PM PDT 24 Aug 15 05:50:21 PM PDT 24 68115469 ps
T557 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.658427041 Aug 15 05:50:15 PM PDT 24 Aug 15 05:50:17 PM PDT 24 129774300 ps
T120 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2014705685 Aug 15 05:50:22 PM PDT 24 Aug 15 05:50:25 PM PDT 24 167579118 ps
T558 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4003371754 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:09 PM PDT 24 465028954 ps
T559 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.378229634 Aug 15 05:50:21 PM PDT 24 Aug 15 05:50:22 PM PDT 24 138358188 ps
T560 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.939541427 Aug 15 05:50:04 PM PDT 24 Aug 15 05:50:05 PM PDT 24 142124195 ps
T122 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.53198347 Aug 15 05:50:18 PM PDT 24 Aug 15 05:50:21 PM PDT 24 886872086 ps
T561 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3313454401 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:17 PM PDT 24 63948152 ps
T562 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2108039793 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:16 PM PDT 24 109449637 ps
T563 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1090152282 Aug 15 05:50:05 PM PDT 24 Aug 15 05:50:06 PM PDT 24 57574877 ps
T564 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1388507449 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:18 PM PDT 24 2292042835 ps
T565 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1382257219 Aug 15 05:50:19 PM PDT 24 Aug 15 05:50:20 PM PDT 24 80414983 ps
T566 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1193054102 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:20 PM PDT 24 453534937 ps
T118 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1476434958 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:16 PM PDT 24 421785226 ps
T567 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2053380031 Aug 15 05:50:15 PM PDT 24 Aug 15 05:50:18 PM PDT 24 124281915 ps
T568 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4008867621 Aug 15 05:50:12 PM PDT 24 Aug 15 05:50:14 PM PDT 24 242455038 ps
T569 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4031707256 Aug 15 05:50:09 PM PDT 24 Aug 15 05:50:15 PM PDT 24 1170659020 ps
T570 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3325451630 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:16 PM PDT 24 119124746 ps
T571 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2361165317 Aug 15 05:50:18 PM PDT 24 Aug 15 05:50:19 PM PDT 24 64331172 ps
T133 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2339246434 Aug 15 05:50:13 PM PDT 24 Aug 15 05:50:16 PM PDT 24 807045937 ps
T572 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2863168381 Aug 15 05:50:18 PM PDT 24 Aug 15 05:50:20 PM PDT 24 131990547 ps
T573 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1395336326 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:17 PM PDT 24 793087784 ps
T574 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2634828244 Aug 15 05:50:19 PM PDT 24 Aug 15 05:50:21 PM PDT 24 130952155 ps
T575 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2661483040 Aug 15 05:50:11 PM PDT 24 Aug 15 05:50:12 PM PDT 24 196989206 ps
T576 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.744465391 Aug 15 05:50:13 PM PDT 24 Aug 15 05:50:15 PM PDT 24 115746965 ps
T577 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2364276768 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:08 PM PDT 24 74735182 ps
T578 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2176621634 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:09 PM PDT 24 264790899 ps
T579 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1936299742 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:08 PM PDT 24 73112999 ps
T580 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3404193398 Aug 15 05:50:05 PM PDT 24 Aug 15 05:50:07 PM PDT 24 136701802 ps
T581 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3226719088 Aug 15 05:50:06 PM PDT 24 Aug 15 05:50:10 PM PDT 24 1247421385 ps
T582 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.854890217 Aug 15 05:50:16 PM PDT 24 Aug 15 05:50:18 PM PDT 24 101325742 ps
T583 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2790704556 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:15 PM PDT 24 66188066 ps
T584 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3048382842 Aug 15 05:50:15 PM PDT 24 Aug 15 05:50:17 PM PDT 24 151620662 ps
T585 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1985667153 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:11 PM PDT 24 420410381 ps
T115 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1280969723 Aug 15 05:50:17 PM PDT 24 Aug 15 05:50:20 PM PDT 24 782455165 ps
T586 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1452797072 Aug 15 05:50:22 PM PDT 24 Aug 15 05:50:24 PM PDT 24 77367510 ps
T116 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.491145747 Aug 15 05:50:18 PM PDT 24 Aug 15 05:50:22 PM PDT 24 888212352 ps
T587 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3468888820 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:09 PM PDT 24 184041387 ps
T588 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3374613933 Aug 15 05:50:18 PM PDT 24 Aug 15 05:50:21 PM PDT 24 417369954 ps
T589 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4119999733 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:09 PM PDT 24 248278633 ps
T117 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1154546512 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:12 PM PDT 24 901617808 ps
T590 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.500189454 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:15 PM PDT 24 91952492 ps
T591 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1592097258 Aug 15 05:50:21 PM PDT 24 Aug 15 05:50:22 PM PDT 24 81873568 ps
T592 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1615024789 Aug 15 05:50:13 PM PDT 24 Aug 15 05:50:14 PM PDT 24 121318044 ps
T593 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2888517129 Aug 15 05:50:23 PM PDT 24 Aug 15 05:50:26 PM PDT 24 793206483 ps
T594 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1226342897 Aug 15 05:50:26 PM PDT 24 Aug 15 05:50:27 PM PDT 24 66860941 ps
T595 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3202357260 Aug 15 05:50:17 PM PDT 24 Aug 15 05:50:18 PM PDT 24 138624972 ps
T596 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2777753133 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:09 PM PDT 24 410234405 ps
T597 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3147560806 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:10 PM PDT 24 161363394 ps
T598 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.16523355 Aug 15 05:50:09 PM PDT 24 Aug 15 05:50:10 PM PDT 24 73611646 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4060523255 Aug 15 05:50:09 PM PDT 24 Aug 15 05:50:10 PM PDT 24 175623508 ps
T123 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2897896878 Aug 15 05:50:15 PM PDT 24 Aug 15 05:50:17 PM PDT 24 421538060 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2867233247 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:09 PM PDT 24 102609486 ps
T601 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2142715840 Aug 15 05:50:27 PM PDT 24 Aug 15 05:50:28 PM PDT 24 122195771 ps
T602 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2866529966 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:08 PM PDT 24 129483600 ps
T603 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.403493254 Aug 15 05:50:23 PM PDT 24 Aug 15 05:50:24 PM PDT 24 128239352 ps
T604 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3725785731 Aug 15 05:50:20 PM PDT 24 Aug 15 05:50:22 PM PDT 24 264866292 ps
T605 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3715532295 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:10 PM PDT 24 150155076 ps
T606 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3588227701 Aug 15 05:50:30 PM PDT 24 Aug 15 05:50:31 PM PDT 24 188791871 ps
T607 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.758644173 Aug 15 05:50:23 PM PDT 24 Aug 15 05:50:25 PM PDT 24 423333756 ps
T608 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1104255667 Aug 15 05:50:05 PM PDT 24 Aug 15 05:50:06 PM PDT 24 64828479 ps
T609 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.301291991 Aug 15 05:50:08 PM PDT 24 Aug 15 05:50:09 PM PDT 24 165439457 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3578758648 Aug 15 05:50:05 PM PDT 24 Aug 15 05:50:06 PM PDT 24 122163867 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2062893238 Aug 15 05:50:19 PM PDT 24 Aug 15 05:50:21 PM PDT 24 210863740 ps
T612 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3453129698 Aug 15 05:50:17 PM PDT 24 Aug 15 05:50:19 PM PDT 24 186871740 ps
T613 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1963650729 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:08 PM PDT 24 77113236 ps
T614 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2964597529 Aug 15 05:50:11 PM PDT 24 Aug 15 05:50:12 PM PDT 24 150482680 ps
T615 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.647755090 Aug 15 05:50:10 PM PDT 24 Aug 15 05:50:18 PM PDT 24 405942462 ps
T616 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1368657005 Aug 15 05:50:25 PM PDT 24 Aug 15 05:50:26 PM PDT 24 63859085 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2337866941 Aug 15 05:50:11 PM PDT 24 Aug 15 05:50:16 PM PDT 24 794917280 ps
T618 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1170795957 Aug 15 05:50:20 PM PDT 24 Aug 15 05:50:21 PM PDT 24 99284737 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.921184562 Aug 15 05:50:07 PM PDT 24 Aug 15 05:50:12 PM PDT 24 817241686 ps
T620 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.489667781 Aug 15 05:50:14 PM PDT 24 Aug 15 05:50:15 PM PDT 24 84860599 ps

Test location /workspace/coverage/default/22.rstmgr_stress_all.3945283104
Short name T10
Test name
Test status
Simulation time 3096965666 ps
CPU time 11.66 seconds
Started Aug 15 04:49:44 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 208964 kb
Host smart-3cc6ac9e-9eb2-4672-8afc-acf75e966220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945283104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3945283104
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.311019819
Short name T41
Test name
Test status
Simulation time 268081009 ps
CPU time 1.89 seconds
Started Aug 15 04:49:28 PM PDT 24
Finished Aug 15 04:49:31 PM PDT 24
Peak memory 200468 kb
Host smart-7217d282-9407-4c47-8313-1e88ecf4477e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311019819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.311019819
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1866617553
Short name T53
Test name
Test status
Simulation time 867041825 ps
CPU time 3.3 seconds
Started Aug 15 05:50:19 PM PDT 24
Finished Aug 15 05:50:23 PM PDT 24
Peak memory 200836 kb
Host smart-876bdeba-3373-4ce9-87fc-71386617feae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866617553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1866617553
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.854431870
Short name T6
Test name
Test status
Simulation time 1229072505 ps
CPU time 5.82 seconds
Started Aug 15 04:49:22 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 221848 kb
Host smart-fe0ba1ec-6391-4e8d-bcd5-96b28490e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854431870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.854431870
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3701213561
Short name T60
Test name
Test status
Simulation time 18528895939 ps
CPU time 28.31 seconds
Started Aug 15 04:48:55 PM PDT 24
Finished Aug 15 04:49:23 PM PDT 24
Peak memory 217592 kb
Host smart-439d1f48-dbe9-4557-91c6-260911c7a881
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701213561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3701213561
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.51284177
Short name T98
Test name
Test status
Simulation time 6014036783 ps
CPU time 20.41 seconds
Started Aug 15 04:50:25 PM PDT 24
Finished Aug 15 04:50:46 PM PDT 24
Peak memory 200756 kb
Host smart-c14b6cf3-6c9d-4c08-bc78-39e8775913c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51284177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.51284177
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3346020380
Short name T88
Test name
Test status
Simulation time 320868289 ps
CPU time 2.48 seconds
Started Aug 15 05:50:31 PM PDT 24
Finished Aug 15 05:50:34 PM PDT 24
Peak memory 209188 kb
Host smart-e53fcf1f-8b67-4840-b8a9-25cccea8b8a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346020380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3346020380
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.423216281
Short name T83
Test name
Test status
Simulation time 6990667110 ps
CPU time 28.59 seconds
Started Aug 15 04:48:56 PM PDT 24
Finished Aug 15 04:49:24 PM PDT 24
Peak memory 200792 kb
Host smart-0ce25e96-71b6-4f2e-b6ff-d95e26231b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423216281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.423216281
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.4235744633
Short name T44
Test name
Test status
Simulation time 57533014 ps
CPU time 0.72 seconds
Started Aug 15 04:49:21 PM PDT 24
Finished Aug 15 04:49:22 PM PDT 24
Peak memory 200440 kb
Host smart-859b41e9-8c3d-4cbf-ad8f-13c2ce9fa48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235744633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.4235744633
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.126746481
Short name T130
Test name
Test status
Simulation time 175745215 ps
CPU time 1.2 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:22 PM PDT 24
Peak memory 200448 kb
Host smart-31032b45-1420-4e3c-8cf8-2cfd4a2843c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126746481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.126746481
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.734529971
Short name T37
Test name
Test status
Simulation time 1233156565 ps
CPU time 5.78 seconds
Started Aug 15 04:50:26 PM PDT 24
Finished Aug 15 04:50:32 PM PDT 24
Peak memory 220968 kb
Host smart-cafc2f38-3660-4ee2-b4c4-11ea83ebbbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734529971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.734529971
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.166455975
Short name T121
Test name
Test status
Simulation time 924035645 ps
CPU time 3.29 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:19 PM PDT 24
Peak memory 201000 kb
Host smart-78c4b6b1-98d2-47c1-8ef2-0c7e3cfc609a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166455975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err
.166455975
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2283177746
Short name T26
Test name
Test status
Simulation time 151453586 ps
CPU time 1.25 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 200656 kb
Host smart-a15c25bc-21d7-4eee-ab42-35ea89461608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283177746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2283177746
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1504765543
Short name T549
Test name
Test status
Simulation time 185195646 ps
CPU time 2.79 seconds
Started Aug 15 05:50:13 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 209108 kb
Host smart-424a4ffb-66ca-4a8d-8a4d-ec2044762054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504765543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1504765543
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.170349503
Short name T30
Test name
Test status
Simulation time 2354677826 ps
CPU time 9.23 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:54 PM PDT 24
Peak memory 221928 kb
Host smart-fb89ce35-a77a-4951-afb8-363c715810e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170349503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.170349503
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1280969723
Short name T115
Test name
Test status
Simulation time 782455165 ps
CPU time 3.13 seconds
Started Aug 15 05:50:17 PM PDT 24
Finished Aug 15 05:50:20 PM PDT 24
Peak memory 200976 kb
Host smart-02bdd493-f312-49ff-85e2-aba352148096
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280969723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.1280969723
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3740718039
Short name T111
Test name
Test status
Simulation time 112946073 ps
CPU time 1.16 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:07 PM PDT 24
Peak memory 200836 kb
Host smart-4b468b65-1715-4ccb-bd45-1eae151cc057
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740718039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3740718039
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.2536738347
Short name T18
Test name
Test status
Simulation time 208244947 ps
CPU time 0.92 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:36 PM PDT 24
Peak memory 200368 kb
Host smart-614dbda7-3127-4a84-861f-bfd2968b15fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536738347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.2536738347
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1906214638
Short name T49
Test name
Test status
Simulation time 2360258027 ps
CPU time 8.58 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:44 PM PDT 24
Peak memory 221960 kb
Host smart-55b0925e-6c91-4fb9-b570-f6e882dff0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906214638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1906214638
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3468888820
Short name T587
Test name
Test status
Simulation time 184041387 ps
CPU time 1.56 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 209400 kb
Host smart-7f921cd4-8e58-4094-b6be-5c4bc6bf4b6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468888820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3468888820
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.123841141
Short name T92
Test name
Test status
Simulation time 468698556 ps
CPU time 2.06 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 201044 kb
Host smart-b7bab890-99c9-473d-a022-fb53948fd144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123841141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.123841141
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1164334905
Short name T266
Test name
Test status
Simulation time 140745601 ps
CPU time 1.86 seconds
Started Aug 15 04:48:57 PM PDT 24
Finished Aug 15 04:48:59 PM PDT 24
Peak memory 200472 kb
Host smart-2b267fe7-e395-4092-abd3-c1516eacc761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164334905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1164334905
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3715532295
Short name T605
Test name
Test status
Simulation time 150155076 ps
CPU time 2.14 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:10 PM PDT 24
Peak memory 200916 kb
Host smart-9fc44c0b-d504-4e84-b4f7-bb7461f7511e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715532295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3
715532295
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.2534130519
Short name T555
Test name
Test status
Simulation time 483650812 ps
CPU time 5.93 seconds
Started Aug 15 05:50:11 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200908 kb
Host smart-9757ef20-3722-480c-9287-a95a5ab8069b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534130519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.2
534130519
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2866529966
Short name T602
Test name
Test status
Simulation time 129483600 ps
CPU time 0.88 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:08 PM PDT 24
Peak memory 200764 kb
Host smart-dd999051-0f8f-4008-acf9-c2e15ce51482
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866529966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
866529966
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3404193398
Short name T580
Test name
Test status
Simulation time 136701802 ps
CPU time 1.62 seconds
Started Aug 15 05:50:05 PM PDT 24
Finished Aug 15 05:50:07 PM PDT 24
Peak memory 209232 kb
Host smart-193f9aa2-7431-4f74-9341-6d0b0a81e767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404193398 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3404193398
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.16523355
Short name T598
Test name
Test status
Simulation time 73611646 ps
CPU time 0.86 seconds
Started Aug 15 05:50:09 PM PDT 24
Finished Aug 15 05:50:10 PM PDT 24
Peak memory 200776 kb
Host smart-137f06b9-974c-4def-8a02-271fbf5c0756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.16523355
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1256434667
Short name T119
Test name
Test status
Simulation time 872240331 ps
CPU time 3.2 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:12 PM PDT 24
Peak memory 201008 kb
Host smart-b2835c14-0378-4546-aa67-728e4b5063b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256434667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.1256434667
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1985667153
Short name T585
Test name
Test status
Simulation time 420410381 ps
CPU time 2.7 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:11 PM PDT 24
Peak memory 200920 kb
Host smart-f92efc96-0d18-4a3d-8c48-e4f482371435
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985667153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1
985667153
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1388507449
Short name T564
Test name
Test status
Simulation time 2292042835 ps
CPU time 9.48 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:18 PM PDT 24
Peak memory 200972 kb
Host smart-7fa6ddc5-f1f5-4430-93a3-51df471746d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388507449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
388507449
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2867233247
Short name T600
Test name
Test status
Simulation time 102609486 ps
CPU time 0.84 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 200748 kb
Host smart-2684b985-a606-460f-9450-a36e028711a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867233247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
867233247
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3437184217
Short name T58
Test name
Test status
Simulation time 200147908 ps
CPU time 1.38 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 209076 kb
Host smart-a5d90936-b59b-4079-989c-c26fe912affb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437184217 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3437184217
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2364276768
Short name T577
Test name
Test status
Simulation time 74735182 ps
CPU time 0.8 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:08 PM PDT 24
Peak memory 200768 kb
Host smart-f1164610-e823-4e5d-80e9-de97270bfa8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364276768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2364276768
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2215706570
Short name T551
Test name
Test status
Simulation time 265779325 ps
CPU time 1.64 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:08 PM PDT 24
Peak memory 200976 kb
Host smart-353e4b4d-7c02-4982-839f-dcabe8a4fd8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215706570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2215706570
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.4119999733
Short name T589
Test name
Test status
Simulation time 248278633 ps
CPU time 2.1 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 209136 kb
Host smart-6a0f7c23-bddc-44e8-917e-c75e9e4d38bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119999733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4119999733
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3226719088
Short name T581
Test name
Test status
Simulation time 1247421385 ps
CPU time 3.68 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:10 PM PDT 24
Peak memory 201104 kb
Host smart-94704db8-75d0-4256-898b-5bb01e8d1ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226719088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3226719088
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3359470364
Short name T87
Test name
Test status
Simulation time 197692299 ps
CPU time 1.38 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:22 PM PDT 24
Peak memory 209112 kb
Host smart-9f80e84d-b808-4be6-b4b0-5d0fcaff0834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359470364 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3359470364
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1382257219
Short name T565
Test name
Test status
Simulation time 80414983 ps
CPU time 0.88 seconds
Started Aug 15 05:50:19 PM PDT 24
Finished Aug 15 05:50:20 PM PDT 24
Peak memory 200756 kb
Host smart-d701e7fe-bb33-457c-be5b-00a9b2871458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382257219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1382257219
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2560722257
Short name T108
Test name
Test status
Simulation time 96202512 ps
CPU time 1.18 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:15 PM PDT 24
Peak memory 200964 kb
Host smart-5c95d992-6fba-44fc-bbbd-906241a3dd5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560722257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.2560722257
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1417920551
Short name T57
Test name
Test status
Simulation time 105772011 ps
CPU time 1.45 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 209156 kb
Host smart-ffb05d55-ab92-4fcf-abb3-9cc4989b9b45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417920551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1417920551
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.403493254
Short name T603
Test name
Test status
Simulation time 128239352 ps
CPU time 1.3 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 209036 kb
Host smart-829bbdc8-80ee-4796-bfdf-39e3703c5a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403493254 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.403493254
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2361165317
Short name T571
Test name
Test status
Simulation time 64331172 ps
CPU time 0.83 seconds
Started Aug 15 05:50:18 PM PDT 24
Finished Aug 15 05:50:19 PM PDT 24
Peak memory 200200 kb
Host smart-96e5ddec-92fc-40af-813b-d90305d4ee5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361165317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2361165317
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.4008867621
Short name T568
Test name
Test status
Simulation time 242455038 ps
CPU time 1.79 seconds
Started Aug 15 05:50:12 PM PDT 24
Finished Aug 15 05:50:14 PM PDT 24
Peak memory 209192 kb
Host smart-03fa2136-6fbc-4f29-9772-6e2a46fc0c98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008867621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.4008867621
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.4153544283
Short name T86
Test name
Test status
Simulation time 193282182 ps
CPU time 1.48 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 200780 kb
Host smart-afdcfa79-7e93-4a05-a3f1-91a07927f2e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153544283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.4153544283
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.749551474
Short name T132
Test name
Test status
Simulation time 787735561 ps
CPU time 2.98 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 200980 kb
Host smart-7faafcb2-02f1-4ec7-b464-dba981ce9ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749551474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err
.749551474
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3202357260
Short name T595
Test name
Test status
Simulation time 138624972 ps
CPU time 1.15 seconds
Started Aug 15 05:50:17 PM PDT 24
Finished Aug 15 05:50:18 PM PDT 24
Peak memory 209100 kb
Host smart-72a7f41e-641b-4898-b10a-a2f30d04c511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202357260 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.3202357260
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2143476618
Short name T553
Test name
Test status
Simulation time 88955902 ps
CPU time 0.85 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200760 kb
Host smart-961ba010-1c42-4a5c-a1a5-477a0f23e64a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143476618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2143476618
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2634828244
Short name T574
Test name
Test status
Simulation time 130952155 ps
CPU time 1.11 seconds
Started Aug 15 05:50:19 PM PDT 24
Finished Aug 15 05:50:21 PM PDT 24
Peak memory 200772 kb
Host smart-b86962e8-e924-4905-b74d-e7f13802a01f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634828244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2634828244
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.744465391
Short name T576
Test name
Test status
Simulation time 115746965 ps
CPU time 1.73 seconds
Started Aug 15 05:50:13 PM PDT 24
Finished Aug 15 05:50:15 PM PDT 24
Peak memory 209220 kb
Host smart-8ba759d1-902a-4870-8c77-2ebad8694efc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744465391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.744465391
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2142715840
Short name T601
Test name
Test status
Simulation time 122195771 ps
CPU time 0.99 seconds
Started Aug 15 05:50:27 PM PDT 24
Finished Aug 15 05:50:28 PM PDT 24
Peak memory 200824 kb
Host smart-22451646-8efa-4628-b809-ee8821240340
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142715840 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2142715840
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.1368657005
Short name T616
Test name
Test status
Simulation time 63859085 ps
CPU time 0.78 seconds
Started Aug 15 05:50:25 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 200704 kb
Host smart-b2f0851e-9fe7-4a80-a8dd-4575566cbdfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368657005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1368657005
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.672736049
Short name T110
Test name
Test status
Simulation time 126784220 ps
CPU time 1.21 seconds
Started Aug 15 05:50:18 PM PDT 24
Finished Aug 15 05:50:19 PM PDT 24
Peak memory 200260 kb
Host smart-7f168a5f-d03b-4cec-9649-0dd787bc6988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672736049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.672736049
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1359536714
Short name T548
Test name
Test status
Simulation time 309737882 ps
CPU time 2.18 seconds
Started Aug 15 05:50:15 PM PDT 24
Finished Aug 15 05:50:18 PM PDT 24
Peak memory 209180 kb
Host smart-c2bbc9b9-6f12-453d-880c-ea12d4631d01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359536714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1359536714
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2888517129
Short name T593
Test name
Test status
Simulation time 793206483 ps
CPU time 2.81 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:26 PM PDT 24
Peak memory 200992 kb
Host smart-c87d3aca-b4d8-4b1a-a2fc-fbb166b016de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888517129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.2888517129
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.861930375
Short name T89
Test name
Test status
Simulation time 124362844 ps
CPU time 1.01 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 200852 kb
Host smart-a324c03d-bed1-4c5e-b7e5-c419e573c812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861930375 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.861930375
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1452797072
Short name T586
Test name
Test status
Simulation time 77367510 ps
CPU time 0.91 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:24 PM PDT 24
Peak memory 200712 kb
Host smart-1a4685ea-37f2-4d1e-a464-d90c57dcb604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452797072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1452797072
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.378229634
Short name T559
Test name
Test status
Simulation time 138358188 ps
CPU time 1.15 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:22 PM PDT 24
Peak memory 200856 kb
Host smart-ffdfdbc8-fe33-4601-b0df-2e35f6f673d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378229634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.378229634
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.2524602799
Short name T113
Test name
Test status
Simulation time 505080261 ps
CPU time 3.2 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:20 PM PDT 24
Peak memory 209180 kb
Host smart-70afd57f-7a10-4ee5-912f-1517888aaecd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524602799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2524602799
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.658427041
Short name T557
Test name
Test status
Simulation time 129774300 ps
CPU time 1.55 seconds
Started Aug 15 05:50:15 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 209252 kb
Host smart-fb7023ad-d1d3-43f1-b9c1-2145a5dded73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658427041 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.658427041
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.489667781
Short name T620
Test name
Test status
Simulation time 84860599 ps
CPU time 0.93 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:15 PM PDT 24
Peak memory 200752 kb
Host smart-a3cfbe67-f91e-4461-a0db-2c5771dc87f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489667781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.489667781
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1640457418
Short name T106
Test name
Test status
Simulation time 214075419 ps
CPU time 1.46 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:18 PM PDT 24
Peak memory 200880 kb
Host smart-fbb9ed6e-680e-49f5-b58f-57c8dbc1babe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640457418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.1640457418
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.758644173
Short name T607
Test name
Test status
Simulation time 423333756 ps
CPU time 1.96 seconds
Started Aug 15 05:50:23 PM PDT 24
Finished Aug 15 05:50:25 PM PDT 24
Peak memory 200984 kb
Host smart-4d5433a3-7491-4881-bade-e6c89591e2a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758644173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.758644173
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3453129698
Short name T612
Test name
Test status
Simulation time 186871740 ps
CPU time 1.84 seconds
Started Aug 15 05:50:17 PM PDT 24
Finished Aug 15 05:50:19 PM PDT 24
Peak memory 214528 kb
Host smart-91cda1ad-c3ad-45a4-b42e-e5cd10fb41b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453129698 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3453129698
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1592097258
Short name T591
Test name
Test status
Simulation time 81873568 ps
CPU time 0.87 seconds
Started Aug 15 05:50:21 PM PDT 24
Finished Aug 15 05:50:22 PM PDT 24
Peak memory 200764 kb
Host smart-0ccbefc1-5ebb-478d-ab66-724808b8367d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592097258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1592097258
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3725785731
Short name T604
Test name
Test status
Simulation time 264866292 ps
CPU time 1.74 seconds
Started Aug 15 05:50:20 PM PDT 24
Finished Aug 15 05:50:22 PM PDT 24
Peak memory 200932 kb
Host smart-ab359fda-ba9c-496f-93d3-728870d262ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725785731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3725785731
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3209727189
Short name T547
Test name
Test status
Simulation time 216164327 ps
CPU time 1.68 seconds
Started Aug 15 05:50:27 PM PDT 24
Finished Aug 15 05:50:29 PM PDT 24
Peak memory 209120 kb
Host smart-1bd223d9-5b52-4a2d-bfe0-36437e5be693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209727189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3209727189
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2339246434
Short name T133
Test name
Test status
Simulation time 807045937 ps
CPU time 2.81 seconds
Started Aug 15 05:50:13 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 201012 kb
Host smart-9d4a23fd-5107-4396-869f-09f4c46e2042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339246434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2339246434
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3048382842
Short name T584
Test name
Test status
Simulation time 151620662 ps
CPU time 1.41 seconds
Started Aug 15 05:50:15 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 209156 kb
Host smart-2ae39289-e8b2-42d5-99f3-3adfcc0ea7e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048382842 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3048382842
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3313454401
Short name T561
Test name
Test status
Simulation time 63948152 ps
CPU time 0.83 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200756 kb
Host smart-4193ab3f-ab26-4317-9ce4-05b0956f1478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313454401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3313454401
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.540241972
Short name T56
Test name
Test status
Simulation time 137406509 ps
CPU time 1.17 seconds
Started Aug 15 05:50:15 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200828 kb
Host smart-d6338a31-345a-4dcf-b175-4be743a4533e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540241972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.540241972
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2053380031
Short name T567
Test name
Test status
Simulation time 124281915 ps
CPU time 1.94 seconds
Started Aug 15 05:50:15 PM PDT 24
Finished Aug 15 05:50:18 PM PDT 24
Peak memory 209160 kb
Host smart-e7e24d29-8f5e-4582-b379-f721efa80b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053380031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2053380031
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.491145747
Short name T116
Test name
Test status
Simulation time 888212352 ps
CPU time 3.22 seconds
Started Aug 15 05:50:18 PM PDT 24
Finished Aug 15 05:50:22 PM PDT 24
Peak memory 200968 kb
Host smart-de566206-6b86-4e60-aaa7-3ec0b0beaeb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491145747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err
.491145747
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3588227701
Short name T606
Test name
Test status
Simulation time 188791871 ps
CPU time 1.44 seconds
Started Aug 15 05:50:30 PM PDT 24
Finished Aug 15 05:50:31 PM PDT 24
Peak memory 209072 kb
Host smart-5782979f-389c-4866-bd7a-6578f25292fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588227701 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3588227701
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1226342897
Short name T594
Test name
Test status
Simulation time 66860941 ps
CPU time 0.78 seconds
Started Aug 15 05:50:26 PM PDT 24
Finished Aug 15 05:50:27 PM PDT 24
Peak memory 200772 kb
Host smart-1ac755a9-b1a2-4223-b405-3a9420d9b7d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226342897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1226342897
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.854890217
Short name T582
Test name
Test status
Simulation time 101325742 ps
CPU time 1.24 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:18 PM PDT 24
Peak memory 200944 kb
Host smart-943742d4-e648-4a2c-886d-0c1cf764eb0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854890217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.854890217
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1193054102
Short name T566
Test name
Test status
Simulation time 453534937 ps
CPU time 3.34 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:20 PM PDT 24
Peak memory 200952 kb
Host smart-ed82e84e-a96c-442d-a54a-ae8dbbd5afd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193054102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1193054102
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1476434958
Short name T118
Test name
Test status
Simulation time 421785226 ps
CPU time 1.86 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 200996 kb
Host smart-dc4dcf90-66d5-4bc2-81ab-3bc69f877e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476434958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1476434958
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1152842806
Short name T546
Test name
Test status
Simulation time 163858042 ps
CPU time 1.12 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200756 kb
Host smart-e6242daa-ee63-4b61-864d-6bff20da3c93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152842806 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1152842806
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1673293258
Short name T556
Test name
Test status
Simulation time 68115469 ps
CPU time 0.84 seconds
Started Aug 15 05:50:20 PM PDT 24
Finished Aug 15 05:50:21 PM PDT 24
Peak memory 200680 kb
Host smart-0683ae73-d561-4fc6-bd5a-fd22d831ebb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673293258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1673293258
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1681765330
Short name T552
Test name
Test status
Simulation time 120696964 ps
CPU time 1.06 seconds
Started Aug 15 05:50:27 PM PDT 24
Finished Aug 15 05:50:28 PM PDT 24
Peak memory 200744 kb
Host smart-daba814e-9d78-4b7a-a6e3-7dc3c027dc62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681765330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1681765330
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.819572761
Short name T59
Test name
Test status
Simulation time 690948109 ps
CPU time 4.26 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:20 PM PDT 24
Peak memory 212736 kb
Host smart-c59e2ce6-1c09-4110-bc10-cc1e5789ea51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819572761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.819572761
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3147560806
Short name T597
Test name
Test status
Simulation time 161363394 ps
CPU time 2.08 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:10 PM PDT 24
Peak memory 200928 kb
Host smart-60313634-f3ce-4362-bb6a-276f526e10d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147560806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
147560806
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2337866941
Short name T617
Test name
Test status
Simulation time 794917280 ps
CPU time 4.31 seconds
Started Aug 15 05:50:11 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 200968 kb
Host smart-f37c07d0-cc74-48ba-900a-b51846143fb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337866941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2
337866941
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3748949053
Short name T54
Test name
Test status
Simulation time 122605384 ps
CPU time 0.91 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:07 PM PDT 24
Peak memory 200708 kb
Host smart-eaef8892-1ece-423b-a551-889e5d04965d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748949053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
748949053
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3578758648
Short name T610
Test name
Test status
Simulation time 122163867 ps
CPU time 1.25 seconds
Started Aug 15 05:50:05 PM PDT 24
Finished Aug 15 05:50:06 PM PDT 24
Peak memory 209088 kb
Host smart-c9995a20-4d78-4b40-9164-2cfd4a56d130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578758648 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.3578758648
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1104255667
Short name T608
Test name
Test status
Simulation time 64828479 ps
CPU time 0.82 seconds
Started Aug 15 05:50:05 PM PDT 24
Finished Aug 15 05:50:06 PM PDT 24
Peak memory 200748 kb
Host smart-797b9bb1-8818-4948-8c4a-29519994857a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104255667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1104255667
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1709333972
Short name T103
Test name
Test status
Simulation time 213159555 ps
CPU time 1.49 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:08 PM PDT 24
Peak memory 200988 kb
Host smart-fda9b000-ee36-419a-a3e1-2e3f3163e8f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709333972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1709333972
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4060523255
Short name T599
Test name
Test status
Simulation time 175623508 ps
CPU time 1.45 seconds
Started Aug 15 05:50:09 PM PDT 24
Finished Aug 15 05:50:10 PM PDT 24
Peak memory 211836 kb
Host smart-35316438-c593-4ead-8763-70c8dc902fef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060523255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.4060523255
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4003371754
Short name T558
Test name
Test status
Simulation time 465028954 ps
CPU time 2.06 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 201016 kb
Host smart-46d21f61-6aa7-4f67-99e9-458b022cf29e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003371754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.4003371754
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1413574616
Short name T55
Test name
Test status
Simulation time 101692261 ps
CPU time 1.36 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:08 PM PDT 24
Peak memory 200920 kb
Host smart-0841be54-89bd-43df-a40e-b50d96b45298
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413574616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
413574616
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.4031707256
Short name T569
Test name
Test status
Simulation time 1170659020 ps
CPU time 6.04 seconds
Started Aug 15 05:50:09 PM PDT 24
Finished Aug 15 05:50:15 PM PDT 24
Peak memory 200896 kb
Host smart-f764340e-056c-4cce-98c9-a31631a8e49a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031707256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.4
031707256
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1558203392
Short name T112
Test name
Test status
Simulation time 147488544 ps
CPU time 1.05 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:07 PM PDT 24
Peak memory 200768 kb
Host smart-de8389c4-11ec-42f3-8e44-86bff4989b94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558203392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
558203392
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2661483040
Short name T575
Test name
Test status
Simulation time 196989206 ps
CPU time 1.24 seconds
Started Aug 15 05:50:11 PM PDT 24
Finished Aug 15 05:50:12 PM PDT 24
Peak memory 209060 kb
Host smart-5243419e-43c7-4720-99c7-4a5a801aca50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661483040 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2661483040
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.1936299742
Short name T579
Test name
Test status
Simulation time 73112999 ps
CPU time 0.85 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:08 PM PDT 24
Peak memory 200708 kb
Host smart-5defd711-1a06-44ff-b7a8-a6a33ff6a9cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936299742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1936299742
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.939541427
Short name T560
Test name
Test status
Simulation time 142124195 ps
CPU time 1.19 seconds
Started Aug 15 05:50:04 PM PDT 24
Finished Aug 15 05:50:05 PM PDT 24
Peak memory 200724 kb
Host smart-69db8988-4917-4452-b1e1-f4e2dea1195e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939541427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sam
e_csr_outstanding.939541427
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2176621634
Short name T578
Test name
Test status
Simulation time 264790899 ps
CPU time 2.43 seconds
Started Aug 15 05:50:06 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 209196 kb
Host smart-3ba17c9d-bf26-4b98-8107-f18f1062fc51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176621634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2176621634
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2309407595
Short name T134
Test name
Test status
Simulation time 466362401 ps
CPU time 2.19 seconds
Started Aug 15 05:50:04 PM PDT 24
Finished Aug 15 05:50:07 PM PDT 24
Peak memory 201080 kb
Host smart-b9a4f1ec-fa1d-49ef-ae84-5963d113aa68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309407595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.2309407595
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2828059560
Short name T550
Test name
Test status
Simulation time 392860922 ps
CPU time 2.78 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:11 PM PDT 24
Peak memory 200852 kb
Host smart-2c0ff796-d496-4ce8-a88f-99118e07271a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828059560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2
828059560
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.921184562
Short name T619
Test name
Test status
Simulation time 817241686 ps
CPU time 4.93 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:12 PM PDT 24
Peak memory 200908 kb
Host smart-87c3ef89-3d42-41ae-b01e-ec3ab15fe2e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921184562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.921184562
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2964597529
Short name T614
Test name
Test status
Simulation time 150482680 ps
CPU time 0.98 seconds
Started Aug 15 05:50:11 PM PDT 24
Finished Aug 15 05:50:12 PM PDT 24
Peak memory 200752 kb
Host smart-21072cc7-279d-4422-9a78-a1f735e52be5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964597529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
964597529
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.143812397
Short name T91
Test name
Test status
Simulation time 130023985 ps
CPU time 1.34 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 208932 kb
Host smart-064037c6-f0f2-443b-beb6-2d18c84ed5c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143812397 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.143812397
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1963650729
Short name T613
Test name
Test status
Simulation time 77113236 ps
CPU time 0.78 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:08 PM PDT 24
Peak memory 200760 kb
Host smart-e9a350db-671f-42d5-b9a9-87e9bef5a294
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963650729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1963650729
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.301291991
Short name T609
Test name
Test status
Simulation time 165439457 ps
CPU time 1.24 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 200824 kb
Host smart-a2c8c246-3d04-41b4-8b29-76779a21e204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301291991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.301291991
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3473962924
Short name T90
Test name
Test status
Simulation time 124897695 ps
CPU time 1.71 seconds
Started Aug 15 05:50:09 PM PDT 24
Finished Aug 15 05:50:11 PM PDT 24
Peak memory 209148 kb
Host smart-49723c32-b565-49a8-b623-9bcebddf7325
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473962924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3473962924
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1154546512
Short name T117
Test name
Test status
Simulation time 901617808 ps
CPU time 3.36 seconds
Started Aug 15 05:50:08 PM PDT 24
Finished Aug 15 05:50:12 PM PDT 24
Peak memory 200960 kb
Host smart-de27599b-54d5-4508-884a-35965cf1e322
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154546512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.1154546512
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1170795957
Short name T618
Test name
Test status
Simulation time 99284737 ps
CPU time 0.98 seconds
Started Aug 15 05:50:20 PM PDT 24
Finished Aug 15 05:50:21 PM PDT 24
Peak memory 200880 kb
Host smart-f707def5-9f02-441f-a48b-d4be243153dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170795957 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1170795957
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.1090152282
Short name T563
Test name
Test status
Simulation time 57574877 ps
CPU time 0.74 seconds
Started Aug 15 05:50:05 PM PDT 24
Finished Aug 15 05:50:06 PM PDT 24
Peak memory 200752 kb
Host smart-34f5ea2e-21bc-41de-85aa-34f1372b7db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090152282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1090152282
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1545242431
Short name T107
Test name
Test status
Simulation time 257983141 ps
CPU time 1.53 seconds
Started Aug 15 05:50:17 PM PDT 24
Finished Aug 15 05:50:18 PM PDT 24
Peak memory 201004 kb
Host smart-34554f48-b938-4443-96a9-8cba09b7469f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545242431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1545242431
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.647755090
Short name T615
Test name
Test status
Simulation time 405942462 ps
CPU time 2.98 seconds
Started Aug 15 05:50:10 PM PDT 24
Finished Aug 15 05:50:18 PM PDT 24
Peak memory 212868 kb
Host smart-e0dd7ebf-ef66-410e-8e1a-a9fb08e35197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647755090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.647755090
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2777753133
Short name T596
Test name
Test status
Simulation time 410234405 ps
CPU time 1.85 seconds
Started Aug 15 05:50:07 PM PDT 24
Finished Aug 15 05:50:09 PM PDT 24
Peak memory 201000 kb
Host smart-6340efb2-aeb9-4a26-8955-66eb97d10132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777753133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2777753133
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4229002907
Short name T554
Test name
Test status
Simulation time 109940006 ps
CPU time 1.07 seconds
Started Aug 15 05:50:15 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 208948 kb
Host smart-53f8d1f8-e7cb-465e-ae10-60cccd3aeab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229002907 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4229002907
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2790704556
Short name T583
Test name
Test status
Simulation time 66188066 ps
CPU time 0.82 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:15 PM PDT 24
Peak memory 200608 kb
Host smart-0700274b-b87f-4aa3-9d91-48f675c2c282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790704556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2790704556
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2846821202
Short name T105
Test name
Test status
Simulation time 76195614 ps
CPU time 1 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:15 PM PDT 24
Peak memory 200788 kb
Host smart-933478ba-c3ca-4705-95e7-dbba9dcfac2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846821202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.2846821202
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.3374613933
Short name T588
Test name
Test status
Simulation time 417369954 ps
CPU time 3.05 seconds
Started Aug 15 05:50:18 PM PDT 24
Finished Aug 15 05:50:21 PM PDT 24
Peak memory 209180 kb
Host smart-d8abf74a-b1c3-496a-8fbf-28d78a6c3b26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374613933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3374613933
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.53198347
Short name T122
Test name
Test status
Simulation time 886872086 ps
CPU time 3.24 seconds
Started Aug 15 05:50:18 PM PDT 24
Finished Aug 15 05:50:21 PM PDT 24
Peak memory 201008 kb
Host smart-754e8609-e8dd-4478-8bdc-3efa40da9dd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53198347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.53198347
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2863168381
Short name T572
Test name
Test status
Simulation time 131990547 ps
CPU time 1.13 seconds
Started Aug 15 05:50:18 PM PDT 24
Finished Aug 15 05:50:20 PM PDT 24
Peak memory 200872 kb
Host smart-883a97bc-7b08-434d-8082-97d8d9808bc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863168381 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2863168381
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.247184992
Short name T104
Test name
Test status
Simulation time 67443580 ps
CPU time 0.79 seconds
Started Aug 15 05:50:12 PM PDT 24
Finished Aug 15 05:50:13 PM PDT 24
Peak memory 200680 kb
Host smart-fd46ad9a-97ea-43b2-9b74-cada70e35b58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247184992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.247184992
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1615024789
Short name T592
Test name
Test status
Simulation time 121318044 ps
CPU time 1.03 seconds
Started Aug 15 05:50:13 PM PDT 24
Finished Aug 15 05:50:14 PM PDT 24
Peak memory 200848 kb
Host smart-9d296f3d-153c-4c4d-a9ec-387acf4be62a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615024789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1615024789
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1395336326
Short name T573
Test name
Test status
Simulation time 793087784 ps
CPU time 3.22 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200984 kb
Host smart-bb0f1fd7-6836-42d1-878e-1ca9ae80ca62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395336326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1395336326
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2108039793
Short name T562
Test name
Test status
Simulation time 109449637 ps
CPU time 1.25 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 217192 kb
Host smart-6f2ed8df-ecac-401a-98c2-2b33ad7a608d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108039793 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2108039793
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4259954316
Short name T545
Test name
Test status
Simulation time 73363907 ps
CPU time 0.81 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200776 kb
Host smart-34a5d742-add0-4224-8c1c-0e03dad7497c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259954316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4259954316
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2062893238
Short name T611
Test name
Test status
Simulation time 210863740 ps
CPU time 1.6 seconds
Started Aug 15 05:50:19 PM PDT 24
Finished Aug 15 05:50:21 PM PDT 24
Peak memory 200836 kb
Host smart-449ba8cd-16ee-4f28-9cc9-a6b6aab7500d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062893238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.2062893238
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.3325451630
Short name T570
Test name
Test status
Simulation time 119124746 ps
CPU time 1.72 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 209204 kb
Host smart-5ce61504-f3b2-4f5e-bb90-94747cc296cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325451630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3325451630
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2897896878
Short name T123
Test name
Test status
Simulation time 421538060 ps
CPU time 1.83 seconds
Started Aug 15 05:50:15 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200988 kb
Host smart-48fbe94c-4e64-47cc-9eba-d52b7725f913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897896878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.2897896878
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.4265881213
Short name T114
Test name
Test status
Simulation time 94153252 ps
CPU time 1 seconds
Started Aug 15 05:50:15 PM PDT 24
Finished Aug 15 05:50:16 PM PDT 24
Peak memory 200712 kb
Host smart-5ca657e7-57ff-420c-9dd5-3de226bab7c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265881213 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.4265881213
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.500189454
Short name T590
Test name
Test status
Simulation time 91952492 ps
CPU time 0.89 seconds
Started Aug 15 05:50:14 PM PDT 24
Finished Aug 15 05:50:15 PM PDT 24
Peak memory 200992 kb
Host smart-6ca8becd-d86c-473e-8b56-29d05b37afa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500189454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.500189454
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2102407009
Short name T109
Test name
Test status
Simulation time 151790561 ps
CPU time 1.13 seconds
Started Aug 15 05:50:16 PM PDT 24
Finished Aug 15 05:50:17 PM PDT 24
Peak memory 200860 kb
Host smart-5db2f07e-d67e-40a8-814e-b9b773f5a7c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102407009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2102407009
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.2014705685
Short name T120
Test name
Test status
Simulation time 167579118 ps
CPU time 2.36 seconds
Started Aug 15 05:50:22 PM PDT 24
Finished Aug 15 05:50:25 PM PDT 24
Peak memory 209180 kb
Host smart-0ba45654-8498-4b72-bf02-84ea13eeaa96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014705685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2014705685
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1642102422
Short name T65
Test name
Test status
Simulation time 413495572 ps
CPU time 1.76 seconds
Started Aug 15 05:50:19 PM PDT 24
Finished Aug 15 05:50:21 PM PDT 24
Peak memory 201088 kb
Host smart-63bad212-c711-44b1-a2a2-830dacb7b9aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642102422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.1642102422
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.623561350
Short name T275
Test name
Test status
Simulation time 65856543 ps
CPU time 0.74 seconds
Started Aug 15 04:48:55 PM PDT 24
Finished Aug 15 04:48:56 PM PDT 24
Peak memory 200448 kb
Host smart-f4464e5a-57c9-4456-bce4-a2dccf403ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623561350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.623561350
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3187842706
Short name T336
Test name
Test status
Simulation time 1891213075 ps
CPU time 7.18 seconds
Started Aug 15 04:48:55 PM PDT 24
Finished Aug 15 04:49:02 PM PDT 24
Peak memory 217852 kb
Host smart-0e74ac6c-c663-4c60-9b78-f218c53a6d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187842706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3187842706
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2327952454
Short name T348
Test name
Test status
Simulation time 244498675 ps
CPU time 1.25 seconds
Started Aug 15 04:48:55 PM PDT 24
Finished Aug 15 04:48:57 PM PDT 24
Peak memory 217744 kb
Host smart-bd0933f8-af6b-455e-beda-dcab36a47619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327952454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2327952454
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.1759664049
Short name T288
Test name
Test status
Simulation time 132412870 ps
CPU time 0.77 seconds
Started Aug 15 04:48:57 PM PDT 24
Finished Aug 15 04:48:58 PM PDT 24
Peak memory 200248 kb
Host smart-4a4b1cd6-5702-4f85-a993-781d43d66947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759664049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1759664049
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.800623657
Short name T438
Test name
Test status
Simulation time 1012916658 ps
CPU time 5.4 seconds
Started Aug 15 04:48:58 PM PDT 24
Finished Aug 15 04:49:03 PM PDT 24
Peak memory 200776 kb
Host smart-09448de5-6576-41e9-b180-9b9549248136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800623657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.800623657
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.1604907153
Short name T295
Test name
Test status
Simulation time 151733867 ps
CPU time 1.14 seconds
Started Aug 15 04:48:55 PM PDT 24
Finished Aug 15 04:48:56 PM PDT 24
Peak memory 200400 kb
Host smart-53638f9a-45e8-4737-98f2-39abc6b8173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604907153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1604907153
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.28347111
Short name T283
Test name
Test status
Simulation time 106694419 ps
CPU time 1.23 seconds
Started Aug 15 04:48:56 PM PDT 24
Finished Aug 15 04:48:57 PM PDT 24
Peak memory 200660 kb
Host smart-bf8454b4-af45-4cb4-8827-a196e10013c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28347111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.28347111
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.1145301263
Short name T217
Test name
Test status
Simulation time 82688439 ps
CPU time 0.82 seconds
Started Aug 15 04:48:55 PM PDT 24
Finished Aug 15 04:48:56 PM PDT 24
Peak memory 200592 kb
Host smart-fc9b6182-7ba9-4050-9680-c358d3378897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145301263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1145301263
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.559418445
Short name T291
Test name
Test status
Simulation time 60776954 ps
CPU time 0.76 seconds
Started Aug 15 04:49:02 PM PDT 24
Finished Aug 15 04:49:03 PM PDT 24
Peak memory 200328 kb
Host smart-a98c4a7a-7eea-4d3b-a552-6776b15daa7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559418445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.559418445
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.780580603
Short name T501
Test name
Test status
Simulation time 1223119039 ps
CPU time 5.29 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:09 PM PDT 24
Peak memory 217704 kb
Host smart-ae6066dd-eee7-4372-844f-dc15a6a92ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780580603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.780580603
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1953299540
Short name T535
Test name
Test status
Simulation time 244277109 ps
CPU time 1.08 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:06 PM PDT 24
Peak memory 217804 kb
Host smart-9acc95c3-6d00-4dd3-b889-f30c4686a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953299540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1953299540
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4030518536
Short name T365
Test name
Test status
Simulation time 181577201 ps
CPU time 0.91 seconds
Started Aug 15 04:48:55 PM PDT 24
Finished Aug 15 04:48:56 PM PDT 24
Peak memory 200352 kb
Host smart-72450e61-8153-43c9-b023-94b3f774cf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030518536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4030518536
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.405662481
Short name T338
Test name
Test status
Simulation time 853069910 ps
CPU time 4.15 seconds
Started Aug 15 04:48:55 PM PDT 24
Finished Aug 15 04:48:59 PM PDT 24
Peak memory 200720 kb
Host smart-57ab3c8d-5848-464b-aa77-2a8a9dfa8c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405662481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.405662481
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2721202916
Short name T61
Test name
Test status
Simulation time 8336260028 ps
CPU time 12.77 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 217144 kb
Host smart-e2da5093-11ec-4240-b0c5-dcd39dd830d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721202916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2721202916
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.750602468
Short name T393
Test name
Test status
Simulation time 170661747 ps
CPU time 1.24 seconds
Started Aug 15 04:49:02 PM PDT 24
Finished Aug 15 04:49:03 PM PDT 24
Peak memory 200420 kb
Host smart-83cca811-2f09-4acb-86ca-2a0555153c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750602468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.750602468
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2244410477
Short name T526
Test name
Test status
Simulation time 125489003 ps
CPU time 1.21 seconds
Started Aug 15 04:48:57 PM PDT 24
Finished Aug 15 04:48:59 PM PDT 24
Peak memory 200560 kb
Host smart-e77b71b0-5bd5-4f48-99d2-86732a4115dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244410477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2244410477
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2985010236
Short name T213
Test name
Test status
Simulation time 2218714923 ps
CPU time 10.11 seconds
Started Aug 15 04:49:02 PM PDT 24
Finished Aug 15 04:49:12 PM PDT 24
Peak memory 200768 kb
Host smart-84093a99-fcf9-4f95-9bd4-9a9e9480836d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985010236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2985010236
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2795660418
Short name T281
Test name
Test status
Simulation time 322624796 ps
CPU time 2.21 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:06 PM PDT 24
Peak memory 200384 kb
Host smart-11852510-afb9-46d1-b4cd-5bb35a58b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795660418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2795660418
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.956656088
Short name T43
Test name
Test status
Simulation time 125327465 ps
CPU time 1.03 seconds
Started Aug 15 04:49:07 PM PDT 24
Finished Aug 15 04:49:08 PM PDT 24
Peak memory 200552 kb
Host smart-519772d0-86b3-4e12-ac24-0247550cd23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956656088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.956656088
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.983692796
Short name T490
Test name
Test status
Simulation time 64497570 ps
CPU time 0.74 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:21 PM PDT 24
Peak memory 200432 kb
Host smart-4799e878-a431-440a-854a-a3c122ddc2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983692796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.983692796
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.3919440192
Short name T372
Test name
Test status
Simulation time 1888751278 ps
CPU time 7.62 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:28 PM PDT 24
Peak memory 217472 kb
Host smart-e7c9805a-0fcf-4c80-bea1-c1eaa76ea479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919440192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3919440192
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2739775191
Short name T139
Test name
Test status
Simulation time 243455996 ps
CPU time 1.11 seconds
Started Aug 15 04:49:21 PM PDT 24
Finished Aug 15 04:49:22 PM PDT 24
Peak memory 217756 kb
Host smart-fa0bcba1-61fd-4d76-ad40-2c8847aec052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739775191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2739775191
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.283959318
Short name T242
Test name
Test status
Simulation time 154661845 ps
CPU time 0.84 seconds
Started Aug 15 04:49:22 PM PDT 24
Finished Aug 15 04:49:23 PM PDT 24
Peak memory 200296 kb
Host smart-acf8f26b-33f9-496d-8e9b-bf15b08b7691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283959318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.283959318
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.865172744
Short name T527
Test name
Test status
Simulation time 1584002603 ps
CPU time 6.4 seconds
Started Aug 15 04:49:25 PM PDT 24
Finished Aug 15 04:49:32 PM PDT 24
Peak memory 200724 kb
Host smart-93343e3e-b9c5-4a90-81a6-13fec13612af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865172744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.865172744
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3160469778
Short name T268
Test name
Test status
Simulation time 96315747 ps
CPU time 1.04 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:22 PM PDT 24
Peak memory 200476 kb
Host smart-876cf574-4349-4ae1-8274-1d3f4827a3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160469778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3160469778
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.480405852
Short name T416
Test name
Test status
Simulation time 202107470 ps
CPU time 1.45 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:17 PM PDT 24
Peak memory 200568 kb
Host smart-3d3e2833-a038-4e00-8147-9ff2e7d54819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480405852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.480405852
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1693007425
Short name T195
Test name
Test status
Simulation time 1940703447 ps
CPU time 7.6 seconds
Started Aug 15 04:49:23 PM PDT 24
Finished Aug 15 04:49:30 PM PDT 24
Peak memory 200744 kb
Host smart-85f28901-ed51-44ce-a849-837b429c3e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693007425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1693007425
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2458718329
Short name T210
Test name
Test status
Simulation time 356822842 ps
CPU time 2.35 seconds
Started Aug 15 04:49:21 PM PDT 24
Finished Aug 15 04:49:24 PM PDT 24
Peak memory 200472 kb
Host smart-1c13a0f4-da6b-4da4-a2d9-533e504efd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458718329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2458718329
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.1085428460
Short name T533
Test name
Test status
Simulation time 166403570 ps
CPU time 1.11 seconds
Started Aug 15 04:49:23 PM PDT 24
Finished Aug 15 04:49:24 PM PDT 24
Peak memory 200468 kb
Host smart-fad0e23f-528a-4b0b-8d69-12df716720ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085428460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1085428460
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3449267465
Short name T46
Test name
Test status
Simulation time 1882629012 ps
CPU time 6.61 seconds
Started Aug 15 04:49:23 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 217908 kb
Host smart-37fecca1-7be6-49a9-a4fe-44cfe0f70bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449267465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3449267465
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3897168959
Short name T462
Test name
Test status
Simulation time 244417537 ps
CPU time 1.13 seconds
Started Aug 15 04:49:18 PM PDT 24
Finished Aug 15 04:49:20 PM PDT 24
Peak memory 217688 kb
Host smart-0dea460d-b883-4b39-af6b-2c4d5597bca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897168959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3897168959
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3547037795
Short name T392
Test name
Test status
Simulation time 142864301 ps
CPU time 0.9 seconds
Started Aug 15 04:49:22 PM PDT 24
Finished Aug 15 04:49:23 PM PDT 24
Peak memory 200284 kb
Host smart-87027c85-384f-4bff-87ab-d1646678fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547037795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3547037795
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.2032993204
Short name T166
Test name
Test status
Simulation time 742535232 ps
CPU time 3.83 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:24 PM PDT 24
Peak memory 200708 kb
Host smart-08419083-2a32-4525-bc93-30ee70d2f0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032993204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2032993204
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.367884727
Short name T524
Test name
Test status
Simulation time 113527312 ps
CPU time 1.19 seconds
Started Aug 15 04:49:25 PM PDT 24
Finished Aug 15 04:49:26 PM PDT 24
Peak memory 200616 kb
Host smart-5cfbee8b-5cdd-4230-a7ba-c21986875e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367884727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.367884727
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.58915459
Short name T125
Test name
Test status
Simulation time 15645742920 ps
CPU time 55.88 seconds
Started Aug 15 04:49:23 PM PDT 24
Finished Aug 15 04:50:19 PM PDT 24
Peak memory 208884 kb
Host smart-458d2d92-b666-4a0a-929d-5c5bc3c45cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58915459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.58915459
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1943878980
Short name T349
Test name
Test status
Simulation time 373484629 ps
CPU time 2.33 seconds
Started Aug 15 04:49:19 PM PDT 24
Finished Aug 15 04:49:22 PM PDT 24
Peak memory 200364 kb
Host smart-949e952c-d0c5-4b82-ae21-320efa9d51f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943878980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1943878980
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.254052558
Short name T219
Test name
Test status
Simulation time 83322571 ps
CPU time 0.83 seconds
Started Aug 15 04:49:19 PM PDT 24
Finished Aug 15 04:49:20 PM PDT 24
Peak memory 200560 kb
Host smart-1de4f50c-e9fa-4378-8ce5-241e99022534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254052558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.254052558
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3295712627
Short name T543
Test name
Test status
Simulation time 74360700 ps
CPU time 0.82 seconds
Started Aug 15 04:49:19 PM PDT 24
Finished Aug 15 04:49:20 PM PDT 24
Peak memory 200456 kb
Host smart-f1fcff32-3e28-4e46-abb1-720a4118430f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295712627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3295712627
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2640388964
Short name T278
Test name
Test status
Simulation time 2349422179 ps
CPU time 9.37 seconds
Started Aug 15 04:49:22 PM PDT 24
Finished Aug 15 04:49:32 PM PDT 24
Peak memory 221944 kb
Host smart-8bd7f2cc-bd28-4158-9e69-f050ac50fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640388964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2640388964
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2880994250
Short name T323
Test name
Test status
Simulation time 243990847 ps
CPU time 1.04 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:21 PM PDT 24
Peak memory 217748 kb
Host smart-6e788e80-ab67-444f-aee8-5a20d0ad554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880994250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2880994250
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.4165537739
Short name T280
Test name
Test status
Simulation time 152195892 ps
CPU time 0.84 seconds
Started Aug 15 04:49:23 PM PDT 24
Finished Aug 15 04:49:24 PM PDT 24
Peak memory 200332 kb
Host smart-54a2f885-0678-4df1-a8eb-a62f25a9940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165537739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.4165537739
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.513414542
Short name T466
Test name
Test status
Simulation time 2060379895 ps
CPU time 8.15 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 200728 kb
Host smart-7abe54ed-d65b-4dd9-8ed3-85f17a4d5872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513414542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.513414542
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1345054260
Short name T326
Test name
Test status
Simulation time 137541369 ps
CPU time 1.12 seconds
Started Aug 15 04:49:22 PM PDT 24
Finished Aug 15 04:49:24 PM PDT 24
Peak memory 200592 kb
Host smart-f02cd4cb-7031-4b05-8688-62dce6a50d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345054260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1345054260
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1921705552
Short name T231
Test name
Test status
Simulation time 238999089 ps
CPU time 1.45 seconds
Started Aug 15 04:49:25 PM PDT 24
Finished Aug 15 04:49:27 PM PDT 24
Peak memory 200660 kb
Host smart-126eda9f-52b0-44cf-bc27-95a7363b3a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921705552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1921705552
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.225978505
Short name T453
Test name
Test status
Simulation time 5343025920 ps
CPU time 19.8 seconds
Started Aug 15 04:49:21 PM PDT 24
Finished Aug 15 04:49:41 PM PDT 24
Peak memory 208972 kb
Host smart-e5e5a7b9-2dae-4fca-b961-d08dcae1c5a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225978505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.225978505
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3744098581
Short name T324
Test name
Test status
Simulation time 116779434 ps
CPU time 1.56 seconds
Started Aug 15 04:49:23 PM PDT 24
Finished Aug 15 04:49:25 PM PDT 24
Peak memory 200492 kb
Host smart-e5e31c94-f928-45c4-bac7-77acd915e02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744098581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3744098581
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2224260450
Short name T169
Test name
Test status
Simulation time 229658409 ps
CPU time 1.35 seconds
Started Aug 15 04:49:22 PM PDT 24
Finished Aug 15 04:49:23 PM PDT 24
Peak memory 200496 kb
Host smart-440f3507-0e76-4405-9d18-0e8fedeae52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224260450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2224260450
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2851927135
Short name T204
Test name
Test status
Simulation time 69036884 ps
CPU time 0.83 seconds
Started Aug 15 04:49:28 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 200468 kb
Host smart-eb5d46bf-93f4-4f21-8f37-1e732c5041a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851927135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2851927135
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.619063608
Short name T202
Test name
Test status
Simulation time 244024084 ps
CPU time 1.09 seconds
Started Aug 15 04:49:23 PM PDT 24
Finished Aug 15 04:49:25 PM PDT 24
Peak memory 217676 kb
Host smart-cf05d429-521d-4050-9d1a-561689a82868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619063608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.619063608
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1338220098
Short name T224
Test name
Test status
Simulation time 163784293 ps
CPU time 0.86 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:21 PM PDT 24
Peak memory 200312 kb
Host smart-8d79c57a-7362-4d09-975e-2962565305d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338220098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1338220098
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.47071592
Short name T429
Test name
Test status
Simulation time 963372919 ps
CPU time 4.93 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:25 PM PDT 24
Peak memory 200732 kb
Host smart-bb06a34d-e6b3-41e7-8c6e-cc8cf708615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47071592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.47071592
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.33823637
Short name T483
Test name
Test status
Simulation time 139582836 ps
CPU time 1.18 seconds
Started Aug 15 04:49:22 PM PDT 24
Finished Aug 15 04:49:23 PM PDT 24
Peak memory 200472 kb
Host smart-2d0ed20c-4147-4117-8e81-6824772f9e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33823637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.33823637
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2068673986
Short name T424
Test name
Test status
Simulation time 201997762 ps
CPU time 1.59 seconds
Started Aug 15 04:49:21 PM PDT 24
Finished Aug 15 04:49:23 PM PDT 24
Peak memory 200688 kb
Host smart-88969027-2ca1-451b-8cd0-32cc10498a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068673986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2068673986
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1700346173
Short name T138
Test name
Test status
Simulation time 9400152338 ps
CPU time 34.49 seconds
Started Aug 15 04:49:19 PM PDT 24
Finished Aug 15 04:49:54 PM PDT 24
Peak memory 216468 kb
Host smart-8dd7d46c-3e5e-4ef2-a1dc-1b4b771e3051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700346173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1700346173
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.563781803
Short name T221
Test name
Test status
Simulation time 138117676 ps
CPU time 1.84 seconds
Started Aug 15 04:49:21 PM PDT 24
Finished Aug 15 04:49:23 PM PDT 24
Peak memory 200740 kb
Host smart-128837f2-860d-4716-9382-04aabed0f0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563781803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.563781803
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.9144921
Short name T367
Test name
Test status
Simulation time 60912936 ps
CPU time 0.78 seconds
Started Aug 15 04:49:20 PM PDT 24
Finished Aug 15 04:49:21 PM PDT 24
Peak memory 200564 kb
Host smart-bf5cd9ee-614e-4be5-9b45-2903540de13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9144921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.9144921
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3850120008
Short name T215
Test name
Test status
Simulation time 87701165 ps
CPU time 0.87 seconds
Started Aug 15 04:49:32 PM PDT 24
Finished Aug 15 04:49:33 PM PDT 24
Peak memory 200440 kb
Host smart-4b232a2a-4bb9-4b87-ac1c-a93f70ea641a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850120008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3850120008
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.165857693
Short name T47
Test name
Test status
Simulation time 1885760334 ps
CPU time 6.99 seconds
Started Aug 15 04:49:31 PM PDT 24
Finished Aug 15 04:49:38 PM PDT 24
Peak memory 217368 kb
Host smart-ff905169-9105-478a-b05e-64210152c65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165857693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.165857693
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2383528385
Short name T512
Test name
Test status
Simulation time 242774533 ps
CPU time 1.14 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:30 PM PDT 24
Peak memory 217712 kb
Host smart-fa102bea-5ebc-407e-8f4c-65f4d28aafd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383528385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2383528385
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3532311898
Short name T300
Test name
Test status
Simulation time 125739155 ps
CPU time 0.8 seconds
Started Aug 15 04:49:31 PM PDT 24
Finished Aug 15 04:49:31 PM PDT 24
Peak memory 200332 kb
Host smart-78d1f9af-2b2d-4ab3-9c81-534d1982deee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532311898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3532311898
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.1005616427
Short name T299
Test name
Test status
Simulation time 1808244507 ps
CPU time 7.37 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:36 PM PDT 24
Peak memory 200700 kb
Host smart-3b4fc12c-aa2e-489e-82a8-324695468148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005616427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1005616427
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2217491613
Short name T143
Test name
Test status
Simulation time 109114339 ps
CPU time 1.07 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:30 PM PDT 24
Peak memory 200452 kb
Host smart-4f5e090e-9637-41ef-8063-4e2421d5d6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217491613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2217491613
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.3412620818
Short name T454
Test name
Test status
Simulation time 122741779 ps
CPU time 1.31 seconds
Started Aug 15 04:49:31 PM PDT 24
Finished Aug 15 04:49:33 PM PDT 24
Peak memory 200928 kb
Host smart-94b91ee8-318f-4491-b028-35fa5e19bdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412620818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3412620818
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.192608787
Short name T71
Test name
Test status
Simulation time 6296201554 ps
CPU time 27.43 seconds
Started Aug 15 04:49:31 PM PDT 24
Finished Aug 15 04:49:58 PM PDT 24
Peak memory 208976 kb
Host smart-75b2d92c-4ccc-440e-b2f2-febf171109fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192608787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.192608787
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.1293133195
Short name T173
Test name
Test status
Simulation time 266118512 ps
CPU time 1.8 seconds
Started Aug 15 04:49:31 PM PDT 24
Finished Aug 15 04:49:33 PM PDT 24
Peak memory 200460 kb
Host smart-f5a8f455-3038-4f86-b5a3-c5e6d9fcf342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293133195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1293133195
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3242036907
Short name T250
Test name
Test status
Simulation time 228148881 ps
CPU time 1.46 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:31 PM PDT 24
Peak memory 200448 kb
Host smart-6da3a39d-8781-4bb8-880d-5176aec3cd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242036907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3242036907
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.3158172093
Short name T469
Test name
Test status
Simulation time 71362678 ps
CPU time 0.81 seconds
Started Aug 15 04:49:33 PM PDT 24
Finished Aug 15 04:49:34 PM PDT 24
Peak memory 200444 kb
Host smart-43335730-c62d-41fa-ab19-a84fcd6d5bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158172093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3158172093
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.3937327253
Short name T402
Test name
Test status
Simulation time 1878827902 ps
CPU time 7 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 216916 kb
Host smart-d456a787-f340-425d-8d97-ed5b247d1b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937327253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.3937327253
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.229756771
Short name T303
Test name
Test status
Simulation time 243917704 ps
CPU time 1.14 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 217776 kb
Host smart-645a01cd-d1e7-438a-a0e8-0dfbb0264b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229756771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.229756771
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2590411364
Short name T358
Test name
Test status
Simulation time 120953990 ps
CPU time 0.91 seconds
Started Aug 15 04:49:28 PM PDT 24
Finished Aug 15 04:49:30 PM PDT 24
Peak memory 200368 kb
Host smart-9e8ccc1b-3f40-4ba7-84e9-8d965e258377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590411364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2590411364
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.4008912383
Short name T284
Test name
Test status
Simulation time 1875794272 ps
CPU time 7.7 seconds
Started Aug 15 04:49:28 PM PDT 24
Finished Aug 15 04:49:36 PM PDT 24
Peak memory 200680 kb
Host smart-dbcc548b-b265-49a2-bb7c-e91cc82c858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008912383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.4008912383
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3789329692
Short name T532
Test name
Test status
Simulation time 151078452 ps
CPU time 1.11 seconds
Started Aug 15 04:49:27 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 200488 kb
Host smart-158cb4ac-1283-42d8-842e-aeede1ef852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789329692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3789329692
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.4291579833
Short name T536
Test name
Test status
Simulation time 117207099 ps
CPU time 1.22 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:30 PM PDT 24
Peak memory 200704 kb
Host smart-880146cd-058e-4954-9e47-de1a3b988ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291579833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4291579833
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.891148708
Short name T432
Test name
Test status
Simulation time 4664486325 ps
CPU time 20.91 seconds
Started Aug 15 04:49:33 PM PDT 24
Finished Aug 15 04:49:54 PM PDT 24
Peak memory 208952 kb
Host smart-54e5f36a-8021-4742-bc88-37afbbf9fa2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891148708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.891148708
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3111559712
Short name T481
Test name
Test status
Simulation time 233828789 ps
CPU time 1.43 seconds
Started Aug 15 04:49:30 PM PDT 24
Finished Aug 15 04:49:31 PM PDT 24
Peak memory 200580 kb
Host smart-a504332c-3118-4b86-adf5-e50097b01681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111559712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3111559712
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1632015934
Short name T209
Test name
Test status
Simulation time 81109175 ps
CPU time 0.79 seconds
Started Aug 15 04:49:32 PM PDT 24
Finished Aug 15 04:49:33 PM PDT 24
Peak memory 200360 kb
Host smart-bef87127-28d8-4180-9cf3-a1d6ff12cfe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632015934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1632015934
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.3289539612
Short name T379
Test name
Test status
Simulation time 2167262333 ps
CPU time 8.15 seconds
Started Aug 15 04:49:30 PM PDT 24
Finished Aug 15 04:49:38 PM PDT 24
Peak memory 217984 kb
Host smart-6ceee755-ab60-42ac-b914-7141cc81497a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289539612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3289539612
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1961551276
Short name T475
Test name
Test status
Simulation time 244286900 ps
CPU time 1.05 seconds
Started Aug 15 04:49:33 PM PDT 24
Finished Aug 15 04:49:34 PM PDT 24
Peak memory 217784 kb
Host smart-5f6b493f-f45c-4949-aeb5-acdef832ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961551276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1961551276
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.162414285
Short name T245
Test name
Test status
Simulation time 206775102 ps
CPU time 0.9 seconds
Started Aug 15 04:49:30 PM PDT 24
Finished Aug 15 04:49:31 PM PDT 24
Peak memory 200344 kb
Host smart-954c5cde-dfaa-4a95-8a1b-19e8871774a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162414285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.162414285
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4085022061
Short name T423
Test name
Test status
Simulation time 1160088708 ps
CPU time 5.51 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:43 PM PDT 24
Peak memory 200716 kb
Host smart-5905e89a-030e-45d6-b9ad-56aa4527b47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085022061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4085022061
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1804634807
Short name T411
Test name
Test status
Simulation time 185488798 ps
CPU time 1.2 seconds
Started Aug 15 04:49:28 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 200452 kb
Host smart-cba6c4e9-41e8-4a07-8f43-35c1bc1e5d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804634807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1804634807
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3450469309
Short name T84
Test name
Test status
Simulation time 197279316 ps
CPU time 1.34 seconds
Started Aug 15 04:49:28 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 200700 kb
Host smart-70e50575-cbe2-4072-8bd0-f5f53395aca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450469309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3450469309
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1484448849
Short name T439
Test name
Test status
Simulation time 463375602 ps
CPU time 2.75 seconds
Started Aug 15 04:49:32 PM PDT 24
Finished Aug 15 04:49:35 PM PDT 24
Peak memory 200580 kb
Host smart-98cb8db5-b742-4965-b3d7-e9aefdb049c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484448849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1484448849
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1587317850
Short name T497
Test name
Test status
Simulation time 380040781 ps
CPU time 2.43 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:32 PM PDT 24
Peak memory 200496 kb
Host smart-1de0df5b-29fe-46e8-bea1-d321abd72869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587317850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1587317850
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2401954675
Short name T534
Test name
Test status
Simulation time 142738296 ps
CPU time 1.16 seconds
Started Aug 15 04:49:33 PM PDT 24
Finished Aug 15 04:49:34 PM PDT 24
Peak memory 200580 kb
Host smart-485a1d3c-e73f-4587-8da7-0423e90b2536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401954675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2401954675
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.2461369336
Short name T163
Test name
Test status
Simulation time 68733835 ps
CPU time 0.79 seconds
Started Aug 15 04:49:30 PM PDT 24
Finished Aug 15 04:49:31 PM PDT 24
Peak memory 200412 kb
Host smart-ad7a2d34-03be-404a-a391-3cc5ff29dd95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461369336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2461369336
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1852324466
Short name T29
Test name
Test status
Simulation time 1233335090 ps
CPU time 5.88 seconds
Started Aug 15 04:49:28 PM PDT 24
Finished Aug 15 04:49:35 PM PDT 24
Peak memory 216948 kb
Host smart-1d3bdc6d-de99-428d-82f6-a8685740810c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852324466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1852324466
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1818134467
Short name T470
Test name
Test status
Simulation time 244042630 ps
CPU time 1.08 seconds
Started Aug 15 04:49:28 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 217712 kb
Host smart-32f0ba62-8649-4078-b5c6-28c54f661bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818134467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1818134467
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2239546337
Short name T513
Test name
Test status
Simulation time 1240704981 ps
CPU time 5.68 seconds
Started Aug 15 04:49:26 PM PDT 24
Finished Aug 15 04:49:32 PM PDT 24
Peak memory 200748 kb
Host smart-afcd33fd-1a92-4c7c-ad15-7077937520fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239546337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2239546337
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2327225548
Short name T387
Test name
Test status
Simulation time 174075405 ps
CPU time 1.19 seconds
Started Aug 15 04:49:31 PM PDT 24
Finished Aug 15 04:49:32 PM PDT 24
Peak memory 200560 kb
Host smart-974fcbce-b291-4c85-904d-e6a8fe6c0fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327225548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2327225548
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2007433143
Short name T167
Test name
Test status
Simulation time 122695336 ps
CPU time 1.27 seconds
Started Aug 15 04:49:27 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 200536 kb
Host smart-6c66fa7e-2d8c-4be6-8bfc-dc90d5d814f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007433143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2007433143
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.407111485
Short name T408
Test name
Test status
Simulation time 2968344474 ps
CPU time 9.67 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:39 PM PDT 24
Peak memory 208988 kb
Host smart-4e814cce-d5a3-43ce-a06f-110ae6d7dde9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407111485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.407111485
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1351724009
Short name T356
Test name
Test status
Simulation time 458331158 ps
CPU time 2.62 seconds
Started Aug 15 04:49:31 PM PDT 24
Finished Aug 15 04:49:34 PM PDT 24
Peak memory 200380 kb
Host smart-cb1dfd3f-ce97-420d-ab27-b8f1c215fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351724009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1351724009
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3107908258
Short name T176
Test name
Test status
Simulation time 174867914 ps
CPU time 1.41 seconds
Started Aug 15 04:49:30 PM PDT 24
Finished Aug 15 04:49:32 PM PDT 24
Peak memory 200568 kb
Host smart-4b42dee3-947d-44ae-9027-671de23d5df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107908258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3107908258
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.1614297762
Short name T279
Test name
Test status
Simulation time 58614076 ps
CPU time 0.74 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:35 PM PDT 24
Peak memory 200396 kb
Host smart-8c0d7d69-45f1-4a00-b0f0-02995838a4f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614297762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1614297762
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3606719795
Short name T433
Test name
Test status
Simulation time 1224616580 ps
CPU time 5.11 seconds
Started Aug 15 04:49:48 PM PDT 24
Finished Aug 15 04:49:53 PM PDT 24
Peak memory 221820 kb
Host smart-132c4fc8-6c36-4ce6-baba-161642a061d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606719795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3606719795
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1272159824
Short name T22
Test name
Test status
Simulation time 244912212 ps
CPU time 1.03 seconds
Started Aug 15 04:49:36 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 217764 kb
Host smart-12e2bc2b-6fe6-44dc-a715-5b9091f1db8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272159824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1272159824
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.483594331
Short name T327
Test name
Test status
Simulation time 146079203 ps
CPU time 0.89 seconds
Started Aug 15 04:49:30 PM PDT 24
Finished Aug 15 04:49:31 PM PDT 24
Peak memory 200380 kb
Host smart-1e31271a-bd5a-41d3-9451-dc02d51b92f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483594331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.483594331
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.773842845
Short name T97
Test name
Test status
Simulation time 1455838904 ps
CPU time 6.18 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:35 PM PDT 24
Peak memory 200736 kb
Host smart-7e50b78a-9828-4b06-a0be-89da292c4fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773842845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.773842845
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1043618297
Short name T146
Test name
Test status
Simulation time 147364184 ps
CPU time 1.14 seconds
Started Aug 15 04:49:36 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 200560 kb
Host smart-a59e18c0-7424-4853-b1ab-9ce858d695a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043618297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1043618297
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.3255517779
Short name T1
Test name
Test status
Simulation time 199160189 ps
CPU time 1.35 seconds
Started Aug 15 04:49:29 PM PDT 24
Finished Aug 15 04:49:30 PM PDT 24
Peak memory 200640 kb
Host smart-89795452-ff5a-4729-8d20-73f50a3644b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255517779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.3255517779
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1029534768
Short name T73
Test name
Test status
Simulation time 6029877549 ps
CPU time 21.59 seconds
Started Aug 15 04:49:47 PM PDT 24
Finished Aug 15 04:50:09 PM PDT 24
Peak memory 200756 kb
Host smart-db9f035c-b748-4369-892a-5d74dc8d7491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029534768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1029534768
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.2401742381
Short name T360
Test name
Test status
Simulation time 550954170 ps
CPU time 2.73 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:40 PM PDT 24
Peak memory 200740 kb
Host smart-112cd842-42b9-40e3-9a10-71f4c7b1d242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401742381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2401742381
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1453673796
Short name T305
Test name
Test status
Simulation time 121455344 ps
CPU time 1.08 seconds
Started Aug 15 04:49:30 PM PDT 24
Finished Aug 15 04:49:31 PM PDT 24
Peak memory 200476 kb
Host smart-3693a5ef-9db5-4014-8b5c-2259b7307e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453673796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1453673796
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1017718389
Short name T473
Test name
Test status
Simulation time 84856815 ps
CPU time 0.87 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:36 PM PDT 24
Peak memory 200360 kb
Host smart-582b0316-ca5b-4590-b716-21b23445a737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017718389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1017718389
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2156094034
Short name T531
Test name
Test status
Simulation time 2355751986 ps
CPU time 8.43 seconds
Started Aug 15 04:49:34 PM PDT 24
Finished Aug 15 04:49:43 PM PDT 24
Peak memory 218064 kb
Host smart-58561e5e-68aa-4862-9992-6055983e9d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156094034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2156094034
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1631106900
Short name T477
Test name
Test status
Simulation time 243860287 ps
CPU time 1.07 seconds
Started Aug 15 04:49:36 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 217704 kb
Host smart-4bc631e4-0ac1-4e35-bec4-00cb8116f39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631106900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1631106900
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2012897171
Short name T386
Test name
Test status
Simulation time 205564956 ps
CPU time 0.96 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:38 PM PDT 24
Peak memory 200356 kb
Host smart-5f27e383-8009-4a6d-8f79-08fe1ab29405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012897171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2012897171
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3357462298
Short name T474
Test name
Test status
Simulation time 908948619 ps
CPU time 4.76 seconds
Started Aug 15 04:49:34 PM PDT 24
Finished Aug 15 04:49:39 PM PDT 24
Peak memory 200720 kb
Host smart-5de23e93-ce20-42b0-8859-b2d7f50a79da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357462298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3357462298
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3240234351
Short name T7
Test name
Test status
Simulation time 183750366 ps
CPU time 1.15 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 200400 kb
Host smart-26a5b6b2-3ab6-4ebc-b105-68e6686c78bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240234351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3240234351
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.3598423710
Short name T508
Test name
Test status
Simulation time 116494458 ps
CPU time 1.13 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:36 PM PDT 24
Peak memory 200520 kb
Host smart-1e6f4b0b-d036-41ac-983c-5f6d1e645ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598423710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3598423710
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3526151993
Short name T541
Test name
Test status
Simulation time 2576590287 ps
CPU time 9.29 seconds
Started Aug 15 04:49:39 PM PDT 24
Finished Aug 15 04:49:48 PM PDT 24
Peak memory 200812 kb
Host smart-3dde1020-2f56-4696-8000-0aee83b22f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526151993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3526151993
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3640648551
Short name T182
Test name
Test status
Simulation time 270571257 ps
CPU time 1.82 seconds
Started Aug 15 04:49:38 PM PDT 24
Finished Aug 15 04:49:40 PM PDT 24
Peak memory 200372 kb
Host smart-79d5c1e8-a33f-40c3-9032-3a8c0db2e893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640648551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3640648551
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.4091251545
Short name T395
Test name
Test status
Simulation time 238194162 ps
CPU time 1.37 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:38 PM PDT 24
Peak memory 200476 kb
Host smart-d6f87a32-633b-45a6-a8e2-8b487c6d1064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091251545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.4091251545
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.3158129988
Short name T290
Test name
Test status
Simulation time 64829499 ps
CPU time 0.78 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 200416 kb
Host smart-f1d75553-8437-4067-ad2d-c94716f8f4c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158129988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.3158129988
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2655422586
Short name T359
Test name
Test status
Simulation time 1887960801 ps
CPU time 7.08 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:10 PM PDT 24
Peak memory 221848 kb
Host smart-1b3c69af-038a-407e-9da1-3de4a735d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655422586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2655422586
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.868139991
Short name T282
Test name
Test status
Simulation time 244493134 ps
CPU time 1.13 seconds
Started Aug 15 04:49:01 PM PDT 24
Finished Aug 15 04:49:03 PM PDT 24
Peak memory 217640 kb
Host smart-9566f947-e38f-4896-9f5e-0aca86ff704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868139991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.868139991
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.334795955
Short name T517
Test name
Test status
Simulation time 155457473 ps
CPU time 0.88 seconds
Started Aug 15 04:49:07 PM PDT 24
Finished Aug 15 04:49:08 PM PDT 24
Peak memory 200396 kb
Host smart-6db604f2-bcc5-49ca-b72d-ac1f04afd90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334795955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.334795955
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.2709935069
Short name T95
Test name
Test status
Simulation time 830619988 ps
CPU time 4.52 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:08 PM PDT 24
Peak memory 200796 kb
Host smart-2e11998f-63c3-4081-9924-71387d061f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709935069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2709935069
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.3576555053
Short name T67
Test name
Test status
Simulation time 8280439844 ps
CPU time 14.91 seconds
Started Aug 15 04:49:05 PM PDT 24
Finished Aug 15 04:49:20 PM PDT 24
Peak memory 217736 kb
Host smart-70fa5696-b180-49c2-b1c2-bedc05dbf752
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576555053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3576555053
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1545716288
Short name T296
Test name
Test status
Simulation time 144986231 ps
CPU time 1.1 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 200488 kb
Host smart-5c0a9aae-ae73-44b9-845d-364d3937a2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545716288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1545716288
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.3517741192
Short name T308
Test name
Test status
Simulation time 199867037 ps
CPU time 1.69 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 200696 kb
Host smart-e86e9c27-e183-4fde-beb0-0861b8ab59f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517741192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3517741192
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.589922227
Short name T102
Test name
Test status
Simulation time 2606930777 ps
CPU time 8.74 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 199400 kb
Host smart-4691b74a-43ad-4191-a849-95910b1081cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589922227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.589922227
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3301761252
Short name T378
Test name
Test status
Simulation time 119527965 ps
CPU time 1.54 seconds
Started Aug 15 04:49:05 PM PDT 24
Finished Aug 15 04:49:07 PM PDT 24
Peak memory 200460 kb
Host smart-594e8ea7-7c43-4222-874f-3c0e03c7b3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301761252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3301761252
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.3744843992
Short name T151
Test name
Test status
Simulation time 122159375 ps
CPU time 1.17 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 200492 kb
Host smart-6c5ec831-fcde-4f3b-84e4-9cda05e46ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744843992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.3744843992
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.2188683964
Short name T157
Test name
Test status
Simulation time 69357657 ps
CPU time 0.85 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:38 PM PDT 24
Peak memory 200376 kb
Host smart-eeb3bdac-1cb3-4ef6-8b1c-ebb63051e67b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188683964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2188683964
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3650123634
Short name T330
Test name
Test status
Simulation time 243954222 ps
CPU time 1.05 seconds
Started Aug 15 04:49:48 PM PDT 24
Finished Aug 15 04:49:49 PM PDT 24
Peak memory 217704 kb
Host smart-8c256a7d-830c-4f47-a006-b620cbea2f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650123634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3650123634
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.1353091739
Short name T366
Test name
Test status
Simulation time 100702174 ps
CPU time 0.74 seconds
Started Aug 15 04:49:39 PM PDT 24
Finished Aug 15 04:49:40 PM PDT 24
Peak memory 200400 kb
Host smart-51e05b54-15da-45ec-ac6d-05d5cdcc1c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353091739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.1353091739
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1671839785
Short name T232
Test name
Test status
Simulation time 807201915 ps
CPU time 4.47 seconds
Started Aug 15 04:49:38 PM PDT 24
Finished Aug 15 04:49:42 PM PDT 24
Peak memory 200764 kb
Host smart-7a336a94-4ce9-4437-9dcc-5babbf590813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671839785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1671839785
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3938284066
Short name T161
Test name
Test status
Simulation time 183068510 ps
CPU time 1.2 seconds
Started Aug 15 04:49:36 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 200600 kb
Host smart-1edaf5c9-46ae-4465-a487-bb9766b08bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938284066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3938284066
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.2715197323
Short name T82
Test name
Test status
Simulation time 126274339 ps
CPU time 1.14 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:39 PM PDT 24
Peak memory 200580 kb
Host smart-08e8bf3d-6906-4770-b801-e6f57f61b246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715197323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2715197323
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.2625119502
Short name T259
Test name
Test status
Simulation time 3771059837 ps
CPU time 17.33 seconds
Started Aug 15 04:49:38 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 208936 kb
Host smart-b6ab78a7-ebc3-49e1-864b-dde8842bc7a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625119502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2625119502
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2851884817
Short name T256
Test name
Test status
Simulation time 317162372 ps
CPU time 2.22 seconds
Started Aug 15 04:49:38 PM PDT 24
Finished Aug 15 04:49:41 PM PDT 24
Peak memory 200440 kb
Host smart-dfc83e93-316b-44cf-8149-883dc2f698fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851884817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2851884817
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.651169105
Short name T362
Test name
Test status
Simulation time 158314248 ps
CPU time 1.08 seconds
Started Aug 15 04:49:36 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 200444 kb
Host smart-706fd10f-3c96-4f5b-ae47-2b1f96135f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651169105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.651169105
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1146067313
Short name T265
Test name
Test status
Simulation time 75570379 ps
CPU time 0.78 seconds
Started Aug 15 04:49:39 PM PDT 24
Finished Aug 15 04:49:40 PM PDT 24
Peak memory 200456 kb
Host smart-aba4d092-d7d6-4429-b925-79e5ac0b48df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146067313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1146067313
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.741488295
Short name T297
Test name
Test status
Simulation time 1218381493 ps
CPU time 5.43 seconds
Started Aug 15 04:49:48 PM PDT 24
Finished Aug 15 04:49:53 PM PDT 24
Peak memory 217868 kb
Host smart-34ded533-a536-4ef6-ad55-8352cfebdabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741488295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.741488295
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3778466937
Short name T258
Test name
Test status
Simulation time 244196515 ps
CPU time 1.08 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:36 PM PDT 24
Peak memory 217684 kb
Host smart-e50588a3-0a4e-4394-baa7-fc0933017aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778466937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3778466937
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3249488844
Short name T346
Test name
Test status
Simulation time 160865119 ps
CPU time 0.85 seconds
Started Aug 15 04:49:50 PM PDT 24
Finished Aug 15 04:49:51 PM PDT 24
Peak memory 200348 kb
Host smart-25318824-e6f5-47ef-9e16-65b8fab7e436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249488844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3249488844
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2311424233
Short name T149
Test name
Test status
Simulation time 932164460 ps
CPU time 4.98 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:42 PM PDT 24
Peak memory 200776 kb
Host smart-b92a0f0c-a93a-41f6-8686-c39e7870a255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311424233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2311424233
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.476300945
Short name T333
Test name
Test status
Simulation time 104657266 ps
CPU time 0.97 seconds
Started Aug 15 04:49:35 PM PDT 24
Finished Aug 15 04:49:36 PM PDT 24
Peak memory 200580 kb
Host smart-ccc2dcf5-4808-4f3f-b3c5-7528aa556b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476300945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.476300945
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.1096320332
Short name T419
Test name
Test status
Simulation time 253108980 ps
CPU time 1.56 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:39 PM PDT 24
Peak memory 200644 kb
Host smart-00815391-5b18-42a2-a5c1-7efaa1862803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096320332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1096320332
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2607573767
Short name T227
Test name
Test status
Simulation time 8645650749 ps
CPU time 28.97 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:50:06 PM PDT 24
Peak memory 200812 kb
Host smart-38c8293d-1c13-4ede-8a4e-dcb0e3203b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607573767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2607573767
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.4209156488
Short name T400
Test name
Test status
Simulation time 123359384 ps
CPU time 1.64 seconds
Started Aug 15 04:49:36 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 200456 kb
Host smart-40bbc52d-1aab-4487-a7f2-111a6a89df55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209156488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.4209156488
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.400307391
Short name T249
Test name
Test status
Simulation time 151072938 ps
CPU time 1.26 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:38 PM PDT 24
Peak memory 200528 kb
Host smart-20e0e745-b2dc-4387-ba4c-4768346ef93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400307391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.400307391
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.1492093319
Short name T381
Test name
Test status
Simulation time 61774402 ps
CPU time 0.75 seconds
Started Aug 15 04:49:48 PM PDT 24
Finished Aug 15 04:49:49 PM PDT 24
Peak memory 200460 kb
Host smart-e848c7c8-18c6-49ea-a71a-28cf21feaf54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492093319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1492093319
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.835197599
Short name T51
Test name
Test status
Simulation time 2354465643 ps
CPU time 7.79 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:53 PM PDT 24
Peak memory 221920 kb
Host smart-0e967dcd-8f2d-4ff4-9c63-4afb33986708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835197599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.835197599
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2610402911
Short name T304
Test name
Test status
Simulation time 243957743 ps
CPU time 1.13 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:48 PM PDT 24
Peak memory 217696 kb
Host smart-676dbb61-b0aa-4f5e-8439-1e80dc29d7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610402911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2610402911
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.1605634352
Short name T14
Test name
Test status
Simulation time 144148742 ps
CPU time 0.82 seconds
Started Aug 15 04:49:37 PM PDT 24
Finished Aug 15 04:49:38 PM PDT 24
Peak memory 200244 kb
Host smart-e0d1ed92-dcdc-4f67-98f4-1765d0384340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605634352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1605634352
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2583718692
Short name T126
Test name
Test status
Simulation time 1609500669 ps
CPU time 5.98 seconds
Started Aug 15 04:49:34 PM PDT 24
Finished Aug 15 04:49:40 PM PDT 24
Peak memory 200744 kb
Host smart-251b55ad-6f62-469e-ae26-783ef5e3a51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583718692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2583718692
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.4275772176
Short name T12
Test name
Test status
Simulation time 154208064 ps
CPU time 1.11 seconds
Started Aug 15 04:49:36 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 200472 kb
Host smart-90418742-3372-416f-8f99-d0ca50c0617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275772176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.4275772176
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1383186763
Short name T187
Test name
Test status
Simulation time 185201856 ps
CPU time 1.53 seconds
Started Aug 15 04:49:34 PM PDT 24
Finished Aug 15 04:49:36 PM PDT 24
Peak memory 200620 kb
Host smart-e9bf32dd-649f-4504-b614-bd47f8297b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383186763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1383186763
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.4047469204
Short name T430
Test name
Test status
Simulation time 148447763 ps
CPU time 1.84 seconds
Started Aug 15 04:49:36 PM PDT 24
Finished Aug 15 04:49:38 PM PDT 24
Peak memory 200484 kb
Host smart-92e8797f-6a27-4628-be21-2ce6b32a9897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047469204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.4047469204
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.2463710859
Short name T200
Test name
Test status
Simulation time 244541985 ps
CPU time 1.37 seconds
Started Aug 15 04:49:50 PM PDT 24
Finished Aug 15 04:49:52 PM PDT 24
Peak memory 200540 kb
Host smart-d38d12f3-4372-43e9-98e1-fb9e4f1dc3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463710859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2463710859
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3941440061
Short name T257
Test name
Test status
Simulation time 63071341 ps
CPU time 0.77 seconds
Started Aug 15 04:49:44 PM PDT 24
Finished Aug 15 04:49:45 PM PDT 24
Peak memory 200400 kb
Host smart-f9fa8278-b19e-448e-8e08-63ecf4a85822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941440061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3941440061
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2561010788
Short name T207
Test name
Test status
Simulation time 244070039 ps
CPU time 1.08 seconds
Started Aug 15 04:49:48 PM PDT 24
Finished Aug 15 04:49:49 PM PDT 24
Peak memory 217764 kb
Host smart-18deb724-0827-4a5b-ab4f-245647d38b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561010788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2561010788
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2031385543
Short name T177
Test name
Test status
Simulation time 211452378 ps
CPU time 0.92 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200372 kb
Host smart-7e9793bd-697b-42a5-96aa-b5ea4eb1b5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031385543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2031385543
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.4244782619
Short name T171
Test name
Test status
Simulation time 1404948859 ps
CPU time 5.21 seconds
Started Aug 15 04:49:47 PM PDT 24
Finished Aug 15 04:49:53 PM PDT 24
Peak memory 200812 kb
Host smart-1050dad8-10ca-4675-b1f6-e8fd6672b06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244782619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.4244782619
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.921673282
Short name T233
Test name
Test status
Simulation time 106521792 ps
CPU time 1.02 seconds
Started Aug 15 04:49:44 PM PDT 24
Finished Aug 15 04:49:45 PM PDT 24
Peak memory 200560 kb
Host smart-f2b83c35-54d3-41cc-b415-d80505e80676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921673282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.921673282
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.4092339022
Short name T465
Test name
Test status
Simulation time 230164756 ps
CPU time 1.53 seconds
Started Aug 15 04:49:49 PM PDT 24
Finished Aug 15 04:49:51 PM PDT 24
Peak memory 200744 kb
Host smart-f268baa9-1e3f-4b78-9e03-1e7cbbff5022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092339022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.4092339022
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.543182001
Short name T340
Test name
Test status
Simulation time 8770479172 ps
CPU time 33.49 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:50:20 PM PDT 24
Peak memory 209804 kb
Host smart-0cdfa29d-9e33-4e6b-be9e-56b350307588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543182001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.543182001
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.1296196735
Short name T42
Test name
Test status
Simulation time 151952472 ps
CPU time 1.88 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200332 kb
Host smart-ea02d238-6b68-4826-bb03-86be79717936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296196735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1296196735
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3877263304
Short name T301
Test name
Test status
Simulation time 120406367 ps
CPU time 0.98 seconds
Started Aug 15 04:49:44 PM PDT 24
Finished Aug 15 04:49:45 PM PDT 24
Peak memory 200480 kb
Host smart-f729e7cf-7e5d-412d-ae93-425982fe2c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877263304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3877263304
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.4088427973
Short name T63
Test name
Test status
Simulation time 70316360 ps
CPU time 0.82 seconds
Started Aug 15 04:49:44 PM PDT 24
Finished Aug 15 04:49:45 PM PDT 24
Peak memory 200456 kb
Host smart-3602e551-ea35-4bd8-b117-1fd0f044c7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088427973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.4088427973
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.496241044
Short name T28
Test name
Test status
Simulation time 1225954713 ps
CPU time 5.9 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:52 PM PDT 24
Peak memory 217860 kb
Host smart-6d69a5b3-4864-40a6-9ff8-db184db366eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496241044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.496241044
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1011328920
Short name T321
Test name
Test status
Simulation time 244358979 ps
CPU time 1.05 seconds
Started Aug 15 04:49:50 PM PDT 24
Finished Aug 15 04:49:51 PM PDT 24
Peak memory 217768 kb
Host smart-82d70733-dd1e-4217-b4f4-d5ecda989c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011328920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1011328920
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3677124675
Short name T509
Test name
Test status
Simulation time 160358389 ps
CPU time 0.84 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200264 kb
Host smart-fdd57bc5-3340-4705-a2d3-175a3efcad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677124675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3677124675
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.1141266655
Short name T220
Test name
Test status
Simulation time 1194171919 ps
CPU time 4.93 seconds
Started Aug 15 04:49:44 PM PDT 24
Finished Aug 15 04:49:49 PM PDT 24
Peak memory 200748 kb
Host smart-307694f5-e77c-495c-bcc3-27d37590a492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141266655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1141266655
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1878893269
Short name T78
Test name
Test status
Simulation time 175079657 ps
CPU time 1.22 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200548 kb
Host smart-b2159e6b-ed95-40b0-8076-f9bbfa905e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878893269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1878893269
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.604607507
Short name T81
Test name
Test status
Simulation time 197023239 ps
CPU time 1.44 seconds
Started Aug 15 04:49:44 PM PDT 24
Finished Aug 15 04:49:45 PM PDT 24
Peak memory 200732 kb
Host smart-99cb4fd0-18ff-4a0d-a2e7-7721acca617c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604607507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.604607507
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2829720240
Short name T168
Test name
Test status
Simulation time 261698027 ps
CPU time 1.71 seconds
Started Aug 15 04:49:47 PM PDT 24
Finished Aug 15 04:49:49 PM PDT 24
Peak memory 200636 kb
Host smart-f8166327-8802-45b4-b88b-4553c88f1cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829720240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2829720240
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3878284763
Short name T377
Test name
Test status
Simulation time 323327855 ps
CPU time 2.28 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:48 PM PDT 24
Peak memory 200448 kb
Host smart-4967e1ef-e972-4b1b-9050-4cf1e2e87b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878284763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3878284763
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.1005892645
Short name T514
Test name
Test status
Simulation time 227201911 ps
CPU time 1.35 seconds
Started Aug 15 04:49:44 PM PDT 24
Finished Aug 15 04:49:46 PM PDT 24
Peak memory 200572 kb
Host smart-33f92f93-b0ab-417e-93b8-60f41e54ab5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005892645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.1005892645
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.2617645922
Short name T172
Test name
Test status
Simulation time 101948740 ps
CPU time 0.82 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200472 kb
Host smart-f1d55b72-afed-4d5a-830e-a5f0af4177aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617645922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2617645922
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1563835302
Short name T495
Test name
Test status
Simulation time 1221285839 ps
CPU time 5.55 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:51 PM PDT 24
Peak memory 221484 kb
Host smart-9a0a87d7-ab39-45be-ab9f-9e6064d94715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563835302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1563835302
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.735607882
Short name T225
Test name
Test status
Simulation time 247732661 ps
CPU time 1.03 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 217660 kb
Host smart-a1a93e65-c528-411a-8dda-fba7ac72bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735607882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.735607882
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1170178669
Short name T293
Test name
Test status
Simulation time 164439537 ps
CPU time 0.88 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200384 kb
Host smart-671c0949-deda-47bc-b60b-ba40692b112b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170178669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1170178669
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1463818857
Short name T306
Test name
Test status
Simulation time 933837354 ps
CPU time 5.18 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:50 PM PDT 24
Peak memory 200748 kb
Host smart-c2f7c2f9-01c5-460b-acd6-10c552507998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463818857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1463818857
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.133494387
Short name T181
Test name
Test status
Simulation time 111484231 ps
CPU time 1.1 seconds
Started Aug 15 04:49:43 PM PDT 24
Finished Aug 15 04:49:45 PM PDT 24
Peak memory 200524 kb
Host smart-28f017d2-d13b-44da-87a6-82c0c13b6d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133494387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.133494387
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.3021795712
Short name T131
Test name
Test status
Simulation time 206321030 ps
CPU time 1.38 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200560 kb
Host smart-962f3c73-10b3-4391-a7b5-76771bb99802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021795712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3021795712
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.344762658
Short name T539
Test name
Test status
Simulation time 4373776996 ps
CPU time 20.08 seconds
Started Aug 15 04:49:48 PM PDT 24
Finished Aug 15 04:50:08 PM PDT 24
Peak memory 209000 kb
Host smart-606959f1-bdd3-4253-9ce7-9831774fdcbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344762658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.344762658
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1423531505
Short name T441
Test name
Test status
Simulation time 556877934 ps
CPU time 2.9 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:49 PM PDT 24
Peak memory 200488 kb
Host smart-f3508909-3eef-4522-9c1b-83de90c791cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423531505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1423531505
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1806614642
Short name T11
Test name
Test status
Simulation time 176994973 ps
CPU time 1.29 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200636 kb
Host smart-504e521b-27ee-4ac7-b03b-5093fbeee318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806614642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1806614642
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2536070088
Short name T422
Test name
Test status
Simulation time 64358266 ps
CPU time 0.76 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:46 PM PDT 24
Peak memory 200440 kb
Host smart-433165ff-dbbb-47c1-845a-11e179d4aca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536070088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2536070088
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2945145025
Short name T461
Test name
Test status
Simulation time 2361891874 ps
CPU time 7.79 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:54 PM PDT 24
Peak memory 217996 kb
Host smart-013c1f3b-e1b7-4176-a6e1-2759f2f5c374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945145025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2945145025
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2739575130
Short name T463
Test name
Test status
Simulation time 244579273 ps
CPU time 1.13 seconds
Started Aug 15 04:49:48 PM PDT 24
Finished Aug 15 04:49:49 PM PDT 24
Peak memory 217724 kb
Host smart-54e65e4c-3d8e-45ec-80c2-4f5312c85b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739575130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2739575130
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3250811238
Short name T511
Test name
Test status
Simulation time 121490125 ps
CPU time 0.81 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 199880 kb
Host smart-84e62457-ad34-415f-b905-812a56e2f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250811238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3250811238
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.388175567
Short name T342
Test name
Test status
Simulation time 2134709302 ps
CPU time 7.72 seconds
Started Aug 15 04:49:45 PM PDT 24
Finished Aug 15 04:49:52 PM PDT 24
Peak memory 200744 kb
Host smart-dd7a95fb-d967-46b4-99e0-6baaa1ebbbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388175567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.388175567
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.539664925
Short name T540
Test name
Test status
Simulation time 180747960 ps
CPU time 1.26 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:48 PM PDT 24
Peak memory 200552 kb
Host smart-1f8c2c47-a968-432f-97d6-d37891b511b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539664925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.539664925
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1839428528
Short name T488
Test name
Test status
Simulation time 235667364 ps
CPU time 1.59 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200168 kb
Host smart-bb1d6e24-3b45-4c43-a270-899e79fcc881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839428528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1839428528
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2957533490
Short name T434
Test name
Test status
Simulation time 2888172495 ps
CPU time 13.26 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:50:00 PM PDT 24
Peak memory 200716 kb
Host smart-82080ba6-afa1-44bb-bb03-fc23d98a7cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957533490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2957533490
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3453042060
Short name T471
Test name
Test status
Simulation time 122206620 ps
CPU time 1.65 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:48 PM PDT 24
Peak memory 208624 kb
Host smart-065b101c-fab6-42a5-80e1-4f1a447e7714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453042060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3453042060
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.230327960
Short name T529
Test name
Test status
Simulation time 118415190 ps
CPU time 1.06 seconds
Started Aug 15 04:49:50 PM PDT 24
Finished Aug 15 04:49:51 PM PDT 24
Peak memory 200540 kb
Host smart-0124c0d3-92ad-439e-a496-c7a2dbf62779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230327960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.230327960
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2959434595
Short name T152
Test name
Test status
Simulation time 61860683 ps
CPU time 0.8 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200428 kb
Host smart-93bc3c2a-e57c-4c5d-9b0e-b70131de96e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959434595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2959434595
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.618723907
Short name T484
Test name
Test status
Simulation time 2378516841 ps
CPU time 8.04 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 217968 kb
Host smart-00d57e26-2c38-4c3c-9a0f-c3cab81004ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618723907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.618723907
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2789612845
Short name T521
Test name
Test status
Simulation time 243782317 ps
CPU time 1.09 seconds
Started Aug 15 04:49:52 PM PDT 24
Finished Aug 15 04:49:53 PM PDT 24
Peak memory 217776 kb
Host smart-8b163150-49e6-4af7-b5b8-2f965744a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789612845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2789612845
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.833193678
Short name T442
Test name
Test status
Simulation time 118861360 ps
CPU time 0.8 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:47 PM PDT 24
Peak memory 200652 kb
Host smart-9cf17266-8783-45aa-aa3b-08c2fb7a8cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833193678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.833193678
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.4212882667
Short name T390
Test name
Test status
Simulation time 806411877 ps
CPU time 4.19 seconds
Started Aug 15 04:49:53 PM PDT 24
Finished Aug 15 04:49:58 PM PDT 24
Peak memory 200720 kb
Host smart-38eb0ef4-a660-409b-97e7-7e0b067474d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212882667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4212882667
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.823651520
Short name T27
Test name
Test status
Simulation time 181791365 ps
CPU time 1.24 seconds
Started Aug 15 04:49:52 PM PDT 24
Finished Aug 15 04:49:54 PM PDT 24
Peak memory 200528 kb
Host smart-e50dfb21-6ea4-4d58-a1a1-e1161d10f689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823651520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.823651520
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2706707647
Short name T223
Test name
Test status
Simulation time 252198662 ps
CPU time 1.56 seconds
Started Aug 15 04:49:46 PM PDT 24
Finished Aug 15 04:49:48 PM PDT 24
Peak memory 200664 kb
Host smart-7e161043-877a-4c7d-adda-a822562769d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706707647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2706707647
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.632270565
Short name T286
Test name
Test status
Simulation time 4107228205 ps
CPU time 15.43 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:50:10 PM PDT 24
Peak memory 200796 kb
Host smart-b5bc74b0-acba-4fe4-bc6f-a81df5657926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632270565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.632270565
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2215382781
Short name T538
Test name
Test status
Simulation time 115438750 ps
CPU time 1.49 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200332 kb
Host smart-408c181e-b663-4cf9-b908-293f5c80b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215382781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2215382781
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4290068194
Short name T211
Test name
Test status
Simulation time 211649700 ps
CPU time 1.24 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200544 kb
Host smart-427aa6d0-e723-4008-97bb-1e0e2598d24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290068194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4290068194
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4171011464
Short name T500
Test name
Test status
Simulation time 71579930 ps
CPU time 0.88 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200412 kb
Host smart-a8a84ff7-9194-47d9-b299-9f9d985b0b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171011464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4171011464
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3081621883
Short name T31
Test name
Test status
Simulation time 1215132058 ps
CPU time 5.64 seconds
Started Aug 15 04:50:03 PM PDT 24
Finished Aug 15 04:50:08 PM PDT 24
Peak memory 217716 kb
Host smart-cd638a48-1db2-46c8-bfb6-84a5c6519fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081621883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3081621883
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3613069955
Short name T262
Test name
Test status
Simulation time 244832443 ps
CPU time 1.29 seconds
Started Aug 15 04:49:53 PM PDT 24
Finished Aug 15 04:49:55 PM PDT 24
Peak memory 217696 kb
Host smart-b81b2d8e-6d46-45a6-a514-6966c0d41406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613069955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3613069955
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.4001541111
Short name T21
Test name
Test status
Simulation time 168031513 ps
CPU time 0.92 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200364 kb
Host smart-9b6e60b4-a400-4870-9b7f-ac3b7a593860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001541111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4001541111
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3817518390
Short name T69
Test name
Test status
Simulation time 1195950755 ps
CPU time 5.63 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:50:00 PM PDT 24
Peak memory 200772 kb
Host smart-6bcd7c05-c6d1-4d4f-a3fb-96c05ce49948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817518390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3817518390
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1589570736
Short name T147
Test name
Test status
Simulation time 156313986 ps
CPU time 1.19 seconds
Started Aug 15 04:50:00 PM PDT 24
Finished Aug 15 04:50:01 PM PDT 24
Peak memory 200564 kb
Host smart-40977466-0cbd-4262-af06-a93ad19675d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589570736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1589570736
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.583305027
Short name T194
Test name
Test status
Simulation time 202151851 ps
CPU time 1.42 seconds
Started Aug 15 04:49:54 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200700 kb
Host smart-f0e8a596-8179-4565-b05d-73c290be6ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583305027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.583305027
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.857047991
Short name T24
Test name
Test status
Simulation time 10132977281 ps
CPU time 33.9 seconds
Started Aug 15 04:49:52 PM PDT 24
Finished Aug 15 04:50:26 PM PDT 24
Peak memory 209032 kb
Host smart-e4a9797c-1377-4c47-acf3-77292a086ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857047991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.857047991
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.1506571831
Short name T205
Test name
Test status
Simulation time 481208385 ps
CPU time 2.63 seconds
Started Aug 15 04:49:54 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 208684 kb
Host smart-5a4bc871-2eff-442f-b2b3-3429ace75d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506571831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1506571831
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.4257371569
Short name T192
Test name
Test status
Simulation time 166152720 ps
CPU time 1.15 seconds
Started Aug 15 04:49:54 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200508 kb
Host smart-368054be-8380-419d-abe6-23e53c65afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257371569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.4257371569
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.3878904624
Short name T468
Test name
Test status
Simulation time 73443391 ps
CPU time 0.76 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200436 kb
Host smart-5016bdf9-4778-4b17-871e-74a53370b83f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878904624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3878904624
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2601439242
Short name T52
Test name
Test status
Simulation time 1883997634 ps
CPU time 7.23 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 217740 kb
Host smart-977e0386-cf9b-4dbc-ab62-e626f4b9d015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601439242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2601439242
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.4231115609
Short name T4
Test name
Test status
Simulation time 244577193 ps
CPU time 1.18 seconds
Started Aug 15 04:49:53 PM PDT 24
Finished Aug 15 04:49:55 PM PDT 24
Peak memory 217732 kb
Host smart-1a79aee0-6866-462c-b760-2cb5a68462e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231115609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.4231115609
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1521970870
Short name T17
Test name
Test status
Simulation time 103231534 ps
CPU time 0.84 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200312 kb
Host smart-84ee3d15-7066-4fdf-9a41-681c424fdf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521970870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1521970870
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.71307678
Short name T313
Test name
Test status
Simulation time 745745140 ps
CPU time 3.68 seconds
Started Aug 15 04:49:57 PM PDT 24
Finished Aug 15 04:50:00 PM PDT 24
Peak memory 200748 kb
Host smart-ab1a2857-85ff-46a1-ac5b-d2e0a11061d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71307678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.71307678
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3367829286
Short name T235
Test name
Test status
Simulation time 99454076 ps
CPU time 0.99 seconds
Started Aug 15 04:49:53 PM PDT 24
Finished Aug 15 04:49:54 PM PDT 24
Peak memory 200484 kb
Host smart-0f813d8a-59c5-48a6-8a48-c56069044dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367829286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3367829286
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.811127579
Short name T129
Test name
Test status
Simulation time 243495295 ps
CPU time 1.58 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200708 kb
Host smart-a34bcd64-3c9f-4629-afa9-5c57e012b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811127579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.811127579
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.2205976269
Short name T246
Test name
Test status
Simulation time 1246287898 ps
CPU time 5.48 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:08 PM PDT 24
Peak memory 200732 kb
Host smart-9cf75134-40d8-48ba-9bb0-4eecdf30d20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205976269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2205976269
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3637399475
Short name T516
Test name
Test status
Simulation time 426482594 ps
CPU time 2.71 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:58 PM PDT 24
Peak memory 200484 kb
Host smart-6d92d6e6-2add-4edb-a2af-f3b9227f76bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637399475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3637399475
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.159680259
Short name T455
Test name
Test status
Simulation time 169081977 ps
CPU time 1.32 seconds
Started Aug 15 04:49:53 PM PDT 24
Finished Aug 15 04:49:55 PM PDT 24
Peak memory 200712 kb
Host smart-cc55d9ff-71a9-4f70-b60b-d62cbb5116c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159680259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.159680259
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2106850897
Short name T64
Test name
Test status
Simulation time 58655685 ps
CPU time 0.72 seconds
Started Aug 15 04:49:02 PM PDT 24
Finished Aug 15 04:49:03 PM PDT 24
Peak memory 200348 kb
Host smart-1dee6e30-4dda-4498-b475-ad1f6dfdc852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106850897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2106850897
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2437352060
Short name T344
Test name
Test status
Simulation time 1224703496 ps
CPU time 5.8 seconds
Started Aug 15 04:49:08 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 217896 kb
Host smart-ba4fa315-c7f9-4bc9-9161-3cd69313b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437352060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2437352060
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1706825049
Short name T544
Test name
Test status
Simulation time 244233805 ps
CPU time 1.09 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 217672 kb
Host smart-7097dbd7-ca2c-432f-820a-9a48091f47b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706825049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1706825049
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.1277861760
Short name T180
Test name
Test status
Simulation time 139904923 ps
CPU time 0.9 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 200380 kb
Host smart-5d19f1fb-2d75-435b-b616-18705703d590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277861760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1277861760
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.183917564
Short name T444
Test name
Test status
Simulation time 1504626929 ps
CPU time 5.89 seconds
Started Aug 15 04:49:02 PM PDT 24
Finished Aug 15 04:49:08 PM PDT 24
Peak memory 200660 kb
Host smart-df39922b-7c8e-4d61-8eea-f1ec64c91ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183917564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.183917564
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1476295507
Short name T66
Test name
Test status
Simulation time 16963333803 ps
CPU time 26.39 seconds
Started Aug 15 04:49:07 PM PDT 24
Finished Aug 15 04:49:33 PM PDT 24
Peak memory 217228 kb
Host smart-0cd1dd39-f8f9-44cb-a033-b3ae373216b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476295507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1476295507
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.316355130
Short name T74
Test name
Test status
Simulation time 148034851 ps
CPU time 1.07 seconds
Started Aug 15 04:49:07 PM PDT 24
Finished Aug 15 04:49:08 PM PDT 24
Peak memory 200564 kb
Host smart-7d835c04-a122-48a8-a89f-a9ff03d9d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316355130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.316355130
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1852119214
Short name T162
Test name
Test status
Simulation time 203118292 ps
CPU time 1.34 seconds
Started Aug 15 04:49:02 PM PDT 24
Finished Aug 15 04:49:03 PM PDT 24
Peak memory 200624 kb
Host smart-3075e7ec-a0f1-463c-8d67-326a7ec05581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852119214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1852119214
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.2842401128
Short name T389
Test name
Test status
Simulation time 2676172969 ps
CPU time 10.3 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 207580 kb
Host smart-3b3b3464-74c8-4354-b5e7-00c83ea65d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842401128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2842401128
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1325074356
Short name T370
Test name
Test status
Simulation time 121616595 ps
CPU time 1.56 seconds
Started Aug 15 04:49:05 PM PDT 24
Finished Aug 15 04:49:07 PM PDT 24
Peak memory 200320 kb
Host smart-fef98421-86b5-4231-865f-8954a6fb5227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325074356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1325074356
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3726036052
Short name T307
Test name
Test status
Simulation time 116823610 ps
CPU time 1.08 seconds
Started Aug 15 04:49:07 PM PDT 24
Finished Aug 15 04:49:08 PM PDT 24
Peak memory 200440 kb
Host smart-0632b0f7-f3ce-4f9d-907b-fc69f672866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726036052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3726036052
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3185296076
Short name T507
Test name
Test status
Simulation time 75165858 ps
CPU time 0.79 seconds
Started Aug 15 04:49:57 PM PDT 24
Finished Aug 15 04:49:58 PM PDT 24
Peak memory 200428 kb
Host smart-c4d33620-2e45-4d0e-af1d-1083c12f8920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185296076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3185296076
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1467520615
Short name T388
Test name
Test status
Simulation time 1896210699 ps
CPU time 7.2 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:50:02 PM PDT 24
Peak memory 221844 kb
Host smart-6cdeba21-21fa-4462-8cfc-6cda3c0ac7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467520615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1467520615
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1714800965
Short name T459
Test name
Test status
Simulation time 243939929 ps
CPU time 1.13 seconds
Started Aug 15 04:50:00 PM PDT 24
Finished Aug 15 04:50:01 PM PDT 24
Peak memory 217732 kb
Host smart-13de101a-4a10-4e1c-9e64-3fc51937ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714800965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1714800965
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1710058531
Short name T542
Test name
Test status
Simulation time 146614335 ps
CPU time 0.87 seconds
Started Aug 15 04:49:54 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200272 kb
Host smart-4af7426d-fc51-4bab-ad11-1988c1cf6947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710058531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1710058531
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3773964224
Short name T208
Test name
Test status
Simulation time 1473248976 ps
CPU time 6 seconds
Started Aug 15 04:49:58 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200716 kb
Host smart-72cf264f-bc73-4a86-b088-73ac547f9088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773964224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3773964224
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1150510741
Short name T530
Test name
Test status
Simulation time 97331880 ps
CPU time 1.01 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200572 kb
Host smart-fbb24e1d-3241-4034-a058-171d051dddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150510741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1150510741
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.1890001493
Short name T188
Test name
Test status
Simulation time 113778916 ps
CPU time 1.21 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200684 kb
Host smart-95db719b-761a-42e9-b485-9c22b9161804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890001493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1890001493
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.858269449
Short name T270
Test name
Test status
Simulation time 870167313 ps
CPU time 4.33 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:59 PM PDT 24
Peak memory 200776 kb
Host smart-097ad6d9-8786-44e2-8dca-44d7de2b05ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858269449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.858269449
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3689998583
Short name T347
Test name
Test status
Simulation time 147117648 ps
CPU time 1.74 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200332 kb
Host smart-cea97baf-4ae0-44eb-8b8f-95fdb2b9c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689998583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3689998583
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3195264300
Short name T427
Test name
Test status
Simulation time 146873475 ps
CPU time 1.06 seconds
Started Aug 15 04:49:54 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200488 kb
Host smart-8188b849-dd5c-4ca6-a7aa-f00368cbd8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195264300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3195264300
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.241974325
Short name T197
Test name
Test status
Simulation time 72869971 ps
CPU time 0.79 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200464 kb
Host smart-15250de8-852b-47dc-bbd9-434c1ca557f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241974325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.241974325
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.970708135
Short name T350
Test name
Test status
Simulation time 2359462717 ps
CPU time 8.19 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 222004 kb
Host smart-dae144d5-b7e9-4ca9-a9b2-d8a7d689873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970708135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.970708135
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2380514151
Short name T369
Test name
Test status
Simulation time 243908383 ps
CPU time 1.15 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 217728 kb
Host smart-485e6285-7106-449b-aa60-2dae4991cf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380514151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2380514151
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.972743733
Short name T425
Test name
Test status
Simulation time 152317580 ps
CPU time 0.93 seconds
Started Aug 15 04:50:00 PM PDT 24
Finished Aug 15 04:50:01 PM PDT 24
Peak memory 200404 kb
Host smart-4c8bda14-70d7-4904-96b4-ef50cdc1687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972743733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.972743733
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2460251444
Short name T96
Test name
Test status
Simulation time 949745392 ps
CPU time 5.07 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:50:01 PM PDT 24
Peak memory 200784 kb
Host smart-b55bd6b6-9211-451e-b272-3fe16488f0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460251444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2460251444
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.574541407
Short name T142
Test name
Test status
Simulation time 158534354 ps
CPU time 1.14 seconds
Started Aug 15 04:49:53 PM PDT 24
Finished Aug 15 04:49:54 PM PDT 24
Peak memory 200476 kb
Host smart-3eca949d-af87-4ac9-988d-bbef32518987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574541407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.574541407
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.3671502804
Short name T401
Test name
Test status
Simulation time 118790990 ps
CPU time 1.19 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200676 kb
Host smart-300b0107-419d-4853-aa1b-8ec621f0db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671502804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3671502804
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.1463373386
Short name T183
Test name
Test status
Simulation time 2790727863 ps
CPU time 13.34 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:50:10 PM PDT 24
Peak memory 200812 kb
Host smart-09e5fb7e-ec83-4217-8ae8-13a186357d3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463373386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.1463373386
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.761043746
Short name T80
Test name
Test status
Simulation time 401741001 ps
CPU time 2.19 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200460 kb
Host smart-787d8441-94a3-4fe5-8ef9-12bf6c5c3aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761043746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.761043746
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.575189113
Short name T486
Test name
Test status
Simulation time 243359905 ps
CPU time 1.46 seconds
Started Aug 15 04:49:53 PM PDT 24
Finished Aug 15 04:49:55 PM PDT 24
Peak memory 200700 kb
Host smart-7d96e305-e4db-4716-866f-bcaec881066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575189113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.575189113
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.508228324
Short name T446
Test name
Test status
Simulation time 67567989 ps
CPU time 0.78 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200440 kb
Host smart-c5a13479-9d3b-473c-b444-d45475120941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508228324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.508228324
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2896884308
Short name T319
Test name
Test status
Simulation time 1228124211 ps
CPU time 5.59 seconds
Started Aug 15 04:49:57 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 216956 kb
Host smart-d6322d74-71bc-4f0a-b66f-b42b4889fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896884308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2896884308
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.255488988
Short name T506
Test name
Test status
Simulation time 244120141 ps
CPU time 1.17 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 217748 kb
Host smart-f9c1c70b-5936-4399-ba6e-c8c95955899f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255488988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.255488988
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1889842394
Short name T253
Test name
Test status
Simulation time 125202070 ps
CPU time 0.88 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200364 kb
Host smart-513e36a4-d6f1-47af-a7fe-5773dbc7ebb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889842394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1889842394
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.105136736
Short name T480
Test name
Test status
Simulation time 1807302785 ps
CPU time 6.97 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200720 kb
Host smart-9215bc58-dcef-4d13-bbb3-e08b2effd962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105136736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.105136736
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.657082241
Short name T436
Test name
Test status
Simulation time 178789699 ps
CPU time 1.13 seconds
Started Aug 15 04:49:59 PM PDT 24
Finished Aug 15 04:50:01 PM PDT 24
Peak memory 200568 kb
Host smart-06a57ace-0d43-401e-8a7b-79a233369f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657082241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.657082241
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.835169588
Short name T154
Test name
Test status
Simulation time 115575514 ps
CPU time 1.3 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:49:58 PM PDT 24
Peak memory 200656 kb
Host smart-4808ae97-3a09-4739-b792-4d8c69b5d61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835169588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.835169588
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.1025538656
Short name T99
Test name
Test status
Simulation time 1756175294 ps
CPU time 7.98 seconds
Started Aug 15 04:49:59 PM PDT 24
Finished Aug 15 04:50:07 PM PDT 24
Peak memory 200724 kb
Host smart-ac49cbe0-61a0-4168-bd6a-76f2e8c4eba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025538656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1025538656
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1733407025
Short name T391
Test name
Test status
Simulation time 284785295 ps
CPU time 2.14 seconds
Started Aug 15 04:49:54 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200468 kb
Host smart-c231a5a4-3ce1-4749-9c74-eef6d55284fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733407025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1733407025
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.487516858
Short name T457
Test name
Test status
Simulation time 113659909 ps
CPU time 0.98 seconds
Started Aug 15 04:49:53 PM PDT 24
Finished Aug 15 04:49:54 PM PDT 24
Peak memory 200560 kb
Host smart-5b2420f6-8476-424c-b4ec-15ff9923f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487516858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.487516858
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1792124922
Short name T337
Test name
Test status
Simulation time 67746743 ps
CPU time 0.75 seconds
Started Aug 15 04:50:07 PM PDT 24
Finished Aug 15 04:50:08 PM PDT 24
Peak memory 200464 kb
Host smart-4abca5c8-98e0-4643-929b-d524bd85aa6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792124922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1792124922
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2540466613
Short name T36
Test name
Test status
Simulation time 1209839999 ps
CPU time 5.43 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:50:02 PM PDT 24
Peak memory 221884 kb
Host smart-3aa9741a-faf5-40fb-9030-29bee0b48fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540466613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2540466613
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.646335955
Short name T428
Test name
Test status
Simulation time 244331542 ps
CPU time 1.13 seconds
Started Aug 15 04:50:00 PM PDT 24
Finished Aug 15 04:50:01 PM PDT 24
Peak memory 217816 kb
Host smart-0d26bb00-bbf7-4ae3-9491-ef3f630b6337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646335955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.646335955
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2320664039
Short name T9
Test name
Test status
Simulation time 85032453 ps
CPU time 0.79 seconds
Started Aug 15 04:49:54 PM PDT 24
Finished Aug 15 04:49:55 PM PDT 24
Peak memory 200340 kb
Host smart-14d8a327-d427-42c3-8134-93cb7b7be95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320664039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2320664039
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3270781747
Short name T199
Test name
Test status
Simulation time 918167911 ps
CPU time 4.69 seconds
Started Aug 15 04:49:56 PM PDT 24
Finished Aug 15 04:50:01 PM PDT 24
Peak memory 200612 kb
Host smart-f3cc1569-1713-427e-8597-3bb09ba57587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270781747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3270781747
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.709189301
Short name T404
Test name
Test status
Simulation time 108497239 ps
CPU time 0.99 seconds
Started Aug 15 04:49:59 PM PDT 24
Finished Aug 15 04:50:00 PM PDT 24
Peak memory 200560 kb
Host smart-9fe4b63c-7bc6-41d4-9541-279c14dc3b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709189301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.709189301
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2654942661
Short name T128
Test name
Test status
Simulation time 241873351 ps
CPU time 1.41 seconds
Started Aug 15 04:49:58 PM PDT 24
Finished Aug 15 04:49:59 PM PDT 24
Peak memory 200700 kb
Host smart-df978761-1a0a-4778-975c-2c5a83f28b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654942661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2654942661
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1685389104
Short name T178
Test name
Test status
Simulation time 1962846888 ps
CPU time 8.83 seconds
Started Aug 15 04:50:08 PM PDT 24
Finished Aug 15 04:50:17 PM PDT 24
Peak memory 208960 kb
Host smart-1b2055a2-8fb0-496c-8e14-a9bcc643f0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685389104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1685389104
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1874818380
Short name T510
Test name
Test status
Simulation time 141663233 ps
CPU time 1.82 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:57 PM PDT 24
Peak memory 200488 kb
Host smart-934c6f56-fc82-48c2-98b0-c740e3ad7beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874818380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1874818380
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.4256826247
Short name T186
Test name
Test status
Simulation time 214581144 ps
CPU time 1.32 seconds
Started Aug 15 04:49:55 PM PDT 24
Finished Aug 15 04:49:56 PM PDT 24
Peak memory 200480 kb
Host smart-29ebad64-cf86-4659-be66-398ae6251d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256826247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.4256826247
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2295291707
Short name T496
Test name
Test status
Simulation time 74193655 ps
CPU time 0.75 seconds
Started Aug 15 04:50:06 PM PDT 24
Finished Aug 15 04:50:07 PM PDT 24
Peak memory 200432 kb
Host smart-d259007d-9d2d-4113-9ee5-9793df1bed9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295291707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2295291707
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.891120366
Short name T353
Test name
Test status
Simulation time 1884379961 ps
CPU time 7.16 seconds
Started Aug 15 04:50:08 PM PDT 24
Finished Aug 15 04:50:15 PM PDT 24
Peak memory 217956 kb
Host smart-20f19f67-4e9d-4246-b302-bb95389adb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891120366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.891120366
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4151930654
Short name T325
Test name
Test status
Simulation time 246784128 ps
CPU time 1.04 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:02 PM PDT 24
Peak memory 217752 kb
Host smart-1dba1f1f-b89c-406d-bc62-440719dfd71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151930654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4151930654
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2128728228
Short name T20
Test name
Test status
Simulation time 143496767 ps
CPU time 0.86 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:02 PM PDT 24
Peak memory 200400 kb
Host smart-0d1a0910-28aa-4d3a-81a8-d7eea926d81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128728228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2128728228
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.226627323
Short name T376
Test name
Test status
Simulation time 699835996 ps
CPU time 4.04 seconds
Started Aug 15 04:50:08 PM PDT 24
Finished Aug 15 04:50:13 PM PDT 24
Peak memory 200804 kb
Host smart-b2e68293-4776-4e55-9a55-f5fa06934527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226627323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.226627323
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1676640974
Short name T341
Test name
Test status
Simulation time 114499265 ps
CPU time 1.04 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:02 PM PDT 24
Peak memory 200584 kb
Host smart-a92f94a3-fb06-40b1-a74c-d1e50106635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676640974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1676640974
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3127961307
Short name T368
Test name
Test status
Simulation time 121697806 ps
CPU time 1.21 seconds
Started Aug 15 04:50:03 PM PDT 24
Finished Aug 15 04:50:05 PM PDT 24
Peak memory 200572 kb
Host smart-41dd30b8-449f-466e-8d46-0b2c18cce4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127961307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3127961307
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2793757884
Short name T407
Test name
Test status
Simulation time 2001712211 ps
CPU time 9.2 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 208948 kb
Host smart-123f3e48-1549-47cb-b9cc-dc06630a99bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793757884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2793757884
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.3138637751
Short name T523
Test name
Test status
Simulation time 253483185 ps
CPU time 1.8 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 200360 kb
Host smart-8cd4ed70-ff83-40d4-beb7-a0e8d3623f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138637751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3138637751
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1082913914
Short name T170
Test name
Test status
Simulation time 228330858 ps
CPU time 1.38 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 200596 kb
Host smart-a0ef9575-f2b9-4273-b6e7-2222d5bc460b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082913914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1082913914
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1173181501
Short name T351
Test name
Test status
Simulation time 79525950 ps
CPU time 0.79 seconds
Started Aug 15 04:50:04 PM PDT 24
Finished Aug 15 04:50:05 PM PDT 24
Peak memory 200356 kb
Host smart-c9c7b368-5987-44ce-8896-bbd6de176e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173181501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1173181501
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.2327592961
Short name T48
Test name
Test status
Simulation time 2348179167 ps
CPU time 8.46 seconds
Started Aug 15 04:50:00 PM PDT 24
Finished Aug 15 04:50:08 PM PDT 24
Peak memory 217968 kb
Host smart-750655bc-12d2-4480-86f6-92fdc06d6940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327592961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2327592961
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2408152929
Short name T412
Test name
Test status
Simulation time 244958259 ps
CPU time 0.99 seconds
Started Aug 15 04:50:05 PM PDT 24
Finished Aug 15 04:50:06 PM PDT 24
Peak memory 217764 kb
Host smart-ecdb0fb3-0c92-48be-b4ab-84d9c919dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408152929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2408152929
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.3397900627
Short name T494
Test name
Test status
Simulation time 148242868 ps
CPU time 0.81 seconds
Started Aug 15 04:50:03 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200376 kb
Host smart-203726b6-e60d-459d-87f1-94040932c4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397900627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3397900627
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3073713837
Short name T77
Test name
Test status
Simulation time 1578288761 ps
CPU time 6.07 seconds
Started Aug 15 04:50:08 PM PDT 24
Finished Aug 15 04:50:14 PM PDT 24
Peak memory 200744 kb
Host smart-d6054a41-02ec-40a4-9fe9-bb0a39525923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073713837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3073713837
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3933824469
Short name T156
Test name
Test status
Simulation time 95865058 ps
CPU time 1.03 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 200592 kb
Host smart-306e4835-b488-4527-a08b-887f5d780be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933824469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3933824469
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.583811823
Short name T414
Test name
Test status
Simulation time 119578879 ps
CPU time 1.16 seconds
Started Aug 15 04:50:03 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200620 kb
Host smart-28641024-1032-4060-b313-a577dd39db8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583811823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.583811823
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2087971976
Short name T254
Test name
Test status
Simulation time 5565531369 ps
CPU time 18.26 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:20 PM PDT 24
Peak memory 200748 kb
Host smart-6ca264bf-531d-409d-9ec1-dab88aa13811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087971976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2087971976
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.892782246
Short name T251
Test name
Test status
Simulation time 542279314 ps
CPU time 3.02 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200516 kb
Host smart-6dd437af-ae14-40a1-9c74-e4411168ddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892782246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.892782246
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1724025455
Short name T72
Test name
Test status
Simulation time 233653430 ps
CPU time 1.48 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:02 PM PDT 24
Peak memory 200600 kb
Host smart-53d316db-6b95-4034-9703-3d7175db157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724025455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1724025455
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3809864573
Short name T216
Test name
Test status
Simulation time 75404522 ps
CPU time 0.85 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 200428 kb
Host smart-256d384b-0ad5-4419-9419-aaf77773ba58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809864573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3809864573
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2840339396
Short name T451
Test name
Test status
Simulation time 1226130006 ps
CPU time 5.59 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:08 PM PDT 24
Peak memory 217760 kb
Host smart-e4f333b2-f51d-42c8-b6fc-a129d7663bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840339396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2840339396
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1085080940
Short name T339
Test name
Test status
Simulation time 243704295 ps
CPU time 1.24 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 217688 kb
Host smart-17491602-fc21-4d00-9ad7-e309b8f58eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085080940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1085080940
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3919155330
Short name T19
Test name
Test status
Simulation time 230780647 ps
CPU time 0.98 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 200340 kb
Host smart-232ac1d5-cd73-41f2-9217-33967916da2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919155330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3919155330
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.396837404
Short name T417
Test name
Test status
Simulation time 1285123192 ps
CPU time 5.31 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:07 PM PDT 24
Peak memory 200612 kb
Host smart-f758cb3a-18f2-45f0-abeb-ba2cd325ffdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396837404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.396837404
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1698984634
Short name T315
Test name
Test status
Simulation time 149539669 ps
CPU time 1.25 seconds
Started Aug 15 04:50:03 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200492 kb
Host smart-cd7bc3bb-352d-4bd1-9ea4-fa5a08b7f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698984634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1698984634
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4119837824
Short name T243
Test name
Test status
Simulation time 248858293 ps
CPU time 1.47 seconds
Started Aug 15 04:50:03 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200728 kb
Host smart-764dbbba-83e9-4520-8ba8-a3c87919951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119837824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4119837824
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.818787928
Short name T240
Test name
Test status
Simulation time 9200736490 ps
CPU time 35.1 seconds
Started Aug 15 04:50:06 PM PDT 24
Finished Aug 15 04:50:41 PM PDT 24
Peak memory 200832 kb
Host smart-224f7ea9-38f5-4025-8cc3-225a330c387c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818787928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.818787928
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1335459487
Short name T320
Test name
Test status
Simulation time 262958232 ps
CPU time 1.89 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:04 PM PDT 24
Peak memory 200476 kb
Host smart-310f2186-c3bc-4e82-8849-14bf3009c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335459487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1335459487
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2983555979
Short name T522
Test name
Test status
Simulation time 114030883 ps
CPU time 0.96 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:02 PM PDT 24
Peak memory 200564 kb
Host smart-e18d48e5-3ab7-4494-9e76-e1e98d196641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983555979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2983555979
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1975575984
Short name T155
Test name
Test status
Simulation time 101316172 ps
CPU time 0.83 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200464 kb
Host smart-8314bee0-a91b-402a-9707-9fe67ecc2c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975575984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1975575984
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.179268302
Short name T32
Test name
Test status
Simulation time 1225544219 ps
CPU time 6.17 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:07 PM PDT 24
Peak memory 217956 kb
Host smart-75c71b92-d690-4391-965c-ac9a58e6af58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179268302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.179268302
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1578608501
Short name T79
Test name
Test status
Simulation time 244036541 ps
CPU time 1.1 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 217680 kb
Host smart-3006a8fd-7cae-42bd-a1b0-b7ceb40ca6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578608501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1578608501
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.3447528341
Short name T237
Test name
Test status
Simulation time 143480933 ps
CPU time 0.85 seconds
Started Aug 15 04:50:08 PM PDT 24
Finished Aug 15 04:50:09 PM PDT 24
Peak memory 200412 kb
Host smart-ba48ee9c-38a3-482d-bb9a-9dbdfa5631f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447528341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3447528341
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2719532342
Short name T354
Test name
Test status
Simulation time 1379331584 ps
CPU time 5.58 seconds
Started Aug 15 04:50:06 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200720 kb
Host smart-cb6954f6-feca-4195-9a75-36d36ae4a8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719532342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2719532342
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3246653669
Short name T185
Test name
Test status
Simulation time 174951788 ps
CPU time 1.21 seconds
Started Aug 15 04:50:04 PM PDT 24
Finished Aug 15 04:50:05 PM PDT 24
Peak memory 200484 kb
Host smart-be067d80-8ec2-4858-a681-92e9251adfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246653669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3246653669
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2141786769
Short name T464
Test name
Test status
Simulation time 108489809 ps
CPU time 1.2 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 200684 kb
Host smart-608956aa-c470-4937-9fab-38168e0469d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141786769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2141786769
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3957464470
Short name T101
Test name
Test status
Simulation time 6141036650 ps
CPU time 22.92 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:34 PM PDT 24
Peak memory 200780 kb
Host smart-8758cad6-34f6-4f42-99f9-cf677063fb21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957464470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3957464470
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.1341941751
Short name T76
Test name
Test status
Simulation time 144074573 ps
CPU time 1.74 seconds
Started Aug 15 04:50:01 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 200448 kb
Host smart-40dde62e-75b3-414b-8628-8033581b40b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341941751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1341941751
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.3848830213
Short name T255
Test name
Test status
Simulation time 73619803 ps
CPU time 0.86 seconds
Started Aug 15 04:50:02 PM PDT 24
Finished Aug 15 04:50:03 PM PDT 24
Peak memory 200492 kb
Host smart-76bda3cc-79f6-44bd-a27c-01a11b39fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848830213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.3848830213
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3779048544
Short name T212
Test name
Test status
Simulation time 97374115 ps
CPU time 0.87 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 200448 kb
Host smart-a707cf66-0d66-48f5-a24d-1f33b1272a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779048544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3779048544
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.3542290261
Short name T352
Test name
Test status
Simulation time 1876425251 ps
CPU time 7.66 seconds
Started Aug 15 04:50:09 PM PDT 24
Finished Aug 15 04:50:17 PM PDT 24
Peak memory 217668 kb
Host smart-5c56d94a-8f69-4baf-ad53-402c6bc1e6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542290261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3542290261
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3940843807
Short name T269
Test name
Test status
Simulation time 243449360 ps
CPU time 1.13 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:13 PM PDT 24
Peak memory 217732 kb
Host smart-87a06742-0b8d-4fce-a88e-8356cbcca2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940843807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3940843807
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.1558875398
Short name T287
Test name
Test status
Simulation time 207872790 ps
CPU time 0.91 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200352 kb
Host smart-8f2d9a13-94c6-4cb4-bb8c-f8f81604d29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558875398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1558875398
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.202324435
Short name T239
Test name
Test status
Simulation time 699495031 ps
CPU time 3.65 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:15 PM PDT 24
Peak memory 200776 kb
Host smart-9f8d90c9-1136-4c2e-b329-1456cf81657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202324435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.202324435
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2684253837
Short name T261
Test name
Test status
Simulation time 142371365 ps
CPU time 1.32 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 200568 kb
Host smart-0f58a03a-ec80-49e0-9f3c-bda877010860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684253837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2684253837
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.337245464
Short name T68
Test name
Test status
Simulation time 195203735 ps
CPU time 1.36 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200684 kb
Host smart-109f3c69-52ef-4c8e-ac55-d9f3907bbfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337245464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.337245464
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.1686890436
Short name T409
Test name
Test status
Simulation time 6931830555 ps
CPU time 25.31 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 200844 kb
Host smart-a885c93d-7240-453b-b0d5-72964fa0f2e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686890436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1686890436
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3169276039
Short name T397
Test name
Test status
Simulation time 132068519 ps
CPU time 1.73 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200524 kb
Host smart-dde17cc1-4581-41d2-95f8-bc16ac082fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169276039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3169276039
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.2557490789
Short name T273
Test name
Test status
Simulation time 149566663 ps
CPU time 1.07 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200452 kb
Host smart-152b1a6f-1209-4e85-b607-436a2cdaf5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557490789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2557490789
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.408623051
Short name T38
Test name
Test status
Simulation time 67652490 ps
CPU time 0.74 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 200456 kb
Host smart-64e03304-b34a-4b4c-a24d-f2e0c70e10bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408623051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.408623051
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3315891861
Short name T50
Test name
Test status
Simulation time 2159546515 ps
CPU time 8.77 seconds
Started Aug 15 04:50:12 PM PDT 24
Finished Aug 15 04:50:21 PM PDT 24
Peak memory 222008 kb
Host smart-35b35f64-9e40-4a7b-b78e-fcf6d0cb848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315891861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3315891861
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3688655535
Short name T322
Test name
Test status
Simulation time 245907970 ps
CPU time 1.06 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 217692 kb
Host smart-28d1da94-da86-46f9-a1c7-e1c9e6e22637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688655535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3688655535
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.3065677028
Short name T298
Test name
Test status
Simulation time 202040510 ps
CPU time 0.92 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 200296 kb
Host smart-499d0b0c-0444-4f3c-a084-938058c58d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065677028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3065677028
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1044138517
Short name T505
Test name
Test status
Simulation time 1859248356 ps
CPU time 7.49 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:18 PM PDT 24
Peak memory 200704 kb
Host smart-491deb25-aadb-4bd0-ba59-ac15d365faf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044138517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1044138517
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3388316053
Short name T396
Test name
Test status
Simulation time 151408403 ps
CPU time 1.06 seconds
Started Aug 15 04:50:14 PM PDT 24
Finished Aug 15 04:50:15 PM PDT 24
Peak memory 200564 kb
Host smart-42575600-8177-49b8-937a-7f2ed600de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388316053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3388316053
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.3612009280
Short name T450
Test name
Test status
Simulation time 122124882 ps
CPU time 1.24 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 200684 kb
Host smart-f1f909c0-1f33-46b8-93d2-48bc2fdfadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612009280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3612009280
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.209488377
Short name T437
Test name
Test status
Simulation time 2108831991 ps
CPU time 10.01 seconds
Started Aug 15 04:50:13 PM PDT 24
Finished Aug 15 04:50:23 PM PDT 24
Peak memory 200728 kb
Host smart-0acf023d-d95f-4473-ad6c-a83a3d7b0a35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209488377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.209488377
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4040253507
Short name T150
Test name
Test status
Simulation time 297791180 ps
CPU time 2.21 seconds
Started Aug 15 04:50:09 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 208612 kb
Host smart-e6ece05e-d9f0-4ced-956a-9a8c9985fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040253507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4040253507
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.1543789293
Short name T385
Test name
Test status
Simulation time 95069846 ps
CPU time 0.89 seconds
Started Aug 15 04:50:14 PM PDT 24
Finished Aug 15 04:50:15 PM PDT 24
Peak memory 200568 kb
Host smart-26d71784-0f8f-4588-a308-6fc63d27aca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543789293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.1543789293
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.615237242
Short name T158
Test name
Test status
Simulation time 61688132 ps
CPU time 0.76 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 200320 kb
Host smart-8ba3db3d-f132-4334-8b3e-6ae3a9697759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615237242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.615237242
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.1719025610
Short name T5
Test name
Test status
Simulation time 2341166694 ps
CPU time 8.2 seconds
Started Aug 15 04:49:05 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 217272 kb
Host smart-361c1ebc-9741-480d-9c0b-80fa7f2b23b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719025610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1719025610
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4018941338
Short name T140
Test name
Test status
Simulation time 246876061 ps
CPU time 1.19 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 217968 kb
Host smart-4467b2a0-fe74-473f-97f9-45c013b92697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018941338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4018941338
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2471049105
Short name T274
Test name
Test status
Simulation time 157743654 ps
CPU time 0.93 seconds
Started Aug 15 04:49:02 PM PDT 24
Finished Aug 15 04:49:04 PM PDT 24
Peak memory 200256 kb
Host smart-543e6294-d489-464a-8a81-29006e91f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471049105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2471049105
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.333132877
Short name T394
Test name
Test status
Simulation time 901489254 ps
CPU time 4.75 seconds
Started Aug 15 04:49:11 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 200740 kb
Host smart-dc26a92e-3af0-471a-9bb4-c02e478b1d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333132877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.333132877
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.935349224
Short name T62
Test name
Test status
Simulation time 8944349844 ps
CPU time 13.11 seconds
Started Aug 15 04:49:06 PM PDT 24
Finished Aug 15 04:49:19 PM PDT 24
Peak memory 217300 kb
Host smart-f5d69f6a-f47d-4bde-95c0-58566bb3e5f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935349224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.935349224
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3529049197
Short name T317
Test name
Test status
Simulation time 101367947 ps
CPU time 1.04 seconds
Started Aug 15 04:49:07 PM PDT 24
Finished Aug 15 04:49:08 PM PDT 24
Peak memory 200560 kb
Host smart-ae00542f-29d8-4c9a-b9e4-5eac6e0ad611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529049197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3529049197
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.4270582412
Short name T361
Test name
Test status
Simulation time 203625649 ps
CPU time 1.44 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:06 PM PDT 24
Peak memory 200744 kb
Host smart-4d234eb4-5af8-499c-a7d0-87ede30df185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270582412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.4270582412
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.89516627
Short name T374
Test name
Test status
Simulation time 9931642015 ps
CPU time 33.13 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:37 PM PDT 24
Peak memory 208980 kb
Host smart-c5940de1-d025-40ef-ba9e-0c15806c80ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89516627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.89516627
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.1074606438
Short name T191
Test name
Test status
Simulation time 421860943 ps
CPU time 2.33 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:06 PM PDT 24
Peak memory 208524 kb
Host smart-39b78210-9dc9-4965-b648-de858e52b273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074606438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1074606438
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2782355875
Short name T384
Test name
Test status
Simulation time 178286665 ps
CPU time 1.2 seconds
Started Aug 15 04:49:08 PM PDT 24
Finished Aug 15 04:49:10 PM PDT 24
Peak memory 200468 kb
Host smart-7af59089-ae96-48b0-bc0e-e66bb1c3813c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782355875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2782355875
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1922342927
Short name T504
Test name
Test status
Simulation time 63528430 ps
CPU time 0.74 seconds
Started Aug 15 04:50:09 PM PDT 24
Finished Aug 15 04:50:10 PM PDT 24
Peak memory 200448 kb
Host smart-f2b9df3c-63fa-467d-8357-c11438095022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922342927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1922342927
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.10282988
Short name T35
Test name
Test status
Simulation time 1905081296 ps
CPU time 7.32 seconds
Started Aug 15 04:50:08 PM PDT 24
Finished Aug 15 04:50:15 PM PDT 24
Peak memory 217532 kb
Host smart-0525aca4-db71-424a-ae5a-b41978f39be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10282988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.10282988
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3868800615
Short name T405
Test name
Test status
Simulation time 244155610 ps
CPU time 1.16 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 217724 kb
Host smart-dfc79211-484a-4b78-ab7e-75839cc5b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868800615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3868800615
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.454903294
Short name T15
Test name
Test status
Simulation time 143619659 ps
CPU time 0.85 seconds
Started Aug 15 04:50:09 PM PDT 24
Finished Aug 15 04:50:10 PM PDT 24
Peak memory 200316 kb
Host smart-5fa5a05f-3658-46af-95ee-6e92eaf6bc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454903294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.454903294
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2037458365
Short name T426
Test name
Test status
Simulation time 941920065 ps
CPU time 4.48 seconds
Started Aug 15 04:50:07 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200720 kb
Host smart-b7e707b0-4644-4e4d-bc34-b86c61e08886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037458365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2037458365
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2278516660
Short name T236
Test name
Test status
Simulation time 183163581 ps
CPU time 1.29 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200584 kb
Host smart-e7b66519-d648-49e6-99c4-84ec14cce555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278516660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2278516660
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2312882115
Short name T318
Test name
Test status
Simulation time 114404347 ps
CPU time 1.23 seconds
Started Aug 15 04:50:08 PM PDT 24
Finished Aug 15 04:50:10 PM PDT 24
Peak memory 200660 kb
Host smart-d9e1a657-d873-400b-9fa4-c079153c4700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312882115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2312882115
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.301397604
Short name T23
Test name
Test status
Simulation time 1864334439 ps
CPU time 8.31 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:19 PM PDT 24
Peak memory 208948 kb
Host smart-d2e95961-66fc-4f1b-ac59-867d46dce486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301397604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.301397604
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.620241783
Short name T498
Test name
Test status
Simulation time 360917671 ps
CPU time 2.34 seconds
Started Aug 15 04:50:09 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200504 kb
Host smart-4f9a5038-41bf-4d3d-8f39-3ee221ea254f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620241783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.620241783
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1925817780
Short name T421
Test name
Test status
Simulation time 154647834 ps
CPU time 1.29 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 200516 kb
Host smart-8c2f6d70-98b6-417e-b29d-28de8594eeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925817780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1925817780
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3264189387
Short name T289
Test name
Test status
Simulation time 69240149 ps
CPU time 0.75 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 200436 kb
Host smart-129da9ff-1f17-48f0-830b-1e6efaf3ab99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264189387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3264189387
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1044245837
Short name T316
Test name
Test status
Simulation time 1222047778 ps
CPU time 6.13 seconds
Started Aug 15 04:50:09 PM PDT 24
Finished Aug 15 04:50:16 PM PDT 24
Peak memory 217884 kb
Host smart-bd101af5-0af4-46db-a35d-96474cef5a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044245837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1044245837
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1919434291
Short name T148
Test name
Test status
Simulation time 245318627 ps
CPU time 1.09 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:12 PM PDT 24
Peak memory 217688 kb
Host smart-76253659-cf67-40df-b457-51d173404697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919434291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1919434291
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1870358830
Short name T222
Test name
Test status
Simulation time 94947828 ps
CPU time 0.77 seconds
Started Aug 15 04:50:09 PM PDT 24
Finished Aug 15 04:50:10 PM PDT 24
Peak memory 200264 kb
Host smart-50d64dee-09c0-47c9-9db6-087472eab459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870358830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1870358830
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1961150314
Short name T479
Test name
Test status
Simulation time 1539879636 ps
CPU time 5.96 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:16 PM PDT 24
Peak memory 200744 kb
Host smart-8650ba78-be75-4f73-af49-98778f2974d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961150314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1961150314
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3665545268
Short name T435
Test name
Test status
Simulation time 105915630 ps
CPU time 1.07 seconds
Started Aug 15 04:50:13 PM PDT 24
Finished Aug 15 04:50:14 PM PDT 24
Peak memory 200568 kb
Host smart-36aec741-d1c7-4890-9171-93a9109b7601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665545268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3665545268
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1596184922
Short name T174
Test name
Test status
Simulation time 123442502 ps
CPU time 1.21 seconds
Started Aug 15 04:50:08 PM PDT 24
Finished Aug 15 04:50:09 PM PDT 24
Peak memory 200724 kb
Host smart-005c6d8a-bd03-4b17-8ed1-4edc33697a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596184922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1596184922
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.511587147
Short name T85
Test name
Test status
Simulation time 3418304311 ps
CPU time 15.7 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:26 PM PDT 24
Peak memory 210220 kb
Host smart-7c5cc955-ce90-41a1-a0bf-e2e47c33570e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511587147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.511587147
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3775625786
Short name T226
Test name
Test status
Simulation time 309951645 ps
CPU time 2.05 seconds
Started Aug 15 04:50:12 PM PDT 24
Finished Aug 15 04:50:14 PM PDT 24
Peak memory 208680 kb
Host smart-6da920ef-d67d-47eb-b1e4-d64c423afb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775625786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3775625786
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.630113470
Short name T456
Test name
Test status
Simulation time 120524206 ps
CPU time 0.99 seconds
Started Aug 15 04:50:09 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 200552 kb
Host smart-30285c5b-02e1-4473-8149-df08d92329f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630113470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.630113470
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3483637472
Short name T449
Test name
Test status
Simulation time 92286784 ps
CPU time 0.83 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200400 kb
Host smart-7155af46-287d-4675-ad96-e970bd2c6ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483637472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3483637472
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.933208994
Short name T520
Test name
Test status
Simulation time 1898005826 ps
CPU time 7.76 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:29 PM PDT 24
Peak memory 221804 kb
Host smart-89d55768-5d36-4fe3-91d4-f1b4831aa53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933208994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.933208994
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2076263808
Short name T364
Test name
Test status
Simulation time 244998733 ps
CPU time 1.22 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 217800 kb
Host smart-d4c5b3f6-6119-4ed3-bdc3-27f9be96ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076263808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2076263808
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1765163198
Short name T311
Test name
Test status
Simulation time 165413465 ps
CPU time 0.86 seconds
Started Aug 15 04:50:10 PM PDT 24
Finished Aug 15 04:50:11 PM PDT 24
Peak memory 200384 kb
Host smart-1ad0fab8-3c46-4f31-ac7f-18c1385c2944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765163198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1765163198
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.1572690783
Short name T159
Test name
Test status
Simulation time 1239210838 ps
CPU time 5.16 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:29 PM PDT 24
Peak memory 200720 kb
Host smart-cf099530-cf79-437e-bbb9-35dc4f3ef65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572690783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1572690783
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2410492149
Short name T39
Test name
Test status
Simulation time 112953807 ps
CPU time 1.05 seconds
Started Aug 15 04:50:19 PM PDT 24
Finished Aug 15 04:50:20 PM PDT 24
Peak memory 200560 kb
Host smart-5f9bcad0-db3d-4f8b-8836-66dfd2bbc413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410492149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2410492149
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2173550343
Short name T458
Test name
Test status
Simulation time 116775615 ps
CPU time 1.2 seconds
Started Aug 15 04:50:11 PM PDT 24
Finished Aug 15 04:50:13 PM PDT 24
Peak memory 200660 kb
Host smart-691a889c-8d94-436e-82b0-35196169f19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173550343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2173550343
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.4291058365
Short name T203
Test name
Test status
Simulation time 3553940159 ps
CPU time 13.91 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 208980 kb
Host smart-8140fcd4-27f5-4877-a31c-a9f3cb968289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291058365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4291058365
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3922384264
Short name T493
Test name
Test status
Simulation time 422865838 ps
CPU time 2.22 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 208664 kb
Host smart-626dabfa-88ce-4ba0-b73c-a3a76d3aff08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922384264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3922384264
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2318878294
Short name T127
Test name
Test status
Simulation time 131611394 ps
CPU time 1 seconds
Started Aug 15 04:50:25 PM PDT 24
Finished Aug 15 04:50:26 PM PDT 24
Peak memory 200532 kb
Host smart-d364cace-456f-4ea4-b84c-93f8f58b94fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318878294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2318878294
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2922828248
Short name T355
Test name
Test status
Simulation time 67998381 ps
CPU time 0.81 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200396 kb
Host smart-18458d33-21c8-4ef3-95d4-5271c2a8d06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922828248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2922828248
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2335761302
Short name T75
Test name
Test status
Simulation time 246238332 ps
CPU time 1.06 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:23 PM PDT 24
Peak memory 217780 kb
Host smart-13e60a3a-0efc-478d-b636-9f9ee3f617a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335761302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2335761302
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.3043653742
Short name T234
Test name
Test status
Simulation time 186069777 ps
CPU time 0.87 seconds
Started Aug 15 04:50:24 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 200412 kb
Host smart-77b4e348-c3fa-43d9-9c1d-ad4242698125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043653742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3043653742
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2228651654
Short name T153
Test name
Test status
Simulation time 694912013 ps
CPU time 3.8 seconds
Started Aug 15 04:50:18 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200744 kb
Host smart-4b07d5db-cecd-4830-b2d7-7524e10a15e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228651654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2228651654
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.523616508
Short name T272
Test name
Test status
Simulation time 109204213 ps
CPU time 1.03 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200472 kb
Host smart-62dfc40f-0ddb-4c56-8bee-82b4c048b5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523616508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.523616508
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.3241542879
Short name T328
Test name
Test status
Simulation time 201034223 ps
CPU time 1.52 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200640 kb
Host smart-7795ee81-a43d-4e96-b870-77c8be0b2e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241542879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3241542879
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.314211546
Short name T478
Test name
Test status
Simulation time 1420165058 ps
CPU time 5.99 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:27 PM PDT 24
Peak memory 200696 kb
Host smart-c8a4e26a-62f1-4376-af86-60f003618f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314211546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.314211546
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3460324541
Short name T332
Test name
Test status
Simulation time 116081621 ps
CPU time 1.59 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 200496 kb
Host smart-15c4791f-8870-4cdd-b182-0b65ce01adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460324541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3460324541
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1205276929
Short name T502
Test name
Test status
Simulation time 253358635 ps
CPU time 1.54 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200600 kb
Host smart-9965bbbf-7b68-4847-894b-4d07228799e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205276929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1205276929
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.1834420464
Short name T515
Test name
Test status
Simulation time 92329659 ps
CPU time 0.87 seconds
Started Aug 15 04:50:25 PM PDT 24
Finished Aug 15 04:50:26 PM PDT 24
Peak memory 200444 kb
Host smart-f932c275-e6c4-4d13-b10f-dec6ff9d8d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834420464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1834420464
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.964680341
Short name T34
Test name
Test status
Simulation time 1234498361 ps
CPU time 5.56 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:27 PM PDT 24
Peak memory 221820 kb
Host smart-4e720880-ea4b-42fd-a1e2-a8b8bea8e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964680341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.964680341
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3292757054
Short name T184
Test name
Test status
Simulation time 244498375 ps
CPU time 1.13 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 217720 kb
Host smart-1d89bfd9-c74c-4b2a-9649-36c7f5d41d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292757054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3292757054
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2308613116
Short name T403
Test name
Test status
Simulation time 154982854 ps
CPU time 0.85 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200412 kb
Host smart-250b6d8a-1e89-44b6-a349-713664bc10c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308613116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2308613116
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3562149995
Short name T198
Test name
Test status
Simulation time 1400243462 ps
CPU time 5.97 seconds
Started Aug 15 04:50:24 PM PDT 24
Finished Aug 15 04:50:30 PM PDT 24
Peak memory 200680 kb
Host smart-8c8caa99-032b-4b67-8296-73524a81c9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562149995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3562149995
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2875426364
Short name T331
Test name
Test status
Simulation time 104623913 ps
CPU time 1 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:21 PM PDT 24
Peak memory 200584 kb
Host smart-e46b1350-5db6-48eb-af80-2f2732a133c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875426364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2875426364
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1000280519
Short name T271
Test name
Test status
Simulation time 252527089 ps
CPU time 1.59 seconds
Started Aug 15 04:50:19 PM PDT 24
Finished Aug 15 04:50:21 PM PDT 24
Peak memory 200568 kb
Host smart-6b5b99ae-d2fc-4aaf-8e79-58103559e98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000280519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1000280519
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.4209443579
Short name T499
Test name
Test status
Simulation time 11727546115 ps
CPU time 47.77 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:51:11 PM PDT 24
Peak memory 200768 kb
Host smart-aa76200c-d67a-446a-b463-5772bb138ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209443579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.4209443579
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.2848604943
Short name T2
Test name
Test status
Simulation time 401252202 ps
CPU time 2.35 seconds
Started Aug 15 04:50:26 PM PDT 24
Finished Aug 15 04:50:28 PM PDT 24
Peak memory 200480 kb
Host smart-6eec96e7-2c41-4d2b-8273-c11e8aae3944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848604943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2848604943
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2207077147
Short name T489
Test name
Test status
Simulation time 136079943 ps
CPU time 1 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200580 kb
Host smart-54f334bf-6c10-4f04-9525-aac872704a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207077147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2207077147
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1471523788
Short name T252
Test name
Test status
Simulation time 94782341 ps
CPU time 0.86 seconds
Started Aug 15 04:50:19 PM PDT 24
Finished Aug 15 04:50:20 PM PDT 24
Peak memory 200320 kb
Host smart-b9aa0fbf-4b80-4203-b57a-1404bd26fecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471523788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1471523788
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3609136256
Short name T528
Test name
Test status
Simulation time 1221172669 ps
CPU time 5.62 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:27 PM PDT 24
Peak memory 217920 kb
Host smart-a1bb431a-99c5-4fc9-92f5-5c1e516ee1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609136256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3609136256
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2126469247
Short name T201
Test name
Test status
Simulation time 245206910 ps
CPU time 1.08 seconds
Started Aug 15 04:50:25 PM PDT 24
Finished Aug 15 04:50:26 PM PDT 24
Peak memory 217672 kb
Host smart-b5d54a90-deb9-4bb3-8b84-3d6898157573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126469247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2126469247
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3538910940
Short name T247
Test name
Test status
Simulation time 96822609 ps
CPU time 0.82 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:21 PM PDT 24
Peak memory 200368 kb
Host smart-ac383b0f-6f48-4319-8181-bf96106cdd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538910940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3538910940
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1926117223
Short name T263
Test name
Test status
Simulation time 2049666524 ps
CPU time 7.39 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:28 PM PDT 24
Peak memory 200640 kb
Host smart-4a072a5a-e1e7-4105-a7cb-fd2e7371032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926117223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1926117223
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.2586095056
Short name T276
Test name
Test status
Simulation time 153491653 ps
CPU time 1.14 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200576 kb
Host smart-d3dee574-5f4c-488a-966d-ae5b0dd3cbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586095056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.2586095056
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.177112244
Short name T380
Test name
Test status
Simulation time 126161939 ps
CPU time 1.24 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200756 kb
Host smart-063df75d-9016-4361-9b55-edff4d6f1ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177112244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.177112244
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.2626002061
Short name T310
Test name
Test status
Simulation time 7275540090 ps
CPU time 28.72 seconds
Started Aug 15 04:50:25 PM PDT 24
Finished Aug 15 04:50:53 PM PDT 24
Peak memory 208908 kb
Host smart-615c3d31-01e4-4b59-a19b-220991b8ec4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626002061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2626002061
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.4106526760
Short name T309
Test name
Test status
Simulation time 361825123 ps
CPU time 2.43 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 200436 kb
Host smart-3d077bce-9384-46a4-8ee2-4317f074135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106526760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.4106526760
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2803651866
Short name T375
Test name
Test status
Simulation time 183909175 ps
CPU time 1.19 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200556 kb
Host smart-0a8c0f32-8859-4c30-ab01-400a7bbc7caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803651866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2803651866
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1166831054
Short name T329
Test name
Test status
Simulation time 66114928 ps
CPU time 0.83 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:23 PM PDT 24
Peak memory 200448 kb
Host smart-386dc95c-0a7d-4e97-8110-7cf9ce8e2957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166831054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1166831054
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.72023083
Short name T373
Test name
Test status
Simulation time 1230833691 ps
CPU time 5.27 seconds
Started Aug 15 04:50:26 PM PDT 24
Finished Aug 15 04:50:31 PM PDT 24
Peak memory 216956 kb
Host smart-2d885003-1d53-4d5b-8880-9eb28e9edee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72023083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.72023083
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3424113162
Short name T485
Test name
Test status
Simulation time 244208748 ps
CPU time 1.09 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:21 PM PDT 24
Peak memory 217748 kb
Host smart-3c9e65f1-e774-4926-8d28-a5555120c6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424113162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3424113162
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3209042658
Short name T16
Test name
Test status
Simulation time 108442572 ps
CPU time 0.78 seconds
Started Aug 15 04:50:19 PM PDT 24
Finished Aug 15 04:50:20 PM PDT 24
Peak memory 200316 kb
Host smart-2feb139c-4b57-4483-9e52-002d99c9958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209042658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3209042658
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2453739438
Short name T94
Test name
Test status
Simulation time 922586446 ps
CPU time 4.5 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 200720 kb
Host smart-e0117fd7-872e-40ed-990a-b9c828072df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453739438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2453739438
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1307487808
Short name T491
Test name
Test status
Simulation time 172950992 ps
CPU time 1.32 seconds
Started Aug 15 04:50:24 PM PDT 24
Finished Aug 15 04:50:26 PM PDT 24
Peak memory 200420 kb
Host smart-aa15f182-4182-4769-b46e-34ccd791afd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307487808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1307487808
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.573319090
Short name T415
Test name
Test status
Simulation time 110953706 ps
CPU time 1.22 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200712 kb
Host smart-3608438c-7806-4b37-841f-097787db94e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573319090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.573319090
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1923813456
Short name T93
Test name
Test status
Simulation time 5660419323 ps
CPU time 20.94 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:44 PM PDT 24
Peak memory 200808 kb
Host smart-f7825a66-5b86-49b2-80e3-00ba88c1de89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923813456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1923813456
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2531087060
Short name T418
Test name
Test status
Simulation time 141409381 ps
CPU time 1.85 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200440 kb
Host smart-b61fee4c-240b-4b75-aa08-927e24a03da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531087060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2531087060
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.3916254432
Short name T160
Test name
Test status
Simulation time 106703366 ps
CPU time 1.04 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:21 PM PDT 24
Peak memory 200552 kb
Host smart-8da4dc5b-d964-46a4-be4c-e4c852a9974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916254432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3916254432
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.1122102766
Short name T248
Test name
Test status
Simulation time 72287516 ps
CPU time 0.78 seconds
Started Aug 15 04:50:24 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 200404 kb
Host smart-b424b1f4-adff-4b34-8f22-97e720bf0987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122102766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.1122102766
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1336332815
Short name T33
Test name
Test status
Simulation time 2159796352 ps
CPU time 7.86 seconds
Started Aug 15 04:50:25 PM PDT 24
Finished Aug 15 04:50:33 PM PDT 24
Peak memory 221996 kb
Host smart-b583dde6-8375-4b29-a0f9-f72957694a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336332815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1336332815
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2546489084
Short name T334
Test name
Test status
Simulation time 244664801 ps
CPU time 1.1 seconds
Started Aug 15 04:50:24 PM PDT 24
Finished Aug 15 04:50:26 PM PDT 24
Peak memory 217688 kb
Host smart-a3805b07-274b-488d-882d-3e58a46cb4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546489084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2546489084
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.549009187
Short name T13
Test name
Test status
Simulation time 245531316 ps
CPU time 1.02 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200372 kb
Host smart-3e382aaf-eb10-4a5e-bda8-56f14b5f3ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549009187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.549009187
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.394980726
Short name T267
Test name
Test status
Simulation time 1632343638 ps
CPU time 5.92 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:28 PM PDT 24
Peak memory 200740 kb
Host smart-05bbb1f6-a5e0-465a-b2f8-a62bfb24a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394980726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.394980726
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2563059828
Short name T141
Test name
Test status
Simulation time 175898783 ps
CPU time 1.28 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:23 PM PDT 24
Peak memory 200420 kb
Host smart-fe43c1c3-2700-49cc-9174-1998eec36dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563059828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2563059828
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.3866622432
Short name T190
Test name
Test status
Simulation time 261650117 ps
CPU time 1.63 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200712 kb
Host smart-2fa04268-b866-4d0f-9e0b-f117d9314c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866622432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3866622432
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.3510863905
Short name T420
Test name
Test status
Simulation time 444408017 ps
CPU time 2.36 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:23 PM PDT 24
Peak memory 200448 kb
Host smart-e7526a51-de7c-4867-8259-a47c4c1f68af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510863905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3510863905
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2376276237
Short name T452
Test name
Test status
Simulation time 216788505 ps
CPU time 1.41 seconds
Started Aug 15 04:50:20 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200572 kb
Host smart-c66732c7-891f-41c5-8a94-64c678771b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376276237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2376276237
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3639036968
Short name T363
Test name
Test status
Simulation time 70789388 ps
CPU time 0.85 seconds
Started Aug 15 04:50:32 PM PDT 24
Finished Aug 15 04:50:33 PM PDT 24
Peak memory 200468 kb
Host smart-c5ba82a1-a8ce-4709-aee6-cc2d7b4014ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639036968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3639036968
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.893146169
Short name T314
Test name
Test status
Simulation time 1226955645 ps
CPU time 6.12 seconds
Started Aug 15 04:50:22 PM PDT 24
Finished Aug 15 04:50:28 PM PDT 24
Peak memory 217908 kb
Host smart-c419190e-7268-4868-8580-563d46955b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893146169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.893146169
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3285023568
Short name T40
Test name
Test status
Simulation time 243073032 ps
CPU time 1.21 seconds
Started Aug 15 04:50:24 PM PDT 24
Finished Aug 15 04:50:26 PM PDT 24
Peak memory 217744 kb
Host smart-1ce86faa-a0a1-4081-99bf-5c0517e68b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285023568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3285023568
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.4240985219
Short name T525
Test name
Test status
Simulation time 183240678 ps
CPU time 0.9 seconds
Started Aug 15 04:50:24 PM PDT 24
Finished Aug 15 04:50:25 PM PDT 24
Peak memory 200408 kb
Host smart-1c477616-e750-4fd1-b22d-80a9fae808da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240985219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.4240985219
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.372154455
Short name T179
Test name
Test status
Simulation time 1410583413 ps
CPU time 5.49 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:27 PM PDT 24
Peak memory 200772 kb
Host smart-518d217e-753c-4cdd-a3a1-c409d1312e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372154455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.372154455
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.157625299
Short name T448
Test name
Test status
Simulation time 188734754 ps
CPU time 1.2 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200528 kb
Host smart-2618b4b5-0411-4d16-a674-599096342938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157625299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.157625299
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.481201848
Short name T472
Test name
Test status
Simulation time 114359677 ps
CPU time 1.15 seconds
Started Aug 15 04:50:23 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200692 kb
Host smart-cee484e7-d1c8-497a-9d62-9c0e7fb6e906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481201848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.481201848
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.697868926
Short name T371
Test name
Test status
Simulation time 6309615533 ps
CPU time 23.7 seconds
Started Aug 15 04:50:28 PM PDT 24
Finished Aug 15 04:50:52 PM PDT 24
Peak memory 208964 kb
Host smart-c83a753f-f324-4c3b-bc88-41ac7722f902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697868926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.697868926
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3652966213
Short name T264
Test name
Test status
Simulation time 377234242 ps
CPU time 2.54 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:24 PM PDT 24
Peak memory 200472 kb
Host smart-23b50507-7d70-45bc-b297-b6028d8d1740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652966213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3652966213
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.308290545
Short name T164
Test name
Test status
Simulation time 66355073 ps
CPU time 0.83 seconds
Started Aug 15 04:50:21 PM PDT 24
Finished Aug 15 04:50:22 PM PDT 24
Peak memory 200576 kb
Host smart-90d0bd4e-d9b0-45db-b05c-46086a724bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308290545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.308290545
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.2534000303
Short name T302
Test name
Test status
Simulation time 74540406 ps
CPU time 0.82 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 200436 kb
Host smart-5cd4e65b-1358-442c-8cda-87a795f0c510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534000303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2534000303
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.710403544
Short name T285
Test name
Test status
Simulation time 2354385748 ps
CPU time 9.2 seconds
Started Aug 15 04:50:28 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 221964 kb
Host smart-eaa40039-d23b-4868-a3f8-9e1a505d6c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710403544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.710403544
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2510860888
Short name T519
Test name
Test status
Simulation time 244038400 ps
CPU time 1.16 seconds
Started Aug 15 04:50:28 PM PDT 24
Finished Aug 15 04:50:30 PM PDT 24
Peak memory 217628 kb
Host smart-7598175f-e431-402e-b4b8-9c3b4c41447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510860888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2510860888
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1433655315
Short name T406
Test name
Test status
Simulation time 140996302 ps
CPU time 0.88 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 200388 kb
Host smart-8429b4b4-d33a-4406-ba82-8e4f78ea97b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433655315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1433655315
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.2483926488
Short name T294
Test name
Test status
Simulation time 1182708528 ps
CPU time 5.42 seconds
Started Aug 15 04:50:34 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200712 kb
Host smart-42e34f98-4f98-4e71-87d2-9a83a8ed6e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483926488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2483926488
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2955202750
Short name T206
Test name
Test status
Simulation time 159191781 ps
CPU time 1.11 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 04:50:34 PM PDT 24
Peak memory 200552 kb
Host smart-60ac8cd4-75b6-4db2-915b-2ba071984ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955202750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2955202750
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.833202794
Short name T460
Test name
Test status
Simulation time 118951927 ps
CPU time 1.23 seconds
Started Aug 15 04:50:30 PM PDT 24
Finished Aug 15 04:50:31 PM PDT 24
Peak memory 200688 kb
Host smart-cca55579-4104-47ed-9e4a-c12d608fbd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833202794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.833202794
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3530967588
Short name T100
Test name
Test status
Simulation time 4808451203 ps
CPU time 18.65 seconds
Started Aug 15 04:50:32 PM PDT 24
Finished Aug 15 04:50:51 PM PDT 24
Peak memory 208992 kb
Host smart-485583fa-94b7-493f-a909-4a16ce0e9af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530967588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3530967588
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.1400401901
Short name T230
Test name
Test status
Simulation time 360241327 ps
CPU time 2.06 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 200468 kb
Host smart-65fb6ae0-d264-433f-b591-e3ce0b47c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400401901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1400401901
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.812548538
Short name T136
Test name
Test status
Simulation time 221824793 ps
CPU time 1.34 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 04:50:34 PM PDT 24
Peak memory 200564 kb
Host smart-c49414d5-7d27-406c-bcce-b46384247267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812548538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.812548538
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2308380092
Short name T193
Test name
Test status
Simulation time 83150911 ps
CPU time 0.83 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200308 kb
Host smart-1c84239a-dc38-457d-8f8a-8c54c076d527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308380092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2308380092
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.4001130307
Short name T440
Test name
Test status
Simulation time 1225754841 ps
CPU time 5.48 seconds
Started Aug 15 04:49:08 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 221820 kb
Host smart-3d969744-15af-4efe-a259-0517ed440af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001130307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4001130307
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.825901935
Short name T399
Test name
Test status
Simulation time 244656652 ps
CPU time 1.14 seconds
Started Aug 15 04:49:05 PM PDT 24
Finished Aug 15 04:49:06 PM PDT 24
Peak memory 217716 kb
Host smart-44bc96cd-8c09-408c-bdbd-e8773220c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825901935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.825901935
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.121276227
Short name T241
Test name
Test status
Simulation time 217792351 ps
CPU time 0.93 seconds
Started Aug 15 04:49:08 PM PDT 24
Finished Aug 15 04:49:09 PM PDT 24
Peak memory 200376 kb
Host smart-44d918af-dc69-4f15-8d03-807c09d5390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121276227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.121276227
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1313314914
Short name T124
Test name
Test status
Simulation time 1877372173 ps
CPU time 6.88 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:10 PM PDT 24
Peak memory 200620 kb
Host smart-c8101f12-e994-4e38-b243-b4af746abc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313314914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1313314914
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.915095064
Short name T383
Test name
Test status
Simulation time 116025117 ps
CPU time 1.06 seconds
Started Aug 15 04:49:03 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 200532 kb
Host smart-2dbb3ff3-e79d-4848-a910-56cc18cd5ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915095064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.915095064
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.2850429784
Short name T260
Test name
Test status
Simulation time 196073580 ps
CPU time 1.34 seconds
Started Aug 15 04:49:05 PM PDT 24
Finished Aug 15 04:49:06 PM PDT 24
Peak memory 199288 kb
Host smart-1ae0e675-5e1c-4e0e-bf67-f8fd73ddaf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850429784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2850429784
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1673498077
Short name T445
Test name
Test status
Simulation time 7078721367 ps
CPU time 27.14 seconds
Started Aug 15 04:49:05 PM PDT 24
Finished Aug 15 04:49:33 PM PDT 24
Peak memory 200788 kb
Host smart-e17e1bae-eeed-41e6-868b-e77a308bbcc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673498077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1673498077
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2652652870
Short name T431
Test name
Test status
Simulation time 139233247 ps
CPU time 1.82 seconds
Started Aug 15 04:49:09 PM PDT 24
Finished Aug 15 04:49:11 PM PDT 24
Peak memory 208560 kb
Host smart-02262962-93df-4a36-ba67-72261a5bba3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652652870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2652652870
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2398869878
Short name T503
Test name
Test status
Simulation time 66290720 ps
CPU time 0.79 seconds
Started Aug 15 04:49:04 PM PDT 24
Finished Aug 15 04:49:05 PM PDT 24
Peak memory 200560 kb
Host smart-3a8e9906-cac1-4200-b58a-822c68169935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398869878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2398869878
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1001965621
Short name T175
Test name
Test status
Simulation time 69197162 ps
CPU time 0.88 seconds
Started Aug 15 04:49:14 PM PDT 24
Finished Aug 15 04:49:15 PM PDT 24
Peak memory 200348 kb
Host smart-20c7a93f-9f60-47cb-bdf5-ea5b8ee7aa0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001965621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1001965621
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.239028787
Short name T45
Test name
Test status
Simulation time 2160298921 ps
CPU time 8.37 seconds
Started Aug 15 04:49:14 PM PDT 24
Finished Aug 15 04:49:22 PM PDT 24
Peak memory 217996 kb
Host smart-5ff179a4-d9b3-4a98-aff5-91f8a4c0e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239028787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.239028787
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.690988072
Short name T165
Test name
Test status
Simulation time 243872915 ps
CPU time 1.09 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 217624 kb
Host smart-8f7a945b-e759-4045-9bb6-e7d60ba4eaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690988072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.690988072
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.581776887
Short name T312
Test name
Test status
Simulation time 182374964 ps
CPU time 0.86 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 200404 kb
Host smart-c576c3eb-b42d-4ba0-aba1-535f76b827dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581776887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.581776887
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.720723997
Short name T70
Test name
Test status
Simulation time 1780678425 ps
CPU time 6.63 seconds
Started Aug 15 04:49:18 PM PDT 24
Finished Aug 15 04:49:24 PM PDT 24
Peak memory 200736 kb
Host smart-cf42607c-1fcd-4be3-b3c8-2f0de14a785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720723997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.720723997
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1772802691
Short name T487
Test name
Test status
Simulation time 103036891 ps
CPU time 1.05 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200548 kb
Host smart-19250532-1163-4613-8817-ba66bb0740eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772802691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1772802691
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1888456050
Short name T467
Test name
Test status
Simulation time 198487202 ps
CPU time 1.41 seconds
Started Aug 15 04:49:11 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200624 kb
Host smart-f9d66825-57da-4ead-b011-530943b10714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888456050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1888456050
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1038599594
Short name T410
Test name
Test status
Simulation time 2189917364 ps
CPU time 7.49 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:20 PM PDT 24
Peak memory 200868 kb
Host smart-ccc4308c-9341-4d42-8a24-0b14516095d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038599594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1038599594
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.304116199
Short name T189
Test name
Test status
Simulation time 326115702 ps
CPU time 2.08 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:17 PM PDT 24
Peak memory 200500 kb
Host smart-c1576f91-a022-4f45-a214-48ff2c442c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304116199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.304116199
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2505326779
Short name T145
Test name
Test status
Simulation time 98702183 ps
CPU time 0.94 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200528 kb
Host smart-115bab56-4c08-4f57-b26f-5aca10fecdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505326779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2505326779
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.722949227
Short name T345
Test name
Test status
Simulation time 65523396 ps
CPU time 0.74 seconds
Started Aug 15 04:49:18 PM PDT 24
Finished Aug 15 04:49:18 PM PDT 24
Peak memory 200424 kb
Host smart-753d571c-58e1-429f-ba36-0fc6fe7b80d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722949227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.722949227
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2827965153
Short name T343
Test name
Test status
Simulation time 1227614660 ps
CPU time 5.65 seconds
Started Aug 15 04:49:11 PM PDT 24
Finished Aug 15 04:49:17 PM PDT 24
Peak memory 217680 kb
Host smart-73c736ff-93e4-4b2c-956a-d5044b774f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827965153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2827965153
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3470910031
Short name T214
Test name
Test status
Simulation time 243329742 ps
CPU time 1.15 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 217732 kb
Host smart-0c5c5bd9-ec24-4dcd-a4f1-829790d81f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470910031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3470910031
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1014223743
Short name T218
Test name
Test status
Simulation time 116777028 ps
CPU time 0.8 seconds
Started Aug 15 04:49:14 PM PDT 24
Finished Aug 15 04:49:15 PM PDT 24
Peak memory 200332 kb
Host smart-00935693-f96b-4b21-a6cd-fdcaae3a2842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014223743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1014223743
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1363754792
Short name T335
Test name
Test status
Simulation time 832754039 ps
CPU time 4.04 seconds
Started Aug 15 04:49:14 PM PDT 24
Finished Aug 15 04:49:18 PM PDT 24
Peak memory 200692 kb
Host smart-d44c626c-9a43-40c7-b2c8-226b66856be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363754792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1363754792
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3126146025
Short name T3
Test name
Test status
Simulation time 108072049 ps
CPU time 1.03 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 200472 kb
Host smart-965a6cf4-1853-43a5-a3e3-01427e5770c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126146025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3126146025
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.631768984
Short name T144
Test name
Test status
Simulation time 126406704 ps
CPU time 1.21 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200656 kb
Host smart-87d52449-889e-4f0b-92de-a27f700db78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631768984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.631768984
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.430645703
Short name T196
Test name
Test status
Simulation time 3716763729 ps
CPU time 16.3 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:32 PM PDT 24
Peak memory 209004 kb
Host smart-47522004-cb41-49fd-b7de-6ba78e8c2c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430645703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.430645703
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1270068168
Short name T537
Test name
Test status
Simulation time 276026921 ps
CPU time 1.92 seconds
Started Aug 15 04:49:13 PM PDT 24
Finished Aug 15 04:49:15 PM PDT 24
Peak memory 200368 kb
Host smart-d633c6ab-b9e4-4fee-b7b1-5fa87f8811a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270068168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1270068168
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.425206844
Short name T135
Test name
Test status
Simulation time 124332506 ps
CPU time 1.1 seconds
Started Aug 15 04:49:11 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200584 kb
Host smart-26416970-e9e9-44de-9907-08ef474e67f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425206844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.425206844
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1117997849
Short name T398
Test name
Test status
Simulation time 82947704 ps
CPU time 0.78 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200368 kb
Host smart-19ee510f-8c9f-49fc-9dba-2ce27fcbe6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117997849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1117997849
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2406234933
Short name T228
Test name
Test status
Simulation time 1220957658 ps
CPU time 5.69 seconds
Started Aug 15 04:49:10 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 221784 kb
Host smart-9e8651d8-1e8a-44a8-8c04-6024a41af96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406234933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2406234933
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3086058907
Short name T443
Test name
Test status
Simulation time 243981611 ps
CPU time 1.11 seconds
Started Aug 15 04:49:18 PM PDT 24
Finished Aug 15 04:49:19 PM PDT 24
Peak memory 217716 kb
Host smart-a0db2adf-850d-4b46-87f8-329eb0359cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086058907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3086058907
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.330944917
Short name T382
Test name
Test status
Simulation time 91906267 ps
CPU time 0.78 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 200404 kb
Host smart-c7541fa7-9354-46e2-9f91-e9a59d29aeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330944917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.330944917
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.1515354635
Short name T8
Test name
Test status
Simulation time 782159778 ps
CPU time 4.12 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 200620 kb
Host smart-458bf6de-b70b-4c92-a9e0-026ee191238c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515354635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1515354635
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.40281865
Short name T277
Test name
Test status
Simulation time 154578901 ps
CPU time 1.09 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 200564 kb
Host smart-b9577bfa-04cc-4dcd-b3b9-8e69b1fad7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40281865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.40281865
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.895468945
Short name T238
Test name
Test status
Simulation time 206947986 ps
CPU time 1.38 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200684 kb
Host smart-c90be0f1-04ab-44a6-b3ba-54cca6005fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895468945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.895468945
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.90682887
Short name T137
Test name
Test status
Simulation time 795994886 ps
CPU time 4.28 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:20 PM PDT 24
Peak memory 200564 kb
Host smart-2485f631-3baf-4494-89f3-4e85c27fba7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90682887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.90682887
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.939481817
Short name T244
Test name
Test status
Simulation time 345075162 ps
CPU time 1.87 seconds
Started Aug 15 04:49:11 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200408 kb
Host smart-934e23dc-9dc4-4fb0-a45e-db1abe5f3663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939481817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.939481817
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.1993137572
Short name T492
Test name
Test status
Simulation time 286064768 ps
CPU time 1.51 seconds
Started Aug 15 04:49:16 PM PDT 24
Finished Aug 15 04:49:17 PM PDT 24
Peak memory 200496 kb
Host smart-c601b6f5-73f3-4f37-bb51-ec5b4ac2c0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993137572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1993137572
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3323714810
Short name T447
Test name
Test status
Simulation time 80483319 ps
CPU time 0.84 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200416 kb
Host smart-d049ec96-cc5d-479c-85c7-d125033cbb6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323714810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3323714810
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2759293860
Short name T357
Test name
Test status
Simulation time 2150842701 ps
CPU time 7.93 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:23 PM PDT 24
Peak memory 218048 kb
Host smart-9dc9e463-335f-474b-9dc3-ea79d527d482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759293860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2759293860
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2068804158
Short name T476
Test name
Test status
Simulation time 245286971 ps
CPU time 1.03 seconds
Started Aug 15 04:49:13 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 218640 kb
Host smart-9ef03ffa-e42e-41de-8e3f-0b00b5f43715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068804158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2068804158
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3525891487
Short name T413
Test name
Test status
Simulation time 161981341 ps
CPU time 0.84 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:13 PM PDT 24
Peak memory 200248 kb
Host smart-1dcfb3a0-4b7e-4f68-8aee-f09cde52cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525891487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3525891487
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.748493201
Short name T229
Test name
Test status
Simulation time 1364494274 ps
CPU time 5.22 seconds
Started Aug 15 04:49:15 PM PDT 24
Finished Aug 15 04:49:21 PM PDT 24
Peak memory 200732 kb
Host smart-329a86dd-b4d9-49a3-b282-1953d80ab841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748493201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.748493201
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2991145736
Short name T292
Test name
Test status
Simulation time 145609502 ps
CPU time 1.23 seconds
Started Aug 15 04:49:14 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 200560 kb
Host smart-48e84589-0814-4059-9bf7-665dc022b37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991145736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2991145736
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.3912205146
Short name T482
Test name
Test status
Simulation time 124152320 ps
CPU time 1.23 seconds
Started Aug 15 04:49:14 PM PDT 24
Finished Aug 15 04:49:16 PM PDT 24
Peak memory 200696 kb
Host smart-7193ab95-783b-481f-afc9-0aadcd3751ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912205146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3912205146
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1754947401
Short name T518
Test name
Test status
Simulation time 13376089273 ps
CPU time 45.47 seconds
Started Aug 15 04:49:12 PM PDT 24
Finished Aug 15 04:49:58 PM PDT 24
Peak memory 209040 kb
Host smart-c6a0aa02-7fc4-4076-b603-3253ed07e0d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754947401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1754947401
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3838106843
Short name T25
Test name
Test status
Simulation time 123982150 ps
CPU time 1.55 seconds
Started Aug 15 04:49:14 PM PDT 24
Finished Aug 15 04:49:15 PM PDT 24
Peak memory 200456 kb
Host smart-f7c65b6c-2875-4f33-9efd-00122e83c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838106843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3838106843
Directory /workspace/9.rstmgr_sw_rst/latest
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