Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8674

1

T1

6

T2

4

T6

136

auto[1]

11577

1

T1

1

T2

1

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6094	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6922	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3186	1			T4	1		T6	39		T7	1
reset_info_cp[4]	4092	1			T4	1		T6	62		T7	1
reset_info_cp[8]	115	1			T13	1		T25	1		T26	1
reset_info_cp[16]	110	1			T6	2		T25	1		T40	4
reset_info_cp[32]	112	1			T1	1		T6	2		T9	1
reset_info_cp[64]	120	1			T2	1		T6	2		T13	2
reset_info_cp[128]	120	1			T2	1		T6	2		T24	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3385	1			T6	53		T8	10		T13	18
reset_info_cp[1]	auto[1]	2917	1			T4	1		T6	42		T7	1
reset_info_cp[2]	auto[0]	1017	1			T6	14		T8	2		T25	16
reset_info_cp[2]	auto[1]	2169	1			T4	1		T6	25		T7	1
reset_info_cp[4]	auto[0]	1458	1			T6	32		T8	7		T25	29
reset_info_cp[4]	auto[1]	2634	1			T4	1		T6	30		T7	1
reset_info_cp[8]	auto[0]	44	1			T25	1		T26	1		T132	1
reset_info_cp[8]	auto[1]	71	1			T13	1		T39	2		T30	1
reset_info_cp[16]	auto[0]	42	1			T6	1		T40	2		T59	1
reset_info_cp[16]	auto[1]	68	1			T6	1		T25	1		T40	2
reset_info_cp[32]	auto[0]	55	1			T1	1		T6	1		T40	1
reset_info_cp[32]	auto[1]	57	1			T6	1		T9	1		T38	1
reset_info_cp[64]	auto[0]	44	1			T2	1		T82	1		T134	1
reset_info_cp[64]	auto[1]	76	1			T6	2		T13	2		T39	3
reset_info_cp[128]	auto[0]	51	1			T6	1		T24	1		T25	2
reset_info_cp[128]	auto[1]	69	1			T2	1		T6	1		T38	1