Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T538 /workspace/coverage/default/43.rstmgr_sw_rst.2679954677 Aug 16 04:52:40 PM PDT 24 Aug 16 04:52:42 PM PDT 24 132903158 ps
T539 /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.499633790 Aug 16 04:51:47 PM PDT 24 Aug 16 04:51:49 PM PDT 24 105165659 ps
T540 /workspace/coverage/default/6.rstmgr_smoke.1490638671 Aug 16 04:51:31 PM PDT 24 Aug 16 04:51:33 PM PDT 24 198490394 ps
T541 /workspace/coverage/default/25.rstmgr_stress_all.1941463428 Aug 16 04:52:01 PM PDT 24 Aug 16 04:52:44 PM PDT 24 11786087527 ps
T542 /workspace/coverage/default/10.rstmgr_stress_all.550536045 Aug 16 04:51:38 PM PDT 24 Aug 16 04:52:01 PM PDT 24 6300916261 ps
T61 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2509814119 Aug 16 04:51:12 PM PDT 24 Aug 16 04:51:13 PM PDT 24 66323739 ps
T62 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3266591370 Aug 16 04:51:01 PM PDT 24 Aug 16 04:51:05 PM PDT 24 765282757 ps
T63 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.489874058 Aug 16 04:51:12 PM PDT 24 Aug 16 04:51:15 PM PDT 24 924039571 ps
T64 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.841549688 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:11 PM PDT 24 109915230 ps
T100 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1378618899 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:12 PM PDT 24 243533198 ps
T65 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1677028136 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:12 PM PDT 24 938250395 ps
T101 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4276668223 Aug 16 04:50:59 PM PDT 24 Aug 16 04:51:00 PM PDT 24 148581064 ps
T543 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2147085385 Aug 16 04:51:04 PM PDT 24 Aug 16 04:51:05 PM PDT 24 137897275 ps
T66 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.155692482 Aug 16 04:51:20 PM PDT 24 Aug 16 04:51:22 PM PDT 24 115329030 ps
T67 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1270632357 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:13 PM PDT 24 174525093 ps
T68 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.732607805 Aug 16 04:51:15 PM PDT 24 Aug 16 04:51:17 PM PDT 24 107414315 ps
T102 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1056250249 Aug 16 04:51:11 PM PDT 24 Aug 16 04:51:12 PM PDT 24 60073025 ps
T85 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3410760896 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:17 PM PDT 24 116743526 ps
T86 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1274325927 Aug 16 04:51:06 PM PDT 24 Aug 16 04:51:08 PM PDT 24 162535808 ps
T544 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1363123452 Aug 16 04:51:00 PM PDT 24 Aug 16 04:51:03 PM PDT 24 275859805 ps
T87 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3239229977 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:05 PM PDT 24 294317689 ps
T88 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1042681850 Aug 16 04:51:12 PM PDT 24 Aug 16 04:51:14 PM PDT 24 133619510 ps
T545 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2895035503 Aug 16 04:51:01 PM PDT 24 Aug 16 04:51:02 PM PDT 24 113860596 ps
T103 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.775672964 Aug 16 04:51:06 PM PDT 24 Aug 16 04:51:07 PM PDT 24 111414646 ps
T104 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3610736789 Aug 16 04:51:18 PM PDT 24 Aug 16 04:51:19 PM PDT 24 99656307 ps
T89 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2223309615 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:11 PM PDT 24 326906946 ps
T90 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2262551501 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:10 PM PDT 24 190788318 ps
T105 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1213164382 Aug 16 04:51:01 PM PDT 24 Aug 16 04:51:02 PM PDT 24 79907538 ps
T546 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2055747652 Aug 16 04:51:11 PM PDT 24 Aug 16 04:51:12 PM PDT 24 119784162 ps
T106 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1824446109 Aug 16 04:51:20 PM PDT 24 Aug 16 04:51:21 PM PDT 24 68233051 ps
T547 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.620585483 Aug 16 04:51:18 PM PDT 24 Aug 16 04:51:21 PM PDT 24 181498107 ps
T117 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.377568976 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:20 PM PDT 24 367376185 ps
T114 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1435638277 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:18 PM PDT 24 497741998 ps
T548 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2469848972 Aug 16 04:51:01 PM PDT 24 Aug 16 04:51:11 PM PDT 24 2279167422 ps
T118 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3742745125 Aug 16 04:51:07 PM PDT 24 Aug 16 04:51:08 PM PDT 24 125066612 ps
T107 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3775866658 Aug 16 04:51:03 PM PDT 24 Aug 16 04:51:05 PM PDT 24 206621798 ps
T108 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2471390812 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:17 PM PDT 24 129906161 ps
T109 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1639959223 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:09 PM PDT 24 215943777 ps
T549 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1334334458 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:10 PM PDT 24 68281384 ps
T550 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1059295046 Aug 16 04:51:01 PM PDT 24 Aug 16 04:51:03 PM PDT 24 135828028 ps
T551 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2788172782 Aug 16 04:51:01 PM PDT 24 Aug 16 04:51:03 PM PDT 24 165202639 ps
T552 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3270246467 Aug 16 04:51:12 PM PDT 24 Aug 16 04:51:14 PM PDT 24 183624702 ps
T553 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3401652571 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:09 PM PDT 24 66815297 ps
T554 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.68844472 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:12 PM PDT 24 142938715 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2913390884 Aug 16 04:50:59 PM PDT 24 Aug 16 04:51:00 PM PDT 24 58188316 ps
T115 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1208684643 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:11 PM PDT 24 502446109 ps
T556 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.973001485 Aug 16 04:51:22 PM PDT 24 Aug 16 04:51:24 PM PDT 24 131659636 ps
T557 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1222353333 Aug 16 04:51:00 PM PDT 24 Aug 16 04:51:02 PM PDT 24 213955720 ps
T558 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1716148880 Aug 16 04:51:00 PM PDT 24 Aug 16 04:51:01 PM PDT 24 95288461 ps
T129 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3163532347 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:12 PM PDT 24 471910197 ps
T559 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1975157122 Aug 16 04:51:17 PM PDT 24 Aug 16 04:51:18 PM PDT 24 90237093 ps
T560 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3570047317 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:10 PM PDT 24 182075566 ps
T561 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4133925684 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:10 PM PDT 24 499615627 ps
T562 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3194590899 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:06 PM PDT 24 773780228 ps
T563 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.850859249 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:17 PM PDT 24 60737058 ps
T564 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.7194699 Aug 16 04:51:04 PM PDT 24 Aug 16 04:51:05 PM PDT 24 62452738 ps
T565 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1428220989 Aug 16 04:51:07 PM PDT 24 Aug 16 04:51:10 PM PDT 24 351153375 ps
T566 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.48649363 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:13 PM PDT 24 910462991 ps
T112 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2759618304 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:18 PM PDT 24 529202614 ps
T567 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.805691660 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:11 PM PDT 24 78072248 ps
T568 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3370960545 Aug 16 04:51:17 PM PDT 24 Aug 16 04:51:21 PM PDT 24 397873581 ps
T569 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.204166783 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:10 PM PDT 24 130737738 ps
T570 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.193108111 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:12 PM PDT 24 537025808 ps
T571 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2659471546 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:04 PM PDT 24 203404356 ps
T572 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2758732391 Aug 16 04:50:59 PM PDT 24 Aug 16 04:51:00 PM PDT 24 80166319 ps
T573 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2421462893 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:18 PM PDT 24 59111546 ps
T574 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1485304600 Aug 16 04:51:07 PM PDT 24 Aug 16 04:51:08 PM PDT 24 98992507 ps
T575 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2360479008 Aug 16 04:51:15 PM PDT 24 Aug 16 04:51:19 PM PDT 24 506570591 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1077177904 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:03 PM PDT 24 127072001 ps
T577 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1079214700 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:18 PM PDT 24 89497260 ps
T578 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4176658904 Aug 16 04:51:07 PM PDT 24 Aug 16 04:51:09 PM PDT 24 123241119 ps
T579 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.435640765 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:13 PM PDT 24 939208744 ps
T580 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.542422485 Aug 16 04:51:11 PM PDT 24 Aug 16 04:51:11 PM PDT 24 54573594 ps
T110 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1790449306 Aug 16 04:51:04 PM PDT 24 Aug 16 04:51:06 PM PDT 24 449983316 ps
T581 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.106386705 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:12 PM PDT 24 321334089 ps
T582 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.647314140 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:03 PM PDT 24 105787304 ps
T583 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1685144437 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:19 PM PDT 24 457070695 ps
T584 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.85346330 Aug 16 04:51:12 PM PDT 24 Aug 16 04:51:13 PM PDT 24 72021520 ps
T585 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2759571711 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:12 PM PDT 24 123032945 ps
T586 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2318882496 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:11 PM PDT 24 96036665 ps
T127 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4217251320 Aug 16 04:51:06 PM PDT 24 Aug 16 04:51:09 PM PDT 24 889030817 ps
T587 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1723881874 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:10 PM PDT 24 130540936 ps
T588 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4206088989 Aug 16 04:51:12 PM PDT 24 Aug 16 04:51:13 PM PDT 24 72789071 ps
T589 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3940766331 Aug 16 04:51:15 PM PDT 24 Aug 16 04:51:17 PM PDT 24 143397800 ps
T590 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4279588845 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:10 PM PDT 24 113782399 ps
T591 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3110071399 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:05 PM PDT 24 198027454 ps
T93 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.651807143 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:09 PM PDT 24 58498113 ps
T592 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2450963039 Aug 16 04:51:18 PM PDT 24 Aug 16 04:51:20 PM PDT 24 197067478 ps
T593 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1264191957 Aug 16 04:51:07 PM PDT 24 Aug 16 04:51:10 PM PDT 24 320707528 ps
T594 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.816512225 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:10 PM PDT 24 73166158 ps
T595 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1351452339 Aug 16 04:51:10 PM PDT 24 Aug 16 04:51:11 PM PDT 24 123664067 ps
T596 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3124557703 Aug 16 04:51:00 PM PDT 24 Aug 16 04:51:04 PM PDT 24 396830078 ps
T128 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.105174336 Aug 16 04:51:03 PM PDT 24 Aug 16 04:51:07 PM PDT 24 886499072 ps
T597 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2140234596 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:10 PM PDT 24 487737480 ps
T598 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.414589853 Aug 16 04:51:00 PM PDT 24 Aug 16 04:51:01 PM PDT 24 99361266 ps
T599 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1955484799 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:07 PM PDT 24 795959381 ps
T600 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2010005129 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:03 PM PDT 24 124241126 ps
T601 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2972070421 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:10 PM PDT 24 214240420 ps
T602 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3922659922 Aug 16 04:51:12 PM PDT 24 Aug 16 04:51:13 PM PDT 24 203571428 ps
T603 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.799801091 Aug 16 04:51:06 PM PDT 24 Aug 16 04:51:07 PM PDT 24 180076711 ps
T116 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1966084231 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:20 PM PDT 24 886742062 ps
T604 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.732293809 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:07 PM PDT 24 1030588012 ps
T605 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3850048170 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:17 PM PDT 24 72203912 ps
T606 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2578324406 Aug 16 04:51:14 PM PDT 24 Aug 16 04:51:17 PM PDT 24 923992458 ps
T607 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2029788130 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:09 PM PDT 24 99866940 ps
T608 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.442762252 Aug 16 04:51:08 PM PDT 24 Aug 16 04:51:09 PM PDT 24 195870744 ps
T609 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1386687057 Aug 16 04:51:16 PM PDT 24 Aug 16 04:51:18 PM PDT 24 159870905 ps
T610 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.482925963 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:03 PM PDT 24 105066385 ps
T611 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2123429862 Aug 16 04:51:17 PM PDT 24 Aug 16 04:51:18 PM PDT 24 134866563 ps
T612 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.866855297 Aug 16 04:51:04 PM PDT 24 Aug 16 04:51:06 PM PDT 24 207782531 ps
T111 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2173913711 Aug 16 04:51:17 PM PDT 24 Aug 16 04:51:19 PM PDT 24 476708050 ps
T613 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3282865921 Aug 16 04:50:59 PM PDT 24 Aug 16 04:51:00 PM PDT 24 65772582 ps
T614 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2519210205 Aug 16 04:51:00 PM PDT 24 Aug 16 04:51:02 PM PDT 24 107737664 ps
T615 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.360620660 Aug 16 04:51:15 PM PDT 24 Aug 16 04:51:16 PM PDT 24 85900628 ps
T616 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3390258019 Aug 16 04:51:18 PM PDT 24 Aug 16 04:51:20 PM PDT 24 76778511 ps
T113 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4162680542 Aug 16 04:51:02 PM PDT 24 Aug 16 04:51:04 PM PDT 24 460115359 ps
T617 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4015552814 Aug 16 04:51:11 PM PDT 24 Aug 16 04:51:13 PM PDT 24 464661536 ps
T618 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3569888540 Aug 16 04:51:01 PM PDT 24 Aug 16 04:51:03 PM PDT 24 211911987 ps
T619 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2810829399 Aug 16 04:51:00 PM PDT 24 Aug 16 04:51:03 PM PDT 24 406323895 ps
T620 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1371980344 Aug 16 04:51:09 PM PDT 24 Aug 16 04:51:20 PM PDT 24 1972348157 ps

Test location /workspace/coverage/default/43.rstmgr_stress_all.3245756102
Short name T6
Test name
Test status
Simulation time 7822181786 ps
CPU time 26.88 seconds
Started Aug 16 04:52:33 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 209016 kb
Host smart-e1dba9c4-3e4b-44f2-877a-c278d3a5797b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245756102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3245756102
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.196196202
Short name T11
Test name
Test status
Simulation time 136288217 ps
CPU time 1.76 seconds
Started Aug 16 04:51:53 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 200496 kb
Host smart-8e4c5744-3536-402d-8176-765fd6101389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196196202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.196196202
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1038742775
Short name T39
Test name
Test status
Simulation time 2142753805 ps
CPU time 8.2 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:08 PM PDT 24
Peak memory 217740 kb
Host smart-e2887e0b-b10a-4249-8665-4d1e3f07a758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038742775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1038742775
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1677028136
Short name T65
Test name
Test status
Simulation time 938250395 ps
CPU time 3.37 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 200880 kb
Host smart-da2c78e8-35f5-4f17-aec5-c6e3ef382473
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677028136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1677028136
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1538504492
Short name T72
Test name
Test status
Simulation time 16573246543 ps
CPU time 26.64 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:45 PM PDT 24
Peak memory 217732 kb
Host smart-e2cdd82c-6028-4aa7-8139-f4f16fa46590
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538504492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1538504492
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2262551501
Short name T90
Test name
Test status
Simulation time 190788318 ps
CPU time 2.62 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 209064 kb
Host smart-00a53c28-6cde-4d83-b0ed-0d38b1623f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262551501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2262551501
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.772347493
Short name T25
Test name
Test status
Simulation time 8576107311 ps
CPU time 32.45 seconds
Started Aug 16 04:51:28 PM PDT 24
Finished Aug 16 04:52:01 PM PDT 24
Peak memory 200812 kb
Host smart-9cde3ebc-8415-4e55-bbe0-6b0a14366bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772347493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.772347493
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.571722399
Short name T53
Test name
Test status
Simulation time 72448673 ps
CPU time 0.83 seconds
Started Aug 16 04:52:01 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 200508 kb
Host smart-b0f842e8-a36d-4787-9653-297440f7c198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571722399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.571722399
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3771435138
Short name T157
Test name
Test status
Simulation time 112708087 ps
CPU time 1.11 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 200512 kb
Host smart-c38d80f6-f94d-4467-ab21-1159c0d25767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771435138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3771435138
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2251627990
Short name T32
Test name
Test status
Simulation time 2164715110 ps
CPU time 7.95 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 217768 kb
Host smart-a0888a67-e80f-4d75-a85e-e74e5cfe5b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251627990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2251627990
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2608850242
Short name T160
Test name
Test status
Simulation time 284036475 ps
CPU time 1.52 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200692 kb
Host smart-43b14632-f15c-4b29-8c31-3d8c59256e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608850242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2608850242
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1966084231
Short name T116
Test name
Test status
Simulation time 886742062 ps
CPU time 2.97 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:20 PM PDT 24
Peak memory 200964 kb
Host smart-3eb049fd-e013-446d-b631-a19d1ed4c2c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966084231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.1966084231
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1274325927
Short name T86
Test name
Test status
Simulation time 162535808 ps
CPU time 1.43 seconds
Started Aug 16 04:51:06 PM PDT 24
Finished Aug 16 04:51:08 PM PDT 24
Peak memory 209256 kb
Host smart-04a2dbfc-b952-4a12-a54a-9889214fee7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274325927 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1274325927
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2805283499
Short name T211
Test name
Test status
Simulation time 141114707 ps
CPU time 1.1 seconds
Started Aug 16 04:51:22 PM PDT 24
Finished Aug 16 04:51:23 PM PDT 24
Peak memory 200588 kb
Host smart-bb79f638-81fd-4648-806f-2a9836f7ab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805283499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2805283499
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.358728711
Short name T44
Test name
Test status
Simulation time 1905996965 ps
CPU time 6.88 seconds
Started Aug 16 04:51:50 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 217184 kb
Host smart-18349d97-ec3c-400a-a117-854eb5a1021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358728711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.358728711
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.489874058
Short name T63
Test name
Test status
Simulation time 924039571 ps
CPU time 3.4 seconds
Started Aug 16 04:51:12 PM PDT 24
Finished Aug 16 04:51:15 PM PDT 24
Peak memory 200984 kb
Host smart-1edee013-c46c-4edc-bebd-2d415b640870
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489874058 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.
489874058
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.1213164382
Short name T105
Test name
Test status
Simulation time 79907538 ps
CPU time 0.87 seconds
Started Aug 16 04:51:01 PM PDT 24
Finished Aug 16 04:51:02 PM PDT 24
Peak memory 200664 kb
Host smart-25dad6dc-381e-47bc-b247-12cf76212801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213164382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1213164382
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3543297689
Short name T18
Test name
Test status
Simulation time 112536297 ps
CPU time 0.75 seconds
Started Aug 16 04:51:37 PM PDT 24
Finished Aug 16 04:51:38 PM PDT 24
Peak memory 200388 kb
Host smart-57fd4851-73de-41d3-9fbe-0708b6fed3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543297689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3543297689
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2173913711
Short name T111
Test name
Test status
Simulation time 476708050 ps
CPU time 1.91 seconds
Started Aug 16 04:51:17 PM PDT 24
Finished Aug 16 04:51:19 PM PDT 24
Peak memory 201032 kb
Host smart-121434e5-2843-435c-9065-c8a6bf90f1f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173913711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2173913711
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.866855297
Short name T612
Test name
Test status
Simulation time 207782531 ps
CPU time 1.54 seconds
Started Aug 16 04:51:04 PM PDT 24
Finished Aug 16 04:51:06 PM PDT 24
Peak memory 200796 kb
Host smart-92880cd4-bc5d-48ab-b774-4f6db1cbda22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866855297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.866855297
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1363123452
Short name T544
Test name
Test status
Simulation time 275859805 ps
CPU time 3.19 seconds
Started Aug 16 04:51:00 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 200840 kb
Host smart-33a4a9da-45e6-4843-b91f-26b302583513
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363123452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
363123452
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2147085385
Short name T543
Test name
Test status
Simulation time 137897275 ps
CPU time 0.94 seconds
Started Aug 16 04:51:04 PM PDT 24
Finished Aug 16 04:51:05 PM PDT 24
Peak memory 200772 kb
Host smart-ae004281-41df-4d3f-9027-367d198a421d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147085385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
147085385
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1059295046
Short name T550
Test name
Test status
Simulation time 135828028 ps
CPU time 1.1 seconds
Started Aug 16 04:51:01 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 209092 kb
Host smart-9aae4bd2-e2a6-46fd-a225-53d7dc4f7394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059295046 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1059295046
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.2913390884
Short name T555
Test name
Test status
Simulation time 58188316 ps
CPU time 0.82 seconds
Started Aug 16 04:50:59 PM PDT 24
Finished Aug 16 04:51:00 PM PDT 24
Peak memory 200748 kb
Host smart-efdf8c34-971e-49cb-be1b-1c3e83b43781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913390884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2913390884
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3569888540
Short name T618
Test name
Test status
Simulation time 211911987 ps
CPU time 1.38 seconds
Started Aug 16 04:51:01 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 200884 kb
Host smart-a9df0053-0604-4115-a4ed-ccfb8b6738fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569888540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.3569888540
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3239229977
Short name T87
Test name
Test status
Simulation time 294317689 ps
CPU time 2.16 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:05 PM PDT 24
Peak memory 211904 kb
Host smart-2caf6dee-2dd3-48e5-9903-9b3147eeaa19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239229977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3239229977
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3266591370
Short name T62
Test name
Test status
Simulation time 765282757 ps
CPU time 3.16 seconds
Started Aug 16 04:51:01 PM PDT 24
Finished Aug 16 04:51:05 PM PDT 24
Peak memory 200956 kb
Host smart-c4f74ffb-3da5-46e8-9409-5921c6990948
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266591370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3266591370
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2659471546
Short name T571
Test name
Test status
Simulation time 203404356 ps
CPU time 1.6 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:04 PM PDT 24
Peak memory 200904 kb
Host smart-d0724a60-5361-4d1b-9310-590a6a6511b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659471546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
659471546
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.732293809
Short name T604
Test name
Test status
Simulation time 1030588012 ps
CPU time 4.91 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:07 PM PDT 24
Peak memory 200808 kb
Host smart-164b442c-6d75-41c9-b2ea-89284164557f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732293809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.732293809
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2895035503
Short name T545
Test name
Test status
Simulation time 113860596 ps
CPU time 0.9 seconds
Started Aug 16 04:51:01 PM PDT 24
Finished Aug 16 04:51:02 PM PDT 24
Peak memory 200776 kb
Host smart-c0cf671b-6d15-43bd-a6b8-a81da8267cc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895035503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2
895035503
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3570047317
Short name T560
Test name
Test status
Simulation time 182075566 ps
CPU time 1.25 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 210176 kb
Host smart-3d19a30d-2557-4871-a7a4-e032baa2c9b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570047317 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3570047317
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1077177904
Short name T576
Test name
Test status
Simulation time 127072001 ps
CPU time 1.13 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 200832 kb
Host smart-90b6ea97-c05e-4d94-b254-60a3a0d10e76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077177904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1077177904
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.3124557703
Short name T596
Test name
Test status
Simulation time 396830078 ps
CPU time 3.28 seconds
Started Aug 16 04:51:00 PM PDT 24
Finished Aug 16 04:51:04 PM PDT 24
Peak memory 209204 kb
Host smart-43f85502-dd49-475d-a97e-e955d143e9eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124557703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3124557703
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.105174336
Short name T128
Test name
Test status
Simulation time 886499072 ps
CPU time 3.46 seconds
Started Aug 16 04:51:03 PM PDT 24
Finished Aug 16 04:51:07 PM PDT 24
Peak memory 200900 kb
Host smart-eec4f369-ce6a-43d2-bc86-4846da9e0f58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105174336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.
105174336
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2029788130
Short name T607
Test name
Test status
Simulation time 99866940 ps
CPU time 1.03 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:09 PM PDT 24
Peak memory 209096 kb
Host smart-85e54c3b-13de-4e37-8f9e-f66c7a1762da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029788130 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2029788130
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.4206088989
Short name T588
Test name
Test status
Simulation time 72789071 ps
CPU time 0.85 seconds
Started Aug 16 04:51:12 PM PDT 24
Finished Aug 16 04:51:13 PM PDT 24
Peak memory 200636 kb
Host smart-4e957ebf-7027-457c-9dfa-6054fe239ce9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206088989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.4206088989
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1351452339
Short name T595
Test name
Test status
Simulation time 123664067 ps
CPU time 1.06 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:11 PM PDT 24
Peak memory 200736 kb
Host smart-7ad39932-0c18-4932-9390-d0ba19b1b21e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351452339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1351452339
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1723881874
Short name T587
Test name
Test status
Simulation time 130540936 ps
CPU time 1.81 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 200960 kb
Host smart-2dd38187-08d9-4555-bf7b-ec0b1fee3957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723881874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1723881874
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2140234596
Short name T597
Test name
Test status
Simulation time 487737480 ps
CPU time 2.12 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 201084 kb
Host smart-7fda31b9-bb55-4d7b-a378-d98feba98a85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140234596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2140234596
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3270246467
Short name T552
Test name
Test status
Simulation time 183624702 ps
CPU time 1.99 seconds
Started Aug 16 04:51:12 PM PDT 24
Finished Aug 16 04:51:14 PM PDT 24
Peak memory 209268 kb
Host smart-0d66b9f2-661c-4c09-a1a8-1efb0e973b2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270246467 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3270246467
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.816512225
Short name T594
Test name
Test status
Simulation time 73166158 ps
CPU time 0.88 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 200668 kb
Host smart-d8cbd485-b371-4803-9915-e50b69b255cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816512225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.816512225
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2318882496
Short name T586
Test name
Test status
Simulation time 96036665 ps
CPU time 1.26 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:11 PM PDT 24
Peak memory 200916 kb
Host smart-c450acb0-38b9-433c-a757-36f7b9142287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318882496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2318882496
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.68844472
Short name T554
Test name
Test status
Simulation time 142938715 ps
CPU time 2.2 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 212624 kb
Host smart-ab0fa30c-2e11-48e2-889b-93856e095b26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68844472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.68844472
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4133925684
Short name T561
Test name
Test status
Simulation time 499615627 ps
CPU time 2.16 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 201160 kb
Host smart-2f1d06c6-a046-409e-b899-9bb1c8989df7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133925684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4133925684
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2759571711
Short name T585
Test name
Test status
Simulation time 123032945 ps
CPU time 1.5 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 208988 kb
Host smart-1c1e9b0e-358f-4e5e-b158-6d885616191d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759571711 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2759571711
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.651807143
Short name T93
Test name
Test status
Simulation time 58498113 ps
CPU time 0.74 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:09 PM PDT 24
Peak memory 200744 kb
Host smart-0014ae61-f48a-4739-a475-35615b1de74a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651807143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.651807143
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1485304600
Short name T574
Test name
Test status
Simulation time 98992507 ps
CPU time 1.23 seconds
Started Aug 16 04:51:07 PM PDT 24
Finished Aug 16 04:51:08 PM PDT 24
Peak memory 200888 kb
Host smart-7a85f752-2825-49c3-98a1-3d0066e32f97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485304600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1485304600
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.1428220989
Short name T565
Test name
Test status
Simulation time 351153375 ps
CPU time 2.51 seconds
Started Aug 16 04:51:07 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 209100 kb
Host smart-66ea5ca6-c5fa-44d9-8228-0d671f08cf4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428220989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1428220989
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4217251320
Short name T127
Test name
Test status
Simulation time 889030817 ps
CPU time 3.01 seconds
Started Aug 16 04:51:06 PM PDT 24
Finished Aug 16 04:51:09 PM PDT 24
Peak memory 200876 kb
Host smart-5e2847a2-ac37-4cae-8732-17ff1df21c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217251320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4217251320
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2055747652
Short name T546
Test name
Test status
Simulation time 119784162 ps
CPU time 0.98 seconds
Started Aug 16 04:51:11 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 200852 kb
Host smart-48dbaf27-89cc-41eb-b7f9-a31f45ecd363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055747652 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.2055747652
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.85346330
Short name T584
Test name
Test status
Simulation time 72021520 ps
CPU time 0.75 seconds
Started Aug 16 04:51:12 PM PDT 24
Finished Aug 16 04:51:13 PM PDT 24
Peak memory 200568 kb
Host smart-207ddfb0-3583-40bc-93a1-64c0c38a4f9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85346330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.85346330
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.805691660
Short name T567
Test name
Test status
Simulation time 78072248 ps
CPU time 0.96 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:11 PM PDT 24
Peak memory 200736 kb
Host smart-838bb38f-e04d-4ac6-85f7-2b9bfb0bd0fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805691660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.805691660
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.4176658904
Short name T578
Test name
Test status
Simulation time 123241119 ps
CPU time 1.73 seconds
Started Aug 16 04:51:07 PM PDT 24
Finished Aug 16 04:51:09 PM PDT 24
Peak memory 200880 kb
Host smart-c8c862ee-b2d5-40af-9356-f8620883a50b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176658904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.4176658904
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3410760896
Short name T85
Test name
Test status
Simulation time 116743526 ps
CPU time 1.02 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:17 PM PDT 24
Peak memory 200744 kb
Host smart-dbe43530-f5c0-465b-a006-4a5b5d39b3d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410760896 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3410760896
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.850859249
Short name T563
Test name
Test status
Simulation time 60737058 ps
CPU time 0.78 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:17 PM PDT 24
Peak memory 200664 kb
Host smart-6165c8b1-6443-4e59-a5fe-643b3120b838
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850859249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.850859249
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3390258019
Short name T616
Test name
Test status
Simulation time 76778511 ps
CPU time 1 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:20 PM PDT 24
Peak memory 200676 kb
Host smart-fca0760a-a7e1-4127-9820-e70bcdddcdd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390258019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3390258019
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.106386705
Short name T581
Test name
Test status
Simulation time 321334089 ps
CPU time 2.41 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 209164 kb
Host smart-83774d1e-f37e-480f-aed0-93e45321a066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106386705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.106386705
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.4015552814
Short name T617
Test name
Test status
Simulation time 464661536 ps
CPU time 2.09 seconds
Started Aug 16 04:51:11 PM PDT 24
Finished Aug 16 04:51:13 PM PDT 24
Peak memory 200936 kb
Host smart-11ab9652-f91c-45c6-be36-7593ed93be41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015552814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.4015552814
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2450963039
Short name T592
Test name
Test status
Simulation time 197067478 ps
CPU time 1.34 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:20 PM PDT 24
Peak memory 209008 kb
Host smart-907e2ffb-6762-49fb-86d4-39b48d660433
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450963039 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.2450963039
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.1975157122
Short name T559
Test name
Test status
Simulation time 90237093 ps
CPU time 0.91 seconds
Started Aug 16 04:51:17 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 200720 kb
Host smart-4a8b4aa0-6688-4dce-a8a1-d9f798450745
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975157122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1975157122
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3610736789
Short name T104
Test name
Test status
Simulation time 99656307 ps
CPU time 1.2 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:19 PM PDT 24
Peak memory 200888 kb
Host smart-dfdc626a-eb57-4125-8d7d-804d22bbde7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610736789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3610736789
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.3370960545
Short name T568
Test name
Test status
Simulation time 397873581 ps
CPU time 2.97 seconds
Started Aug 16 04:51:17 PM PDT 24
Finished Aug 16 04:51:21 PM PDT 24
Peak memory 209156 kb
Host smart-dc572b68-145e-41f5-8957-01c21036e5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370960545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.3370960545
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.620585483
Short name T547
Test name
Test status
Simulation time 181498107 ps
CPU time 1.77 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:21 PM PDT 24
Peak memory 209188 kb
Host smart-e20ff63c-45b2-4a1d-addd-f3e0250f84a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620585483 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.620585483
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1824446109
Short name T106
Test name
Test status
Simulation time 68233051 ps
CPU time 0.85 seconds
Started Aug 16 04:51:20 PM PDT 24
Finished Aug 16 04:51:21 PM PDT 24
Peak memory 200620 kb
Host smart-2663786e-d03e-4281-b1d6-d27c2f7fe359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824446109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1824446109
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2123429862
Short name T611
Test name
Test status
Simulation time 134866563 ps
CPU time 1.08 seconds
Started Aug 16 04:51:17 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 200816 kb
Host smart-2f76635a-946d-4a0e-a1ad-a694feec6cc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123429862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.2123429862
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.2360479008
Short name T575
Test name
Test status
Simulation time 506570591 ps
CPU time 3.72 seconds
Started Aug 16 04:51:15 PM PDT 24
Finished Aug 16 04:51:19 PM PDT 24
Peak memory 217080 kb
Host smart-89a5e3a6-7b61-4734-b6c6-5a72f8673526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360479008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2360479008
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2578324406
Short name T606
Test name
Test status
Simulation time 923992458 ps
CPU time 3.18 seconds
Started Aug 16 04:51:14 PM PDT 24
Finished Aug 16 04:51:17 PM PDT 24
Peak memory 200924 kb
Host smart-d4a0b5b2-6f99-4350-a134-e6c04d5a780a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578324406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.2578324406
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.973001485
Short name T556
Test name
Test status
Simulation time 131659636 ps
CPU time 1.12 seconds
Started Aug 16 04:51:22 PM PDT 24
Finished Aug 16 04:51:24 PM PDT 24
Peak memory 200888 kb
Host smart-dea237bb-efcd-40b6-ba3f-d31c85540701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973001485 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.973001485
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.3850048170
Short name T605
Test name
Test status
Simulation time 72203912 ps
CPU time 0.83 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:17 PM PDT 24
Peak memory 200676 kb
Host smart-01d6485b-aae4-4a7d-9dfd-9b9b3ecf2fa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850048170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3850048170
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.360620660
Short name T615
Test name
Test status
Simulation time 85900628 ps
CPU time 1.01 seconds
Started Aug 16 04:51:15 PM PDT 24
Finished Aug 16 04:51:16 PM PDT 24
Peak memory 200840 kb
Host smart-51d06c73-8081-4135-8256-fff348be8ba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360620660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_sa
me_csr_outstanding.360620660
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.377568976
Short name T117
Test name
Test status
Simulation time 367376185 ps
CPU time 2.7 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:20 PM PDT 24
Peak memory 209048 kb
Host smart-a5fb9b3a-e137-4768-ae8c-69eb2b63ba58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377568976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.377568976
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2759618304
Short name T112
Test name
Test status
Simulation time 529202614 ps
CPU time 2.02 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 200956 kb
Host smart-6e15d71a-43f5-4d36-8c31-bd66938fc4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759618304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2759618304
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.732607805
Short name T68
Test name
Test status
Simulation time 107414315 ps
CPU time 0.94 seconds
Started Aug 16 04:51:15 PM PDT 24
Finished Aug 16 04:51:17 PM PDT 24
Peak memory 200896 kb
Host smart-38dc14c6-b01c-4dd0-9239-578c55dfac0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732607805 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.732607805
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1079214700
Short name T577
Test name
Test status
Simulation time 89497260 ps
CPU time 0.89 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 200612 kb
Host smart-bcf726cc-9d5a-498e-8c6c-6241fbda09e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079214700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1079214700
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3940766331
Short name T589
Test name
Test status
Simulation time 143397800 ps
CPU time 1.1 seconds
Started Aug 16 04:51:15 PM PDT 24
Finished Aug 16 04:51:17 PM PDT 24
Peak memory 200816 kb
Host smart-16e3543e-e6a7-4f7c-be9a-1c192fe67524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940766331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.3940766331
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.1685144437
Short name T583
Test name
Test status
Simulation time 457070695 ps
CPU time 2.88 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:19 PM PDT 24
Peak memory 209112 kb
Host smart-7f0775fb-a190-49df-8c55-b60cc24c78de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685144437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1685144437
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1386687057
Short name T609
Test name
Test status
Simulation time 159870905 ps
CPU time 1.38 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 208996 kb
Host smart-84275072-ce28-4354-a586-9b374c96446e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386687057 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1386687057
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2421462893
Short name T573
Test name
Test status
Simulation time 59111546 ps
CPU time 0.8 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 200724 kb
Host smart-68101303-0783-44e6-96ea-73f3d7d2041e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421462893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2421462893
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2471390812
Short name T108
Test name
Test status
Simulation time 129906161 ps
CPU time 1.26 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:17 PM PDT 24
Peak memory 200988 kb
Host smart-4e897e2c-f4af-4e32-ae4c-4c5af1ad059a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471390812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2471390812
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.155692482
Short name T66
Test name
Test status
Simulation time 115329030 ps
CPU time 1.71 seconds
Started Aug 16 04:51:20 PM PDT 24
Finished Aug 16 04:51:22 PM PDT 24
Peak memory 217156 kb
Host smart-873d8a38-c55b-4e75-a0d8-7ebc8294173f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155692482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.155692482
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1435638277
Short name T114
Test name
Test status
Simulation time 497741998 ps
CPU time 1.84 seconds
Started Aug 16 04:51:16 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 200956 kb
Host smart-174ee639-9c5b-425b-9af5-8332c32dd214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435638277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1435638277
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.647314140
Short name T582
Test name
Test status
Simulation time 105787304 ps
CPU time 1.47 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 200832 kb
Host smart-a032bde3-442a-46a2-a61e-6c9e24d6250c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647314140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.647314140
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1955484799
Short name T599
Test name
Test status
Simulation time 795959381 ps
CPU time 4.77 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:07 PM PDT 24
Peak memory 200844 kb
Host smart-481b0cb5-2e6b-4e51-a226-ab25d11699e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955484799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
955484799
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2010005129
Short name T600
Test name
Test status
Simulation time 124241126 ps
CPU time 0.92 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 200724 kb
Host smart-33706fe2-8695-4bdb-a092-462f9f46f8a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010005129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
010005129
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.482925963
Short name T610
Test name
Test status
Simulation time 105066385 ps
CPU time 1.14 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 209048 kb
Host smart-7c17c7c7-dee1-47b8-ac9f-b86abf5b2dde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482925963 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.482925963
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.2758732391
Short name T572
Test name
Test status
Simulation time 80166319 ps
CPU time 0.89 seconds
Started Aug 16 04:50:59 PM PDT 24
Finished Aug 16 04:51:00 PM PDT 24
Peak memory 200752 kb
Host smart-fe8c6cc7-6247-42d4-a782-3c6e17ee2e05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758732391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2758732391
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3775866658
Short name T107
Test name
Test status
Simulation time 206621798 ps
CPU time 1.53 seconds
Started Aug 16 04:51:03 PM PDT 24
Finished Aug 16 04:51:05 PM PDT 24
Peak memory 200960 kb
Host smart-d03f4b0c-6358-497c-bdaf-ee056509152f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775866658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3775866658
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2519210205
Short name T614
Test name
Test status
Simulation time 107737664 ps
CPU time 1.47 seconds
Started Aug 16 04:51:00 PM PDT 24
Finished Aug 16 04:51:02 PM PDT 24
Peak memory 217216 kb
Host smart-ff2a94f4-128b-4789-a9dd-5f7a5ec26989
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519210205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2519210205
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3194590899
Short name T562
Test name
Test status
Simulation time 773780228 ps
CPU time 2.92 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:06 PM PDT 24
Peak memory 200836 kb
Host smart-90793b26-a759-4743-a3ae-1ba926510226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194590899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3194590899
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1222353333
Short name T557
Test name
Test status
Simulation time 213955720 ps
CPU time 1.73 seconds
Started Aug 16 04:51:00 PM PDT 24
Finished Aug 16 04:51:02 PM PDT 24
Peak memory 200940 kb
Host smart-5a107d6c-9882-4128-9db5-44434646e9f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222353333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
222353333
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2469848972
Short name T548
Test name
Test status
Simulation time 2279167422 ps
CPU time 9.83 seconds
Started Aug 16 04:51:01 PM PDT 24
Finished Aug 16 04:51:11 PM PDT 24
Peak memory 209232 kb
Host smart-7e78a2f8-2e46-44bd-996c-f6096d68961d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469848972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2
469848972
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1716148880
Short name T558
Test name
Test status
Simulation time 95288461 ps
CPU time 0.89 seconds
Started Aug 16 04:51:00 PM PDT 24
Finished Aug 16 04:51:01 PM PDT 24
Peak memory 200748 kb
Host smart-d71a5b88-fc8b-4bc2-862a-5e59f160b862
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716148880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
716148880
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2788172782
Short name T551
Test name
Test status
Simulation time 165202639 ps
CPU time 1.63 seconds
Started Aug 16 04:51:01 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 209232 kb
Host smart-4ddbb035-2d55-40f6-8ba2-77e5c4d28ffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788172782 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2788172782
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.3282865921
Short name T613
Test name
Test status
Simulation time 65772582 ps
CPU time 0.76 seconds
Started Aug 16 04:50:59 PM PDT 24
Finished Aug 16 04:51:00 PM PDT 24
Peak memory 200748 kb
Host smart-e9124ba1-e423-4812-abfc-d24561556768
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282865921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3282865921
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4276668223
Short name T101
Test name
Test status
Simulation time 148581064 ps
CPU time 1.12 seconds
Started Aug 16 04:50:59 PM PDT 24
Finished Aug 16 04:51:00 PM PDT 24
Peak memory 200840 kb
Host smart-bd21f0d1-9233-461b-8626-d3c79eb56082
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276668223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4276668223
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.2810829399
Short name T619
Test name
Test status
Simulation time 406323895 ps
CPU time 2.9 seconds
Started Aug 16 04:51:00 PM PDT 24
Finished Aug 16 04:51:03 PM PDT 24
Peak memory 212412 kb
Host smart-dea9c2d7-ef67-42be-a21e-bb26061410d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810829399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2810829399
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1790449306
Short name T110
Test name
Test status
Simulation time 449983316 ps
CPU time 1.81 seconds
Started Aug 16 04:51:04 PM PDT 24
Finished Aug 16 04:51:06 PM PDT 24
Peak memory 200872 kb
Host smart-17a815ce-b3a1-453e-81d2-1c1081f56b13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790449306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1790449306
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.841549688
Short name T64
Test name
Test status
Simulation time 109915230 ps
CPU time 1.36 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:11 PM PDT 24
Peak memory 200828 kb
Host smart-0648faaa-9bda-41a8-a4ba-a7b869734e36
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841549688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.841549688
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1371980344
Short name T620
Test name
Test status
Simulation time 1972348157 ps
CPU time 10.48 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:20 PM PDT 24
Peak memory 200848 kb
Host smart-e1bfb886-78f5-404c-9d87-8dd36abca1d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371980344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
371980344
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.414589853
Short name T598
Test name
Test status
Simulation time 99361266 ps
CPU time 0.83 seconds
Started Aug 16 04:51:00 PM PDT 24
Finished Aug 16 04:51:01 PM PDT 24
Peak memory 200676 kb
Host smart-9cd5c8b7-8419-4ac5-a4f7-64835f2c0a40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414589853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.414589853
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.7194699
Short name T564
Test name
Test status
Simulation time 62452738 ps
CPU time 0.78 seconds
Started Aug 16 04:51:04 PM PDT 24
Finished Aug 16 04:51:05 PM PDT 24
Peak memory 200796 kb
Host smart-0e9fac3c-8c5e-45ba-a99e-9cac040ee76f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7194699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.7194699
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3922659922
Short name T602
Test name
Test status
Simulation time 203571428 ps
CPU time 1.51 seconds
Started Aug 16 04:51:12 PM PDT 24
Finished Aug 16 04:51:13 PM PDT 24
Peak memory 209200 kb
Host smart-3ebb67f1-bbb5-40ba-93a8-1069031692f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922659922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.3922659922
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3110071399
Short name T591
Test name
Test status
Simulation time 198027454 ps
CPU time 3.03 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:05 PM PDT 24
Peak memory 209132 kb
Host smart-7c155f0d-4b73-4b1c-8df3-763ad925f7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110071399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3110071399
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4162680542
Short name T113
Test name
Test status
Simulation time 460115359 ps
CPU time 2.04 seconds
Started Aug 16 04:51:02 PM PDT 24
Finished Aug 16 04:51:04 PM PDT 24
Peak memory 200992 kb
Host smart-b4afbfb8-3758-48c7-8642-83f780b1c43d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162680542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.4162680542
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4279588845
Short name T590
Test name
Test status
Simulation time 113782399 ps
CPU time 0.98 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 200780 kb
Host smart-5feb7a32-e72f-4a5c-9b0a-8a532f5b8ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279588845 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.4279588845
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3401652571
Short name T553
Test name
Test status
Simulation time 66815297 ps
CPU time 0.91 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:09 PM PDT 24
Peak memory 200668 kb
Host smart-d9178810-cac8-4acf-9196-ec799261b828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401652571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3401652571
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1639959223
Short name T109
Test name
Test status
Simulation time 215943777 ps
CPU time 1.46 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:09 PM PDT 24
Peak memory 200996 kb
Host smart-ab58b511-824c-4997-969f-3bda28f96ea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639959223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1639959223
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1270632357
Short name T67
Test name
Test status
Simulation time 174525093 ps
CPU time 2.82 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:13 PM PDT 24
Peak memory 209152 kb
Host smart-0832e388-5f6d-43ee-8b27-c0a0bac0cfc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270632357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1270632357
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.48649363
Short name T566
Test name
Test status
Simulation time 910462991 ps
CPU time 3.53 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:13 PM PDT 24
Peak memory 200972 kb
Host smart-c111b289-1fd3-4248-94b2-ecbff0b58b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48649363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.48649363
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.204166783
Short name T569
Test name
Test status
Simulation time 130737738 ps
CPU time 1.33 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 208928 kb
Host smart-b1134e8e-154c-4fed-826f-1dbbbcaa546b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204166783 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.204166783
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2509814119
Short name T61
Test name
Test status
Simulation time 66323739 ps
CPU time 0.81 seconds
Started Aug 16 04:51:12 PM PDT 24
Finished Aug 16 04:51:13 PM PDT 24
Peak memory 200560 kb
Host smart-ffda94ee-c349-4886-982d-b538c7dbd482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509814119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2509814119
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.442762252
Short name T608
Test name
Test status
Simulation time 195870744 ps
CPU time 1.39 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:09 PM PDT 24
Peak memory 200952 kb
Host smart-82518e40-1048-42e9-b2b0-a0da1506b0a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442762252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.442762252
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2223309615
Short name T89
Test name
Test status
Simulation time 326906946 ps
CPU time 2.26 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:11 PM PDT 24
Peak memory 209044 kb
Host smart-e2534111-18d8-47c6-ad35-ee4a7b5f63a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223309615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2223309615
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3163532347
Short name T129
Test name
Test status
Simulation time 471910197 ps
CPU time 1.94 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 200928 kb
Host smart-3bb9f2ca-e081-40a6-94fc-ac172a03c4ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163532347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3163532347
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.799801091
Short name T603
Test name
Test status
Simulation time 180076711 ps
CPU time 1.17 seconds
Started Aug 16 04:51:06 PM PDT 24
Finished Aug 16 04:51:07 PM PDT 24
Peak memory 200956 kb
Host smart-23883a69-431f-494b-b6a8-0fcfbae26347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799801091 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.799801091
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.1056250249
Short name T102
Test name
Test status
Simulation time 60073025 ps
CPU time 0.75 seconds
Started Aug 16 04:51:11 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 200600 kb
Host smart-452f6ce2-40c0-423e-ac69-a8d631d74ce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056250249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1056250249
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1378618899
Short name T100
Test name
Test status
Simulation time 243533198 ps
CPU time 1.58 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 200880 kb
Host smart-9d88197d-067f-4039-b6f6-b3352e286240
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378618899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1378618899
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1042681850
Short name T88
Test name
Test status
Simulation time 133619510 ps
CPU time 1.46 seconds
Started Aug 16 04:51:12 PM PDT 24
Finished Aug 16 04:51:14 PM PDT 24
Peak memory 209392 kb
Host smart-ae0a78ab-5766-4514-aa10-5fd8760d07ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042681850 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1042681850
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.542422485
Short name T580
Test name
Test status
Simulation time 54573594 ps
CPU time 0.79 seconds
Started Aug 16 04:51:11 PM PDT 24
Finished Aug 16 04:51:11 PM PDT 24
Peak memory 200656 kb
Host smart-fab811f5-c256-4cad-9713-ac7c795edf06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542422485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.542422485
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.775672964
Short name T103
Test name
Test status
Simulation time 111414646 ps
CPU time 1.25 seconds
Started Aug 16 04:51:06 PM PDT 24
Finished Aug 16 04:51:07 PM PDT 24
Peak memory 200904 kb
Host smart-d32b0944-6d21-4893-80e6-2aa1e041c275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775672964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.775672964
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1264191957
Short name T593
Test name
Test status
Simulation time 320707528 ps
CPU time 2.6 seconds
Started Aug 16 04:51:07 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 217152 kb
Host smart-b1c94aa9-cac9-428d-bc7a-56b7e93fd2df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264191957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1264191957
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1208684643
Short name T115
Test name
Test status
Simulation time 502446109 ps
CPU time 2.21 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:11 PM PDT 24
Peak memory 201016 kb
Host smart-5e3c8d89-9491-4c7e-9675-d947e577ade5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208684643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1208684643
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3742745125
Short name T118
Test name
Test status
Simulation time 125066612 ps
CPU time 1.19 seconds
Started Aug 16 04:51:07 PM PDT 24
Finished Aug 16 04:51:08 PM PDT 24
Peak memory 209048 kb
Host smart-c79c13d1-7f3b-4062-830d-375bf9614e28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742745125 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.3742745125
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1334334458
Short name T549
Test name
Test status
Simulation time 68281384 ps
CPU time 0.8 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 200632 kb
Host smart-6cb3e785-78ad-4548-9aac-1d03aa981a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334334458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1334334458
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2972070421
Short name T601
Test name
Test status
Simulation time 214240420 ps
CPU time 1.41 seconds
Started Aug 16 04:51:09 PM PDT 24
Finished Aug 16 04:51:10 PM PDT 24
Peak memory 200984 kb
Host smart-e7ba9eff-bcb9-4771-9628-dec990bb26d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972070421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.2972070421
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.193108111
Short name T570
Test name
Test status
Simulation time 537025808 ps
CPU time 3.36 seconds
Started Aug 16 04:51:08 PM PDT 24
Finished Aug 16 04:51:12 PM PDT 24
Peak memory 209172 kb
Host smart-ddf57e45-24a8-45bf-ae06-ad097fa3b973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193108111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.193108111
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.435640765
Short name T579
Test name
Test status
Simulation time 939208744 ps
CPU time 3.23 seconds
Started Aug 16 04:51:10 PM PDT 24
Finished Aug 16 04:51:13 PM PDT 24
Peak memory 200884 kb
Host smart-45aa5e0e-1abc-4255-96ee-fe60255c784d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435640765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.
435640765
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2348907486
Short name T255
Test name
Test status
Simulation time 71404311 ps
CPU time 0.78 seconds
Started Aug 16 04:51:15 PM PDT 24
Finished Aug 16 04:51:16 PM PDT 24
Peak memory 200340 kb
Host smart-dc849fdc-7f62-4c0e-945b-6b11d8f655c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348907486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2348907486
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3914025491
Short name T30
Test name
Test status
Simulation time 1221005689 ps
CPU time 5.58 seconds
Started Aug 16 04:51:19 PM PDT 24
Finished Aug 16 04:51:25 PM PDT 24
Peak memory 217184 kb
Host smart-8b93444d-e488-4423-8bcf-2e59d67c9627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914025491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3914025491
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.740907500
Short name T397
Test name
Test status
Simulation time 243816605 ps
CPU time 1.16 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:20 PM PDT 24
Peak memory 217648 kb
Host smart-ca2bb4f2-1ba2-4adf-9a78-23315ac167cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740907500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.740907500
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.497976787
Short name T482
Test name
Test status
Simulation time 178163054 ps
CPU time 0.9 seconds
Started Aug 16 04:51:17 PM PDT 24
Finished Aug 16 04:51:18 PM PDT 24
Peak memory 200352 kb
Host smart-4c8b23c1-0139-46a2-bdbb-089e754e39c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497976787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.497976787
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1469435092
Short name T517
Test name
Test status
Simulation time 1799793392 ps
CPU time 6.42 seconds
Started Aug 16 04:51:22 PM PDT 24
Finished Aug 16 04:51:29 PM PDT 24
Peak memory 200788 kb
Host smart-f861a338-7647-4ed5-b351-e0068ff28042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469435092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1469435092
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.2272059835
Short name T386
Test name
Test status
Simulation time 108866990 ps
CPU time 1.25 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:19 PM PDT 24
Peak memory 200600 kb
Host smart-f15eceff-a95e-4312-8ef5-252f63c3b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272059835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2272059835
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.180803955
Short name T507
Test name
Test status
Simulation time 1465507400 ps
CPU time 6.56 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:25 PM PDT 24
Peak memory 200716 kb
Host smart-2ba10931-63cd-44d6-a6ea-1dc830984607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180803955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.180803955
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1939072407
Short name T383
Test name
Test status
Simulation time 142742170 ps
CPU time 1.93 seconds
Started Aug 16 04:51:17 PM PDT 24
Finished Aug 16 04:51:19 PM PDT 24
Peak memory 200492 kb
Host smart-0a47d0d3-cf1a-42e5-a2c4-535c0a29bb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939072407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1939072407
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.650468872
Short name T310
Test name
Test status
Simulation time 76162521 ps
CPU time 0.8 seconds
Started Aug 16 04:51:27 PM PDT 24
Finished Aug 16 04:51:28 PM PDT 24
Peak memory 200484 kb
Host smart-8a08b0d2-10ed-4d63-8285-c4dd3a11d293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650468872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.650468872
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.481731064
Short name T447
Test name
Test status
Simulation time 1901134015 ps
CPU time 7.52 seconds
Started Aug 16 04:51:23 PM PDT 24
Finished Aug 16 04:51:31 PM PDT 24
Peak memory 217944 kb
Host smart-c240fdba-76cd-4fd3-861f-6a366c2ae84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481731064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.481731064
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3669000567
Short name T251
Test name
Test status
Simulation time 244699783 ps
CPU time 1.08 seconds
Started Aug 16 04:51:22 PM PDT 24
Finished Aug 16 04:51:24 PM PDT 24
Peak memory 217708 kb
Host smart-881d833c-a177-42b9-8124-1e8922cf7bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669000567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3669000567
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3941738464
Short name T230
Test name
Test status
Simulation time 127488105 ps
CPU time 0.82 seconds
Started Aug 16 04:51:20 PM PDT 24
Finished Aug 16 04:51:21 PM PDT 24
Peak memory 200248 kb
Host smart-ff1abdbb-8144-4bf1-8037-7fb25f47c463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941738464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3941738464
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.565535159
Short name T435
Test name
Test status
Simulation time 1989163778 ps
CPU time 6.99 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:31 PM PDT 24
Peak memory 200732 kb
Host smart-0af5879f-85ec-4b04-921d-ab4d5110f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565535159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.565535159
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2168744477
Short name T70
Test name
Test status
Simulation time 17382384463 ps
CPU time 26.44 seconds
Started Aug 16 04:51:25 PM PDT 24
Finished Aug 16 04:51:52 PM PDT 24
Peak memory 217300 kb
Host smart-aba3989f-ec96-4a8a-b2e6-3888f4631c3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168744477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2168744477
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1047499300
Short name T360
Test name
Test status
Simulation time 166744901 ps
CPU time 1.14 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:25 PM PDT 24
Peak memory 200552 kb
Host smart-4da02cc3-8c8a-4e19-b424-a0820900263d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047499300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1047499300
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1730788846
Short name T402
Test name
Test status
Simulation time 197443602 ps
CPU time 1.37 seconds
Started Aug 16 04:51:18 PM PDT 24
Finished Aug 16 04:51:20 PM PDT 24
Peak memory 200636 kb
Host smart-da338111-4e8d-4594-97cb-7fdbe69c4124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730788846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1730788846
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3386671711
Short name T380
Test name
Test status
Simulation time 1524126184 ps
CPU time 6.07 seconds
Started Aug 16 04:51:26 PM PDT 24
Finished Aug 16 04:51:33 PM PDT 24
Peak memory 200684 kb
Host smart-be4b72d9-47e2-4880-9754-900f1436ac41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386671711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3386671711
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1719590764
Short name T302
Test name
Test status
Simulation time 149856874 ps
CPU time 1.91 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:26 PM PDT 24
Peak memory 200488 kb
Host smart-da07efcd-a23e-4c20-95f6-bf12dad12889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719590764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1719590764
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.1247373417
Short name T493
Test name
Test status
Simulation time 217154435 ps
CPU time 1.45 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:26 PM PDT 24
Peak memory 200492 kb
Host smart-b53f749d-9bd0-43fa-afb6-a772ea76886a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247373417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1247373417
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.292928265
Short name T331
Test name
Test status
Simulation time 61367891 ps
CPU time 0.74 seconds
Started Aug 16 04:51:38 PM PDT 24
Finished Aug 16 04:51:39 PM PDT 24
Peak memory 200380 kb
Host smart-60071128-0d1a-4795-819e-029353ce5ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292928265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.292928265
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1904586601
Short name T353
Test name
Test status
Simulation time 1885051984 ps
CPU time 6.91 seconds
Started Aug 16 04:51:36 PM PDT 24
Finished Aug 16 04:51:43 PM PDT 24
Peak memory 217908 kb
Host smart-721d7fb8-6ffa-4f4a-b5de-7c324742f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904586601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1904586601
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1582166232
Short name T346
Test name
Test status
Simulation time 244912323 ps
CPU time 1.16 seconds
Started Aug 16 04:51:38 PM PDT 24
Finished Aug 16 04:51:39 PM PDT 24
Peak memory 217740 kb
Host smart-09de37ac-292b-439a-a8a6-bffae53849c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582166232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1582166232
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.1211391160
Short name T495
Test name
Test status
Simulation time 225648489 ps
CPU time 0.95 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:51:40 PM PDT 24
Peak memory 200432 kb
Host smart-d51d1d6e-74ba-415d-a8f5-5f1c44a0f694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211391160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1211391160
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1801460290
Short name T249
Test name
Test status
Simulation time 989834016 ps
CPU time 4.8 seconds
Started Aug 16 04:51:41 PM PDT 24
Finished Aug 16 04:51:45 PM PDT 24
Peak memory 200628 kb
Host smart-8e011f48-e046-417d-bf2c-a50f36d4b8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801460290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1801460290
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2780736879
Short name T511
Test name
Test status
Simulation time 98946835 ps
CPU time 1.08 seconds
Started Aug 16 04:51:40 PM PDT 24
Finished Aug 16 04:51:41 PM PDT 24
Peak memory 200588 kb
Host smart-8b15ffbe-6661-4025-8244-82611e90934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780736879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2780736879
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.964433881
Short name T275
Test name
Test status
Simulation time 234196037 ps
CPU time 1.41 seconds
Started Aug 16 04:51:41 PM PDT 24
Finished Aug 16 04:51:42 PM PDT 24
Peak memory 200624 kb
Host smart-4afb9f59-29bb-4079-b6ad-fb45e04ed2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964433881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.964433881
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.550536045
Short name T542
Test name
Test status
Simulation time 6300916261 ps
CPU time 22.12 seconds
Started Aug 16 04:51:38 PM PDT 24
Finished Aug 16 04:52:01 PM PDT 24
Peak memory 200816 kb
Host smart-e1945877-bfcd-4618-828f-4eb2f0fe2a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550536045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.550536045
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2986433184
Short name T188
Test name
Test status
Simulation time 130869443 ps
CPU time 1.71 seconds
Started Aug 16 04:51:37 PM PDT 24
Finished Aug 16 04:51:39 PM PDT 24
Peak memory 200460 kb
Host smart-6d426bce-9db1-4ddb-9a82-6d46d0302c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986433184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2986433184
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.70446257
Short name T179
Test name
Test status
Simulation time 87865865 ps
CPU time 0.85 seconds
Started Aug 16 04:51:37 PM PDT 24
Finished Aug 16 04:51:38 PM PDT 24
Peak memory 200472 kb
Host smart-a4258546-b9d9-4734-88d9-0d9917cdede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70446257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.70446257
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1128638600
Short name T318
Test name
Test status
Simulation time 75788434 ps
CPU time 0.79 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:51:40 PM PDT 24
Peak memory 200460 kb
Host smart-5c471963-43ae-4bb4-8ae0-1a02dbc31f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128638600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1128638600
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2786756400
Short name T512
Test name
Test status
Simulation time 2359263460 ps
CPU time 9.24 seconds
Started Aug 16 04:51:40 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 218020 kb
Host smart-72d25511-08a4-4fd0-ac84-00e8e5f431ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786756400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2786756400
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3349661880
Short name T534
Test name
Test status
Simulation time 255116437 ps
CPU time 1.07 seconds
Started Aug 16 04:51:43 PM PDT 24
Finished Aug 16 04:51:44 PM PDT 24
Peak memory 217748 kb
Host smart-186ac05e-8b35-4961-bde2-72f493d5506d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349661880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3349661880
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2357983408
Short name T475
Test name
Test status
Simulation time 167072871 ps
CPU time 0.9 seconds
Started Aug 16 04:51:42 PM PDT 24
Finished Aug 16 04:51:43 PM PDT 24
Peak memory 200300 kb
Host smart-27c463b6-0bfe-4d19-bc0e-d22b55bac3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357983408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2357983408
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1613832034
Short name T350
Test name
Test status
Simulation time 1510582947 ps
CPU time 5.57 seconds
Started Aug 16 04:51:40 PM PDT 24
Finished Aug 16 04:51:45 PM PDT 24
Peak memory 200776 kb
Host smart-70806b3b-f50e-49da-956e-cbb650a08773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613832034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1613832034
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.221241945
Short name T185
Test name
Test status
Simulation time 104454960 ps
CPU time 1.03 seconds
Started Aug 16 04:51:44 PM PDT 24
Finished Aug 16 04:51:45 PM PDT 24
Peak memory 200508 kb
Host smart-59531dc3-a640-4d74-ace0-66569422f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221241945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.221241945
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.138322255
Short name T77
Test name
Test status
Simulation time 193158318 ps
CPU time 1.44 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:51:41 PM PDT 24
Peak memory 200752 kb
Host smart-dd9d1bba-889a-4471-83b1-ae7b1a4e87d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138322255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.138322255
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1714787311
Short name T316
Test name
Test status
Simulation time 11724163513 ps
CPU time 47.32 seconds
Started Aug 16 04:51:37 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 200696 kb
Host smart-723c6633-d2ce-4392-8ee5-832dcb9a4efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714787311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1714787311
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2579243659
Short name T262
Test name
Test status
Simulation time 136522221 ps
CPU time 1.76 seconds
Started Aug 16 04:51:40 PM PDT 24
Finished Aug 16 04:51:42 PM PDT 24
Peak memory 200348 kb
Host smart-d2ba69b9-804b-4577-88b9-2f1efe423e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579243659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2579243659
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.2901797889
Short name T1
Test name
Test status
Simulation time 115574575 ps
CPU time 1 seconds
Started Aug 16 04:51:43 PM PDT 24
Finished Aug 16 04:51:44 PM PDT 24
Peak memory 200492 kb
Host smart-7ca857db-de49-4df1-9f76-d19a4e11a94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901797889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2901797889
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.3743652590
Short name T487
Test name
Test status
Simulation time 74069214 ps
CPU time 0.77 seconds
Started Aug 16 04:51:48 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 200380 kb
Host smart-8bdcd2d7-e7a7-4952-a447-06743b65b70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743652590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3743652590
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1155291923
Short name T277
Test name
Test status
Simulation time 243875036 ps
CPU time 1.2 seconds
Started Aug 16 04:51:45 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 217760 kb
Host smart-87c3063a-098b-47de-940d-d32e51caa60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155291923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1155291923
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2981088465
Short name T119
Test name
Test status
Simulation time 1672748653 ps
CPU time 5.99 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:52 PM PDT 24
Peak memory 200760 kb
Host smart-84c44bbd-81e6-439a-b71c-f9a596f2824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981088465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2981088465
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2407189062
Short name T203
Test name
Test status
Simulation time 178441530 ps
CPU time 1.26 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 200612 kb
Host smart-8acfcbc5-7e66-4b9f-bd43-720bc381c61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407189062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2407189062
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3276768429
Short name T254
Test name
Test status
Simulation time 118734597 ps
CPU time 1.24 seconds
Started Aug 16 04:51:43 PM PDT 24
Finished Aug 16 04:51:44 PM PDT 24
Peak memory 200716 kb
Host smart-f636a004-b331-4bf9-b6a0-fec756d6f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276768429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3276768429
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.941031462
Short name T342
Test name
Test status
Simulation time 4818981511 ps
CPU time 15.77 seconds
Started Aug 16 04:51:49 PM PDT 24
Finished Aug 16 04:52:04 PM PDT 24
Peak memory 200816 kb
Host smart-5b185e69-027b-4c23-a957-24c6e948c11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941031462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.941031462
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2964897376
Short name T451
Test name
Test status
Simulation time 147284802 ps
CPU time 1.77 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 208748 kb
Host smart-4f702d3a-3188-4358-a070-b0cd516ca0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964897376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2964897376
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.154382719
Short name T233
Test name
Test status
Simulation time 122863270 ps
CPU time 1.05 seconds
Started Aug 16 04:51:45 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 200588 kb
Host smart-62cba8ff-01f4-4f6f-9cdd-15e5980772c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154382719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.154382719
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3622640815
Short name T388
Test name
Test status
Simulation time 81490682 ps
CPU time 0.83 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 200308 kb
Host smart-5e25e407-c8c4-4d92-af96-48656c949e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622640815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3622640815
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.3787401338
Short name T339
Test name
Test status
Simulation time 1226201624 ps
CPU time 6.44 seconds
Started Aug 16 04:51:45 PM PDT 24
Finished Aug 16 04:51:51 PM PDT 24
Peak memory 217808 kb
Host smart-5a2dc1bf-9927-4107-916c-42528522978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787401338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3787401338
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.413518227
Short name T144
Test name
Test status
Simulation time 244288863 ps
CPU time 1.05 seconds
Started Aug 16 04:51:44 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 217800 kb
Host smart-4aba3beb-7521-4430-a50e-621973f2d55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413518227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.413518227
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1639396625
Short name T281
Test name
Test status
Simulation time 190083432 ps
CPU time 0.87 seconds
Started Aug 16 04:51:49 PM PDT 24
Finished Aug 16 04:51:50 PM PDT 24
Peak memory 200408 kb
Host smart-eb479696-718e-4072-b2e1-ca7f8e2bf886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639396625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1639396625
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3888813597
Short name T120
Test name
Test status
Simulation time 1520040621 ps
CPU time 5.83 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:52 PM PDT 24
Peak memory 200648 kb
Host smart-bbe5cf7d-c283-499c-8bad-ba9ac978fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888813597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3888813597
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1853979160
Short name T427
Test name
Test status
Simulation time 102615025 ps
CPU time 1.03 seconds
Started Aug 16 04:51:44 PM PDT 24
Finished Aug 16 04:51:45 PM PDT 24
Peak memory 200592 kb
Host smart-6de74656-6b1a-48ed-b4c7-492960595960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853979160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1853979160
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1448538413
Short name T439
Test name
Test status
Simulation time 192162002 ps
CPU time 1.42 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 200624 kb
Host smart-683292f4-5123-4578-b675-9c101c2c3961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448538413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1448538413
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.3042949350
Short name T498
Test name
Test status
Simulation time 10532706693 ps
CPU time 40.04 seconds
Started Aug 16 04:51:44 PM PDT 24
Finished Aug 16 04:52:24 PM PDT 24
Peak memory 200756 kb
Host smart-47bb4d1b-fb32-48f7-b36c-d8d634583d57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042949350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.3042949350
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.3032699758
Short name T300
Test name
Test status
Simulation time 324448871 ps
CPU time 2.04 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 208680 kb
Host smart-03526edc-ff5d-4fac-90d3-79992aae798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032699758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3032699758
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3251395201
Short name T54
Test name
Test status
Simulation time 63660692 ps
CPU time 0.77 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:47 PM PDT 24
Peak memory 200588 kb
Host smart-20328694-e27a-42d4-870a-f582036b740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251395201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3251395201
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2515695363
Short name T223
Test name
Test status
Simulation time 66531144 ps
CPU time 0.76 seconds
Started Aug 16 04:51:45 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 200468 kb
Host smart-b143df34-7d9d-4491-9d27-66365625209a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515695363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2515695363
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3429331822
Short name T341
Test name
Test status
Simulation time 1221713796 ps
CPU time 5.97 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:52 PM PDT 24
Peak memory 217924 kb
Host smart-ec669f1c-ca30-4cc2-88e9-a976e33f7c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429331822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3429331822
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3595364523
Short name T326
Test name
Test status
Simulation time 244027018 ps
CPU time 1.03 seconds
Started Aug 16 04:51:45 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 217788 kb
Host smart-3640fa5f-bbd2-4493-89b1-26fa2354814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595364523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3595364523
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.3058312064
Short name T484
Test name
Test status
Simulation time 135903004 ps
CPU time 0.83 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 200324 kb
Host smart-b0f59389-fcbf-4a88-b579-bbe30a1713b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058312064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3058312064
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2260087989
Short name T467
Test name
Test status
Simulation time 1240008721 ps
CPU time 5.58 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:52 PM PDT 24
Peak memory 200744 kb
Host smart-9e0d33de-83a7-406b-a2d9-51c006d9cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260087989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2260087989
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.499633790
Short name T539
Test name
Test status
Simulation time 105165659 ps
CPU time 1.03 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 200588 kb
Host smart-ba0ae588-0937-43e3-935a-a1961a9f609b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499633790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.499633790
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.684973841
Short name T384
Test name
Test status
Simulation time 118239959 ps
CPU time 1.1 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 200684 kb
Host smart-86a2965b-1fa2-4f19-8866-a7555150a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684973841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.684973841
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3044640077
Short name T445
Test name
Test status
Simulation time 13516561575 ps
CPU time 53.24 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:52:40 PM PDT 24
Peak memory 200860 kb
Host smart-4d87405b-c1b0-4910-be58-23819d4f9569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044640077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3044640077
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.616366366
Short name T214
Test name
Test status
Simulation time 135992375 ps
CPU time 1.86 seconds
Started Aug 16 04:51:44 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 200404 kb
Host smart-eb86848f-6717-420a-9b12-21ab7e8898b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616366366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.616366366
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.1729208585
Short name T489
Test name
Test status
Simulation time 91776589 ps
CPU time 0.89 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 200520 kb
Host smart-5bd27281-fb2f-4857-b978-4294158959f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729208585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1729208585
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.122930618
Short name T145
Test name
Test status
Simulation time 63162687 ps
CPU time 0.79 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 200416 kb
Host smart-1ef078f7-ff5c-4f93-8caf-a38be4c7b01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122930618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.122930618
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1747363465
Short name T56
Test name
Test status
Simulation time 2350301453 ps
CPU time 9.51 seconds
Started Aug 16 04:51:48 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 218068 kb
Host smart-1474811d-65bd-4d73-b9a4-92e940e23a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747363465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1747363465
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.284577382
Short name T143
Test name
Test status
Simulation time 246205825 ps
CPU time 1.1 seconds
Started Aug 16 04:51:48 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 217748 kb
Host smart-1d61db5d-6ec8-4e8e-a851-91237e01c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284577382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.284577382
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.117686650
Short name T248
Test name
Test status
Simulation time 184954390 ps
CPU time 0.85 seconds
Started Aug 16 04:51:45 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 200440 kb
Host smart-c28e1411-2087-4003-aa98-7b1c7680beca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117686650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.117686650
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.932958226
Short name T483
Test name
Test status
Simulation time 1414550925 ps
CPU time 5.75 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:53 PM PDT 24
Peak memory 200820 kb
Host smart-83f45813-409c-4a57-94fb-7088415dccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932958226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.932958226
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.697469284
Short name T463
Test name
Test status
Simulation time 153194478 ps
CPU time 1.18 seconds
Started Aug 16 04:51:49 PM PDT 24
Finished Aug 16 04:51:50 PM PDT 24
Peak memory 200612 kb
Host smart-74f383ca-4d4c-43f3-8b61-0c90fe92334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697469284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.697469284
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.788161300
Short name T198
Test name
Test status
Simulation time 192370328 ps
CPU time 1.39 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 200608 kb
Host smart-2f5ee8bf-44b6-422a-8f66-68d9afb06789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788161300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.788161300
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.1531648484
Short name T99
Test name
Test status
Simulation time 4205400662 ps
CPU time 15.25 seconds
Started Aug 16 04:51:48 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 208896 kb
Host smart-be474900-72b7-44d5-b0ee-758930566ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531648484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1531648484
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.1707518197
Short name T234
Test name
Test status
Simulation time 131198024 ps
CPU time 1.58 seconds
Started Aug 16 04:51:44 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 200396 kb
Host smart-76c96aeb-7454-4589-bd82-79614441f71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707518197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1707518197
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1026720016
Short name T486
Test name
Test status
Simulation time 112246501 ps
CPU time 1.02 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:47 PM PDT 24
Peak memory 200484 kb
Host smart-c4e45882-d0cc-4d98-9153-1ad0dffd948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026720016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1026720016
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1490336716
Short name T431
Test name
Test status
Simulation time 74244994 ps
CPU time 0.79 seconds
Started Aug 16 04:51:55 PM PDT 24
Finished Aug 16 04:51:56 PM PDT 24
Peak memory 200348 kb
Host smart-3d5226f9-3837-4299-ae26-8290f45072c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490336716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1490336716
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.679037307
Short name T55
Test name
Test status
Simulation time 1219114342 ps
CPU time 5.68 seconds
Started Aug 16 04:51:49 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 218012 kb
Host smart-3ed8b50a-73a7-46bc-a76c-60b86b348ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679037307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.679037307
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.141626484
Short name T433
Test name
Test status
Simulation time 244825924 ps
CPU time 1.07 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 217808 kb
Host smart-ce882bd9-3af8-47ac-a8e5-1b2c4352cd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141626484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.141626484
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.1446674566
Short name T227
Test name
Test status
Simulation time 101814889 ps
CPU time 0.76 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 200408 kb
Host smart-ce788d84-09de-47e8-b398-47e9a04d8dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446674566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1446674566
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4210570159
Short name T358
Test name
Test status
Simulation time 1259127915 ps
CPU time 5.33 seconds
Started Aug 16 04:51:48 PM PDT 24
Finished Aug 16 04:51:54 PM PDT 24
Peak memory 200652 kb
Host smart-5ef353c9-64ea-4c7f-bdbb-c2a91f92381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210570159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4210570159
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.839274128
Short name T345
Test name
Test status
Simulation time 156119594 ps
CPU time 1.17 seconds
Started Aug 16 04:51:48 PM PDT 24
Finished Aug 16 04:51:50 PM PDT 24
Peak memory 200588 kb
Host smart-4e1ef44c-fe80-40d7-b218-d89bfd0fae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839274128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.839274128
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2854577195
Short name T320
Test name
Test status
Simulation time 118660115 ps
CPU time 1.26 seconds
Started Aug 16 04:51:46 PM PDT 24
Finished Aug 16 04:51:47 PM PDT 24
Peak memory 200600 kb
Host smart-ea79ee7a-ff6d-4ffd-afc8-27e74acdccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854577195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2854577195
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2386331912
Short name T193
Test name
Test status
Simulation time 5687196886 ps
CPU time 22.73 seconds
Started Aug 16 04:51:53 PM PDT 24
Finished Aug 16 04:52:16 PM PDT 24
Peak memory 200808 kb
Host smart-fac2b073-4812-466a-9ca8-58e908fc01f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386331912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2386331912
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2660305442
Short name T481
Test name
Test status
Simulation time 268582520 ps
CPU time 1.82 seconds
Started Aug 16 04:51:47 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 200484 kb
Host smart-ac8e373a-7757-42af-8728-751760735913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660305442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2660305442
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1902396958
Short name T407
Test name
Test status
Simulation time 119536277 ps
CPU time 1.09 seconds
Started Aug 16 04:51:48 PM PDT 24
Finished Aug 16 04:51:49 PM PDT 24
Peak memory 200568 kb
Host smart-2ef910ab-117a-4f3e-8841-eb26e981a8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902396958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1902396958
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3686423618
Short name T459
Test name
Test status
Simulation time 74111620 ps
CPU time 0.82 seconds
Started Aug 16 04:51:53 PM PDT 24
Finished Aug 16 04:51:54 PM PDT 24
Peak memory 200380 kb
Host smart-cdc12157-a78b-4990-a920-122d025a1834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686423618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3686423618
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.4030219394
Short name T363
Test name
Test status
Simulation time 1226086023 ps
CPU time 5.5 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 221888 kb
Host smart-9f2f65da-91b0-463c-b788-ab846c50bf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030219394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.4030219394
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1110502062
Short name T448
Test name
Test status
Simulation time 245371427 ps
CPU time 1.06 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 217696 kb
Host smart-7681fc9b-fc65-42e7-9b62-d8dc5b14e5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110502062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1110502062
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1745811223
Short name T19
Test name
Test status
Simulation time 123499213 ps
CPU time 0.85 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:51:53 PM PDT 24
Peak memory 200320 kb
Host smart-79450078-3a69-40aa-a250-02a6646e9548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745811223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1745811223
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.468485560
Short name T228
Test name
Test status
Simulation time 885864508 ps
CPU time 5.03 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:05 PM PDT 24
Peak memory 200704 kb
Host smart-98c8f902-cb76-4b9d-9206-ed82e8145b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468485560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.468485560
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.885996858
Short name T164
Test name
Test status
Simulation time 142234423 ps
CPU time 1.14 seconds
Started Aug 16 04:51:59 PM PDT 24
Finished Aug 16 04:52:00 PM PDT 24
Peak memory 200524 kb
Host smart-3a25730f-facf-46b2-8bdd-9b6e24052ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885996858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.885996858
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.2670026299
Short name T168
Test name
Test status
Simulation time 110326292 ps
CPU time 1.15 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200580 kb
Host smart-0e92330f-90bb-4860-b7cb-9bd752761c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670026299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2670026299
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.3518260430
Short name T247
Test name
Test status
Simulation time 3259344832 ps
CPU time 14.86 seconds
Started Aug 16 04:51:55 PM PDT 24
Finished Aug 16 04:52:10 PM PDT 24
Peak memory 200704 kb
Host smart-38e5fd17-74cd-4cd2-b753-b168ef8b7401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518260430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3518260430
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4124168418
Short name T24
Test name
Test status
Simulation time 133778168 ps
CPU time 1.14 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:51:53 PM PDT 24
Peak memory 200604 kb
Host smart-0a037565-bdcc-4911-9e9f-eb0104f845cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124168418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4124168418
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.4170009080
Short name T409
Test name
Test status
Simulation time 65488596 ps
CPU time 0.8 seconds
Started Aug 16 04:51:54 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 200440 kb
Host smart-7d9ad213-27d6-4b5d-bb9a-f5f33bfbecc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170009080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4170009080
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2296363241
Short name T35
Test name
Test status
Simulation time 1233582361 ps
CPU time 6.14 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 216972 kb
Host smart-854eca10-2cb6-4b4e-a4e5-d74385d0b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296363241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2296363241
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.2727910900
Short name T361
Test name
Test status
Simulation time 244531399 ps
CPU time 1.13 seconds
Started Aug 16 04:51:57 PM PDT 24
Finished Aug 16 04:51:59 PM PDT 24
Peak memory 217800 kb
Host smart-86a9859d-ca89-4c1b-ad95-f2e00679d3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727910900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.2727910900
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1876293071
Short name T15
Test name
Test status
Simulation time 200615457 ps
CPU time 0.87 seconds
Started Aug 16 04:51:57 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200348 kb
Host smart-0c553104-e77c-4659-a799-dfd72a169fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876293071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1876293071
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.492456974
Short name T374
Test name
Test status
Simulation time 1159663345 ps
CPU time 4.59 seconds
Started Aug 16 04:51:53 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 200796 kb
Host smart-cf6683b1-95de-4a59-a031-2134036a9552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492456974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.492456974
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.958132161
Short name T456
Test name
Test status
Simulation time 113320578 ps
CPU time 1.06 seconds
Started Aug 16 04:51:58 PM PDT 24
Finished Aug 16 04:51:59 PM PDT 24
Peak memory 200436 kb
Host smart-763057f1-960c-4542-a12b-a8dace79b593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958132161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.958132161
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.127782170
Short name T171
Test name
Test status
Simulation time 119828159 ps
CPU time 1.26 seconds
Started Aug 16 04:51:58 PM PDT 24
Finished Aug 16 04:51:59 PM PDT 24
Peak memory 200672 kb
Host smart-7fdf51e6-1c21-4a21-b49a-3d5816d6da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127782170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.127782170
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.3215842124
Short name T94
Test name
Test status
Simulation time 2216332743 ps
CPU time 10.6 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 208912 kb
Host smart-51b551fa-57f8-4917-89f2-7214602e39ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215842124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3215842124
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.48701407
Short name T330
Test name
Test status
Simulation time 142868360 ps
CPU time 1.87 seconds
Started Aug 16 04:51:57 PM PDT 24
Finished Aug 16 04:51:59 PM PDT 24
Peak memory 200388 kb
Host smart-1191e2fa-c486-4db8-ad65-8a1e637e426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48701407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.48701407
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.2370760315
Short name T436
Test name
Test status
Simulation time 83947511 ps
CPU time 0.85 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 200500 kb
Host smart-180ac84c-0595-4cb1-812f-aeb1d0057a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370760315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2370760315
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.4108583303
Short name T401
Test name
Test status
Simulation time 62374579 ps
CPU time 0.79 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:51:53 PM PDT 24
Peak memory 200376 kb
Host smart-fe105168-de80-4631-a4da-e4a4c59d7791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108583303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4108583303
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2505805433
Short name T38
Test name
Test status
Simulation time 2177090988 ps
CPU time 8.56 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:52:01 PM PDT 24
Peak memory 221956 kb
Host smart-68ce9d6e-d505-4924-94a0-b6dc50f18280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505805433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2505805433
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4152553046
Short name T404
Test name
Test status
Simulation time 244566996 ps
CPU time 1.14 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 217752 kb
Host smart-40137a9c-9939-4de2-9524-08c50406fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152553046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4152553046
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.2789618515
Short name T22
Test name
Test status
Simulation time 187191120 ps
CPU time 0.85 seconds
Started Aug 16 04:51:58 PM PDT 24
Finished Aug 16 04:51:59 PM PDT 24
Peak memory 200244 kb
Host smart-d8fb0121-9c45-4b52-a927-00ba8f90b524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789618515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2789618515
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3561999203
Short name T147
Test name
Test status
Simulation time 1300632614 ps
CPU time 5.05 seconds
Started Aug 16 04:51:55 PM PDT 24
Finished Aug 16 04:52:00 PM PDT 24
Peak memory 200660 kb
Host smart-9516cd19-6ef6-4c40-92b0-36bdd03809e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561999203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3561999203
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4153683470
Short name T425
Test name
Test status
Simulation time 108859388 ps
CPU time 1.02 seconds
Started Aug 16 04:51:54 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 200536 kb
Host smart-fdae03ba-2b6c-423e-9774-97f925ee368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153683470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4153683470
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2071428777
Short name T288
Test name
Test status
Simulation time 199583195 ps
CPU time 1.41 seconds
Started Aug 16 04:51:57 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200708 kb
Host smart-e2ac2500-7c0e-4d86-9cb3-1aea4e685fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071428777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2071428777
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.699743316
Short name T192
Test name
Test status
Simulation time 2738557575 ps
CPU time 9.81 seconds
Started Aug 16 04:51:55 PM PDT 24
Finished Aug 16 04:52:05 PM PDT 24
Peak memory 200760 kb
Host smart-227977b2-446d-4216-8e90-85420b6050bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699743316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.699743316
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.3916860627
Short name T429
Test name
Test status
Simulation time 108533626 ps
CPU time 1.48 seconds
Started Aug 16 04:51:58 PM PDT 24
Finished Aug 16 04:51:59 PM PDT 24
Peak memory 200444 kb
Host smart-b172dadd-ed55-4c1d-afb1-333b928b58ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916860627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3916860627
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.84061813
Short name T189
Test name
Test status
Simulation time 61662551 ps
CPU time 0.77 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:25 PM PDT 24
Peak memory 200336 kb
Host smart-de6cb95e-8649-48f6-b795-d8cde41bfe3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84061813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.84061813
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2347483358
Short name T408
Test name
Test status
Simulation time 1892050463 ps
CPU time 7.51 seconds
Started Aug 16 04:51:27 PM PDT 24
Finished Aug 16 04:51:35 PM PDT 24
Peak memory 217644 kb
Host smart-d280efc6-856a-4a88-82c6-c93180cb8e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347483358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2347483358
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.824091040
Short name T176
Test name
Test status
Simulation time 245617567 ps
CPU time 1.05 seconds
Started Aug 16 04:51:25 PM PDT 24
Finished Aug 16 04:51:26 PM PDT 24
Peak memory 217816 kb
Host smart-fab24019-db00-4200-9293-1f9b7c6fbbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824091040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.824091040
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1325966423
Short name T23
Test name
Test status
Simulation time 125208278 ps
CPU time 0.82 seconds
Started Aug 16 04:51:27 PM PDT 24
Finished Aug 16 04:51:28 PM PDT 24
Peak memory 200368 kb
Host smart-9f11786d-00a6-42fc-b581-7db1a31a70f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325966423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1325966423
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1024712199
Short name T97
Test name
Test status
Simulation time 751123341 ps
CPU time 4.02 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:28 PM PDT 24
Peak memory 200680 kb
Host smart-c24be6d8-88c2-4446-bf13-f05a98040f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024712199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1024712199
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.530925291
Short name T71
Test name
Test status
Simulation time 8355396999 ps
CPU time 13.46 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:37 PM PDT 24
Peak memory 217208 kb
Host smart-af17b1f0-87bc-4b72-9b66-ca0c2b59e59e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530925291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.530925291
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2420559765
Short name T256
Test name
Test status
Simulation time 143452953 ps
CPU time 1.09 seconds
Started Aug 16 04:51:26 PM PDT 24
Finished Aug 16 04:51:27 PM PDT 24
Peak memory 200592 kb
Host smart-8c3e9125-b0c2-4d28-b85c-d7e302dbd3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420559765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2420559765
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2083311462
Short name T305
Test name
Test status
Simulation time 195817734 ps
CPU time 1.34 seconds
Started Aug 16 04:51:25 PM PDT 24
Finished Aug 16 04:51:27 PM PDT 24
Peak memory 200764 kb
Host smart-34328522-710b-4d0b-9f75-a1f798bdd780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083311462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2083311462
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.3753236890
Short name T173
Test name
Test status
Simulation time 514867374 ps
CPU time 2.87 seconds
Started Aug 16 04:51:26 PM PDT 24
Finished Aug 16 04:51:29 PM PDT 24
Peak memory 200428 kb
Host smart-2819d131-b6f2-4362-8145-a337eb11a988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753236890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.3753236890
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.4011383365
Short name T473
Test name
Test status
Simulation time 142333169 ps
CPU time 1.17 seconds
Started Aug 16 04:51:23 PM PDT 24
Finished Aug 16 04:51:24 PM PDT 24
Peak memory 200548 kb
Host smart-53870a26-496a-446a-84d9-0ad8e71c437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011383365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4011383365
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1106578028
Short name T530
Test name
Test status
Simulation time 72746457 ps
CPU time 0.76 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:51:53 PM PDT 24
Peak memory 200492 kb
Host smart-7a4b9453-41a7-4edb-ac92-0d409bfdbb5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106578028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1106578028
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2607097738
Short name T356
Test name
Test status
Simulation time 1223954312 ps
CPU time 5.96 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 221888 kb
Host smart-644f8c18-c762-4cca-9564-754fc32009e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607097738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2607097738
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1019251543
Short name T522
Test name
Test status
Simulation time 244115667 ps
CPU time 1.1 seconds
Started Aug 16 04:51:54 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 217696 kb
Host smart-1e2fbbf9-80cb-4594-8bce-708e26f68750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019251543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1019251543
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3318379087
Short name T217
Test name
Test status
Simulation time 94247704 ps
CPU time 0.78 seconds
Started Aug 16 04:51:53 PM PDT 24
Finished Aug 16 04:51:54 PM PDT 24
Peak memory 200316 kb
Host smart-c36e3171-c371-45a2-bf82-06663b726b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318379087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3318379087
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.3472568598
Short name T502
Test name
Test status
Simulation time 1616746375 ps
CPU time 6.47 seconds
Started Aug 16 04:51:55 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 200676 kb
Host smart-1d996332-3f40-47f2-84ac-90d3b1b21716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472568598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3472568598
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1987189360
Short name T273
Test name
Test status
Simulation time 160622964 ps
CPU time 1.24 seconds
Started Aug 16 04:51:57 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200620 kb
Host smart-eb264113-e95f-4664-aaf9-53c29237a2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987189360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1987189360
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.239672441
Short name T480
Test name
Test status
Simulation time 192119259 ps
CPU time 1.3 seconds
Started Aug 16 04:51:54 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 200752 kb
Host smart-865a7c68-379e-4dbc-80c2-93dd248c458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239672441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.239672441
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.3429508980
Short name T472
Test name
Test status
Simulation time 4845321328 ps
CPU time 18.86 seconds
Started Aug 16 04:51:54 PM PDT 24
Finished Aug 16 04:52:13 PM PDT 24
Peak memory 208924 kb
Host smart-4cfc8a99-566e-4477-9e75-3b07c3de6044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429508980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.3429508980
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.3930601357
Short name T243
Test name
Test status
Simulation time 134033879 ps
CPU time 1.83 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200392 kb
Host smart-4d50691b-5f9f-460b-b52d-ccb42c4d3cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930601357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3930601357
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1663005534
Short name T134
Test name
Test status
Simulation time 102540787 ps
CPU time 0.99 seconds
Started Aug 16 04:51:57 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200592 kb
Host smart-fd55d5c7-5762-45d3-897a-73e48f41f0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663005534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1663005534
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2975793928
Short name T156
Test name
Test status
Simulation time 73531263 ps
CPU time 0.76 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:51:53 PM PDT 24
Peak memory 200432 kb
Host smart-12264d34-f81c-458f-8789-ed01842ffefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975793928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2975793928
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1285951298
Short name T423
Test name
Test status
Simulation time 1211253903 ps
CPU time 5.63 seconds
Started Aug 16 04:51:54 PM PDT 24
Finished Aug 16 04:52:00 PM PDT 24
Peak memory 221884 kb
Host smart-2faa5873-ecdf-4be8-85b0-b13b75c36b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285951298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1285951298
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.3136990035
Short name T317
Test name
Test status
Simulation time 250403086 ps
CPU time 1.04 seconds
Started Aug 16 04:51:57 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 217696 kb
Host smart-ad610f65-a3c1-4ad0-9fbb-e79d012f9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136990035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.3136990035
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2844661625
Short name T177
Test name
Test status
Simulation time 208321136 ps
CPU time 0.9 seconds
Started Aug 16 04:51:58 PM PDT 24
Finished Aug 16 04:51:59 PM PDT 24
Peak memory 200364 kb
Host smart-df2c877d-3850-4004-9fa6-66b6e72306d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844661625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2844661625
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3129089559
Short name T476
Test name
Test status
Simulation time 1532118192 ps
CPU time 6.08 seconds
Started Aug 16 04:51:52 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200744 kb
Host smart-a37a2e62-d054-4da0-81c4-7eb07f89a06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129089559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3129089559
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1679228280
Short name T370
Test name
Test status
Simulation time 140777319 ps
CPU time 1.1 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 200584 kb
Host smart-ebaa336e-1632-495d-83ba-1aa8e379e790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679228280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1679228280
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3774557116
Short name T528
Test name
Test status
Simulation time 117164121 ps
CPU time 1.26 seconds
Started Aug 16 04:51:57 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200632 kb
Host smart-d94bd29f-f0e0-437b-a1dc-14eee206f290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774557116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3774557116
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3301643066
Short name T237
Test name
Test status
Simulation time 3038180519 ps
CPU time 13.09 seconds
Started Aug 16 04:51:55 PM PDT 24
Finished Aug 16 04:52:08 PM PDT 24
Peak memory 200760 kb
Host smart-904695d4-814f-41de-b817-c6f036e4d5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301643066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3301643066
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.27888824
Short name T142
Test name
Test status
Simulation time 116065104 ps
CPU time 1.57 seconds
Started Aug 16 04:51:53 PM PDT 24
Finished Aug 16 04:51:54 PM PDT 24
Peak memory 200488 kb
Host smart-25d6fc54-7678-4971-ba2d-52b27f37b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27888824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.27888824
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3780929653
Short name T132
Test name
Test status
Simulation time 98445111 ps
CPU time 0.98 seconds
Started Aug 16 04:51:54 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 200540 kb
Host smart-a2b2bd3d-67d3-4a1d-92f3-a8fa935a070a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780929653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3780929653
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2943907457
Short name T413
Test name
Test status
Simulation time 1229911941 ps
CPU time 5.68 seconds
Started Aug 16 04:51:51 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 217660 kb
Host smart-c6b9d079-8486-454d-b7e9-aab86f278c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943907457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2943907457
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1706563650
Short name T460
Test name
Test status
Simulation time 245209411 ps
CPU time 1.2 seconds
Started Aug 16 04:52:02 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 217712 kb
Host smart-b51f84eb-950e-417a-acbc-8c41c660655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706563650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1706563650
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.4156090529
Short name T334
Test name
Test status
Simulation time 120194375 ps
CPU time 0.78 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 200404 kb
Host smart-1adc0881-7fa5-441c-ba5b-490314502828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156090529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.4156090529
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.2991732899
Short name T58
Test name
Test status
Simulation time 1024408089 ps
CPU time 4.93 seconds
Started Aug 16 04:51:54 PM PDT 24
Finished Aug 16 04:51:59 PM PDT 24
Peak memory 200764 kb
Host smart-e544ae58-8945-4901-95b2-f77f15741d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991732899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2991732899
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.358769442
Short name T162
Test name
Test status
Simulation time 153748638 ps
CPU time 1.23 seconds
Started Aug 16 04:51:56 PM PDT 24
Finished Aug 16 04:51:58 PM PDT 24
Peak memory 200492 kb
Host smart-2b0715d8-3ede-468b-812b-a5a238501136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358769442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.358769442
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.4143881654
Short name T349
Test name
Test status
Simulation time 246447983 ps
CPU time 1.48 seconds
Started Aug 16 04:51:53 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 200724 kb
Host smart-202b0046-f22f-4d67-b7b6-8fdaedb36ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143881654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4143881654
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1821332942
Short name T78
Test name
Test status
Simulation time 1074120365 ps
CPU time 5.64 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:06 PM PDT 24
Peak memory 208916 kb
Host smart-4c5007c1-78d4-48de-84d8-a9045022baf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821332942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1821332942
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.2285896521
Short name T359
Test name
Test status
Simulation time 352732305 ps
CPU time 2.3 seconds
Started Aug 16 04:51:53 PM PDT 24
Finished Aug 16 04:51:55 PM PDT 24
Peak memory 200364 kb
Host smart-d164be87-b2c7-4ac5-a70e-59b3fc1547b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285896521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.2285896521
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.506447993
Short name T204
Test name
Test status
Simulation time 218527252 ps
CPU time 1.35 seconds
Started Aug 16 04:51:55 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 200452 kb
Host smart-9cf0a2fc-8a5d-418f-9e23-cd978a8f5c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506447993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.506447993
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.329678314
Short name T323
Test name
Test status
Simulation time 77416313 ps
CPU time 0.83 seconds
Started Aug 16 04:52:05 PM PDT 24
Finished Aug 16 04:52:06 PM PDT 24
Peak memory 200464 kb
Host smart-7d72676b-1d44-4919-9b72-468c9485b97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329678314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.329678314
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.874490688
Short name T43
Test name
Test status
Simulation time 1228299355 ps
CPU time 6.05 seconds
Started Aug 16 04:51:59 PM PDT 24
Finished Aug 16 04:52:05 PM PDT 24
Peak memory 221864 kb
Host smart-936f3d52-9e43-4cd1-9a24-6965b4b44ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874490688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.874490688
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.677617570
Short name T490
Test name
Test status
Simulation time 244706569 ps
CPU time 1.21 seconds
Started Aug 16 04:52:01 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 217752 kb
Host smart-1b006895-c1b6-451f-b66e-b556310e573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677617570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.677617570
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3536001267
Short name T355
Test name
Test status
Simulation time 168195061 ps
CPU time 0.85 seconds
Started Aug 16 04:52:02 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 200288 kb
Host smart-455ac590-e9c7-4054-89e1-5f772b3f31c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536001267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3536001267
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2742948338
Short name T27
Test name
Test status
Simulation time 1467877745 ps
CPU time 6.18 seconds
Started Aug 16 04:52:03 PM PDT 24
Finished Aug 16 04:52:10 PM PDT 24
Peak memory 200824 kb
Host smart-85d2ab0d-badd-4106-9cb0-612a256b14de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742948338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2742948338
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3135537238
Short name T520
Test name
Test status
Simulation time 157534171 ps
CPU time 1.17 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:01 PM PDT 24
Peak memory 200504 kb
Host smart-7c6f001e-2061-4f81-a1d6-2cd9e51f226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135537238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3135537238
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.427170370
Short name T79
Test name
Test status
Simulation time 202481604 ps
CPU time 1.48 seconds
Started Aug 16 04:52:03 PM PDT 24
Finished Aug 16 04:52:05 PM PDT 24
Peak memory 200532 kb
Host smart-4eac9f09-1b5b-4607-97a8-80960afb397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427170370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.427170370
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2879990560
Short name T412
Test name
Test status
Simulation time 6524633450 ps
CPU time 28.44 seconds
Started Aug 16 04:52:05 PM PDT 24
Finished Aug 16 04:52:34 PM PDT 24
Peak memory 209020 kb
Host smart-236bc9d3-e1ea-4231-9a17-405282afd9ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879990560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2879990560
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3788647567
Short name T513
Test name
Test status
Simulation time 137488780 ps
CPU time 1.88 seconds
Started Aug 16 04:51:59 PM PDT 24
Finished Aug 16 04:52:00 PM PDT 24
Peak memory 200484 kb
Host smart-2aeb23f2-d8dd-4a08-a2fc-2c1ab1df8009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788647567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3788647567
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4146446112
Short name T229
Test name
Test status
Simulation time 162743045 ps
CPU time 1.21 seconds
Started Aug 16 04:52:03 PM PDT 24
Finished Aug 16 04:52:05 PM PDT 24
Peak memory 200540 kb
Host smart-46d8bc45-8638-47dd-b30c-395628848425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146446112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4146446112
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1868004589
Short name T170
Test name
Test status
Simulation time 89036826 ps
CPU time 0.86 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:01 PM PDT 24
Peak memory 200452 kb
Host smart-b0db69ff-69c3-4998-95cd-2c79ebc7920f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868004589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1868004589
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.4220902122
Short name T424
Test name
Test status
Simulation time 1914137179 ps
CPU time 7.17 seconds
Started Aug 16 04:52:02 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 221888 kb
Host smart-7e69406a-bbb2-4828-9f7b-aeb42e7a151b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220902122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.4220902122
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2741258235
Short name T432
Test name
Test status
Simulation time 244618518 ps
CPU time 1.05 seconds
Started Aug 16 04:52:02 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 217704 kb
Host smart-ba5bdd57-c236-4602-89b4-61c35f223180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741258235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2741258235
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1563210364
Short name T252
Test name
Test status
Simulation time 117534871 ps
CPU time 0.88 seconds
Started Aug 16 04:52:02 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 200340 kb
Host smart-7f0bfad5-0b06-4b9a-89e1-d906ef9c11c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563210364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1563210364
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2343085628
Short name T536
Test name
Test status
Simulation time 1732297633 ps
CPU time 7.17 seconds
Started Aug 16 04:52:04 PM PDT 24
Finished Aug 16 04:52:11 PM PDT 24
Peak memory 200748 kb
Host smart-c61ac723-b399-4b5a-a087-081418456c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343085628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2343085628
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.874385272
Short name T267
Test name
Test status
Simulation time 96897485 ps
CPU time 1.05 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 200588 kb
Host smart-cef84378-d0e2-44a9-a7ed-7341fbb42f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874385272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.874385272
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2698887695
Short name T12
Test name
Test status
Simulation time 194167157 ps
CPU time 1.53 seconds
Started Aug 16 04:52:03 PM PDT 24
Finished Aug 16 04:52:05 PM PDT 24
Peak memory 200804 kb
Host smart-ff56a511-6397-4523-955d-7a50ef227d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698887695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2698887695
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.3777745352
Short name T468
Test name
Test status
Simulation time 6219083175 ps
CPU time 23.7 seconds
Started Aug 16 04:52:02 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 209016 kb
Host smart-f71620b8-1d29-4920-8f16-24866fa45eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777745352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3777745352
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.2620960635
Short name T3
Test name
Test status
Simulation time 302915444 ps
CPU time 2.03 seconds
Started Aug 16 04:52:01 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 208684 kb
Host smart-307515c2-f936-4ded-a3a5-9a974b893d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620960635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2620960635
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2563322076
Short name T357
Test name
Test status
Simulation time 76742539 ps
CPU time 0.8 seconds
Started Aug 16 04:52:01 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 200724 kb
Host smart-f9d689f9-3d23-49d6-84a4-7c6849ba1c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563322076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2563322076
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.806893810
Short name T210
Test name
Test status
Simulation time 59114656 ps
CPU time 0.76 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:01 PM PDT 24
Peak memory 200460 kb
Host smart-b3661614-12c0-422a-a0ca-c753006d56f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806893810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.806893810
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.1467468027
Short name T399
Test name
Test status
Simulation time 1226085206 ps
CPU time 5.59 seconds
Started Aug 16 04:52:02 PM PDT 24
Finished Aug 16 04:52:08 PM PDT 24
Peak memory 221828 kb
Host smart-56b80b2b-5842-4ec9-b5d0-76be10860351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467468027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1467468027
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.913590754
Short name T146
Test name
Test status
Simulation time 243909652 ps
CPU time 1.1 seconds
Started Aug 16 04:52:01 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 217860 kb
Host smart-d6657253-9cc4-4fbd-8399-f9a8aa97484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913590754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.913590754
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.2227084798
Short name T523
Test name
Test status
Simulation time 112780225 ps
CPU time 0.82 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:01 PM PDT 24
Peak memory 200300 kb
Host smart-83ea98be-ffc5-4020-8592-d0734ebb9120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227084798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2227084798
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.2197069868
Short name T8
Test name
Test status
Simulation time 2207300658 ps
CPU time 8.4 seconds
Started Aug 16 04:52:00 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 200952 kb
Host smart-02d44cc7-f8c3-49c1-be9a-44dc8cd4e6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197069868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.2197069868
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2761943605
Short name T206
Test name
Test status
Simulation time 100700882 ps
CPU time 1.01 seconds
Started Aug 16 04:52:05 PM PDT 24
Finished Aug 16 04:52:06 PM PDT 24
Peak memory 200460 kb
Host smart-a8a1ffc7-27ef-4bf0-8e6a-ccb3b82bb3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761943605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2761943605
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.993446279
Short name T161
Test name
Test status
Simulation time 201200852 ps
CPU time 1.47 seconds
Started Aug 16 04:52:01 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 200672 kb
Host smart-401cea10-8413-4daa-a174-f6bf7b466e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993446279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.993446279
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.1941463428
Short name T541
Test name
Test status
Simulation time 11786087527 ps
CPU time 43.22 seconds
Started Aug 16 04:52:01 PM PDT 24
Finished Aug 16 04:52:44 PM PDT 24
Peak memory 200776 kb
Host smart-212b3d3a-05e8-45ac-99d5-8074f0b526ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941463428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1941463428
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2476977293
Short name T298
Test name
Test status
Simulation time 381238458 ps
CPU time 2.38 seconds
Started Aug 16 04:51:59 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 208712 kb
Host smart-b0e7fc8c-5505-4ded-8acb-a7a8e44f88f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476977293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2476977293
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1505051340
Short name T295
Test name
Test status
Simulation time 88241129 ps
CPU time 0.85 seconds
Started Aug 16 04:52:03 PM PDT 24
Finished Aug 16 04:52:04 PM PDT 24
Peak memory 200440 kb
Host smart-40025391-042d-4083-b986-809228dca7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505051340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1505051340
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4183199553
Short name T250
Test name
Test status
Simulation time 82611331 ps
CPU time 0.83 seconds
Started Aug 16 04:52:05 PM PDT 24
Finished Aug 16 04:52:06 PM PDT 24
Peak memory 200328 kb
Host smart-67f62e80-4569-4547-a124-54ae3042ebef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183199553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4183199553
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1441939719
Short name T199
Test name
Test status
Simulation time 243995153 ps
CPU time 1.05 seconds
Started Aug 16 04:52:03 PM PDT 24
Finished Aug 16 04:52:04 PM PDT 24
Peak memory 217716 kb
Host smart-56b78cc0-8484-4e77-914f-bf591e0f4a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441939719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1441939719
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.603171684
Short name T20
Test name
Test status
Simulation time 182234832 ps
CPU time 0.92 seconds
Started Aug 16 04:51:59 PM PDT 24
Finished Aug 16 04:52:00 PM PDT 24
Peak memory 200396 kb
Host smart-95798640-3fd3-45fb-b5c1-12d2b8dff7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603171684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.603171684
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.3808365600
Short name T59
Test name
Test status
Simulation time 1318325555 ps
CPU time 5.21 seconds
Started Aug 16 04:51:59 PM PDT 24
Finished Aug 16 04:52:04 PM PDT 24
Peak memory 200748 kb
Host smart-98634a2a-4046-48fc-abb7-7ac30b2f046d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808365600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3808365600
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3196464275
Short name T131
Test name
Test status
Simulation time 185702852 ps
CPU time 1.28 seconds
Started Aug 16 04:52:02 PM PDT 24
Finished Aug 16 04:52:04 PM PDT 24
Peak memory 200592 kb
Host smart-b4924f28-72d6-44b0-95bf-f1a37a1fc1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196464275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3196464275
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.1991945121
Short name T438
Test name
Test status
Simulation time 110406134 ps
CPU time 1.2 seconds
Started Aug 16 04:51:59 PM PDT 24
Finished Aug 16 04:52:00 PM PDT 24
Peak memory 200556 kb
Host smart-dc07daef-9a7c-4182-b68a-536d0635fc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991945121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.1991945121
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.2039279387
Short name T226
Test name
Test status
Simulation time 382041975 ps
CPU time 2.64 seconds
Started Aug 16 04:52:05 PM PDT 24
Finished Aug 16 04:52:08 PM PDT 24
Peak memory 200548 kb
Host smart-98dc23a3-2f85-4500-b196-09c64f978fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039279387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2039279387
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2885012305
Short name T126
Test name
Test status
Simulation time 508083126 ps
CPU time 2.67 seconds
Started Aug 16 04:51:59 PM PDT 24
Finished Aug 16 04:52:02 PM PDT 24
Peak memory 200484 kb
Host smart-ec8ad30c-d588-4476-85e9-53824712ae07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885012305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2885012305
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.262296886
Short name T244
Test name
Test status
Simulation time 152028100 ps
CPU time 1.14 seconds
Started Aug 16 04:52:04 PM PDT 24
Finished Aug 16 04:52:05 PM PDT 24
Peak memory 200596 kb
Host smart-1f44cb70-446e-4a2f-af79-adaf0b44559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262296886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.262296886
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3693427357
Short name T333
Test name
Test status
Simulation time 71447201 ps
CPU time 0.8 seconds
Started Aug 16 04:52:09 PM PDT 24
Finished Aug 16 04:52:10 PM PDT 24
Peak memory 200412 kb
Host smart-b56d8fd3-a38b-4f9f-8f40-f59517d5c71e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693427357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3693427357
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.2702486775
Short name T471
Test name
Test status
Simulation time 2343137287 ps
CPU time 9.14 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 218144 kb
Host smart-002f8bd2-0ae4-49c9-aa8c-ab67729653ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702486775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2702486775
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.3128756080
Short name T293
Test name
Test status
Simulation time 250493685 ps
CPU time 1.05 seconds
Started Aug 16 04:52:06 PM PDT 24
Finished Aug 16 04:52:07 PM PDT 24
Peak memory 217724 kb
Host smart-9c099914-609b-40b8-97e9-ace66e20615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128756080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.3128756080
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3159055898
Short name T364
Test name
Test status
Simulation time 127701521 ps
CPU time 0.82 seconds
Started Aug 16 04:52:04 PM PDT 24
Finished Aug 16 04:52:05 PM PDT 24
Peak memory 200248 kb
Host smart-ae20f8e4-7ab2-46e9-9ddf-a343cfad3776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159055898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3159055898
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.3942097297
Short name T74
Test name
Test status
Simulation time 1693508147 ps
CPU time 6.08 seconds
Started Aug 16 04:52:01 PM PDT 24
Finished Aug 16 04:52:07 PM PDT 24
Peak memory 200688 kb
Host smart-6141eb80-36d5-4df6-8a31-31efd5d82480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942097297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3942097297
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2102315879
Short name T130
Test name
Test status
Simulation time 109195762 ps
CPU time 1.05 seconds
Started Aug 16 04:52:09 PM PDT 24
Finished Aug 16 04:52:10 PM PDT 24
Peak memory 200540 kb
Host smart-e8de5db2-d423-4795-942f-8f07496fd7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102315879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2102315879
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2489999580
Short name T521
Test name
Test status
Simulation time 117824638 ps
CPU time 1.16 seconds
Started Aug 16 04:52:03 PM PDT 24
Finished Aug 16 04:52:04 PM PDT 24
Peak memory 200600 kb
Host smart-78c761b8-0ad1-480f-8cf5-92ee620cbe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489999580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2489999580
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3810038954
Short name T392
Test name
Test status
Simulation time 158523933 ps
CPU time 1.13 seconds
Started Aug 16 04:52:11 PM PDT 24
Finished Aug 16 04:52:13 PM PDT 24
Peak memory 200596 kb
Host smart-21434682-aa50-467c-bb71-71038c95648f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810038954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3810038954
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1172106106
Short name T183
Test name
Test status
Simulation time 129538308 ps
CPU time 1.71 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:08 PM PDT 24
Peak memory 208716 kb
Host smart-39b73b4e-ddcb-4d80-8010-9c928285a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172106106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1172106106
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2801741712
Short name T419
Test name
Test status
Simulation time 111775618 ps
CPU time 0.96 seconds
Started Aug 16 04:52:06 PM PDT 24
Finished Aug 16 04:52:07 PM PDT 24
Peak memory 200504 kb
Host smart-5bc5ae54-945a-46e6-b6b7-ce6083910e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801741712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2801741712
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.7914739
Short name T155
Test name
Test status
Simulation time 78831713 ps
CPU time 0.86 seconds
Started Aug 16 04:52:08 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 200476 kb
Host smart-78f83abd-9d95-42ac-972f-aa91552bd0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7914739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.7914739
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.4015564173
Short name T45
Test name
Test status
Simulation time 1880501715 ps
CPU time 8.07 seconds
Started Aug 16 04:52:06 PM PDT 24
Finished Aug 16 04:52:14 PM PDT 24
Peak memory 217732 kb
Host smart-2341d7d8-a998-4f07-a500-52e579f95277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015564173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.4015564173
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2794516365
Short name T14
Test name
Test status
Simulation time 244190601 ps
CPU time 1.1 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 217804 kb
Host smart-5de3d4e0-e387-477b-8de3-227172ad77ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794516365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2794516365
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2450904275
Short name T16
Test name
Test status
Simulation time 150319513 ps
CPU time 0.88 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:08 PM PDT 24
Peak memory 200396 kb
Host smart-0e290fc9-b61e-4109-b6d8-57bb6dfca5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450904275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2450904275
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3406497795
Short name T266
Test name
Test status
Simulation time 1736384661 ps
CPU time 7.05 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:15 PM PDT 24
Peak memory 200624 kb
Host smart-dd7f0402-918c-4141-9517-6be32631de86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406497795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3406497795
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.28662865
Short name T526
Test name
Test status
Simulation time 154789302 ps
CPU time 1.13 seconds
Started Aug 16 04:52:08 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 200584 kb
Host smart-4118bb42-2501-48c2-a5e7-1dee7d9eacb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28662865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.28662865
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2607619579
Short name T270
Test name
Test status
Simulation time 206073372 ps
CPU time 1.42 seconds
Started Aug 16 04:52:09 PM PDT 24
Finished Aug 16 04:52:11 PM PDT 24
Peak memory 200636 kb
Host smart-083140bd-0e3a-436a-a535-aaf25a587cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607619579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2607619579
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.1367612441
Short name T261
Test name
Test status
Simulation time 4862198866 ps
CPU time 22.02 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:29 PM PDT 24
Peak memory 200764 kb
Host smart-fbbcb28e-eefb-48d0-af6f-d3ddad66224b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367612441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1367612441
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2299281702
Short name T294
Test name
Test status
Simulation time 554410724 ps
CPU time 2.69 seconds
Started Aug 16 04:52:09 PM PDT 24
Finished Aug 16 04:52:12 PM PDT 24
Peak memory 200460 kb
Host smart-a55fba76-5858-4a14-879f-4ca24989d681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299281702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2299281702
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3125170847
Short name T338
Test name
Test status
Simulation time 134651823 ps
CPU time 1.05 seconds
Started Aug 16 04:52:06 PM PDT 24
Finished Aug 16 04:52:07 PM PDT 24
Peak memory 200568 kb
Host smart-50785754-5b52-47b4-afb3-e120ec0f01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125170847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3125170847
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.2481307333
Short name T165
Test name
Test status
Simulation time 72607896 ps
CPU time 0.79 seconds
Started Aug 16 04:52:12 PM PDT 24
Finished Aug 16 04:52:13 PM PDT 24
Peak memory 200464 kb
Host smart-05e449ba-d6ee-4644-bae9-9f7b3ff8670c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481307333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.2481307333
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.447950662
Short name T29
Test name
Test status
Simulation time 1878722394 ps
CPU time 7.08 seconds
Started Aug 16 04:52:10 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 217984 kb
Host smart-d23d8c0b-06b7-452d-9971-cb2f065bad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447950662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.447950662
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3057326314
Short name T221
Test name
Test status
Simulation time 244081790 ps
CPU time 1.08 seconds
Started Aug 16 04:52:08 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 217736 kb
Host smart-607187f9-4f11-45d1-b2c2-7fef66660c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057326314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3057326314
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3889808665
Short name T348
Test name
Test status
Simulation time 92780302 ps
CPU time 0.85 seconds
Started Aug 16 04:52:12 PM PDT 24
Finished Aug 16 04:52:13 PM PDT 24
Peak memory 200400 kb
Host smart-f1835bd4-ad45-416e-975f-87f89e4ad047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889808665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3889808665
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.2983628793
Short name T518
Test name
Test status
Simulation time 1596577547 ps
CPU time 5.93 seconds
Started Aug 16 04:52:06 PM PDT 24
Finished Aug 16 04:52:12 PM PDT 24
Peak memory 200688 kb
Host smart-335f7c9e-3b97-411c-aa2d-60d164ebb0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983628793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2983628793
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1343163072
Short name T352
Test name
Test status
Simulation time 171357743 ps
CPU time 1.24 seconds
Started Aug 16 04:52:08 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 200616 kb
Host smart-ba7c5b18-8072-4563-9c7a-15dfd50659c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343163072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1343163072
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2132410630
Short name T501
Test name
Test status
Simulation time 198206223 ps
CPU time 1.42 seconds
Started Aug 16 04:52:11 PM PDT 24
Finished Aug 16 04:52:12 PM PDT 24
Peak memory 200668 kb
Host smart-03853f23-5539-4116-a561-d4a08a6ef59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132410630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2132410630
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3245504055
Short name T500
Test name
Test status
Simulation time 1403838005 ps
CPU time 6.4 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:14 PM PDT 24
Peak memory 200732 kb
Host smart-f7e0e798-e988-43af-a64f-492f044973c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245504055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3245504055
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.1869227862
Short name T322
Test name
Test status
Simulation time 137401594 ps
CPU time 1.8 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 208684 kb
Host smart-7c05299e-55ae-483b-8f44-61b00d11643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869227862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1869227862
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2009548670
Short name T329
Test name
Test status
Simulation time 129701185 ps
CPU time 1.11 seconds
Started Aug 16 04:52:08 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 200592 kb
Host smart-caffed31-1af5-4b37-9448-21f495ac2c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009548670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2009548670
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3338318924
Short name T236
Test name
Test status
Simulation time 74699593 ps
CPU time 0.82 seconds
Started Aug 16 04:51:26 PM PDT 24
Finished Aug 16 04:51:27 PM PDT 24
Peak memory 200400 kb
Host smart-954e74ca-4ebf-4ca4-9e01-29402f5f5cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338318924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3338318924
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3013577454
Short name T52
Test name
Test status
Simulation time 1229116777 ps
CPU time 5.95 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:30 PM PDT 24
Peak memory 217916 kb
Host smart-3eab5387-88ac-4ce9-ad5a-9cf436201cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013577454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3013577454
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1665657802
Short name T373
Test name
Test status
Simulation time 244700296 ps
CPU time 1.11 seconds
Started Aug 16 04:51:28 PM PDT 24
Finished Aug 16 04:51:29 PM PDT 24
Peak memory 217808 kb
Host smart-c6f1d12a-cec9-4cee-9fdc-2a2a6c46ebff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665657802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1665657802
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2181098539
Short name T274
Test name
Test status
Simulation time 138071215 ps
CPU time 0.88 seconds
Started Aug 16 04:51:26 PM PDT 24
Finished Aug 16 04:51:27 PM PDT 24
Peak memory 200336 kb
Host smart-12956664-0b0f-40a9-8c20-0548bed1549a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181098539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2181098539
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.3882734700
Short name T393
Test name
Test status
Simulation time 1492836155 ps
CPU time 6.5 seconds
Started Aug 16 04:51:26 PM PDT 24
Finished Aug 16 04:51:33 PM PDT 24
Peak memory 200692 kb
Host smart-95566860-a0a1-410a-9480-89dc0f16133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882734700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3882734700
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.4125504539
Short name T73
Test name
Test status
Simulation time 8300604769 ps
CPU time 14.83 seconds
Started Aug 16 04:51:23 PM PDT 24
Finished Aug 16 04:51:38 PM PDT 24
Peak memory 217460 kb
Host smart-908449c9-0630-428a-9a9c-363c5ec4ca23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125504539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.4125504539
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1464173512
Short name T186
Test name
Test status
Simulation time 145162456 ps
CPU time 1.1 seconds
Started Aug 16 04:51:29 PM PDT 24
Finished Aug 16 04:51:30 PM PDT 24
Peak memory 200592 kb
Host smart-15a88933-220a-4e0e-8ee7-895af2c8ca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464173512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1464173512
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.25085127
Short name T290
Test name
Test status
Simulation time 190287140 ps
CPU time 1.37 seconds
Started Aug 16 04:51:25 PM PDT 24
Finished Aug 16 04:51:26 PM PDT 24
Peak memory 200688 kb
Host smart-c6b697eb-f716-4b34-a659-f2a44fb5d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25085127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.25085127
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1343934137
Short name T40
Test name
Test status
Simulation time 11675201287 ps
CPU time 40.06 seconds
Started Aug 16 04:51:23 PM PDT 24
Finished Aug 16 04:52:03 PM PDT 24
Peak memory 200788 kb
Host smart-40ea97be-8cda-45f5-a15c-0db35b690872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343934137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1343934137
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1872625675
Short name T51
Test name
Test status
Simulation time 455575507 ps
CPU time 2.61 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:26 PM PDT 24
Peak memory 200368 kb
Host smart-c0447f9b-4477-4b7e-a2b0-2eda172a5047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872625675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1872625675
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.1062760330
Short name T208
Test name
Test status
Simulation time 70788184 ps
CPU time 0.79 seconds
Started Aug 16 04:51:27 PM PDT 24
Finished Aug 16 04:51:28 PM PDT 24
Peak memory 200508 kb
Host smart-43a29e2e-c93b-4da3-a9c2-17a367f6203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062760330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1062760330
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.507496629
Short name T453
Test name
Test status
Simulation time 56899380 ps
CPU time 0.75 seconds
Started Aug 16 04:52:10 PM PDT 24
Finished Aug 16 04:52:11 PM PDT 24
Peak memory 200444 kb
Host smart-b44b42ad-2128-4ec6-adb4-971b524fe8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507496629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.507496629
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.399553632
Short name T57
Test name
Test status
Simulation time 2172628540 ps
CPU time 9.42 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 218048 kb
Host smart-f732f070-4113-4cfc-982d-c56a8e0259ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399553632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.399553632
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1343462421
Short name T153
Test name
Test status
Simulation time 244284045 ps
CPU time 1.01 seconds
Started Aug 16 04:52:05 PM PDT 24
Finished Aug 16 04:52:06 PM PDT 24
Peak memory 217720 kb
Host smart-26d28d43-9978-46fa-8e8d-bfefb72e1937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343462421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1343462421
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1651680803
Short name T343
Test name
Test status
Simulation time 175367988 ps
CPU time 0.92 seconds
Started Aug 16 04:52:09 PM PDT 24
Finished Aug 16 04:52:10 PM PDT 24
Peak memory 200404 kb
Host smart-3ee73879-43f8-4226-924a-61dcb46b7a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651680803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1651680803
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1832316165
Short name T123
Test name
Test status
Simulation time 1546788312 ps
CPU time 6.14 seconds
Started Aug 16 04:52:10 PM PDT 24
Finished Aug 16 04:52:16 PM PDT 24
Peak memory 200704 kb
Host smart-4df171f5-ff42-4272-864a-d817bb107d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832316165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1832316165
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1715053704
Short name T292
Test name
Test status
Simulation time 106415185 ps
CPU time 1.1 seconds
Started Aug 16 04:52:10 PM PDT 24
Finished Aug 16 04:52:11 PM PDT 24
Peak memory 200576 kb
Host smart-25da4f36-e223-4a8d-8a47-ff5ed62bf01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715053704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1715053704
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.47099732
Short name T365
Test name
Test status
Simulation time 207775692 ps
CPU time 1.34 seconds
Started Aug 16 04:52:08 PM PDT 24
Finished Aug 16 04:52:10 PM PDT 24
Peak memory 200708 kb
Host smart-e412a477-92d6-42c1-9bde-0bc3b2f37247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47099732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.47099732
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.2387587823
Short name T282
Test name
Test status
Simulation time 224278416 ps
CPU time 1.3 seconds
Started Aug 16 04:52:10 PM PDT 24
Finished Aug 16 04:52:11 PM PDT 24
Peak memory 200600 kb
Host smart-320344fa-f10d-484f-90f9-0238cda18220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387587823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2387587823
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.1191489116
Short name T403
Test name
Test status
Simulation time 347946307 ps
CPU time 2.09 seconds
Started Aug 16 04:52:07 PM PDT 24
Finished Aug 16 04:52:09 PM PDT 24
Peak memory 208660 kb
Host smart-2f4fbdbb-f30b-4ae7-9287-8a43b1e117f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191489116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1191489116
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1680659925
Short name T524
Test name
Test status
Simulation time 160197054 ps
CPU time 1.25 seconds
Started Aug 16 04:52:09 PM PDT 24
Finished Aug 16 04:52:10 PM PDT 24
Peak memory 200764 kb
Host smart-3a71bdf0-0245-4383-868f-24f290414d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680659925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1680659925
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.61941349
Short name T135
Test name
Test status
Simulation time 63281348 ps
CPU time 0.77 seconds
Started Aug 16 04:52:17 PM PDT 24
Finished Aug 16 04:52:18 PM PDT 24
Peak memory 200520 kb
Host smart-bcd0bf4e-3c6e-49f6-9fa6-1d9ce6df62ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61941349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.61941349
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2097266339
Short name T163
Test name
Test status
Simulation time 1894661882 ps
CPU time 8.13 seconds
Started Aug 16 04:52:17 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 218016 kb
Host smart-5700f46c-e900-459e-9658-5721d7c9b197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097266339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2097266339
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3885684294
Short name T216
Test name
Test status
Simulation time 243827759 ps
CPU time 1.08 seconds
Started Aug 16 04:52:20 PM PDT 24
Finished Aug 16 04:52:22 PM PDT 24
Peak memory 217792 kb
Host smart-e3d2ebc2-7a16-4346-a219-119983110378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885684294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3885684294
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1945624431
Short name T366
Test name
Test status
Simulation time 79371451 ps
CPU time 0.7 seconds
Started Aug 16 04:52:15 PM PDT 24
Finished Aug 16 04:52:15 PM PDT 24
Peak memory 200396 kb
Host smart-48912241-b708-4700-9e98-4e575274d065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945624431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1945624431
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2537421296
Short name T337
Test name
Test status
Simulation time 1643704012 ps
CPU time 5.93 seconds
Started Aug 16 04:52:17 PM PDT 24
Finished Aug 16 04:52:23 PM PDT 24
Peak memory 200732 kb
Host smart-5ac7b91f-913e-4c0b-b20f-464814f4d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537421296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2537421296
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.447221557
Short name T202
Test name
Test status
Simulation time 187409525 ps
CPU time 1.31 seconds
Started Aug 16 04:52:15 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 200556 kb
Host smart-4e5d5fa1-ecf2-48e9-9da2-4ee6670a3364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447221557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.447221557
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1634026714
Short name T224
Test name
Test status
Simulation time 113106033 ps
CPU time 1.28 seconds
Started Aug 16 04:52:16 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 200704 kb
Host smart-7816f0f4-2a6b-423c-93b7-fa969ea449a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634026714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1634026714
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2702037469
Short name T465
Test name
Test status
Simulation time 11121536419 ps
CPU time 37.89 seconds
Started Aug 16 04:52:15 PM PDT 24
Finished Aug 16 04:52:53 PM PDT 24
Peak memory 209872 kb
Host smart-86eda5c7-213f-4713-a5a2-bc5a0a7b1ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702037469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2702037469
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3808499054
Short name T446
Test name
Test status
Simulation time 461290707 ps
CPU time 2.36 seconds
Started Aug 16 04:52:19 PM PDT 24
Finished Aug 16 04:52:22 PM PDT 24
Peak memory 200448 kb
Host smart-63e3825e-696d-495e-912d-a20526430cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808499054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3808499054
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2767297267
Short name T201
Test name
Test status
Simulation time 79988268 ps
CPU time 0.84 seconds
Started Aug 16 04:52:16 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 200608 kb
Host smart-e77552bc-f308-4b2f-8c9e-2a59877ba278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767297267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2767297267
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.2965487330
Short name T477
Test name
Test status
Simulation time 59041140 ps
CPU time 0.79 seconds
Started Aug 16 04:52:20 PM PDT 24
Finished Aug 16 04:52:21 PM PDT 24
Peak memory 200472 kb
Host smart-a8973903-250c-4799-846f-507bcaf05f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965487330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2965487330
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3679646996
Short name T537
Test name
Test status
Simulation time 1899999108 ps
CPU time 7.23 seconds
Started Aug 16 04:52:18 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 218044 kb
Host smart-5beb54e6-b968-4431-a767-0408877ace77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679646996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3679646996
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4272655743
Short name T449
Test name
Test status
Simulation time 243482971 ps
CPU time 1.11 seconds
Started Aug 16 04:52:18 PM PDT 24
Finished Aug 16 04:52:19 PM PDT 24
Peak memory 217724 kb
Host smart-0d1291db-34cb-4de7-829f-2a73bf170679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272655743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4272655743
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.2994622866
Short name T461
Test name
Test status
Simulation time 209740233 ps
CPU time 0.96 seconds
Started Aug 16 04:52:14 PM PDT 24
Finished Aug 16 04:52:15 PM PDT 24
Peak memory 200400 kb
Host smart-4d668ca3-e43b-4e05-98b2-2cef4616f01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994622866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2994622866
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.280976163
Short name T133
Test name
Test status
Simulation time 1566623986 ps
CPU time 6.33 seconds
Started Aug 16 04:52:18 PM PDT 24
Finished Aug 16 04:52:24 PM PDT 24
Peak memory 200768 kb
Host smart-3a5ac1d4-c6b8-4c17-810c-1096bc70fd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280976163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.280976163
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1064448826
Short name T488
Test name
Test status
Simulation time 141702799 ps
CPU time 1.19 seconds
Started Aug 16 04:52:17 PM PDT 24
Finished Aug 16 04:52:18 PM PDT 24
Peak memory 200588 kb
Host smart-1ef818dc-3850-4c0c-9dd6-9e8e39c1ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064448826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1064448826
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.4187867493
Short name T389
Test name
Test status
Simulation time 201538483 ps
CPU time 1.51 seconds
Started Aug 16 04:52:15 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 200760 kb
Host smart-02b97f32-18fa-4cc5-bf1c-ee73caa2077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187867493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.4187867493
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.889618018
Short name T301
Test name
Test status
Simulation time 7825135525 ps
CPU time 34.24 seconds
Started Aug 16 04:52:16 PM PDT 24
Finished Aug 16 04:52:51 PM PDT 24
Peak memory 208904 kb
Host smart-0b2c126e-3fec-43e5-95f1-53eccc0d4666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889618018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.889618018
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.929856433
Short name T315
Test name
Test status
Simulation time 269109721 ps
CPU time 1.91 seconds
Started Aug 16 04:52:16 PM PDT 24
Finished Aug 16 04:52:18 PM PDT 24
Peak memory 200484 kb
Host smart-9d3997e1-7718-4043-a2b3-71818e5f8363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929856433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.929856433
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.395596875
Short name T375
Test name
Test status
Simulation time 117898587 ps
CPU time 0.97 seconds
Started Aug 16 04:52:14 PM PDT 24
Finished Aug 16 04:52:15 PM PDT 24
Peak memory 200584 kb
Host smart-442f0f71-4b5e-4bf7-b740-c27541718952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395596875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.395596875
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.574259625
Short name T166
Test name
Test status
Simulation time 82576161 ps
CPU time 0.78 seconds
Started Aug 16 04:52:20 PM PDT 24
Finished Aug 16 04:52:21 PM PDT 24
Peak memory 200464 kb
Host smart-77b64a28-91aa-4715-b899-54f185ad779d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574259625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.574259625
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.2317282551
Short name T441
Test name
Test status
Simulation time 1899913962 ps
CPU time 7.07 seconds
Started Aug 16 04:52:20 PM PDT 24
Finished Aug 16 04:52:27 PM PDT 24
Peak memory 217512 kb
Host smart-03b288d9-b4ed-4b5b-a321-b3013cdfd6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317282551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2317282551
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.348854252
Short name T75
Test name
Test status
Simulation time 244452562 ps
CPU time 1.19 seconds
Started Aug 16 04:52:18 PM PDT 24
Finished Aug 16 04:52:19 PM PDT 24
Peak memory 217672 kb
Host smart-89e437df-ff8d-4b7b-99b8-275284a9b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348854252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.348854252
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.1541299073
Short name T207
Test name
Test status
Simulation time 126868028 ps
CPU time 0.78 seconds
Started Aug 16 04:52:22 PM PDT 24
Finished Aug 16 04:52:23 PM PDT 24
Peak memory 200372 kb
Host smart-04f341e4-fb49-4724-8f41-9c52e5f18397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541299073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1541299073
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.444519591
Short name T325
Test name
Test status
Simulation time 1192675197 ps
CPU time 5.33 seconds
Started Aug 16 04:52:18 PM PDT 24
Finished Aug 16 04:52:23 PM PDT 24
Peak memory 200744 kb
Host smart-c54fb3b8-ddf0-4087-b232-e17d089b04f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444519591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.444519591
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3578369943
Short name T285
Test name
Test status
Simulation time 145914293 ps
CPU time 1.15 seconds
Started Aug 16 04:52:16 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 200448 kb
Host smart-d7243dfc-257c-4adc-9224-e28a2e7a0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578369943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3578369943
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.2960731636
Short name T136
Test name
Test status
Simulation time 124159194 ps
CPU time 1.2 seconds
Started Aug 16 04:52:18 PM PDT 24
Finished Aug 16 04:52:19 PM PDT 24
Peak memory 200700 kb
Host smart-13351a35-935c-4893-b12f-9fdd54796c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960731636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.2960731636
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.2544576210
Short name T48
Test name
Test status
Simulation time 9104942920 ps
CPU time 31.8 seconds
Started Aug 16 04:52:17 PM PDT 24
Finished Aug 16 04:52:49 PM PDT 24
Peak memory 200732 kb
Host smart-e2fd77c5-fdcc-4df8-8282-1f191762cfe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544576210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2544576210
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1659529575
Short name T195
Test name
Test status
Simulation time 517873016 ps
CPU time 2.92 seconds
Started Aug 16 04:52:17 PM PDT 24
Finished Aug 16 04:52:20 PM PDT 24
Peak memory 200488 kb
Host smart-d64fc92f-aaeb-48b9-b28b-2ace919799bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659529575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1659529575
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3782113296
Short name T371
Test name
Test status
Simulation time 115073739 ps
CPU time 1.06 seconds
Started Aug 16 04:52:15 PM PDT 24
Finished Aug 16 04:52:16 PM PDT 24
Peak memory 200608 kb
Host smart-1692e918-26a5-4307-90f4-960f92e13dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782113296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3782113296
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2937813205
Short name T257
Test name
Test status
Simulation time 79150160 ps
CPU time 0.81 seconds
Started Aug 16 04:52:19 PM PDT 24
Finished Aug 16 04:52:19 PM PDT 24
Peak memory 200388 kb
Host smart-bcdc4b20-e319-427e-a1a2-2ef74d2a2859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937813205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2937813205
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3831442428
Short name T466
Test name
Test status
Simulation time 1229253334 ps
CPU time 5.57 seconds
Started Aug 16 04:52:19 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 216988 kb
Host smart-ad8a50fa-57a6-444b-8ba9-44bd622afcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831442428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3831442428
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1328690604
Short name T410
Test name
Test status
Simulation time 243915873 ps
CPU time 1.13 seconds
Started Aug 16 04:52:16 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 217700 kb
Host smart-90baa026-2f69-4723-b0ac-14a6a61cfda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328690604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1328690604
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.521480087
Short name T497
Test name
Test status
Simulation time 96540888 ps
CPU time 0.81 seconds
Started Aug 16 04:52:16 PM PDT 24
Finished Aug 16 04:52:17 PM PDT 24
Peak memory 200452 kb
Host smart-0212cae3-43b6-450b-ad39-4c03408bf6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521480087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.521480087
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2938188154
Short name T194
Test name
Test status
Simulation time 786331041 ps
CPU time 4.53 seconds
Started Aug 16 04:52:15 PM PDT 24
Finished Aug 16 04:52:20 PM PDT 24
Peak memory 200828 kb
Host smart-448ffeaa-117b-4e1e-841c-6b71d1bc3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938188154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2938188154
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1557451853
Short name T291
Test name
Test status
Simulation time 181538720 ps
CPU time 1.18 seconds
Started Aug 16 04:52:13 PM PDT 24
Finished Aug 16 04:52:15 PM PDT 24
Peak memory 200584 kb
Host smart-f86ac0de-fe9a-4c4f-b0fd-88a9cd9a731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557451853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1557451853
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1251329827
Short name T289
Test name
Test status
Simulation time 204401644 ps
CPU time 1.48 seconds
Started Aug 16 04:52:18 PM PDT 24
Finished Aug 16 04:52:19 PM PDT 24
Peak memory 200620 kb
Host smart-3f7f2579-b82a-4425-9d9d-567cadcee978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251329827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1251329827
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1324301118
Short name T96
Test name
Test status
Simulation time 4478109160 ps
CPU time 19.49 seconds
Started Aug 16 04:52:22 PM PDT 24
Finished Aug 16 04:52:41 PM PDT 24
Peak memory 209764 kb
Host smart-6e799537-1de6-4327-92f6-5e22d442f902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324301118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1324301118
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.619737746
Short name T458
Test name
Test status
Simulation time 404777685 ps
CPU time 2.2 seconds
Started Aug 16 04:52:20 PM PDT 24
Finished Aug 16 04:52:23 PM PDT 24
Peak memory 200424 kb
Host smart-3d4b4221-4d95-4d4b-a0f3-3c3e9fd4e40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619737746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.619737746
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3456282908
Short name T405
Test name
Test status
Simulation time 103580842 ps
CPU time 0.89 seconds
Started Aug 16 04:52:22 PM PDT 24
Finished Aug 16 04:52:23 PM PDT 24
Peak memory 200564 kb
Host smart-faf14fca-b3bc-4f5f-91d6-ff4603b5be56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456282908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3456282908
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1095923666
Short name T197
Test name
Test status
Simulation time 80824820 ps
CPU time 0.86 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200464 kb
Host smart-c807616d-72bd-4e64-a0f3-501b0a2e6798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095923666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1095923666
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.921626862
Short name T33
Test name
Test status
Simulation time 1225114914 ps
CPU time 5.91 seconds
Started Aug 16 04:52:20 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 217932 kb
Host smart-01058fd2-a94b-4160-9180-1f0a5b5107e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921626862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.921626862
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3070273064
Short name T319
Test name
Test status
Simulation time 243205361 ps
CPU time 1.08 seconds
Started Aug 16 04:52:20 PM PDT 24
Finished Aug 16 04:52:21 PM PDT 24
Peak memory 217812 kb
Host smart-eae4544f-cb53-4a2c-8c0e-c443d9ea1c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070273064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3070273064
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.4130506649
Short name T335
Test name
Test status
Simulation time 161115885 ps
CPU time 0.94 seconds
Started Aug 16 04:52:17 PM PDT 24
Finished Aug 16 04:52:18 PM PDT 24
Peak memory 200448 kb
Host smart-d709600c-3b8b-4241-bd1b-ee4f555e3063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130506649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.4130506649
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.1788826026
Short name T378
Test name
Test status
Simulation time 1111161080 ps
CPU time 5.69 seconds
Started Aug 16 04:52:17 PM PDT 24
Finished Aug 16 04:52:23 PM PDT 24
Peak memory 200780 kb
Host smart-82afa6be-59f1-4cad-8500-95b482675691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788826026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.1788826026
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3238956530
Short name T279
Test name
Test status
Simulation time 108150171 ps
CPU time 1.05 seconds
Started Aug 16 04:52:19 PM PDT 24
Finished Aug 16 04:52:20 PM PDT 24
Peak memory 200604 kb
Host smart-d06105a1-68b6-4388-a9a9-653df5c9cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238956530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3238956530
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4277015900
Short name T272
Test name
Test status
Simulation time 199407421 ps
CPU time 1.54 seconds
Started Aug 16 04:52:20 PM PDT 24
Finished Aug 16 04:52:21 PM PDT 24
Peak memory 200684 kb
Host smart-bce2563c-0830-433c-9562-d9e0f435fae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277015900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4277015900
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2895193087
Short name T362
Test name
Test status
Simulation time 13523469143 ps
CPU time 47.65 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 208928 kb
Host smart-e9a8736d-ae09-4ba8-957e-e5f3acacf741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895193087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2895193087
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3315971263
Short name T149
Test name
Test status
Simulation time 329829811 ps
CPU time 2.23 seconds
Started Aug 16 04:52:18 PM PDT 24
Finished Aug 16 04:52:20 PM PDT 24
Peak memory 200500 kb
Host smart-eddb284d-0952-422d-bcdd-6336c0bdbd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315971263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3315971263
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.3074284250
Short name T231
Test name
Test status
Simulation time 243998703 ps
CPU time 1.59 seconds
Started Aug 16 04:52:16 PM PDT 24
Finished Aug 16 04:52:18 PM PDT 24
Peak memory 200576 kb
Host smart-271d3c1e-06f6-4093-b149-24a2fbf32bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074284250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3074284250
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1629095979
Short name T314
Test name
Test status
Simulation time 77063266 ps
CPU time 0.78 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200464 kb
Host smart-80af0169-3c5b-40a4-8b8a-7b4dcf065c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629095979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1629095979
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1204943014
Short name T296
Test name
Test status
Simulation time 2185789335 ps
CPU time 8.55 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:35 PM PDT 24
Peak memory 218064 kb
Host smart-affaf28d-c004-4b72-bbf1-711eea97c258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204943014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1204943014
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3322713811
Short name T47
Test name
Test status
Simulation time 244119467 ps
CPU time 1.13 seconds
Started Aug 16 04:52:23 PM PDT 24
Finished Aug 16 04:52:24 PM PDT 24
Peak memory 217732 kb
Host smart-df75169f-5163-429f-9024-8300b9675c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322713811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3322713811
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3048235693
Short name T225
Test name
Test status
Simulation time 71985889 ps
CPU time 0.7 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200416 kb
Host smart-d263a659-a64b-4c45-a552-30f7a616515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048235693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3048235693
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.4227761238
Short name T457
Test name
Test status
Simulation time 994738185 ps
CPU time 4.81 seconds
Started Aug 16 04:52:26 PM PDT 24
Finished Aug 16 04:52:31 PM PDT 24
Peak memory 200752 kb
Host smart-377907f8-3b0e-48e5-b587-982ddbf08e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227761238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.4227761238
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.852954727
Short name T309
Test name
Test status
Simulation time 165833763 ps
CPU time 1.26 seconds
Started Aug 16 04:52:26 PM PDT 24
Finished Aug 16 04:52:27 PM PDT 24
Peak memory 200596 kb
Host smart-555afa06-cb96-4904-ac65-e7b16a27ea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852954727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.852954727
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.4003055709
Short name T154
Test name
Test status
Simulation time 197039772 ps
CPU time 1.39 seconds
Started Aug 16 04:52:26 PM PDT 24
Finished Aug 16 04:52:28 PM PDT 24
Peak memory 200616 kb
Host smart-dc2681d9-09dd-43c4-a89b-dc881ce32869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003055709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.4003055709
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.2837403874
Short name T95
Test name
Test status
Simulation time 3526943642 ps
CPU time 15.54 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:41 PM PDT 24
Peak memory 200756 kb
Host smart-bc60f2ec-da54-4b41-9311-b004d76382b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837403874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2837403874
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2650325970
Short name T280
Test name
Test status
Simulation time 147531943 ps
CPU time 1.81 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:29 PM PDT 24
Peak memory 200424 kb
Host smart-a1a69890-8d8c-44eb-82ff-1c95f5f601b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650325970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2650325970
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.4165640625
Short name T180
Test name
Test status
Simulation time 175774722 ps
CPU time 1.25 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200672 kb
Host smart-547b19bc-b751-4dae-b0fb-ff73aeb94e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165640625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.4165640625
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.1663807264
Short name T491
Test name
Test status
Simulation time 73941302 ps
CPU time 0.83 seconds
Started Aug 16 04:52:23 PM PDT 24
Finished Aug 16 04:52:24 PM PDT 24
Peak memory 200472 kb
Host smart-8ecbecc2-3aae-4c4c-833a-a76ee8493d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663807264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1663807264
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.4166201264
Short name T313
Test name
Test status
Simulation time 2163915508 ps
CPU time 9.84 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:52:34 PM PDT 24
Peak memory 217736 kb
Host smart-a4890692-4121-4c80-951e-e78a25be2750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166201264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.4166201264
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2731347985
Short name T159
Test name
Test status
Simulation time 244358488 ps
CPU time 1.09 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:29 PM PDT 24
Peak memory 217808 kb
Host smart-d1cf139c-efb8-4a5f-b9e5-be47b4dd2c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731347985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2731347985
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.4280081325
Short name T10
Test name
Test status
Simulation time 158577687 ps
CPU time 0.85 seconds
Started Aug 16 04:52:29 PM PDT 24
Finished Aug 16 04:52:30 PM PDT 24
Peak memory 200428 kb
Host smart-5b085e32-e0d9-4e4b-b8e7-344e6c260d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280081325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4280081325
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2030778941
Short name T525
Test name
Test status
Simulation time 956042245 ps
CPU time 5.18 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:52:30 PM PDT 24
Peak memory 200820 kb
Host smart-7a99eebf-d6ba-48c8-b8e3-4eaec4ffea37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030778941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2030778941
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3736198211
Short name T240
Test name
Test status
Simulation time 100624505 ps
CPU time 0.95 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200604 kb
Host smart-f41e612b-d34f-48c8-ab0d-208ac6466eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736198211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3736198211
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2252510600
Short name T4
Test name
Test status
Simulation time 256149591 ps
CPU time 1.47 seconds
Started Aug 16 04:52:28 PM PDT 24
Finished Aug 16 04:52:29 PM PDT 24
Peak memory 200680 kb
Host smart-a38d07dc-2a6e-40e8-be79-d7019f70bd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252510600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2252510600
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2425586846
Short name T121
Test name
Test status
Simulation time 5163289559 ps
CPU time 17.9 seconds
Started Aug 16 04:52:23 PM PDT 24
Finished Aug 16 04:52:41 PM PDT 24
Peak memory 209000 kb
Host smart-c6dfa488-2da5-400d-a6d6-a3e66635633a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425586846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2425586846
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.4160234218
Short name T50
Test name
Test status
Simulation time 134746762 ps
CPU time 1.6 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:28 PM PDT 24
Peak memory 208716 kb
Host smart-12adbb1d-d2e0-4290-8fd4-e8b1ca215e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160234218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4160234218
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.2103682792
Short name T169
Test name
Test status
Simulation time 86864152 ps
CPU time 0.88 seconds
Started Aug 16 04:52:28 PM PDT 24
Finished Aug 16 04:52:29 PM PDT 24
Peak memory 200560 kb
Host smart-5c544cc9-3df3-40dd-ae3b-368fa7e52ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103682792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2103682792
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.935206468
Short name T417
Test name
Test status
Simulation time 58704059 ps
CPU time 0.82 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 200440 kb
Host smart-9ed8e033-fd9c-4fd6-9999-68f439b979b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935206468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.935206468
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2335236934
Short name T80
Test name
Test status
Simulation time 244203591 ps
CPU time 1.13 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 217700 kb
Host smart-37205dd5-6459-4dce-9964-fa1a323c2692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335236934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2335236934
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.4281253659
Short name T390
Test name
Test status
Simulation time 205413450 ps
CPU time 0.98 seconds
Started Aug 16 04:52:28 PM PDT 24
Finished Aug 16 04:52:29 PM PDT 24
Peak memory 200424 kb
Host smart-1b034f87-d45e-455d-8555-55d2a9407bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281253659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.4281253659
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3905401514
Short name T98
Test name
Test status
Simulation time 1596717754 ps
CPU time 6.87 seconds
Started Aug 16 04:52:23 PM PDT 24
Finished Aug 16 04:52:30 PM PDT 24
Peak memory 200692 kb
Host smart-a9a66838-85b6-4db8-9e18-8c5b8755f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905401514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3905401514
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3367667266
Short name T382
Test name
Test status
Simulation time 185944242 ps
CPU time 1.28 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:28 PM PDT 24
Peak memory 200448 kb
Host smart-51fff3df-2a2f-47b1-82bc-00ca3a1d2a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367667266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3367667266
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.714576399
Short name T367
Test name
Test status
Simulation time 109314423 ps
CPU time 1.14 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 200692 kb
Host smart-498a9751-f4d9-49dd-a1b2-272b0348e951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714576399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.714576399
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.2222068418
Short name T175
Test name
Test status
Simulation time 1315744935 ps
CPU time 5.01 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:52:29 PM PDT 24
Peak memory 200812 kb
Host smart-845831b7-bc4a-48f3-8301-a2a3f6e48445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222068418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2222068418
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2710218106
Short name T60
Test name
Test status
Simulation time 275242708 ps
CPU time 1.93 seconds
Started Aug 16 04:52:23 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 200484 kb
Host smart-78b5c2ac-6a56-452a-b5d2-a5bca647f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710218106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2710218106
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.111333650
Short name T2
Test name
Test status
Simulation time 132156241 ps
CPU time 0.93 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200604 kb
Host smart-3bdff544-368f-4ede-96e1-0cc1097f1607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111333650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.111333650
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.770865761
Short name T76
Test name
Test status
Simulation time 53536382 ps
CPU time 0.77 seconds
Started Aug 16 04:52:22 PM PDT 24
Finished Aug 16 04:52:23 PM PDT 24
Peak memory 200388 kb
Host smart-668b822a-865c-448c-958e-187602d503a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770865761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.770865761
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.3983001129
Short name T34
Test name
Test status
Simulation time 1895496933 ps
CPU time 8.16 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 221852 kb
Host smart-2bf31d06-99ad-4af2-bb86-29e3b2c1ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983001129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3983001129
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1635736159
Short name T209
Test name
Test status
Simulation time 244246593 ps
CPU time 1.02 seconds
Started Aug 16 04:52:22 PM PDT 24
Finished Aug 16 04:52:23 PM PDT 24
Peak memory 217744 kb
Host smart-d1a30ed0-d12f-4909-9cd8-6218d9302776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635736159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1635736159
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2168074860
Short name T21
Test name
Test status
Simulation time 155204586 ps
CPU time 0.83 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200396 kb
Host smart-522d478a-56c2-438b-a044-83ac32c97847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168074860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2168074860
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.2183343930
Short name T28
Test name
Test status
Simulation time 1460249948 ps
CPU time 5.9 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:33 PM PDT 24
Peak memory 200744 kb
Host smart-44a8d2ee-e0b5-4b04-ad39-8fba0a98abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183343930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2183343930
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.4228252941
Short name T7
Test name
Test status
Simulation time 151065201 ps
CPU time 1.13 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200588 kb
Host smart-cc18e846-cee6-49cd-a046-895a470a1ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228252941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.4228252941
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.603270664
Short name T440
Test name
Test status
Simulation time 254653073 ps
CPU time 1.41 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:27 PM PDT 24
Peak memory 200716 kb
Host smart-1072bba4-50ac-48a6-b33a-a47c48ab0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603270664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.603270664
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.2825226560
Short name T462
Test name
Test status
Simulation time 10239949446 ps
CPU time 40.13 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 200788 kb
Host smart-84b0fcd6-8f67-4fb3-a839-be90c1e71160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825226560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2825226560
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.1788689352
Short name T83
Test name
Test status
Simulation time 128665818 ps
CPU time 1.74 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200488 kb
Host smart-4e0fff37-605b-4a29-bd97-602d99af7100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788689352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1788689352
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.4059890537
Short name T137
Test name
Test status
Simulation time 73241459 ps
CPU time 0.89 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:28 PM PDT 24
Peak memory 200492 kb
Host smart-e298417e-3e32-4bb6-a8d2-35acd1688f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059890537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4059890537
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.195227802
Short name T443
Test name
Test status
Simulation time 75692530 ps
CPU time 0.89 seconds
Started Aug 16 04:51:31 PM PDT 24
Finished Aug 16 04:51:32 PM PDT 24
Peak memory 200456 kb
Host smart-be0cdcd2-a1f2-4d11-81bb-25944b60d42d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195227802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.195227802
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2404733123
Short name T415
Test name
Test status
Simulation time 1241717145 ps
CPU time 5.82 seconds
Started Aug 16 04:51:32 PM PDT 24
Finished Aug 16 04:51:38 PM PDT 24
Peak memory 221896 kb
Host smart-f2c6c373-cecb-406b-89f3-1980c0031dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404733123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2404733123
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4140371626
Short name T232
Test name
Test status
Simulation time 244958739 ps
CPU time 1.22 seconds
Started Aug 16 04:51:30 PM PDT 24
Finished Aug 16 04:51:31 PM PDT 24
Peak memory 217756 kb
Host smart-391bfa3c-6b03-47b0-877f-e4ae5a177697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140371626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4140371626
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1011138326
Short name T17
Test name
Test status
Simulation time 141315067 ps
CPU time 0.8 seconds
Started Aug 16 04:51:24 PM PDT 24
Finished Aug 16 04:51:25 PM PDT 24
Peak memory 200280 kb
Host smart-f7ae380c-7fe7-4278-9378-a6483362e647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011138326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1011138326
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.3444462408
Short name T172
Test name
Test status
Simulation time 983781356 ps
CPU time 4.96 seconds
Started Aug 16 04:51:33 PM PDT 24
Finished Aug 16 04:51:39 PM PDT 24
Peak memory 200776 kb
Host smart-e86f3f10-67cd-42a2-b76f-c94c6052b545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444462408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3444462408
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4169429894
Short name T69
Test name
Test status
Simulation time 8308552205 ps
CPU time 13.41 seconds
Started Aug 16 04:51:30 PM PDT 24
Finished Aug 16 04:51:44 PM PDT 24
Peak memory 217120 kb
Host smart-1b7a57ae-6237-4123-a69a-3733cfcf2742
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169429894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4169429894
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1750356508
Short name T535
Test name
Test status
Simulation time 107244491 ps
CPU time 1.06 seconds
Started Aug 16 04:51:33 PM PDT 24
Finished Aug 16 04:51:35 PM PDT 24
Peak memory 200592 kb
Host smart-c5f1f4ab-44a8-4e3a-92a0-4d7024d5e2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750356508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1750356508
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1621274584
Short name T239
Test name
Test status
Simulation time 114440372 ps
CPU time 1.15 seconds
Started Aug 16 04:51:28 PM PDT 24
Finished Aug 16 04:51:30 PM PDT 24
Peak memory 200684 kb
Host smart-f7d2bb81-780f-4a1a-9a54-922a204f05f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621274584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1621274584
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.1978507856
Short name T82
Test name
Test status
Simulation time 4707442131 ps
CPU time 20.87 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:52:00 PM PDT 24
Peak memory 209036 kb
Host smart-6f85b77b-b780-4a39-afb8-3b43bfc2584f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978507856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1978507856
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.583158769
Short name T84
Test name
Test status
Simulation time 128195766 ps
CPU time 1.53 seconds
Started Aug 16 04:51:31 PM PDT 24
Finished Aug 16 04:51:33 PM PDT 24
Peak memory 208716 kb
Host smart-58f48362-0009-4d3d-a34e-2a4c1354dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583158769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.583158769
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2027103454
Short name T150
Test name
Test status
Simulation time 119782257 ps
CPU time 1.03 seconds
Started Aug 16 04:51:31 PM PDT 24
Finished Aug 16 04:51:32 PM PDT 24
Peak memory 200512 kb
Host smart-219fece8-451a-4f0a-a427-20dae892d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027103454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2027103454
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.4058023575
Short name T297
Test name
Test status
Simulation time 73317106 ps
CPU time 0.82 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 200452 kb
Host smart-51201a52-1295-4b17-8440-f2c72c9245d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058023575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.4058023575
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2136992386
Short name T41
Test name
Test status
Simulation time 1895135400 ps
CPU time 7.21 seconds
Started Aug 16 04:52:26 PM PDT 24
Finished Aug 16 04:52:33 PM PDT 24
Peak memory 221636 kb
Host smart-422d91e2-0309-4312-8877-eafc492d8b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136992386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2136992386
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1781343388
Short name T396
Test name
Test status
Simulation time 246368463 ps
CPU time 1.06 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 217756 kb
Host smart-0c8cdca4-c079-46b8-8f3b-49d8c0a8d04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781343388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1781343388
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3837572597
Short name T369
Test name
Test status
Simulation time 192190409 ps
CPU time 0.88 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:26 PM PDT 24
Peak memory 200368 kb
Host smart-6fce24d0-9f51-4dbb-a3fd-b100895d6b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837572597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3837572597
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.1166843719
Short name T158
Test name
Test status
Simulation time 1432659599 ps
CPU time 6.91 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:32 PM PDT 24
Peak memory 200820 kb
Host smart-c646285d-07c1-455e-be09-6da5bd3ecd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166843719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1166843719
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2854196853
Short name T394
Test name
Test status
Simulation time 169356820 ps
CPU time 1.16 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:29 PM PDT 24
Peak memory 200596 kb
Host smart-a8d370b1-4c14-4b62-81f8-8d846a15135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854196853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2854196853
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.1965458124
Short name T503
Test name
Test status
Simulation time 244279204 ps
CPU time 1.43 seconds
Started Aug 16 04:52:24 PM PDT 24
Finished Aug 16 04:52:25 PM PDT 24
Peak memory 200704 kb
Host smart-b4a1b131-a18f-462a-a7bb-e8c4f545f57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965458124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1965458124
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3086885700
Short name T416
Test name
Test status
Simulation time 2767007748 ps
CPU time 12.87 seconds
Started Aug 16 04:52:28 PM PDT 24
Finished Aug 16 04:52:41 PM PDT 24
Peak memory 200816 kb
Host smart-25b00677-d3cd-4e1b-9c34-d18dedd34a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086885700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3086885700
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1654401755
Short name T303
Test name
Test status
Simulation time 377953245 ps
CPU time 2.33 seconds
Started Aug 16 04:52:25 PM PDT 24
Finished Aug 16 04:52:28 PM PDT 24
Peak memory 200496 kb
Host smart-30543741-dff4-4173-9e6f-f9a982210c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654401755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1654401755
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1702852379
Short name T26
Test name
Test status
Simulation time 77660232 ps
CPU time 0.82 seconds
Started Aug 16 04:52:27 PM PDT 24
Finished Aug 16 04:52:28 PM PDT 24
Peak memory 200492 kb
Host smart-076ae883-032c-443f-9559-300297eaab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702852379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1702852379
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.3234371489
Short name T49
Test name
Test status
Simulation time 72320593 ps
CPU time 0.78 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 200468 kb
Host smart-ee6062f5-03d8-44b5-a336-f1d534daf1fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234371489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3234371489
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1977823587
Short name T434
Test name
Test status
Simulation time 1223714017 ps
CPU time 5.97 seconds
Started Aug 16 04:52:33 PM PDT 24
Finished Aug 16 04:52:39 PM PDT 24
Peak memory 217952 kb
Host smart-b1d4b541-d117-490f-9be9-2732e012cfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977823587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1977823587
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.132271013
Short name T406
Test name
Test status
Simulation time 244608263 ps
CPU time 1.09 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 217828 kb
Host smart-da17bc99-624d-4846-9a2e-77f561d668b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132271013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.132271013
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1250951682
Short name T344
Test name
Test status
Simulation time 190612390 ps
CPU time 0.93 seconds
Started Aug 16 04:52:31 PM PDT 24
Finished Aug 16 04:52:32 PM PDT 24
Peak memory 200388 kb
Host smart-f2b42faf-1e37-4dd7-99a9-ef3b8a6b2abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250951682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1250951682
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3710606634
Short name T376
Test name
Test status
Simulation time 962377934 ps
CPU time 4.41 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:39 PM PDT 24
Peak memory 200792 kb
Host smart-2d1d09fc-29a9-47cc-b4f8-e1ac62d7c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710606634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3710606634
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.377057955
Short name T200
Test name
Test status
Simulation time 138826887 ps
CPU time 1.07 seconds
Started Aug 16 04:52:39 PM PDT 24
Finished Aug 16 04:52:41 PM PDT 24
Peak memory 200648 kb
Host smart-87d7bd7a-9eb5-4651-930f-47cfcff862a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377057955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.377057955
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1660935022
Short name T141
Test name
Test status
Simulation time 115457748 ps
CPU time 1.2 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 200572 kb
Host smart-25310181-5c13-4f75-a617-34785521da63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660935022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1660935022
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1116942864
Short name T92
Test name
Test status
Simulation time 4121645109 ps
CPU time 15.05 seconds
Started Aug 16 04:52:43 PM PDT 24
Finished Aug 16 04:52:58 PM PDT 24
Peak memory 209044 kb
Host smart-2d9f23d2-debe-433e-ab09-71f9b728287f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116942864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1116942864
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.3165005376
Short name T379
Test name
Test status
Simulation time 148105597 ps
CPU time 1.81 seconds
Started Aug 16 04:52:33 PM PDT 24
Finished Aug 16 04:52:35 PM PDT 24
Peak memory 200500 kb
Host smart-13551921-72cc-428c-9c9a-746625a2f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165005376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3165005376
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.2734156802
Short name T286
Test name
Test status
Simulation time 86111791 ps
CPU time 0.85 seconds
Started Aug 16 04:52:39 PM PDT 24
Finished Aug 16 04:52:40 PM PDT 24
Peak memory 200544 kb
Host smart-4ae9bc90-fa37-4433-80b0-98a06ccf0489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734156802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2734156802
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.3515469300
Short name T516
Test name
Test status
Simulation time 69081788 ps
CPU time 0.76 seconds
Started Aug 16 04:52:39 PM PDT 24
Finished Aug 16 04:52:40 PM PDT 24
Peak memory 200472 kb
Host smart-7538ab08-a0da-4603-861f-4da7a8109916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515469300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3515469300
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1027187474
Short name T450
Test name
Test status
Simulation time 1246322753 ps
CPU time 5.66 seconds
Started Aug 16 04:52:31 PM PDT 24
Finished Aug 16 04:52:37 PM PDT 24
Peak memory 217892 kb
Host smart-c1ad226f-71fb-41e9-bc2c-3c891f48592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027187474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1027187474
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2582303248
Short name T442
Test name
Test status
Simulation time 243953572 ps
CPU time 1.12 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 217792 kb
Host smart-87083218-c4b8-450a-83b5-496a00a0e0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582303248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2582303248
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.961103436
Short name T269
Test name
Test status
Simulation time 160652017 ps
CPU time 0.86 seconds
Started Aug 16 04:52:33 PM PDT 24
Finished Aug 16 04:52:34 PM PDT 24
Peak memory 200388 kb
Host smart-17c63e77-9ebd-44fb-a4a4-f6d8754ed2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961103436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.961103436
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2979567034
Short name T411
Test name
Test status
Simulation time 1951374219 ps
CPU time 7.46 seconds
Started Aug 16 04:52:32 PM PDT 24
Finished Aug 16 04:52:40 PM PDT 24
Peak memory 200764 kb
Host smart-61a6241c-02c1-484f-a641-cd9a2bb0e602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979567034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2979567034
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.255710212
Short name T478
Test name
Test status
Simulation time 93527782 ps
CPU time 1.08 seconds
Started Aug 16 04:52:52 PM PDT 24
Finished Aug 16 04:52:53 PM PDT 24
Peak memory 200596 kb
Host smart-6ea4515a-a099-4f39-b020-2f99af4eeb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255710212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.255710212
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1762066098
Short name T213
Test name
Test status
Simulation time 110443257 ps
CPU time 1.12 seconds
Started Aug 16 04:52:31 PM PDT 24
Finished Aug 16 04:52:32 PM PDT 24
Peak memory 200700 kb
Host smart-cb13b6ba-fb37-49cf-936e-7f2a0adfa2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762066098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1762066098
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2650946971
Short name T421
Test name
Test status
Simulation time 11120319378 ps
CPU time 40.21 seconds
Started Aug 16 04:52:39 PM PDT 24
Finished Aug 16 04:53:20 PM PDT 24
Peak memory 200844 kb
Host smart-41f8a693-83a8-48e6-8d99-dde00fc1d16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650946971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2650946971
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2551466223
Short name T139
Test name
Test status
Simulation time 147113192 ps
CPU time 1.78 seconds
Started Aug 16 04:52:41 PM PDT 24
Finished Aug 16 04:52:43 PM PDT 24
Peak memory 200488 kb
Host smart-2ecdac13-33c1-45c0-9546-b4f1b5616606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551466223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2551466223
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.1381745120
Short name T253
Test name
Test status
Simulation time 242948373 ps
CPU time 1.41 seconds
Started Aug 16 04:52:31 PM PDT 24
Finished Aug 16 04:52:33 PM PDT 24
Peak memory 200588 kb
Host smart-ec04d084-2796-4e60-9a03-c56aca21ad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381745120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1381745120
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3778041193
Short name T444
Test name
Test status
Simulation time 59953863 ps
CPU time 0.75 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:35 PM PDT 24
Peak memory 200460 kb
Host smart-6dce674a-2cd3-4440-baee-b964cfac856a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778041193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3778041193
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2351771870
Short name T13
Test name
Test status
Simulation time 1223620061 ps
CPU time 5.55 seconds
Started Aug 16 04:52:33 PM PDT 24
Finished Aug 16 04:52:39 PM PDT 24
Peak memory 217884 kb
Host smart-c8478036-613c-40c8-81a1-c0d313565bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351771870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2351771870
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4062377758
Short name T422
Test name
Test status
Simulation time 244490245 ps
CPU time 1.07 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 217832 kb
Host smart-3b916ca3-264e-4ad0-8cea-26e2639ff83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062377758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4062377758
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.913286397
Short name T372
Test name
Test status
Simulation time 169202374 ps
CPU time 0.89 seconds
Started Aug 16 04:52:37 PM PDT 24
Finished Aug 16 04:52:38 PM PDT 24
Peak memory 200400 kb
Host smart-c5fa5508-a3ce-4a78-bbfc-34acfed566f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913286397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.913286397
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1410372850
Short name T321
Test name
Test status
Simulation time 610951819 ps
CPU time 3.58 seconds
Started Aug 16 04:52:38 PM PDT 24
Finished Aug 16 04:52:42 PM PDT 24
Peak memory 200744 kb
Host smart-9c783888-274d-43e8-8e56-d3521d914278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410372850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1410372850
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1203315640
Short name T278
Test name
Test status
Simulation time 147445910 ps
CPU time 1.14 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 200616 kb
Host smart-56735dc5-c717-48bd-b443-f7c1f3792c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203315640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1203315640
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2390845648
Short name T184
Test name
Test status
Simulation time 113527476 ps
CPU time 1.2 seconds
Started Aug 16 04:52:39 PM PDT 24
Finished Aug 16 04:52:41 PM PDT 24
Peak memory 200808 kb
Host smart-156d1472-f42f-4b3a-a182-cdd5737ffa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390845648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2390845648
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2679954677
Short name T538
Test name
Test status
Simulation time 132903158 ps
CPU time 1.56 seconds
Started Aug 16 04:52:40 PM PDT 24
Finished Aug 16 04:52:42 PM PDT 24
Peak memory 208724 kb
Host smart-e7f0d385-067d-48f0-bada-15a6a5a4c332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679954677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2679954677
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.1390275038
Short name T299
Test name
Test status
Simulation time 103026521 ps
CPU time 0.87 seconds
Started Aug 16 04:52:35 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 200620 kb
Host smart-32eff46b-42ba-40c9-a140-bc127f8f8cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390275038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.1390275038
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.3473525306
Short name T5
Test name
Test status
Simulation time 58776303 ps
CPU time 0.82 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:35 PM PDT 24
Peak memory 200472 kb
Host smart-311fa6d0-7b9e-4c75-bf12-9c71147eb6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473525306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3473525306
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2248893736
Short name T31
Test name
Test status
Simulation time 1883755726 ps
CPU time 7.55 seconds
Started Aug 16 04:52:32 PM PDT 24
Finished Aug 16 04:52:40 PM PDT 24
Peak memory 217916 kb
Host smart-38ae4073-272e-452b-a0ae-a8ea63ab5078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248893736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2248893736
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.210895007
Short name T140
Test name
Test status
Simulation time 244530200 ps
CPU time 1.11 seconds
Started Aug 16 04:52:37 PM PDT 24
Finished Aug 16 04:52:38 PM PDT 24
Peak memory 217784 kb
Host smart-c5e00d91-b7de-4e94-a202-d69c3a40ea92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210895007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.210895007
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2905704520
Short name T245
Test name
Test status
Simulation time 85498520 ps
CPU time 0.77 seconds
Started Aug 16 04:52:39 PM PDT 24
Finished Aug 16 04:52:40 PM PDT 24
Peak memory 200416 kb
Host smart-a747847f-fb38-4073-abc9-c0c39e386c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905704520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2905704520
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.1710314796
Short name T533
Test name
Test status
Simulation time 2108333051 ps
CPU time 8.58 seconds
Started Aug 16 04:52:38 PM PDT 24
Finished Aug 16 04:52:47 PM PDT 24
Peak memory 200684 kb
Host smart-6c10e240-10a7-4b99-a6ac-7c51f3d5ef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710314796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1710314796
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.623527291
Short name T418
Test name
Test status
Simulation time 160124371 ps
CPU time 1.12 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:35 PM PDT 24
Peak memory 200592 kb
Host smart-a577f390-c039-4f47-b308-e27cbb34a1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623527291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.623527291
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.1565364809
Short name T9
Test name
Test status
Simulation time 262870203 ps
CPU time 1.57 seconds
Started Aug 16 04:52:43 PM PDT 24
Finished Aug 16 04:52:45 PM PDT 24
Peak memory 200712 kb
Host smart-105c6699-8b19-41f1-bed6-ecadaa58f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565364809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.1565364809
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.2381771238
Short name T529
Test name
Test status
Simulation time 7840266423 ps
CPU time 27.4 seconds
Started Aug 16 04:52:39 PM PDT 24
Finished Aug 16 04:53:07 PM PDT 24
Peak memory 200816 kb
Host smart-11456d63-8e8d-45b7-a807-c02a0634fd76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381771238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.2381771238
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.687172838
Short name T531
Test name
Test status
Simulation time 148783544 ps
CPU time 1.84 seconds
Started Aug 16 04:52:32 PM PDT 24
Finished Aug 16 04:52:34 PM PDT 24
Peak memory 200452 kb
Host smart-22391a08-52be-4233-9ed6-850cb5bed330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687172838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.687172838
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.3350798476
Short name T455
Test name
Test status
Simulation time 162665193 ps
CPU time 1.18 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 200604 kb
Host smart-98d23a3e-05be-40bd-b3bd-1d1c27ae51bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350798476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3350798476
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1329552355
Short name T152
Test name
Test status
Simulation time 70873953 ps
CPU time 0.86 seconds
Started Aug 16 04:52:32 PM PDT 24
Finished Aug 16 04:52:33 PM PDT 24
Peak memory 200448 kb
Host smart-3fa4e5ab-d9f5-4fa0-beb0-f55fe909ed9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329552355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1329552355
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.1343108136
Short name T395
Test name
Test status
Simulation time 2357547679 ps
CPU time 8.52 seconds
Started Aug 16 04:52:42 PM PDT 24
Finished Aug 16 04:52:50 PM PDT 24
Peak memory 218032 kb
Host smart-5b707688-a96a-4aad-a33f-5cd4f31ce337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343108136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1343108136
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3565771449
Short name T205
Test name
Test status
Simulation time 244242516 ps
CPU time 1.16 seconds
Started Aug 16 04:52:42 PM PDT 24
Finished Aug 16 04:52:43 PM PDT 24
Peak memory 217760 kb
Host smart-1972cbd0-ba50-4c0c-8188-5066e97dd5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565771449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3565771449
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3895325266
Short name T381
Test name
Test status
Simulation time 114065059 ps
CPU time 0.81 seconds
Started Aug 16 04:52:51 PM PDT 24
Finished Aug 16 04:52:51 PM PDT 24
Peak memory 200404 kb
Host smart-0e2aadd0-95db-44a2-9733-5f1d0cd05463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895325266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3895325266
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.608506482
Short name T276
Test name
Test status
Simulation time 1694299433 ps
CPU time 7.01 seconds
Started Aug 16 04:52:48 PM PDT 24
Finished Aug 16 04:52:55 PM PDT 24
Peak memory 200828 kb
Host smart-b06cd79a-6f4b-46bc-9f2a-c08b35acc0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608506482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.608506482
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.304332268
Short name T307
Test name
Test status
Simulation time 140492108 ps
CPU time 1.08 seconds
Started Aug 16 04:52:38 PM PDT 24
Finished Aug 16 04:52:39 PM PDT 24
Peak memory 200532 kb
Host smart-122bddad-b7f5-461b-8481-edac0d1b6ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304332268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.304332268
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1856504895
Short name T167
Test name
Test status
Simulation time 196333839 ps
CPU time 1.47 seconds
Started Aug 16 04:52:34 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 200720 kb
Host smart-1088ebfe-8eaa-4495-b3a8-d9565cf14dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856504895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1856504895
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1387874481
Short name T220
Test name
Test status
Simulation time 3014140282 ps
CPU time 11.43 seconds
Started Aug 16 04:52:30 PM PDT 24
Finished Aug 16 04:52:42 PM PDT 24
Peak memory 200876 kb
Host smart-3fce2efb-2203-4e66-8c2b-d04007791485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387874481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1387874481
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.645127071
Short name T246
Test name
Test status
Simulation time 143700371 ps
CPU time 1.8 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 200480 kb
Host smart-853c1644-bd63-4cc5-b3da-c50609007aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645127071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.645127071
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.820906648
Short name T496
Test name
Test status
Simulation time 133066779 ps
CPU time 1.04 seconds
Started Aug 16 04:52:35 PM PDT 24
Finished Aug 16 04:52:36 PM PDT 24
Peak memory 200580 kb
Host smart-1389753d-7275-4a98-a113-0925370c1611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820906648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.820906648
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.449123608
Short name T222
Test name
Test status
Simulation time 102116307 ps
CPU time 0.85 seconds
Started Aug 16 04:52:42 PM PDT 24
Finished Aug 16 04:52:43 PM PDT 24
Peak memory 200448 kb
Host smart-91cf0152-f586-45b7-8042-6dbfd0e41caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449123608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.449123608
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.845628623
Short name T304
Test name
Test status
Simulation time 1220671139 ps
CPU time 5.58 seconds
Started Aug 16 04:52:52 PM PDT 24
Finished Aug 16 04:52:58 PM PDT 24
Peak memory 221860 kb
Host smart-084301ac-9737-40bd-a3d6-a24a001309de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845628623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.845628623
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3315226607
Short name T385
Test name
Test status
Simulation time 244203911 ps
CPU time 1.16 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 217808 kb
Host smart-0d9f4d3c-ad97-4471-b8d9-8d63878b56d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315226607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3315226607
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.3961184675
Short name T258
Test name
Test status
Simulation time 246243751 ps
CPU time 0.95 seconds
Started Aug 16 04:52:37 PM PDT 24
Finished Aug 16 04:52:38 PM PDT 24
Peak memory 200400 kb
Host smart-704e0a75-e6dc-4466-ad4e-28c98f576b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961184675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3961184675
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.3367282918
Short name T148
Test name
Test status
Simulation time 1809887752 ps
CPU time 7.2 seconds
Started Aug 16 04:52:35 PM PDT 24
Finished Aug 16 04:52:42 PM PDT 24
Peak memory 200760 kb
Host smart-1d73a55f-c86b-4257-ace2-37b178b6b787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367282918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3367282918
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2826159145
Short name T332
Test name
Test status
Simulation time 169284608 ps
CPU time 1.35 seconds
Started Aug 16 04:52:53 PM PDT 24
Finished Aug 16 04:52:54 PM PDT 24
Peak memory 200580 kb
Host smart-519be764-5e1e-4b86-bfd6-d658063936c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826159145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2826159145
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.714662319
Short name T219
Test name
Test status
Simulation time 245830583 ps
CPU time 1.59 seconds
Started Aug 16 04:52:42 PM PDT 24
Finished Aug 16 04:52:44 PM PDT 24
Peak memory 200712 kb
Host smart-d86dca36-0c22-4493-ae6e-17916b45ad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714662319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.714662319
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.2457217051
Short name T151
Test name
Test status
Simulation time 399950959 ps
CPU time 2.3 seconds
Started Aug 16 04:52:40 PM PDT 24
Finished Aug 16 04:52:43 PM PDT 24
Peak memory 200652 kb
Host smart-677c50f1-3a70-4cdb-ac35-d449801afa0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457217051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2457217051
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2087250585
Short name T437
Test name
Test status
Simulation time 385401644 ps
CPU time 2.42 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 200480 kb
Host smart-2895f9f6-26f6-4f4d-b370-5777cb759418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087250585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2087250585
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.385211373
Short name T510
Test name
Test status
Simulation time 79197747 ps
CPU time 0.8 seconds
Started Aug 16 04:52:33 PM PDT 24
Finished Aug 16 04:52:34 PM PDT 24
Peak memory 200604 kb
Host smart-c9047a0c-0d99-41e5-886d-7050bc744a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385211373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.385211373
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.142001233
Short name T328
Test name
Test status
Simulation time 84995964 ps
CPU time 0.84 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 200428 kb
Host smart-3a12f192-331f-4ae3-af05-a92cefc0e22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142001233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.142001233
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3339111846
Short name T46
Test name
Test status
Simulation time 1224756482 ps
CPU time 6.36 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:53 PM PDT 24
Peak memory 217920 kb
Host smart-80939ed4-3816-4788-8826-e7f64dfe0978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339111846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3339111846
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1740188106
Short name T268
Test name
Test status
Simulation time 244124006 ps
CPU time 1.06 seconds
Started Aug 16 04:52:54 PM PDT 24
Finished Aug 16 04:52:56 PM PDT 24
Peak memory 217736 kb
Host smart-efa99ac7-a1aa-49d4-ae94-49add235da04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740188106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1740188106
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.908083549
Short name T430
Test name
Test status
Simulation time 229484755 ps
CPU time 0.94 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 200304 kb
Host smart-b6460147-704c-4c33-9dad-74a558f05a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908083549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.908083549
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4281860515
Short name T426
Test name
Test status
Simulation time 1120747062 ps
CPU time 4.88 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:51 PM PDT 24
Peak memory 200740 kb
Host smart-8f139515-1472-4a6f-a612-f973b9356cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281860515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4281860515
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.295436611
Short name T377
Test name
Test status
Simulation time 111741627 ps
CPU time 1.02 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 200496 kb
Host smart-96f4836b-3369-4c6d-99f0-3fbc899c2a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295436611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.295436611
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.723455590
Short name T509
Test name
Test status
Simulation time 197582591 ps
CPU time 1.41 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 200768 kb
Host smart-7e8f7e80-22b9-4044-a98f-5ce804372829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723455590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.723455590
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2405922601
Short name T354
Test name
Test status
Simulation time 8479889535 ps
CPU time 37.27 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:53:24 PM PDT 24
Peak memory 209024 kb
Host smart-7e53da4c-8a85-4507-b8ac-cd52fff64444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405922601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2405922601
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1873427080
Short name T452
Test name
Test status
Simulation time 528918961 ps
CPU time 2.76 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 200520 kb
Host smart-86f9167c-41d5-40f1-beef-9e56f79fdb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873427080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1873427080
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.707268538
Short name T494
Test name
Test status
Simulation time 160828773 ps
CPU time 1.32 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 200652 kb
Host smart-091472d1-fcba-4bdd-a8d0-c882504c8298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707268538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.707268538
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.4163100761
Short name T196
Test name
Test status
Simulation time 91658892 ps
CPU time 0.83 seconds
Started Aug 16 04:52:42 PM PDT 24
Finished Aug 16 04:52:43 PM PDT 24
Peak memory 200536 kb
Host smart-910fc6f9-191d-491c-93d5-4f5d5c0f16f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163100761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.4163100761
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.875406795
Short name T527
Test name
Test status
Simulation time 1225992752 ps
CPU time 6.05 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 218020 kb
Host smart-065a6412-bcfc-4b52-b63b-51cde4f40f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875406795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.875406795
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.966473221
Short name T508
Test name
Test status
Simulation time 244319067 ps
CPU time 1.07 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 217716 kb
Host smart-58f88d7d-e464-4a69-91e9-b2d77a72d1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966473221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.966473221
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.2182145788
Short name T504
Test name
Test status
Simulation time 225659375 ps
CPU time 0.94 seconds
Started Aug 16 04:52:44 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 200396 kb
Host smart-d80969e0-a051-4d94-9502-bcaec3521332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182145788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2182145788
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1087535120
Short name T414
Test name
Test status
Simulation time 1718745305 ps
CPU time 7.44 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:53 PM PDT 24
Peak memory 200748 kb
Host smart-2fb1d7a6-dfc3-4250-9577-5f5007a12210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087535120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1087535120
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1964394157
Short name T181
Test name
Test status
Simulation time 140275686 ps
CPU time 1.17 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:52:56 PM PDT 24
Peak memory 200556 kb
Host smart-465c6832-1452-42ab-937e-d0ee64324590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964394157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1964394157
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.1185490118
Short name T499
Test name
Test status
Simulation time 112070867 ps
CPU time 1.17 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:52:56 PM PDT 24
Peak memory 200676 kb
Host smart-f63a8894-4083-4f16-8e58-97ef1247e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185490118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1185490118
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.801427521
Short name T340
Test name
Test status
Simulation time 6808910605 ps
CPU time 28.76 seconds
Started Aug 16 04:53:02 PM PDT 24
Finished Aug 16 04:53:31 PM PDT 24
Peak memory 209016 kb
Host smart-a0e33142-8816-4224-9886-001678a026a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801427521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.801427521
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.566642925
Short name T532
Test name
Test status
Simulation time 144286470 ps
CPU time 1.73 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 200484 kb
Host smart-bf6b0045-48f9-4a7f-ada3-7797c3dcd5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566642925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.566642925
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2423763090
Short name T187
Test name
Test status
Simulation time 243247793 ps
CPU time 1.4 seconds
Started Aug 16 04:52:48 PM PDT 24
Finished Aug 16 04:52:49 PM PDT 24
Peak memory 200568 kb
Host smart-e31ab206-4746-4877-9c71-f9dd487cc753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423763090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2423763090
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.4140195814
Short name T492
Test name
Test status
Simulation time 78203829 ps
CPU time 0.81 seconds
Started Aug 16 04:52:56 PM PDT 24
Finished Aug 16 04:52:57 PM PDT 24
Peak memory 200456 kb
Host smart-8aafd8c7-f488-4a9f-a130-6cbdbf205e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140195814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4140195814
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3108722142
Short name T36
Test name
Test status
Simulation time 2169973555 ps
CPU time 7.69 seconds
Started Aug 16 04:52:43 PM PDT 24
Finished Aug 16 04:52:51 PM PDT 24
Peak memory 217228 kb
Host smart-5ecd3cac-1223-4890-95fc-4fe7f65fc17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108722142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3108722142
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.946171817
Short name T241
Test name
Test status
Simulation time 244232086 ps
CPU time 1.19 seconds
Started Aug 16 04:52:52 PM PDT 24
Finished Aug 16 04:52:54 PM PDT 24
Peak memory 217852 kb
Host smart-7ec01033-c15b-474f-8f1f-fd35833d7f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946171817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.946171817
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2121720047
Short name T81
Test name
Test status
Simulation time 103531598 ps
CPU time 0.83 seconds
Started Aug 16 04:52:41 PM PDT 24
Finished Aug 16 04:52:42 PM PDT 24
Peak memory 200372 kb
Host smart-e049735a-89d6-4bf5-b8cb-1e7ba05e9ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121720047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2121720047
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1303459723
Short name T400
Test name
Test status
Simulation time 908411195 ps
CPU time 4.23 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 200812 kb
Host smart-10ff9371-963b-4bda-871a-f8e4f23ffe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303459723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1303459723
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.4288508855
Short name T283
Test name
Test status
Simulation time 149690355 ps
CPU time 1.18 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:52:57 PM PDT 24
Peak memory 200588 kb
Host smart-0726a4d2-2d14-4864-89d6-2a5136d70647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288508855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.4288508855
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.860991564
Short name T124
Test name
Test status
Simulation time 260453910 ps
CPU time 1.59 seconds
Started Aug 16 04:52:53 PM PDT 24
Finished Aug 16 04:52:55 PM PDT 24
Peak memory 200712 kb
Host smart-e1a30291-5ac0-4b49-b62a-4ed5b7ff5954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860991564 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.860991564
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.2700545034
Short name T324
Test name
Test status
Simulation time 7237754414 ps
CPU time 33.55 seconds
Started Aug 16 04:52:43 PM PDT 24
Finished Aug 16 04:53:17 PM PDT 24
Peak memory 208964 kb
Host smart-92fb752c-9d51-4d76-a55d-73fe6ce5a030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700545034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2700545034
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.773657453
Short name T464
Test name
Test status
Simulation time 248078449 ps
CPU time 1.83 seconds
Started Aug 16 04:52:42 PM PDT 24
Finished Aug 16 04:52:44 PM PDT 24
Peak memory 200568 kb
Host smart-5d948047-0e5c-4286-82a8-8ae12cbf92fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773657453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.773657453
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2015871320
Short name T351
Test name
Test status
Simulation time 145189874 ps
CPU time 1.13 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 200592 kb
Host smart-12f8bab6-e1cf-4a7e-9cd1-b88c0bf08560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015871320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2015871320
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.3300997089
Short name T485
Test name
Test status
Simulation time 71615651 ps
CPU time 0.8 seconds
Started Aug 16 04:51:34 PM PDT 24
Finished Aug 16 04:51:35 PM PDT 24
Peak memory 200392 kb
Host smart-12796793-0e85-4f38-9397-423f38561a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300997089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3300997089
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2208395785
Short name T420
Test name
Test status
Simulation time 1222657553 ps
CPU time 5.65 seconds
Started Aug 16 04:51:31 PM PDT 24
Finished Aug 16 04:51:37 PM PDT 24
Peak memory 221840 kb
Host smart-bc0450f8-bcd8-4028-af9a-104a017cc655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208395785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2208395785
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.4025047606
Short name T265
Test name
Test status
Simulation time 244448252 ps
CPU time 1.15 seconds
Started Aug 16 04:51:29 PM PDT 24
Finished Aug 16 04:51:31 PM PDT 24
Peak memory 217596 kb
Host smart-7663747e-876f-4a54-b5d1-57364f24151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025047606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.4025047606
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.2989572874
Short name T454
Test name
Test status
Simulation time 227609483 ps
CPU time 0.97 seconds
Started Aug 16 04:51:34 PM PDT 24
Finished Aug 16 04:51:35 PM PDT 24
Peak memory 200404 kb
Host smart-c122821d-6fb2-43cf-93a2-5e955d1aacf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989572874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2989572874
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.3585112832
Short name T515
Test name
Test status
Simulation time 879004038 ps
CPU time 4.15 seconds
Started Aug 16 04:51:32 PM PDT 24
Finished Aug 16 04:51:36 PM PDT 24
Peak memory 200676 kb
Host smart-1b7d4749-1aa6-40b4-9ca9-ee4a02df9e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585112832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3585112832
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.227894872
Short name T242
Test name
Test status
Simulation time 145248487 ps
CPU time 1.17 seconds
Started Aug 16 04:51:33 PM PDT 24
Finished Aug 16 04:51:35 PM PDT 24
Peak memory 200592 kb
Host smart-9c99d739-333e-44b8-9eb5-0651f8c6c29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227894872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.227894872
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1043330597
Short name T125
Test name
Test status
Simulation time 260955831 ps
CPU time 1.48 seconds
Started Aug 16 04:51:35 PM PDT 24
Finished Aug 16 04:51:37 PM PDT 24
Peak memory 200620 kb
Host smart-dd16e5a1-5889-4658-91cb-45e19324f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043330597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1043330597
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.467383808
Short name T336
Test name
Test status
Simulation time 5445444122 ps
CPU time 21.66 seconds
Started Aug 16 04:51:35 PM PDT 24
Finished Aug 16 04:51:57 PM PDT 24
Peak memory 200780 kb
Host smart-0959360a-67b3-49c6-90a7-1db3a97ba449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467383808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.467383808
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3881747663
Short name T215
Test name
Test status
Simulation time 126063680 ps
CPU time 1.56 seconds
Started Aug 16 04:51:29 PM PDT 24
Finished Aug 16 04:51:31 PM PDT 24
Peak memory 200408 kb
Host smart-71cd672f-633d-4b3e-814f-079b6727fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881747663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3881747663
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2045816160
Short name T284
Test name
Test status
Simulation time 135357102 ps
CPU time 1.07 seconds
Started Aug 16 04:51:34 PM PDT 24
Finished Aug 16 04:51:35 PM PDT 24
Peak memory 200592 kb
Host smart-d85cf8f7-0a7a-41bb-994b-bc97d7934789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045816160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2045816160
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.1607701010
Short name T190
Test name
Test status
Simulation time 63120982 ps
CPU time 0.76 seconds
Started Aug 16 04:51:35 PM PDT 24
Finished Aug 16 04:51:36 PM PDT 24
Peak memory 200372 kb
Host smart-1929cc34-8c21-49a6-b9e9-52454537dc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607701010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1607701010
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.1544073975
Short name T506
Test name
Test status
Simulation time 1894373546 ps
CPU time 7.37 seconds
Started Aug 16 04:51:32 PM PDT 24
Finished Aug 16 04:51:40 PM PDT 24
Peak memory 217892 kb
Host smart-b028c91f-f534-4510-87de-d0843781b062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544073975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1544073975
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2973586000
Short name T178
Test name
Test status
Simulation time 244076785 ps
CPU time 1.16 seconds
Started Aug 16 04:51:30 PM PDT 24
Finished Aug 16 04:51:32 PM PDT 24
Peak memory 217748 kb
Host smart-1a72434e-224c-4bf4-82f8-29dc024fec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973586000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2973586000
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3953696584
Short name T235
Test name
Test status
Simulation time 175208094 ps
CPU time 0.89 seconds
Started Aug 16 04:51:33 PM PDT 24
Finished Aug 16 04:51:34 PM PDT 24
Peak memory 200320 kb
Host smart-c889e2db-5dee-4754-8a0c-5ac2c2090d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953696584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3953696584
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1471358284
Short name T212
Test name
Test status
Simulation time 1572037485 ps
CPU time 6.66 seconds
Started Aug 16 04:51:32 PM PDT 24
Finished Aug 16 04:51:39 PM PDT 24
Peak memory 200724 kb
Host smart-43c71999-ac9e-4aef-acce-1cde8d2d8595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471358284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1471358284
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3786483759
Short name T519
Test name
Test status
Simulation time 180374225 ps
CPU time 1.22 seconds
Started Aug 16 04:51:30 PM PDT 24
Finished Aug 16 04:51:31 PM PDT 24
Peak memory 200596 kb
Host smart-0c7a032d-34fe-4e8c-a85b-e5c49b535541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786483759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3786483759
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1490638671
Short name T540
Test name
Test status
Simulation time 198490394 ps
CPU time 1.39 seconds
Started Aug 16 04:51:31 PM PDT 24
Finished Aug 16 04:51:33 PM PDT 24
Peak memory 200744 kb
Host smart-94bfa415-9171-4bf2-a02b-ff17c6a49585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490638671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1490638671
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.1053049614
Short name T312
Test name
Test status
Simulation time 3621520471 ps
CPU time 14.3 seconds
Started Aug 16 04:51:32 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 209012 kb
Host smart-0030b5ab-6b9f-4684-b39c-bd38735aef19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053049614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1053049614
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1807389869
Short name T287
Test name
Test status
Simulation time 139776370 ps
CPU time 1.88 seconds
Started Aug 16 04:51:34 PM PDT 24
Finished Aug 16 04:51:36 PM PDT 24
Peak memory 200424 kb
Host smart-171f8811-dcb4-419c-81cf-3b0343cd980d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807389869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1807389869
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.1415185879
Short name T368
Test name
Test status
Simulation time 101733984 ps
CPU time 0.91 seconds
Started Aug 16 04:51:33 PM PDT 24
Finished Aug 16 04:51:34 PM PDT 24
Peak memory 200516 kb
Host smart-cbfe2dee-f7b1-43d0-92bc-258e0a673be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415185879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1415185879
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.3640504622
Short name T469
Test name
Test status
Simulation time 83999339 ps
CPU time 0.85 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:51:40 PM PDT 24
Peak memory 200460 kb
Host smart-00124d22-34bb-4711-87e5-3092b3df6479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640504622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3640504622
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.3364692014
Short name T37
Test name
Test status
Simulation time 1894590022 ps
CPU time 7.07 seconds
Started Aug 16 04:51:35 PM PDT 24
Finished Aug 16 04:51:42 PM PDT 24
Peak memory 216980 kb
Host smart-86464695-e707-42c8-bb80-e218cde91f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364692014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3364692014
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2519285550
Short name T238
Test name
Test status
Simulation time 244661912 ps
CPU time 1.07 seconds
Started Aug 16 04:51:34 PM PDT 24
Finished Aug 16 04:51:36 PM PDT 24
Peak memory 217696 kb
Host smart-5c905ffd-6776-4442-9742-396b517798ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519285550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2519285550
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.257511658
Short name T182
Test name
Test status
Simulation time 175449829 ps
CPU time 0.84 seconds
Started Aug 16 04:51:31 PM PDT 24
Finished Aug 16 04:51:32 PM PDT 24
Peak memory 200320 kb
Host smart-5737d7cf-ba2d-4f76-889f-becccc7e7c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257511658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.257511658
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.2853544603
Short name T347
Test name
Test status
Simulation time 2089204245 ps
CPU time 7.77 seconds
Started Aug 16 04:51:30 PM PDT 24
Finished Aug 16 04:51:38 PM PDT 24
Peak memory 200628 kb
Host smart-dfb743a1-d2e9-481a-9f8a-4e18b013e4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853544603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.2853544603
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3399904459
Short name T391
Test name
Test status
Simulation time 180414022 ps
CPU time 1.24 seconds
Started Aug 16 04:51:30 PM PDT 24
Finished Aug 16 04:51:31 PM PDT 24
Peak memory 200480 kb
Host smart-5b2cfea4-5585-4cf7-8103-759b10930224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399904459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3399904459
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4260038656
Short name T514
Test name
Test status
Simulation time 204698238 ps
CPU time 1.39 seconds
Started Aug 16 04:51:35 PM PDT 24
Finished Aug 16 04:51:37 PM PDT 24
Peak memory 200640 kb
Host smart-40a05e9a-e49f-4bf4-9681-832293286997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260038656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4260038656
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.1522779382
Short name T122
Test name
Test status
Simulation time 7564335638 ps
CPU time 28.46 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:52:07 PM PDT 24
Peak memory 200812 kb
Host smart-534f6ec5-f8ba-4b48-8051-0afea8fe3089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522779382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1522779382
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.457476438
Short name T260
Test name
Test status
Simulation time 413242695 ps
CPU time 2.63 seconds
Started Aug 16 04:51:35 PM PDT 24
Finished Aug 16 04:51:38 PM PDT 24
Peak memory 200436 kb
Host smart-8a6a2a1e-24bd-47e5-87d3-91adaf563259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457476438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.457476438
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.1865374089
Short name T191
Test name
Test status
Simulation time 277568067 ps
CPU time 1.66 seconds
Started Aug 16 04:51:30 PM PDT 24
Finished Aug 16 04:51:32 PM PDT 24
Peak memory 200692 kb
Host smart-2e14e848-a815-43af-a01e-6241d2fbb13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865374089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1865374089
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1844827696
Short name T259
Test name
Test status
Simulation time 81041151 ps
CPU time 0.84 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:51:40 PM PDT 24
Peak memory 200332 kb
Host smart-c6a45375-80a6-450e-9b13-ef47e9d7a224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844827696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1844827696
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.3028008306
Short name T42
Test name
Test status
Simulation time 2350464304 ps
CPU time 8.22 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:51:47 PM PDT 24
Peak memory 218108 kb
Host smart-72a8e98e-a21f-4cfd-82e9-3271cfc04ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028008306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.3028008306
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.4281959784
Short name T306
Test name
Test status
Simulation time 245036433 ps
CPU time 1.01 seconds
Started Aug 16 04:51:37 PM PDT 24
Finished Aug 16 04:51:39 PM PDT 24
Peak memory 217744 kb
Host smart-ab790b29-2f70-430d-98d2-118d3f582486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281959784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.4281959784
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3321628349
Short name T271
Test name
Test status
Simulation time 136623257 ps
CPU time 0.81 seconds
Started Aug 16 04:51:35 PM PDT 24
Finished Aug 16 04:51:37 PM PDT 24
Peak memory 200364 kb
Host smart-1c00d9d6-92c8-462d-8c69-5ad2c4c45dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321628349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3321628349
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.280236113
Short name T91
Test name
Test status
Simulation time 831163649 ps
CPU time 4.51 seconds
Started Aug 16 04:51:35 PM PDT 24
Finished Aug 16 04:51:40 PM PDT 24
Peak memory 200756 kb
Host smart-4bb3d481-e856-46c5-8afa-cfa7dde41fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280236113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.280236113
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1295732959
Short name T263
Test name
Test status
Simulation time 179038299 ps
CPU time 1.19 seconds
Started Aug 16 04:51:33 PM PDT 24
Finished Aug 16 04:51:34 PM PDT 24
Peak memory 200452 kb
Host smart-5b0236e7-6033-40f5-83cf-58f8a4d7bc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295732959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1295732959
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2501985995
Short name T387
Test name
Test status
Simulation time 113024182 ps
CPU time 1.24 seconds
Started Aug 16 04:51:32 PM PDT 24
Finished Aug 16 04:51:33 PM PDT 24
Peak memory 200588 kb
Host smart-6f9ad495-9e5f-4472-8c79-c3f06009b1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501985995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2501985995
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.4123335676
Short name T479
Test name
Test status
Simulation time 1119169715 ps
CPU time 5.79 seconds
Started Aug 16 04:51:42 PM PDT 24
Finished Aug 16 04:51:48 PM PDT 24
Peak memory 200692 kb
Host smart-bad486b1-d029-422d-b554-51ea4881d28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123335676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4123335676
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1501350825
Short name T470
Test name
Test status
Simulation time 278069476 ps
CPU time 1.86 seconds
Started Aug 16 04:51:34 PM PDT 24
Finished Aug 16 04:51:36 PM PDT 24
Peak memory 200492 kb
Host smart-478739b3-bcfd-47b1-8a05-0ece62248eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501350825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1501350825
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.2340947210
Short name T505
Test name
Test status
Simulation time 59654378 ps
CPU time 0.74 seconds
Started Aug 16 04:51:33 PM PDT 24
Finished Aug 16 04:51:34 PM PDT 24
Peak memory 200456 kb
Host smart-286be25d-59d8-4576-afee-7e4be06597d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340947210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.2340947210
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.2475171242
Short name T138
Test name
Test status
Simulation time 65535223 ps
CPU time 0.79 seconds
Started Aug 16 04:51:42 PM PDT 24
Finished Aug 16 04:51:43 PM PDT 24
Peak memory 200468 kb
Host smart-f04e6b91-e895-443b-9584-bce65c2f0091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475171242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2475171242
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2504225982
Short name T398
Test name
Test status
Simulation time 1214332084 ps
CPU time 5.47 seconds
Started Aug 16 04:51:41 PM PDT 24
Finished Aug 16 04:51:46 PM PDT 24
Peak memory 217664 kb
Host smart-6168ccf9-0562-49e9-b931-461bed916910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504225982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2504225982
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3603978945
Short name T264
Test name
Test status
Simulation time 245030544 ps
CPU time 1.05 seconds
Started Aug 16 04:51:39 PM PDT 24
Finished Aug 16 04:51:40 PM PDT 24
Peak memory 217724 kb
Host smart-dea9194e-41c3-4a5c-935d-988a00850771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603978945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3603978945
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2419571566
Short name T218
Test name
Test status
Simulation time 86076691 ps
CPU time 0.78 seconds
Started Aug 16 04:51:40 PM PDT 24
Finished Aug 16 04:51:41 PM PDT 24
Peak memory 200384 kb
Host smart-9ae0da35-3740-481a-81d9-87879ca024ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419571566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2419571566
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3835809841
Short name T327
Test name
Test status
Simulation time 1837634939 ps
CPU time 6.98 seconds
Started Aug 16 04:51:36 PM PDT 24
Finished Aug 16 04:51:44 PM PDT 24
Peak memory 200788 kb
Host smart-cb39ffbf-a62e-4d5a-bf0f-2130dc808a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835809841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3835809841
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3171166710
Short name T308
Test name
Test status
Simulation time 173198799 ps
CPU time 1.17 seconds
Started Aug 16 04:51:43 PM PDT 24
Finished Aug 16 04:51:44 PM PDT 24
Peak memory 200608 kb
Host smart-12e4b020-6906-4214-8f8e-771eae5a6909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171166710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3171166710
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1160043891
Short name T474
Test name
Test status
Simulation time 123622336 ps
CPU time 1.24 seconds
Started Aug 16 04:51:43 PM PDT 24
Finished Aug 16 04:51:44 PM PDT 24
Peak memory 200664 kb
Host smart-bf2f9dd3-ecdc-4d6a-9b55-43848eb121f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160043891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1160043891
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.958057579
Short name T311
Test name
Test status
Simulation time 10752907376 ps
CPU time 37.14 seconds
Started Aug 16 04:51:38 PM PDT 24
Finished Aug 16 04:52:15 PM PDT 24
Peak memory 209032 kb
Host smart-9aef26c3-0568-4a08-b5b4-60b6efdadc53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958057579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.958057579
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.4153988901
Short name T428
Test name
Test status
Simulation time 121778407 ps
CPU time 1.63 seconds
Started Aug 16 04:51:38 PM PDT 24
Finished Aug 16 04:51:39 PM PDT 24
Peak memory 208676 kb
Host smart-cd1735f3-6105-4503-8591-0c08acfabd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153988901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.4153988901
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.2727285492
Short name T174
Test name
Test status
Simulation time 255495384 ps
CPU time 1.61 seconds
Started Aug 16 04:51:40 PM PDT 24
Finished Aug 16 04:51:42 PM PDT 24
Peak memory 200688 kb
Host smart-cd90aa54-44cc-45e4-b7c7-29d32b1004c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727285492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2727285492
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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