Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8282

1

T1

66

T4

13

T5

34

auto[1]

11122

1

T1

78

T2

4

T4

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5956	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6530	1			T1	42		T2	2		T3	1
reset_info_cp[2]	2959	1			T1	31		T2	1		T5	8
reset_info_cp[4]	3956	1			T1	26		T2	1		T5	19
reset_info_cp[8]	124	1			T4	1		T6	1		T29	1
reset_info_cp[16]	115	1			T1	1		T4	1		T5	1
reset_info_cp[32]	126	1			T1	1		T4	1		T11	1
reset_info_cp[64]	133	1			T11	1		T29	1		T104	1
reset_info_cp[128]	125	1			T1	2		T5	1		T12	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3161	1			T1	20		T5	7		T11	64
reset_info_cp[1]	auto[1]	2749	1			T1	21		T2	1		T5	10
reset_info_cp[2]	auto[0]	943	1			T1	10		T5	5		T11	35
reset_info_cp[2]	auto[1]	2016	1			T1	21		T2	1		T5	3
reset_info_cp[4]	auto[0]	1463	1			T1	10		T5	9		T11	44
reset_info_cp[4]	auto[1]	2493	1			T1	16		T2	1		T5	10
reset_info_cp[8]	auto[0]	45	1			T4	1		T6	1		T106	1
reset_info_cp[8]	auto[1]	79	1			T29	1		T104	1		T48	2
reset_info_cp[16]	auto[0]	45	1			T1	1		T4	1		T29	1
reset_info_cp[16]	auto[1]	70	1			T5	1		T11	3		T29	1
reset_info_cp[32]	auto[0]	51	1			T4	1		T11	1		T108	2
reset_info_cp[32]	auto[1]	75	1			T1	1		T12	1		T29	3
reset_info_cp[64]	auto[0]	47	1			T29	1		T104	1		T108	2
reset_info_cp[64]	auto[1]	86	1			T11	1		T41	1		T31	2
reset_info_cp[128]	auto[0]	44	1			T5	1		T12	1		T85	1
reset_info_cp[128]	auto[1]	81	1			T1	2		T108	3		T63	1