Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.39 99.40 99.24 99.87 99.83 99.46 98.52


Total test records in report: 620
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T534 /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2033000363 Aug 17 06:37:28 PM PDT 24 Aug 17 06:37:30 PM PDT 24 233073345 ps
T535 /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.900778708 Aug 17 06:37:40 PM PDT 24 Aug 17 06:37:40 PM PDT 24 66328817 ps
T536 /workspace/coverage/default/39.rstmgr_smoke.1773189032 Aug 17 06:37:50 PM PDT 24 Aug 17 06:37:52 PM PDT 24 190615731 ps
T537 /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1332840082 Aug 17 06:37:39 PM PDT 24 Aug 17 06:37:40 PM PDT 24 160746349 ps
T538 /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.807039486 Aug 17 06:37:05 PM PDT 24 Aug 17 06:37:06 PM PDT 24 243948878 ps
T70 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2714758651 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:42 PM PDT 24 188731977 ps
T71 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.958681289 Aug 17 04:52:50 PM PDT 24 Aug 17 04:52:51 PM PDT 24 64821798 ps
T72 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.632277405 Aug 17 04:53:01 PM PDT 24 Aug 17 04:53:02 PM PDT 24 90824049 ps
T73 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4146608293 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:41 PM PDT 24 102651581 ps
T74 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1609590794 Aug 17 04:52:43 PM PDT 24 Aug 17 04:52:45 PM PDT 24 338359431 ps
T91 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3731048032 Aug 17 04:52:33 PM PDT 24 Aug 17 04:52:36 PM PDT 24 270121475 ps
T75 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.447780959 Aug 17 04:52:45 PM PDT 24 Aug 17 04:52:47 PM PDT 24 420747107 ps
T93 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.582366617 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:41 PM PDT 24 61280860 ps
T539 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.711901922 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:42 PM PDT 24 235867548 ps
T92 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2268461290 Aug 17 04:52:41 PM PDT 24 Aug 17 04:52:42 PM PDT 24 80530099 ps
T76 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.804176929 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:46 PM PDT 24 144783359 ps
T114 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2106096976 Aug 17 04:52:45 PM PDT 24 Aug 17 04:52:46 PM PDT 24 56813498 ps
T88 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3921890988 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:47 PM PDT 24 506370832 ps
T121 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4038158011 Aug 17 04:52:29 PM PDT 24 Aug 17 04:52:30 PM PDT 24 250039484 ps
T122 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3001172443 Aug 17 04:52:47 PM PDT 24 Aug 17 04:52:49 PM PDT 24 96624132 ps
T540 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.391271048 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:47 PM PDT 24 348791180 ps
T123 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1469579404 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:45 PM PDT 24 61869998 ps
T89 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2510675056 Aug 17 04:52:51 PM PDT 24 Aug 17 04:52:53 PM PDT 24 414532924 ps
T90 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2563025268 Aug 17 04:52:48 PM PDT 24 Aug 17 04:52:50 PM PDT 24 486570954 ps
T541 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4111462595 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:50 PM PDT 24 65199078 ps
T113 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.220260218 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:41 PM PDT 24 108829782 ps
T124 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2586531013 Aug 17 04:52:36 PM PDT 24 Aug 17 04:52:37 PM PDT 24 85121603 ps
T125 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.652463093 Aug 17 04:52:53 PM PDT 24 Aug 17 04:52:54 PM PDT 24 77396483 ps
T94 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4154660942 Aug 17 04:52:43 PM PDT 24 Aug 17 04:52:45 PM PDT 24 117867535 ps
T542 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2104941078 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:41 PM PDT 24 96028595 ps
T543 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1386230991 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:43 PM PDT 24 454074831 ps
T98 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3459227055 Aug 17 04:52:47 PM PDT 24 Aug 17 04:52:49 PM PDT 24 193609839 ps
T95 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2310602840 Aug 17 04:52:28 PM PDT 24 Aug 17 04:52:31 PM PDT 24 788960901 ps
T99 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1762281273 Aug 17 04:52:45 PM PDT 24 Aug 17 04:52:47 PM PDT 24 172774865 ps
T544 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1845862330 Aug 17 04:52:41 PM PDT 24 Aug 17 04:52:45 PM PDT 24 264612053 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.74129582 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:42 PM PDT 24 155705811 ps
T126 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.758614309 Aug 17 04:52:36 PM PDT 24 Aug 17 04:52:38 PM PDT 24 226280451 ps
T101 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3124813245 Aug 17 04:52:38 PM PDT 24 Aug 17 04:52:41 PM PDT 24 888041663 ps
T127 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1434885663 Aug 17 04:52:41 PM PDT 24 Aug 17 04:52:43 PM PDT 24 100356365 ps
T102 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1963392565 Aug 17 04:52:39 PM PDT 24 Aug 17 04:52:42 PM PDT 24 485532043 ps
T546 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2473983945 Aug 17 04:52:39 PM PDT 24 Aug 17 04:52:41 PM PDT 24 491567007 ps
T547 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.787124869 Aug 17 04:52:46 PM PDT 24 Aug 17 04:52:47 PM PDT 24 115903877 ps
T548 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1993839642 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:41 PM PDT 24 84615424 ps
T96 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2239668418 Aug 17 04:52:41 PM PDT 24 Aug 17 04:52:44 PM PDT 24 894546004 ps
T549 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1090895236 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:50 PM PDT 24 126623309 ps
T550 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1111733445 Aug 17 04:52:37 PM PDT 24 Aug 17 04:52:39 PM PDT 24 139235708 ps
T551 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.905686749 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:45 PM PDT 24 279160331 ps
T552 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2452511986 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:42 PM PDT 24 153031121 ps
T553 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3124063952 Aug 17 04:52:45 PM PDT 24 Aug 17 04:52:46 PM PDT 24 78284247 ps
T100 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4127472345 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:45 PM PDT 24 869460211 ps
T554 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3133407261 Aug 17 04:52:36 PM PDT 24 Aug 17 04:52:43 PM PDT 24 480292622 ps
T555 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1175546553 Aug 17 04:52:31 PM PDT 24 Aug 17 04:52:32 PM PDT 24 147908654 ps
T556 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4235725632 Aug 17 04:52:46 PM PDT 24 Aug 17 04:52:49 PM PDT 24 188986306 ps
T557 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.732688252 Aug 17 04:52:35 PM PDT 24 Aug 17 04:52:37 PM PDT 24 180749714 ps
T97 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4038130747 Aug 17 04:52:45 PM PDT 24 Aug 17 04:52:47 PM PDT 24 476287909 ps
T558 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3313102648 Aug 17 04:52:43 PM PDT 24 Aug 17 04:52:45 PM PDT 24 134783229 ps
T135 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.258663006 Aug 17 04:52:46 PM PDT 24 Aug 17 04:52:48 PM PDT 24 473067791 ps
T559 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1488990566 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:49 PM PDT 24 183023440 ps
T560 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1933488736 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:41 PM PDT 24 122189357 ps
T561 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4139728686 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:42 PM PDT 24 190332939 ps
T562 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3052970482 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:45 PM PDT 24 112698281 ps
T563 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2211364703 Aug 17 04:52:43 PM PDT 24 Aug 17 04:52:44 PM PDT 24 60079535 ps
T564 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3823003825 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:44 PM PDT 24 160902108 ps
T565 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1052908818 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:45 PM PDT 24 220398291 ps
T566 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3649496443 Aug 17 04:52:47 PM PDT 24 Aug 17 04:52:48 PM PDT 24 161575720 ps
T567 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1430694227 Aug 17 04:52:50 PM PDT 24 Aug 17 04:52:52 PM PDT 24 479871396 ps
T568 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.544002882 Aug 17 04:52:43 PM PDT 24 Aug 17 04:52:45 PM PDT 24 143160492 ps
T569 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3541947817 Aug 17 04:52:55 PM PDT 24 Aug 17 04:52:57 PM PDT 24 157280526 ps
T570 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1745162501 Aug 17 04:52:59 PM PDT 24 Aug 17 04:53:04 PM PDT 24 79863742 ps
T571 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1027694139 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:45 PM PDT 24 84439293 ps
T572 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3319096609 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:44 PM PDT 24 195530955 ps
T573 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3076016552 Aug 17 04:52:37 PM PDT 24 Aug 17 04:52:38 PM PDT 24 106123106 ps
T574 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2413538145 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:42 PM PDT 24 471111028 ps
T575 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.992272274 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:42 PM PDT 24 83105177 ps
T576 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.510073056 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:45 PM PDT 24 59904207 ps
T577 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2749276443 Aug 17 04:52:41 PM PDT 24 Aug 17 04:52:42 PM PDT 24 73483039 ps
T578 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2100818949 Aug 17 04:52:28 PM PDT 24 Aug 17 04:52:29 PM PDT 24 142199751 ps
T579 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2935736044 Aug 17 04:52:43 PM PDT 24 Aug 17 04:52:46 PM PDT 24 260319209 ps
T580 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2956531249 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:43 PM PDT 24 103658701 ps
T581 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3480295100 Aug 17 04:52:30 PM PDT 24 Aug 17 04:52:31 PM PDT 24 72524784 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1467554404 Aug 17 04:52:39 PM PDT 24 Aug 17 04:52:40 PM PDT 24 65160816 ps
T583 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2722200122 Aug 17 04:52:39 PM PDT 24 Aug 17 04:52:40 PM PDT 24 90613273 ps
T584 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2689624968 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:44 PM PDT 24 478151220 ps
T585 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.401401415 Aug 17 04:52:59 PM PDT 24 Aug 17 04:53:04 PM PDT 24 142612916 ps
T586 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3765881497 Aug 17 04:52:48 PM PDT 24 Aug 17 04:52:49 PM PDT 24 165244758 ps
T587 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2219712579 Aug 17 04:52:35 PM PDT 24 Aug 17 04:52:36 PM PDT 24 89038610 ps
T588 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4070167109 Aug 17 04:52:45 PM PDT 24 Aug 17 04:52:48 PM PDT 24 1037154233 ps
T589 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3770210857 Aug 17 04:52:41 PM PDT 24 Aug 17 04:52:44 PM PDT 24 439995683 ps
T590 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4179963555 Aug 17 04:52:51 PM PDT 24 Aug 17 04:52:53 PM PDT 24 56821250 ps
T591 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1919373939 Aug 17 04:52:43 PM PDT 24 Aug 17 04:52:45 PM PDT 24 207159157 ps
T592 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2846620313 Aug 17 04:52:43 PM PDT 24 Aug 17 04:52:44 PM PDT 24 63498549 ps
T136 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2852924146 Aug 17 04:52:28 PM PDT 24 Aug 17 04:52:32 PM PDT 24 944199423 ps
T593 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2309542173 Aug 17 04:52:35 PM PDT 24 Aug 17 04:52:38 PM PDT 24 832370799 ps
T594 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2868199468 Aug 17 04:52:38 PM PDT 24 Aug 17 04:52:40 PM PDT 24 140999760 ps
T595 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1199862826 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:46 PM PDT 24 133695554 ps
T596 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3716172686 Aug 17 04:52:38 PM PDT 24 Aug 17 04:52:41 PM PDT 24 928365146 ps
T597 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1757109822 Aug 17 04:52:41 PM PDT 24 Aug 17 04:52:43 PM PDT 24 133109962 ps
T598 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3492233986 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:43 PM PDT 24 118074081 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3143348642 Aug 17 04:52:48 PM PDT 24 Aug 17 04:52:49 PM PDT 24 221457794 ps
T600 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.221673576 Aug 17 04:52:46 PM PDT 24 Aug 17 04:52:50 PM PDT 24 597569362 ps
T601 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4216886504 Aug 17 04:52:45 PM PDT 24 Aug 17 04:52:48 PM PDT 24 154941652 ps
T602 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.547781214 Aug 17 04:52:34 PM PDT 24 Aug 17 04:52:35 PM PDT 24 61703454 ps
T603 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2549836590 Aug 17 04:52:38 PM PDT 24 Aug 17 04:52:40 PM PDT 24 112578860 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.11466101 Aug 17 04:52:34 PM PDT 24 Aug 17 04:52:42 PM PDT 24 1550455752 ps
T605 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2248118999 Aug 17 04:52:42 PM PDT 24 Aug 17 04:52:43 PM PDT 24 65832442 ps
T606 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1898182207 Aug 17 04:52:35 PM PDT 24 Aug 17 04:52:41 PM PDT 24 482789074 ps
T607 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.792311614 Aug 17 04:52:30 PM PDT 24 Aug 17 04:52:34 PM PDT 24 574836967 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1168222347 Aug 17 04:52:34 PM PDT 24 Aug 17 04:52:37 PM PDT 24 169282472 ps
T609 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1537778613 Aug 17 04:52:44 PM PDT 24 Aug 17 04:52:45 PM PDT 24 128065583 ps
T610 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3364991309 Aug 17 04:52:41 PM PDT 24 Aug 17 04:52:42 PM PDT 24 132993414 ps
T611 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2687102202 Aug 17 04:52:39 PM PDT 24 Aug 17 04:52:41 PM PDT 24 176943324 ps
T612 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4016556354 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:41 PM PDT 24 134027615 ps
T613 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2316644683 Aug 17 04:52:34 PM PDT 24 Aug 17 04:52:36 PM PDT 24 156736057 ps
T614 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.551807771 Aug 17 04:52:38 PM PDT 24 Aug 17 04:52:39 PM PDT 24 133158234 ps
T615 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.350465803 Aug 17 04:52:53 PM PDT 24 Aug 17 04:52:54 PM PDT 24 96499573 ps
T616 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.173922767 Aug 17 04:52:40 PM PDT 24 Aug 17 04:52:41 PM PDT 24 118527583 ps
T617 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2014317853 Aug 17 04:52:48 PM PDT 24 Aug 17 04:52:51 PM PDT 24 881295490 ps
T618 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2677665720 Aug 17 04:52:38 PM PDT 24 Aug 17 04:52:40 PM PDT 24 428411033 ps
T619 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1244494701 Aug 17 04:52:33 PM PDT 24 Aug 17 04:52:37 PM PDT 24 949292919 ps
T620 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2981428515 Aug 17 04:52:32 PM PDT 24 Aug 17 04:52:35 PM PDT 24 383948479 ps

Test location /workspace/coverage/default/31.rstmgr_stress_all.4231621692
Short name T1
Test name
Test status
Simulation time 4414943040 ps
CPU time 17.55 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 209088 kb
Host smart-3a0a517a-bac5-4e57-a6f0-3aba3a396aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231621692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.4231621692
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.697879316
Short name T109
Test name
Test status
Simulation time 406627012 ps
CPU time 2.19 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200528 kb
Host smart-24a8db13-187c-4a0a-861b-8ffe47a3b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697879316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.697879316
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2714758651
Short name T70
Test name
Test status
Simulation time 188731977 ps
CPU time 1.8 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 209192 kb
Host smart-653a98ed-c11e-4f4b-b972-57b5c37dd069
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714758651 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2714758651
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.4015972036
Short name T11
Test name
Test status
Simulation time 12654039755 ps
CPU time 42.7 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:38:30 PM PDT 24
Peak memory 209052 kb
Host smart-4e82fa7a-c227-451c-ba52-b05342bbff48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015972036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4015972036
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2228839841
Short name T47
Test name
Test status
Simulation time 8316049918 ps
CPU time 13.49 seconds
Started Aug 17 06:37:01 PM PDT 24
Finished Aug 17 06:37:15 PM PDT 24
Peak memory 217812 kb
Host smart-72727e94-330f-45e5-b005-67b7c082e41e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228839841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2228839841
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1053173993
Short name T48
Test name
Test status
Simulation time 2172415462 ps
CPU time 7.24 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 216532 kb
Host smart-d36df79f-dcad-4fb8-a767-23f537ba141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053173993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1053173993
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2310602840
Short name T95
Test name
Test status
Simulation time 788960901 ps
CPU time 2.71 seconds
Started Aug 17 04:52:28 PM PDT 24
Finished Aug 17 04:52:31 PM PDT 24
Peak memory 201200 kb
Host smart-7a5c9c9a-e042-47a1-9cba-7931d93764e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310602840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2310602840
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.11923668
Short name T117
Test name
Test status
Simulation time 11225954478 ps
CPU time 43.31 seconds
Started Aug 17 06:37:55 PM PDT 24
Finished Aug 17 06:38:38 PM PDT 24
Peak memory 209848 kb
Host smart-5641228e-78c0-45dc-b9a6-3673f43c9a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11923668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.11923668
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.38187835
Short name T79
Test name
Test status
Simulation time 67493547 ps
CPU time 0.83 seconds
Started Aug 17 06:37:28 PM PDT 24
Finished Aug 17 06:37:29 PM PDT 24
Peak memory 200516 kb
Host smart-0aa2ea38-46b2-4b2e-bc2c-fc8f0c0d0c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38187835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.38187835
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2372362512
Short name T57
Test name
Test status
Simulation time 95538600 ps
CPU time 1.03 seconds
Started Aug 17 06:37:26 PM PDT 24
Finished Aug 17 06:37:27 PM PDT 24
Peak memory 200636 kb
Host smart-3d3617c1-94da-4bad-9490-217436345ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372362512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2372362512
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3443583882
Short name T31
Test name
Test status
Simulation time 1226506257 ps
CPU time 5.66 seconds
Started Aug 17 06:37:20 PM PDT 24
Finished Aug 17 06:37:26 PM PDT 24
Peak memory 217884 kb
Host smart-67bb9280-1370-44bf-9182-594e2131482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443583882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3443583882
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.4235725632
Short name T556
Test name
Test status
Simulation time 188986306 ps
CPU time 2.53 seconds
Started Aug 17 04:52:46 PM PDT 24
Finished Aug 17 04:52:49 PM PDT 24
Peak memory 209164 kb
Host smart-a9e1c2c1-311e-42c0-a7ae-732a940d3a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235725632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4235725632
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1060192409
Short name T51
Test name
Test status
Simulation time 2179557847 ps
CPU time 7.93 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 221972 kb
Host smart-998d93e1-3028-4687-bef5-7125149b4327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060192409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1060192409
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2852924146
Short name T136
Test name
Test status
Simulation time 944199423 ps
CPU time 3.13 seconds
Started Aug 17 04:52:28 PM PDT 24
Finished Aug 17 04:52:32 PM PDT 24
Peak memory 200972 kb
Host smart-849628b6-e68b-4e7a-baa8-9a382f6853ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852924146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2852924146
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.155418162
Short name T10
Test name
Test status
Simulation time 71110088 ps
CPU time 0.87 seconds
Started Aug 17 06:37:42 PM PDT 24
Finished Aug 17 06:37:43 PM PDT 24
Peak memory 200656 kb
Host smart-803c0db6-0b82-4f78-a3e2-31b7fe6371bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155418162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.155418162
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2106096976
Short name T114
Test name
Test status
Simulation time 56813498 ps
CPU time 0.81 seconds
Started Aug 17 04:52:45 PM PDT 24
Finished Aug 17 04:52:46 PM PDT 24
Peak memory 200760 kb
Host smart-ff0f7e38-1b60-4d25-884b-00f0d999c060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106096976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2106096976
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.3347997621
Short name T20
Test name
Test status
Simulation time 82529504 ps
CPU time 0.76 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 200408 kb
Host smart-9731af04-5ac4-45b1-9455-b8c8bff1f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347997621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3347997621
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2928959665
Short name T50
Test name
Test status
Simulation time 1228298581 ps
CPU time 5.63 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 221848 kb
Host smart-4fe0401d-8fa5-41d6-bce0-2ef3510b1cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928959665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2928959665
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.4182363223
Short name T112
Test name
Test status
Simulation time 150026032 ps
CPU time 1.95 seconds
Started Aug 17 06:37:30 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 200504 kb
Host smart-756bded9-5d42-42d3-afc1-2ff2588bcbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182363223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.4182363223
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.391271048
Short name T540
Test name
Test status
Simulation time 348791180 ps
CPU time 2.37 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:47 PM PDT 24
Peak memory 200940 kb
Host smart-44470eca-acd7-45ee-bf99-16db2be74d93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391271048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.391271048
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.11466101
Short name T604
Test name
Test status
Simulation time 1550455752 ps
CPU time 7.76 seconds
Started Aug 17 04:52:34 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 200872 kb
Host smart-f4d16218-091f-4a44-ae4e-34c0ed2f5716
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11466101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.11466101
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1175546553
Short name T555
Test name
Test status
Simulation time 147908654 ps
CPU time 0.99 seconds
Started Aug 17 04:52:31 PM PDT 24
Finished Aug 17 04:52:32 PM PDT 24
Peak memory 200816 kb
Host smart-fcf65a6c-8e0b-4579-afa1-1409b4376295
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175546553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1
175546553
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1488990566
Short name T559
Test name
Test status
Simulation time 183023440 ps
CPU time 1.24 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:49 PM PDT 24
Peak memory 209136 kb
Host smart-2ac922d1-20d5-479e-95e4-40c375882226
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488990566 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1488990566
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1467554404
Short name T582
Test name
Test status
Simulation time 65160816 ps
CPU time 0.77 seconds
Started Aug 17 04:52:39 PM PDT 24
Finished Aug 17 04:52:40 PM PDT 24
Peak memory 200776 kb
Host smart-036dfc86-c700-4c3d-990e-422b195f62cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467554404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1467554404
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2586531013
Short name T124
Test name
Test status
Simulation time 85121603 ps
CPU time 0.99 seconds
Started Aug 17 04:52:36 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 200864 kb
Host smart-afef5d89-611f-4b80-ad6b-e3b3cf8289f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586531013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.2586531013
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2981428515
Short name T620
Test name
Test status
Simulation time 383948479 ps
CPU time 2.66 seconds
Started Aug 17 04:52:32 PM PDT 24
Finished Aug 17 04:52:35 PM PDT 24
Peak memory 212600 kb
Host smart-b5ec0480-4978-4ed1-b2c7-568933f40e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981428515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2981428515
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2316644683
Short name T613
Test name
Test status
Simulation time 156736057 ps
CPU time 1.99 seconds
Started Aug 17 04:52:34 PM PDT 24
Finished Aug 17 04:52:36 PM PDT 24
Peak memory 201020 kb
Host smart-05ef4e92-dc67-44bb-bcc1-64e4bd46b8f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316644683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.2
316644683
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3731048032
Short name T91
Test name
Test status
Simulation time 270121475 ps
CPU time 3.27 seconds
Started Aug 17 04:52:33 PM PDT 24
Finished Aug 17 04:52:36 PM PDT 24
Peak memory 200968 kb
Host smart-abee3273-d371-4551-9a72-9f9bef7966ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731048032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3
731048032
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.551807771
Short name T614
Test name
Test status
Simulation time 133158234 ps
CPU time 0.92 seconds
Started Aug 17 04:52:38 PM PDT 24
Finished Aug 17 04:52:39 PM PDT 24
Peak memory 200792 kb
Host smart-3ee11896-926f-4fd1-b336-fff160f589f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551807771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.551807771
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.732688252
Short name T557
Test name
Test status
Simulation time 180749714 ps
CPU time 1.82 seconds
Started Aug 17 04:52:35 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 209188 kb
Host smart-0bc8a6d1-95b1-45e5-887b-e9ec9192d210
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732688252 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.732688252
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2219712579
Short name T587
Test name
Test status
Simulation time 89038610 ps
CPU time 0.88 seconds
Started Aug 17 04:52:35 PM PDT 24
Finished Aug 17 04:52:36 PM PDT 24
Peak memory 200808 kb
Host smart-6df4a535-cb43-45bf-beb6-78159e868406
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219712579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2219712579
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.758614309
Short name T126
Test name
Test status
Simulation time 226280451 ps
CPU time 1.48 seconds
Started Aug 17 04:52:36 PM PDT 24
Finished Aug 17 04:52:38 PM PDT 24
Peak memory 201016 kb
Host smart-116082bf-b599-49de-9ac3-ae5590fc0131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758614309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sam
e_csr_outstanding.758614309
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.792311614
Short name T607
Test name
Test status
Simulation time 574836967 ps
CPU time 3.76 seconds
Started Aug 17 04:52:30 PM PDT 24
Finished Aug 17 04:52:34 PM PDT 24
Peak memory 217120 kb
Host smart-8106432b-d960-4b3e-bb96-5fc9745a19ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792311614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.792311614
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2239668418
Short name T96
Test name
Test status
Simulation time 894546004 ps
CPU time 2.75 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:44 PM PDT 24
Peak memory 201040 kb
Host smart-e467ee2b-cc33-4812-937a-28e21ea40133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239668418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2239668418
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2452511986
Short name T552
Test name
Test status
Simulation time 153031121 ps
CPU time 1.3 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 209128 kb
Host smart-e9ceda2a-c044-46a3-9fb9-be7c695d1f71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452511986 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2452511986
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1933488736
Short name T560
Test name
Test status
Simulation time 122189357 ps
CPU time 1.35 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 201000 kb
Host smart-27751378-6161-4218-b7b8-7e01b0539ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933488736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.1933488736
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3921890988
Short name T88
Test name
Test status
Simulation time 506370832 ps
CPU time 3 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:47 PM PDT 24
Peak memory 209116 kb
Host smart-f6235f42-8d6f-453a-9d25-9d694ca9ba7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921890988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3921890988
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2689624968
Short name T584
Test name
Test status
Simulation time 478151220 ps
CPU time 1.95 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:44 PM PDT 24
Peak memory 201016 kb
Host smart-2554a647-53f1-496e-9631-aa891ed06b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689624968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2689624968
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3823003825
Short name T564
Test name
Test status
Simulation time 160902108 ps
CPU time 1.52 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:44 PM PDT 24
Peak memory 209192 kb
Host smart-07c504ec-8dac-490b-8a58-80f8497131b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823003825 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3823003825
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.632277405
Short name T72
Test name
Test status
Simulation time 90824049 ps
CPU time 0.9 seconds
Started Aug 17 04:53:01 PM PDT 24
Finished Aug 17 04:53:02 PM PDT 24
Peak memory 200788 kb
Host smart-56dcacfe-4113-4203-81a6-c2bb0a254982
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632277405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.632277405
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.173922767
Short name T616
Test name
Test status
Simulation time 118527583 ps
CPU time 1.22 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 200924 kb
Host smart-6b6a56f9-853f-4451-905b-1b03c1bde82e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173922767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_sa
me_csr_outstanding.173922767
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3541947817
Short name T569
Test name
Test status
Simulation time 157280526 ps
CPU time 1.99 seconds
Started Aug 17 04:52:55 PM PDT 24
Finished Aug 17 04:52:57 PM PDT 24
Peak memory 217252 kb
Host smart-9a64889e-114d-4413-8ce0-d47c3c482fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541947817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3541947817
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2563025268
Short name T90
Test name
Test status
Simulation time 486570954 ps
CPU time 1.87 seconds
Started Aug 17 04:52:48 PM PDT 24
Finished Aug 17 04:52:50 PM PDT 24
Peak memory 201020 kb
Host smart-fdfb752a-10c4-4e2d-94fa-9b05bd54240d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563025268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.2563025268
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1199862826
Short name T595
Test name
Test status
Simulation time 133695554 ps
CPU time 1.39 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:46 PM PDT 24
Peak memory 209188 kb
Host smart-7b7f11d7-c660-447c-b3e5-7eb3c03abc2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199862826 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.1199862826
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.1469579404
Short name T123
Test name
Test status
Simulation time 61869998 ps
CPU time 0.83 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 200784 kb
Host smart-eafa41ac-f486-45fe-9382-c8961a4e48bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469579404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1469579404
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3364991309
Short name T610
Test name
Test status
Simulation time 132993414 ps
CPU time 1.04 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 200928 kb
Host smart-9cba55da-04c6-49a9-9b66-91dca4f62a38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364991309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.3364991309
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.905686749
Short name T551
Test name
Test status
Simulation time 279160331 ps
CPU time 2.35 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 209160 kb
Host smart-29464142-74e6-4591-8894-d9772d087653
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905686749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.905686749
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4038130747
Short name T97
Test name
Test status
Simulation time 476287909 ps
CPU time 2.07 seconds
Started Aug 17 04:52:45 PM PDT 24
Finished Aug 17 04:52:47 PM PDT 24
Peak memory 200908 kb
Host smart-6318a974-27e2-4923-868b-dd3a54770818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038130747 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.4038130747
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4146608293
Short name T73
Test name
Test status
Simulation time 102651581 ps
CPU time 0.99 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 200960 kb
Host smart-8d3c8256-1d66-469d-9fb8-6c99752a0286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146608293 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4146608293
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.958681289
Short name T71
Test name
Test status
Simulation time 64821798 ps
CPU time 0.82 seconds
Started Aug 17 04:52:50 PM PDT 24
Finished Aug 17 04:52:51 PM PDT 24
Peak memory 200720 kb
Host smart-4a83930a-2871-41e2-b588-3bc4f36bb189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958681289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.958681289
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1434885663
Short name T127
Test name
Test status
Simulation time 100356365 ps
CPU time 1.31 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 201016 kb
Host smart-81c69fe9-0c53-4590-be32-267d71bd39e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434885663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.1434885663
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.1111733445
Short name T550
Test name
Test status
Simulation time 139235708 ps
CPU time 1.93 seconds
Started Aug 17 04:52:37 PM PDT 24
Finished Aug 17 04:52:39 PM PDT 24
Peak memory 209276 kb
Host smart-1c18fe07-100f-45a6-b873-44e68ed44654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111733445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1111733445
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3716172686
Short name T596
Test name
Test status
Simulation time 928365146 ps
CPU time 3.03 seconds
Started Aug 17 04:52:38 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 201080 kb
Host smart-f908670b-fab1-4401-a278-7c2f87f3633e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716172686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3716172686
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3765881497
Short name T586
Test name
Test status
Simulation time 165244758 ps
CPU time 1.41 seconds
Started Aug 17 04:52:48 PM PDT 24
Finished Aug 17 04:52:49 PM PDT 24
Peak memory 209200 kb
Host smart-b89bc855-6142-4b3c-b8b0-b9cc5154a7b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765881497 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3765881497
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.2211364703
Short name T563
Test name
Test status
Simulation time 60079535 ps
CPU time 0.74 seconds
Started Aug 17 04:52:43 PM PDT 24
Finished Aug 17 04:52:44 PM PDT 24
Peak memory 200744 kb
Host smart-95c98534-c8bc-4235-a926-6aa7af6bd940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211364703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2211364703
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3001172443
Short name T122
Test name
Test status
Simulation time 96624132 ps
CPU time 1.29 seconds
Started Aug 17 04:52:47 PM PDT 24
Finished Aug 17 04:52:49 PM PDT 24
Peak memory 200996 kb
Host smart-e1b927a5-be6b-4a2c-ac81-d6a87e577483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001172443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3001172443
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2413538145
Short name T574
Test name
Test status
Simulation time 471111028 ps
CPU time 1.91 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 201072 kb
Host smart-b207aa2a-69c0-48e7-aef1-3f593b65b271
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413538145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2413538145
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.787124869
Short name T547
Test name
Test status
Simulation time 115903877 ps
CPU time 0.94 seconds
Started Aug 17 04:52:46 PM PDT 24
Finished Aug 17 04:52:47 PM PDT 24
Peak memory 200940 kb
Host smart-4a5fde8e-df2f-4e93-8f08-f8c6eaa4e6ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787124869 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.787124869
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2248118999
Short name T605
Test name
Test status
Simulation time 65832442 ps
CPU time 0.8 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 200788 kb
Host smart-a95ccb79-21e0-4d30-86f1-054fe55451c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248118999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2248118999
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3313102648
Short name T558
Test name
Test status
Simulation time 134783229 ps
CPU time 1.34 seconds
Started Aug 17 04:52:43 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 200956 kb
Host smart-f4793236-ea36-420a-9b51-f77cf15ca1b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313102648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.3313102648
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.804176929
Short name T76
Test name
Test status
Simulation time 144783359 ps
CPU time 2.11 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:46 PM PDT 24
Peak memory 217252 kb
Host smart-1290da76-aec3-445a-8e61-1ae6f761d697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804176929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.804176929
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.447780959
Short name T75
Test name
Test status
Simulation time 420747107 ps
CPU time 1.75 seconds
Started Aug 17 04:52:45 PM PDT 24
Finished Aug 17 04:52:47 PM PDT 24
Peak memory 209232 kb
Host smart-191e63a4-7f7c-4a49-800f-84f8302c3ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447780959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err
.447780959
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.544002882
Short name T568
Test name
Test status
Simulation time 143160492 ps
CPU time 1.22 seconds
Started Aug 17 04:52:43 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 209040 kb
Host smart-abb8f4eb-3b8f-42ef-8a8b-6494ec51854b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544002882 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.544002882
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2846620313
Short name T592
Test name
Test status
Simulation time 63498549 ps
CPU time 0.79 seconds
Started Aug 17 04:52:43 PM PDT 24
Finished Aug 17 04:52:44 PM PDT 24
Peak memory 200660 kb
Host smart-8181554f-04ac-4434-835c-f7051b85cc06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846620313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2846620313
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3492233986
Short name T598
Test name
Test status
Simulation time 118074081 ps
CPU time 0.99 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 200776 kb
Host smart-b1bd3220-5495-4970-bd6a-4a666d22c0f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492233986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_s
ame_csr_outstanding.3492233986
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.4216886504
Short name T601
Test name
Test status
Simulation time 154941652 ps
CPU time 2.4 seconds
Started Aug 17 04:52:45 PM PDT 24
Finished Aug 17 04:52:48 PM PDT 24
Peak memory 217400 kb
Host smart-99dd81e6-7cf9-415d-8d5f-c9424ed714d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216886504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.4216886504
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1430694227
Short name T567
Test name
Test status
Simulation time 479871396 ps
CPU time 1.87 seconds
Started Aug 17 04:52:50 PM PDT 24
Finished Aug 17 04:52:52 PM PDT 24
Peak memory 200984 kb
Host smart-4d639b24-8391-43f1-9030-1523d4a576a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430694227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.1430694227
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3143348642
Short name T599
Test name
Test status
Simulation time 221457794 ps
CPU time 1.38 seconds
Started Aug 17 04:52:48 PM PDT 24
Finished Aug 17 04:52:49 PM PDT 24
Peak memory 209056 kb
Host smart-d5084c46-e88c-4fd3-86c7-9b18fff9977b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143348642 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3143348642
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2268461290
Short name T92
Test name
Test status
Simulation time 80530099 ps
CPU time 0.81 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 200712 kb
Host smart-dc8c8a3a-4f3d-465d-81c1-dfbdecee471c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268461290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2268461290
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1052908818
Short name T565
Test name
Test status
Simulation time 220398291 ps
CPU time 1.39 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 200972 kb
Host smart-951467ba-757c-4ba4-9a9e-32fea0da95f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052908818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1052908818
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1757109822
Short name T597
Test name
Test status
Simulation time 133109962 ps
CPU time 1.69 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 209156 kb
Host smart-675d8606-fe6d-4c9a-890b-48f4755ddb6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757109822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1757109822
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2309542173
Short name T593
Test name
Test status
Simulation time 832370799 ps
CPU time 2.75 seconds
Started Aug 17 04:52:35 PM PDT 24
Finished Aug 17 04:52:38 PM PDT 24
Peak memory 200988 kb
Host smart-543ebe73-a243-4bfb-90a9-68c33494ce13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309542173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2309542173
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3319096609
Short name T572
Test name
Test status
Simulation time 195530955 ps
CPU time 1.3 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:44 PM PDT 24
Peak memory 209124 kb
Host smart-7d208e41-b4de-4de5-9bd6-bf343d2c0c38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319096609 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3319096609
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.4111462595
Short name T541
Test name
Test status
Simulation time 65199078 ps
CPU time 0.77 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:50 PM PDT 24
Peak memory 200636 kb
Host smart-5a7d325b-a24c-413c-a3da-7643ecbfb85b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111462595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.4111462595
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.652463093
Short name T125
Test name
Test status
Simulation time 77396483 ps
CPU time 0.92 seconds
Started Aug 17 04:52:53 PM PDT 24
Finished Aug 17 04:52:54 PM PDT 24
Peak memory 200712 kb
Host smart-c59479e3-0bfa-48ba-9d6c-5534a351cb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652463093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_sa
me_csr_outstanding.652463093
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.3459227055
Short name T98
Test name
Test status
Simulation time 193609839 ps
CPU time 1.61 seconds
Started Aug 17 04:52:47 PM PDT 24
Finished Aug 17 04:52:49 PM PDT 24
Peak memory 209112 kb
Host smart-2e6505c3-9b38-4c22-95a1-62d0b304af83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459227055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3459227055
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2510675056
Short name T89
Test name
Test status
Simulation time 414532924 ps
CPU time 1.79 seconds
Started Aug 17 04:52:51 PM PDT 24
Finished Aug 17 04:52:53 PM PDT 24
Peak memory 200904 kb
Host smart-bd213557-ae85-4236-af57-b70768cbbc13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510675056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2510675056
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3649496443
Short name T566
Test name
Test status
Simulation time 161575720 ps
CPU time 1.37 seconds
Started Aug 17 04:52:47 PM PDT 24
Finished Aug 17 04:52:48 PM PDT 24
Peak memory 209272 kb
Host smart-20eb7ff6-42ef-4aea-afa8-21c6e1f76bdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649496443 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.3649496443
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.1745162501
Short name T570
Test name
Test status
Simulation time 79863742 ps
CPU time 0.9 seconds
Started Aug 17 04:52:59 PM PDT 24
Finished Aug 17 04:53:04 PM PDT 24
Peak memory 200772 kb
Host smart-0bf764dc-0319-4c17-8755-0d17e6c73f66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745162501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1745162501
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.4016556354
Short name T612
Test name
Test status
Simulation time 134027615 ps
CPU time 1.1 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 200772 kb
Host smart-173dc9a7-c188-44a0-b8a7-9305f77d6a2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016556354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.4016556354
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.4154660942
Short name T94
Test name
Test status
Simulation time 117867535 ps
CPU time 1.7 seconds
Started Aug 17 04:52:43 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 209196 kb
Host smart-14e03022-8685-443d-884a-d9a600bc6687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154660942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.4154660942
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.4070167109
Short name T588
Test name
Test status
Simulation time 1037154233 ps
CPU time 3.09 seconds
Started Aug 17 04:52:45 PM PDT 24
Finished Aug 17 04:52:48 PM PDT 24
Peak memory 200992 kb
Host smart-77aa6801-f6d3-48aa-bdb3-8e2e139a4914
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070167109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.4070167109
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.711901922
Short name T539
Test name
Test status
Simulation time 235867548 ps
CPU time 1.55 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 201004 kb
Host smart-da12be18-f1a5-4b75-b19f-95e9f5c27caa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711901922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.711901922
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3133407261
Short name T554
Test name
Test status
Simulation time 480292622 ps
CPU time 6.03 seconds
Started Aug 17 04:52:36 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 200928 kb
Host smart-5daaa1f2-3b28-4e0f-8ac6-232092e01bae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133407261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3
133407261
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3076016552
Short name T573
Test name
Test status
Simulation time 106123106 ps
CPU time 0.85 seconds
Started Aug 17 04:52:37 PM PDT 24
Finished Aug 17 04:52:38 PM PDT 24
Peak memory 200740 kb
Host smart-692ea538-9ea6-467b-88cc-afeb82669e68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076016552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.3
076016552
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2100818949
Short name T578
Test name
Test status
Simulation time 142199751 ps
CPU time 1.21 seconds
Started Aug 17 04:52:28 PM PDT 24
Finished Aug 17 04:52:29 PM PDT 24
Peak memory 209076 kb
Host smart-d40a894b-0ffb-4744-8373-753e7502c1d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100818949 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2100818949
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.547781214
Short name T602
Test name
Test status
Simulation time 61703454 ps
CPU time 0.79 seconds
Started Aug 17 04:52:34 PM PDT 24
Finished Aug 17 04:52:35 PM PDT 24
Peak memory 200704 kb
Host smart-6eb25b02-39b0-42a0-aee3-3fb345ef87b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547781214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.547781214
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3124063952
Short name T553
Test name
Test status
Simulation time 78284247 ps
CPU time 0.97 seconds
Started Aug 17 04:52:45 PM PDT 24
Finished Aug 17 04:52:46 PM PDT 24
Peak memory 200828 kb
Host smart-58e33b7b-d3c4-42a4-b8d3-ee39f7a6dd86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124063952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.3124063952
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2549836590
Short name T603
Test name
Test status
Simulation time 112578860 ps
CPU time 1.43 seconds
Started Aug 17 04:52:38 PM PDT 24
Finished Aug 17 04:52:40 PM PDT 24
Peak memory 211216 kb
Host smart-96495923-3a07-4797-a00e-c0a12e894dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549836590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2549836590
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1244494701
Short name T619
Test name
Test status
Simulation time 949292919 ps
CPU time 3.39 seconds
Started Aug 17 04:52:33 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 200960 kb
Host smart-6d343708-68d8-4a33-83df-faa58d1ba512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244494701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1244494701
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1386230991
Short name T543
Test name
Test status
Simulation time 454074831 ps
CPU time 2.57 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 209192 kb
Host smart-240408e5-aa96-48c6-9eb2-ba679cba74d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386230991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
386230991
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1845862330
Short name T544
Test name
Test status
Simulation time 264612053 ps
CPU time 3.17 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 200836 kb
Host smart-696b9ae8-5c10-4233-b1ec-f7ea9c794ed2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845862330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
845862330
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2956531249
Short name T580
Test name
Test status
Simulation time 103658701 ps
CPU time 0.83 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 200648 kb
Host smart-5cde6440-17af-4de9-972a-33450245a58f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956531249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2
956531249
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.582366617
Short name T93
Test name
Test status
Simulation time 61280860 ps
CPU time 0.82 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 200712 kb
Host smart-49e2c660-28b8-4d6b-9157-54e3f233d34b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582366617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.582366617
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4038158011
Short name T121
Test name
Test status
Simulation time 250039484 ps
CPU time 1.57 seconds
Started Aug 17 04:52:29 PM PDT 24
Finished Aug 17 04:52:30 PM PDT 24
Peak memory 201004 kb
Host smart-b12b9ea7-5009-4b48-8cf4-941c084f0b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038158011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4038158011
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.3770210857
Short name T589
Test name
Test status
Simulation time 439995683 ps
CPU time 3.07 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:44 PM PDT 24
Peak memory 209140 kb
Host smart-3a4c95eb-accd-4464-aff9-5a67ca5e082c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770210857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3770210857
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4127472345
Short name T100
Test name
Test status
Simulation time 869460211 ps
CPU time 3.02 seconds
Started Aug 17 04:52:42 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 209172 kb
Host smart-862b73cd-35bd-4b1c-abbc-14652390eac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127472345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.4127472345
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.74129582
Short name T545
Test name
Test status
Simulation time 155705811 ps
CPU time 1.89 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 201144 kb
Host smart-d212dc7c-a495-4762-be12-851ec03856e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74129582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.74129582
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1898182207
Short name T606
Test name
Test status
Simulation time 482789074 ps
CPU time 5.73 seconds
Started Aug 17 04:52:35 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 200856 kb
Host smart-e6333c45-3448-414f-aa6e-20e2edb482bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898182207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1
898182207
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2104941078
Short name T542
Test name
Test status
Simulation time 96028595 ps
CPU time 0.89 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 200740 kb
Host smart-65a3c0fb-69d5-4683-8c5f-bb108daf21b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104941078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2
104941078
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.350465803
Short name T615
Test name
Test status
Simulation time 96499573 ps
CPU time 0.91 seconds
Started Aug 17 04:52:53 PM PDT 24
Finished Aug 17 04:52:54 PM PDT 24
Peak memory 200900 kb
Host smart-6962360e-200c-4b3a-9f65-542ac0ccb807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350465803 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.350465803
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3480295100
Short name T581
Test name
Test status
Simulation time 72524784 ps
CPU time 0.83 seconds
Started Aug 17 04:52:30 PM PDT 24
Finished Aug 17 04:52:31 PM PDT 24
Peak memory 200780 kb
Host smart-a019fa90-d690-4e8a-b3df-1dcba648ee3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480295100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3480295100
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1537778613
Short name T609
Test name
Test status
Simulation time 128065583 ps
CPU time 1.27 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 201008 kb
Host smart-a180d035-31c2-44e5-a9ee-1666fb3d062d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537778613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.1537778613
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1168222347
Short name T608
Test name
Test status
Simulation time 169282472 ps
CPU time 2.19 seconds
Started Aug 17 04:52:34 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 211668 kb
Host smart-553af486-dfa4-4bba-9ece-0dc549dc7036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168222347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1168222347
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.220260218
Short name T113
Test name
Test status
Simulation time 108829782 ps
CPU time 0.97 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 200776 kb
Host smart-5e81d1ef-5bb8-400c-9265-26b0f885069e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220260218 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.220260218
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.4179963555
Short name T590
Test name
Test status
Simulation time 56821250 ps
CPU time 0.75 seconds
Started Aug 17 04:52:51 PM PDT 24
Finished Aug 17 04:52:53 PM PDT 24
Peak memory 200796 kb
Host smart-56ef0bc5-2865-42e9-b292-9a9d2878afcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179963555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4179963555
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1027694139
Short name T571
Test name
Test status
Simulation time 84439293 ps
CPU time 0.95 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 200828 kb
Host smart-543630b8-f2a9-4879-82a5-660e97a6c425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027694139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1027694139
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.221673576
Short name T600
Test name
Test status
Simulation time 597569362 ps
CPU time 3.93 seconds
Started Aug 17 04:52:46 PM PDT 24
Finished Aug 17 04:52:50 PM PDT 24
Peak memory 209312 kb
Host smart-17bb2780-f5d3-4300-8e9d-89f28678e33f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221673576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.221673576
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2677665720
Short name T618
Test name
Test status
Simulation time 428411033 ps
CPU time 1.84 seconds
Started Aug 17 04:52:38 PM PDT 24
Finished Aug 17 04:52:40 PM PDT 24
Peak memory 201192 kb
Host smart-784a68f1-84da-472d-931e-92116a6d68f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677665720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.2677665720
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1919373939
Short name T591
Test name
Test status
Simulation time 207159157 ps
CPU time 1.39 seconds
Started Aug 17 04:52:43 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 209140 kb
Host smart-9a5ed90d-7892-408c-a5e4-711b93b3e6db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919373939 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1919373939
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2749276443
Short name T577
Test name
Test status
Simulation time 73483039 ps
CPU time 0.83 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 200596 kb
Host smart-064657f1-aa79-490f-90b0-91f9de52e398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749276443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2749276443
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.401401415
Short name T585
Test name
Test status
Simulation time 142612916 ps
CPU time 1.12 seconds
Started Aug 17 04:52:59 PM PDT 24
Finished Aug 17 04:53:04 PM PDT 24
Peak memory 200756 kb
Host smart-7245367e-65f5-444e-a6f4-cc6c9698a3e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401401415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.401401415
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2935736044
Short name T579
Test name
Test status
Simulation time 260319209 ps
CPU time 2.1 seconds
Started Aug 17 04:52:43 PM PDT 24
Finished Aug 17 04:52:46 PM PDT 24
Peak memory 209112 kb
Host smart-9ee91873-ebf6-48bb-b3ca-dc5073fd1a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935736044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2935736044
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2014317853
Short name T617
Test name
Test status
Simulation time 881295490 ps
CPU time 2.8 seconds
Started Aug 17 04:52:48 PM PDT 24
Finished Aug 17 04:52:51 PM PDT 24
Peak memory 200964 kb
Host smart-e31e98c5-a67e-4440-a262-272a458f9b97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014317853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.2014317853
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3052970482
Short name T562
Test name
Test status
Simulation time 112698281 ps
CPU time 0.93 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 200892 kb
Host smart-a4aad52f-bbfd-4473-9215-1b41dfe3c594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052970482 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3052970482
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.510073056
Short name T576
Test name
Test status
Simulation time 59904207 ps
CPU time 0.81 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 200636 kb
Host smart-1318717d-1889-4750-b396-ad2a4036c6a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510073056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.510073056
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1090895236
Short name T549
Test name
Test status
Simulation time 126623309 ps
CPU time 1.24 seconds
Started Aug 17 04:52:44 PM PDT 24
Finished Aug 17 04:52:50 PM PDT 24
Peak memory 200916 kb
Host smart-bfcf117d-00bf-4b0b-89cc-4a9ca160048a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090895236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1090895236
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.1762281273
Short name T99
Test name
Test status
Simulation time 172774865 ps
CPU time 2.32 seconds
Started Aug 17 04:52:45 PM PDT 24
Finished Aug 17 04:52:47 PM PDT 24
Peak memory 209120 kb
Host smart-7db2904b-966a-44a0-ad45-0e38a718f1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762281273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1762281273
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3124813245
Short name T101
Test name
Test status
Simulation time 888041663 ps
CPU time 3.09 seconds
Started Aug 17 04:52:38 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 201048 kb
Host smart-6c69b642-d44c-425b-acaf-542dfcbbe683
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124813245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3124813245
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2687102202
Short name T611
Test name
Test status
Simulation time 176943324 ps
CPU time 1.75 seconds
Started Aug 17 04:52:39 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 209516 kb
Host smart-6c59b697-8f17-4e31-86d0-5b62848fb9b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687102202 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.2687102202
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.1993839642
Short name T548
Test name
Test status
Simulation time 84615424 ps
CPU time 0.85 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 200796 kb
Host smart-296c0109-df84-484f-abf7-662fff9c18c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993839642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1993839642
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.992272274
Short name T575
Test name
Test status
Simulation time 83105177 ps
CPU time 0.97 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 200888 kb
Host smart-c3d91fa1-0a5a-4ea4-9d38-1a3daf08f2c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992272274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.992272274
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1963392565
Short name T102
Test name
Test status
Simulation time 485532043 ps
CPU time 3.23 seconds
Started Aug 17 04:52:39 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 209232 kb
Host smart-cb400422-1a3c-43cc-8f0b-bb34958820b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963392565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1963392565
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.258663006
Short name T135
Test name
Test status
Simulation time 473067791 ps
CPU time 1.89 seconds
Started Aug 17 04:52:46 PM PDT 24
Finished Aug 17 04:52:48 PM PDT 24
Peak memory 200980 kb
Host smart-ecd9d049-46b0-42a9-8003-4ed2723f2392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258663006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
258663006
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2868199468
Short name T594
Test name
Test status
Simulation time 140999760 ps
CPU time 1.09 seconds
Started Aug 17 04:52:38 PM PDT 24
Finished Aug 17 04:52:40 PM PDT 24
Peak memory 209024 kb
Host smart-558183cd-28fb-459a-a64d-297acacb7be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868199468 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2868199468
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.2722200122
Short name T583
Test name
Test status
Simulation time 90613273 ps
CPU time 0.86 seconds
Started Aug 17 04:52:39 PM PDT 24
Finished Aug 17 04:52:40 PM PDT 24
Peak memory 200648 kb
Host smart-f403237a-4088-4f44-94c9-7551725ddb24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722200122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2722200122
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.4139728686
Short name T561
Test name
Test status
Simulation time 190332939 ps
CPU time 1.41 seconds
Started Aug 17 04:52:40 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 200944 kb
Host smart-6cdd73b0-385b-4b50-9dfa-e3d0f2d260ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139728686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.4139728686
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1609590794
Short name T74
Test name
Test status
Simulation time 338359431 ps
CPU time 2.38 seconds
Started Aug 17 04:52:43 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 209288 kb
Host smart-424ab940-861c-447d-afe2-123e2fc91326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609590794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1609590794
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2473983945
Short name T546
Test name
Test status
Simulation time 491567007 ps
CPU time 1.88 seconds
Started Aug 17 04:52:39 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 201064 kb
Host smart-a27bc6fe-fc9e-4749-8f7c-abca4e937925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473983945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2473983945
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.1956020281
Short name T283
Test name
Test status
Simulation time 84040416 ps
CPU time 0.83 seconds
Started Aug 17 06:37:01 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 200444 kb
Host smart-489f6f8b-8c29-4469-944d-ce0ea26239cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956020281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1956020281
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.1833482147
Short name T36
Test name
Test status
Simulation time 1234034257 ps
CPU time 5.86 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 217916 kb
Host smart-ce9c4c18-f0f4-4545-a55a-d6efd424492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833482147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1833482147
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3385035264
Short name T138
Test name
Test status
Simulation time 243746104 ps
CPU time 1.1 seconds
Started Aug 17 06:37:00 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 217720 kb
Host smart-0cd48762-4aad-491a-9e4d-5e94a6486d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385035264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3385035264
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3582709923
Short name T262
Test name
Test status
Simulation time 1261170602 ps
CPU time 5.86 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 200816 kb
Host smart-cff3d615-d9b1-46f1-8290-b3390ec9a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582709923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3582709923
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1757629668
Short name T81
Test name
Test status
Simulation time 16512332608 ps
CPU time 29.27 seconds
Started Aug 17 06:37:11 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 217396 kb
Host smart-db6a2de6-a6d9-4ce9-a26e-34471021ee20
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757629668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1757629668
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.144847632
Short name T252
Test name
Test status
Simulation time 173116031 ps
CPU time 1.22 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 200592 kb
Host smart-dd7fda70-8f62-42ae-9d11-a860c7044e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144847632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.144847632
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.735334304
Short name T183
Test name
Test status
Simulation time 114240237 ps
CPU time 1.18 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:36:57 PM PDT 24
Peak memory 200800 kb
Host smart-37851904-fbd9-484c-af95-da3d15cf0e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735334304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.735334304
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.481349303
Short name T251
Test name
Test status
Simulation time 4571187022 ps
CPU time 17.01 seconds
Started Aug 17 06:37:04 PM PDT 24
Finished Aug 17 06:37:22 PM PDT 24
Peak memory 209064 kb
Host smart-9dc485c2-7dd1-46dc-be82-79e2598e95f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481349303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.481349303
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.1103693318
Short name T156
Test name
Test status
Simulation time 314651672 ps
CPU time 2.03 seconds
Started Aug 17 06:36:54 PM PDT 24
Finished Aug 17 06:36:56 PM PDT 24
Peak memory 208668 kb
Host smart-70ffc522-7278-49ef-879a-e51320345918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103693318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1103693318
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.3344546611
Short name T482
Test name
Test status
Simulation time 71534663 ps
CPU time 0.78 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 200592 kb
Host smart-2819196f-6305-498e-ba90-164f9a1836a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344546611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3344546611
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.4186425146
Short name T263
Test name
Test status
Simulation time 73780463 ps
CPU time 0.76 seconds
Started Aug 17 06:37:04 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 200516 kb
Host smart-09bd6e5a-c11c-46de-887f-8b422fafedc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186425146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.4186425146
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.205345231
Short name T448
Test name
Test status
Simulation time 1901794942 ps
CPU time 7.43 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 221880 kb
Host smart-8bc90487-7b3f-4674-8455-787910b27752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205345231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.205345231
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3683767797
Short name T8
Test name
Test status
Simulation time 244240812 ps
CPU time 1.06 seconds
Started Aug 17 06:36:59 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 217860 kb
Host smart-e2869751-8d7d-472f-a959-d4fa7b33b67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683767797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3683767797
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2004495885
Short name T410
Test name
Test status
Simulation time 90981701 ps
CPU time 0.75 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:10 PM PDT 24
Peak memory 200448 kb
Host smart-2da08287-3a8e-4e68-86a6-0e9c1b3cf83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004495885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2004495885
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.600768306
Short name T470
Test name
Test status
Simulation time 1643459989 ps
CPU time 6.26 seconds
Started Aug 17 06:37:12 PM PDT 24
Finished Aug 17 06:37:19 PM PDT 24
Peak memory 200868 kb
Host smart-483d68a9-1deb-41f0-91a4-3b09045f888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600768306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.600768306
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3438784716
Short name T358
Test name
Test status
Simulation time 152360392 ps
CPU time 1.18 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 200640 kb
Host smart-8b0cc7ed-1231-4786-8643-496c14dacecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438784716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3438784716
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1532412139
Short name T521
Test name
Test status
Simulation time 187449173 ps
CPU time 1.42 seconds
Started Aug 17 06:37:02 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 200800 kb
Host smart-c1783393-5b0d-4037-ab5e-743c280da9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532412139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1532412139
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.2373487027
Short name T455
Test name
Test status
Simulation time 7497308549 ps
CPU time 31.97 seconds
Started Aug 17 06:36:59 PM PDT 24
Finished Aug 17 06:37:31 PM PDT 24
Peak memory 208960 kb
Host smart-7b7095d8-5aa0-44f1-8950-021ca49d0168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373487027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2373487027
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2694582014
Short name T511
Test name
Test status
Simulation time 271079979 ps
CPU time 1.78 seconds
Started Aug 17 06:37:04 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 200508 kb
Host smart-977868cc-6bcb-4e7d-abde-984684668188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694582014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2694582014
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2002581082
Short name T247
Test name
Test status
Simulation time 149951287 ps
CPU time 1.15 seconds
Started Aug 17 06:37:11 PM PDT 24
Finished Aug 17 06:37:13 PM PDT 24
Peak memory 200620 kb
Host smart-ae1f22f8-210e-4bcf-a89f-3305f1e6bd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002581082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2002581082
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1569410035
Short name T226
Test name
Test status
Simulation time 72659147 ps
CPU time 0.77 seconds
Started Aug 17 06:37:17 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 200472 kb
Host smart-4643532d-6321-4cf7-9c5e-dad0e013ee6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569410035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1569410035
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1912793836
Short name T273
Test name
Test status
Simulation time 1902839577 ps
CPU time 6.76 seconds
Started Aug 17 06:37:19 PM PDT 24
Finished Aug 17 06:37:26 PM PDT 24
Peak memory 221952 kb
Host smart-91920c1b-b61f-4224-8fc7-dc7aefd0cb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912793836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1912793836
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2685391042
Short name T173
Test name
Test status
Simulation time 243659794 ps
CPU time 1.12 seconds
Started Aug 17 06:37:23 PM PDT 24
Finished Aug 17 06:37:24 PM PDT 24
Peak memory 217800 kb
Host smart-d9eae0a9-145d-4696-8467-bccb3657bfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685391042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2685391042
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.500874122
Short name T472
Test name
Test status
Simulation time 190235701 ps
CPU time 0.95 seconds
Started Aug 17 06:37:13 PM PDT 24
Finished Aug 17 06:37:14 PM PDT 24
Peak memory 200448 kb
Host smart-b9f7b4c9-778b-4038-940b-6785cb0e98bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500874122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.500874122
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1883832165
Short name T120
Test name
Test status
Simulation time 956545775 ps
CPU time 4.69 seconds
Started Aug 17 06:37:13 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 200812 kb
Host smart-1d967b2f-1625-407d-97a2-228e327292fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883832165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1883832165
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1000141356
Short name T363
Test name
Test status
Simulation time 144916691 ps
CPU time 1.23 seconds
Started Aug 17 06:37:25 PM PDT 24
Finished Aug 17 06:37:26 PM PDT 24
Peak memory 200540 kb
Host smart-bcfe8e84-c5b6-40f8-ac3f-c0b7e89a3d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000141356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1000141356
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.728190743
Short name T202
Test name
Test status
Simulation time 202190827 ps
CPU time 1.41 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:10 PM PDT 24
Peak memory 200640 kb
Host smart-9a1cb4b1-f92c-454e-b3a7-efc55cf08849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728190743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.728190743
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.2508073654
Short name T304
Test name
Test status
Simulation time 6747586722 ps
CPU time 27.22 seconds
Started Aug 17 06:37:20 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 209044 kb
Host smart-21c4e69d-0885-4306-b88b-ed6f72d5e83e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508073654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2508073654
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2947288193
Short name T14
Test name
Test status
Simulation time 260702111 ps
CPU time 1.71 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 200480 kb
Host smart-3f2fd460-1610-41fa-ad9a-68a48cf2e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947288193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2947288193
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2004179204
Short name T241
Test name
Test status
Simulation time 104374685 ps
CPU time 1 seconds
Started Aug 17 06:37:16 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 200652 kb
Host smart-2b373688-686f-43b1-852c-9691dd69d3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004179204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2004179204
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.3939074575
Short name T460
Test name
Test status
Simulation time 70076183 ps
CPU time 0.76 seconds
Started Aug 17 06:37:11 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 200524 kb
Host smart-83b1fd54-e0cb-42ee-b5dd-06431a49ccc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939074575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3939074575
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2565948786
Short name T493
Test name
Test status
Simulation time 244121457 ps
CPU time 1.14 seconds
Started Aug 17 06:37:16 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 217764 kb
Host smart-800f052d-1b06-4936-858d-9005da7e9a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565948786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2565948786
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.3077225585
Short name T481
Test name
Test status
Simulation time 180493310 ps
CPU time 0.86 seconds
Started Aug 17 06:37:17 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 200292 kb
Host smart-c655fd38-c716-4b4b-95e5-f9a8a6764b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077225585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3077225585
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.376794572
Short name T103
Test name
Test status
Simulation time 1703623500 ps
CPU time 6.46 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:15 PM PDT 24
Peak memory 200700 kb
Host smart-72a886c9-112e-4533-b4d3-fe94c776b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376794572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.376794572
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.675219386
Short name T337
Test name
Test status
Simulation time 147700355 ps
CPU time 1.13 seconds
Started Aug 17 06:37:21 PM PDT 24
Finished Aug 17 06:37:22 PM PDT 24
Peak memory 200644 kb
Host smart-ab621b9a-b855-42fe-9bd5-0e87b3513440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675219386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.675219386
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.3121238461
Short name T87
Test name
Test status
Simulation time 223291269 ps
CPU time 1.45 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 200736 kb
Host smart-385d4c00-3685-475c-afad-c43f932b9359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121238461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3121238461
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.1297251553
Short name T311
Test name
Test status
Simulation time 8340559686 ps
CPU time 34.18 seconds
Started Aug 17 06:37:19 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 209088 kb
Host smart-e3d118f9-5dd9-4bbe-98ec-866c722e7ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297251553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1297251553
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.954008302
Short name T86
Test name
Test status
Simulation time 492955282 ps
CPU time 2.63 seconds
Started Aug 17 06:37:20 PM PDT 24
Finished Aug 17 06:37:22 PM PDT 24
Peak memory 200592 kb
Host smart-8546de9e-de4b-40d0-9256-5b5d891ce6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954008302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.954008302
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1343998587
Short name T401
Test name
Test status
Simulation time 114656139 ps
CPU time 0.97 seconds
Started Aug 17 06:37:21 PM PDT 24
Finished Aug 17 06:37:22 PM PDT 24
Peak memory 200652 kb
Host smart-33015e67-4d20-4d3b-918f-fa110646dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343998587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1343998587
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2001910753
Short name T141
Test name
Test status
Simulation time 71693065 ps
CPU time 0.81 seconds
Started Aug 17 06:37:32 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 200524 kb
Host smart-c311f464-ec81-447b-97e6-0e19700c4dee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001910753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2001910753
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3292825396
Short name T302
Test name
Test status
Simulation time 1236414358 ps
CPU time 5.78 seconds
Started Aug 17 06:37:31 PM PDT 24
Finished Aug 17 06:37:37 PM PDT 24
Peak memory 217964 kb
Host smart-a54c83cb-b92e-43e5-ab53-88f3bc057086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292825396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3292825396
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.760259985
Short name T3
Test name
Test status
Simulation time 244984026 ps
CPU time 1.04 seconds
Started Aug 17 06:37:29 PM PDT 24
Finished Aug 17 06:37:31 PM PDT 24
Peak memory 217744 kb
Host smart-8f29840b-1c87-4b2a-8f23-40b59868111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760259985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.760259985
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1383246562
Short name T489
Test name
Test status
Simulation time 182373821 ps
CPU time 0.84 seconds
Started Aug 17 06:37:26 PM PDT 24
Finished Aug 17 06:37:26 PM PDT 24
Peak memory 200448 kb
Host smart-d936e3a2-8ae8-40dc-a66c-24c9bd82388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383246562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1383246562
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2750553263
Short name T507
Test name
Test status
Simulation time 1357589763 ps
CPU time 4.99 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 200816 kb
Host smart-35f48539-c02b-498c-abc9-a452833bb7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750553263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2750553263
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3666108574
Short name T212
Test name
Test status
Simulation time 142573231 ps
CPU time 1.03 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:10 PM PDT 24
Peak memory 200644 kb
Host smart-64f2fa0b-6b8c-45a3-9e39-e1056d5026a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666108574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3666108574
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3714773117
Short name T394
Test name
Test status
Simulation time 239696720 ps
CPU time 1.5 seconds
Started Aug 17 06:37:29 PM PDT 24
Finished Aug 17 06:37:31 PM PDT 24
Peak memory 200760 kb
Host smart-aa34b982-eb51-406f-9fb0-96396f573beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714773117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3714773117
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.887349126
Short name T297
Test name
Test status
Simulation time 249107379 ps
CPU time 1.62 seconds
Started Aug 17 06:37:38 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 200472 kb
Host smart-5db9d87a-2cf7-454f-a61d-4934e419671a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887349126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.887349126
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.1647057334
Short name T438
Test name
Test status
Simulation time 142374295 ps
CPU time 1.83 seconds
Started Aug 17 06:37:15 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 200492 kb
Host smart-bb58b288-64cb-409c-8221-2707fc960e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647057334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1647057334
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2737488512
Short name T299
Test name
Test status
Simulation time 137731478 ps
CPU time 1.19 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:11 PM PDT 24
Peak memory 200648 kb
Host smart-22d011ae-0bbd-4bf7-b6c4-3193ab6bc33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737488512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2737488512
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3362788810
Short name T159
Test name
Test status
Simulation time 107737134 ps
CPU time 0.86 seconds
Started Aug 17 06:37:32 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 200500 kb
Host smart-0398caf2-29c6-4aa5-a519-d7e446110996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362788810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3362788810
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3676860880
Short name T161
Test name
Test status
Simulation time 244403083 ps
CPU time 1.07 seconds
Started Aug 17 06:37:28 PM PDT 24
Finished Aug 17 06:37:29 PM PDT 24
Peak memory 217756 kb
Host smart-f9e15c7e-d005-43f6-a571-aef0c5450106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676860880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3676860880
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.2793875666
Short name T374
Test name
Test status
Simulation time 107998025 ps
CPU time 0.8 seconds
Started Aug 17 06:37:34 PM PDT 24
Finished Aug 17 06:37:35 PM PDT 24
Peak memory 200380 kb
Host smart-09a94dd1-1695-48f5-bc28-8bad010aaa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793875666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2793875666
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3559461770
Short name T412
Test name
Test status
Simulation time 1220840605 ps
CPU time 5.76 seconds
Started Aug 17 06:37:33 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200824 kb
Host smart-87ca7bd8-33fe-4506-9da3-6ff368e72e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559461770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3559461770
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.2202151014
Short name T68
Test name
Test status
Simulation time 257039163 ps
CPU time 1.63 seconds
Started Aug 17 06:37:32 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 200752 kb
Host smart-53c56796-d641-4351-a086-038510894631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202151014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2202151014
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2031733666
Short name T216
Test name
Test status
Simulation time 8405928163 ps
CPU time 32.42 seconds
Started Aug 17 06:37:38 PM PDT 24
Finished Aug 17 06:38:10 PM PDT 24
Peak memory 210332 kb
Host smart-35fd1677-e9ed-4aa6-8517-427096a2a4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031733666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2031733666
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.987401842
Short name T352
Test name
Test status
Simulation time 111456139 ps
CPU time 1.52 seconds
Started Aug 17 06:37:37 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200524 kb
Host smart-228db132-7411-4945-b9f4-ed2d24f13587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987401842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.987401842
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2701432344
Short name T292
Test name
Test status
Simulation time 138078997 ps
CPU time 1.21 seconds
Started Aug 17 06:37:29 PM PDT 24
Finished Aug 17 06:37:30 PM PDT 24
Peak memory 200640 kb
Host smart-ff374c8e-25c9-484c-aa96-8bf0aeb6deb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701432344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2701432344
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3886909586
Short name T428
Test name
Test status
Simulation time 71897188 ps
CPU time 0.8 seconds
Started Aug 17 06:37:33 PM PDT 24
Finished Aug 17 06:37:34 PM PDT 24
Peak memory 200496 kb
Host smart-528f11c1-ac88-4645-a741-fb924e22ca6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886909586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3886909586
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.726677161
Short name T503
Test name
Test status
Simulation time 1875512007 ps
CPU time 7.02 seconds
Started Aug 17 06:37:30 PM PDT 24
Finished Aug 17 06:37:37 PM PDT 24
Peak memory 230088 kb
Host smart-f7011907-c673-47f2-ae86-b723be258bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726677161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.726677161
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1046896309
Short name T279
Test name
Test status
Simulation time 245033814 ps
CPU time 1.03 seconds
Started Aug 17 06:37:36 PM PDT 24
Finished Aug 17 06:37:37 PM PDT 24
Peak memory 217760 kb
Host smart-1e65e922-ac5a-4406-8a88-171800e35a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046896309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1046896309
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.47041870
Short name T18
Test name
Test status
Simulation time 115522936 ps
CPU time 0.79 seconds
Started Aug 17 06:37:38 PM PDT 24
Finished Aug 17 06:37:39 PM PDT 24
Peak memory 200412 kb
Host smart-57e144b6-807c-4baa-930b-a4687a6fa509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47041870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.47041870
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.3956934911
Short name T386
Test name
Test status
Simulation time 704667598 ps
CPU time 3.92 seconds
Started Aug 17 06:37:28 PM PDT 24
Finished Aug 17 06:37:32 PM PDT 24
Peak memory 200808 kb
Host smart-4e3ac84c-18a7-4e7a-89bf-cc1a25470eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956934911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3956934911
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2190775175
Short name T280
Test name
Test status
Simulation time 111025839 ps
CPU time 1.05 seconds
Started Aug 17 06:37:27 PM PDT 24
Finished Aug 17 06:37:28 PM PDT 24
Peak memory 200636 kb
Host smart-175311ab-01fc-41cc-99db-8589409841e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190775175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2190775175
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2599790394
Short name T439
Test name
Test status
Simulation time 121063629 ps
CPU time 1.18 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200720 kb
Host smart-c3440b67-e262-450e-ac48-722a8a527d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599790394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2599790394
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2069882239
Short name T178
Test name
Test status
Simulation time 187441951 ps
CPU time 1.17 seconds
Started Aug 17 06:37:27 PM PDT 24
Finished Aug 17 06:37:29 PM PDT 24
Peak memory 200692 kb
Host smart-419c4a20-d3e3-4580-ab59-141de5557893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069882239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2069882239
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.142637072
Short name T58
Test name
Test status
Simulation time 377443554 ps
CPU time 2.02 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:37 PM PDT 24
Peak memory 200500 kb
Host smart-c39df128-4b8a-4bfe-890b-9f4d41ad6434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142637072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.142637072
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.669769005
Short name T228
Test name
Test status
Simulation time 227202597 ps
CPU time 1.33 seconds
Started Aug 17 06:37:27 PM PDT 24
Finished Aug 17 06:37:28 PM PDT 24
Peak memory 200648 kb
Host smart-2cd078a4-f46b-4dd4-8d06-b057b1f75149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669769005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.669769005
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.599667286
Short name T154
Test name
Test status
Simulation time 60248270 ps
CPU time 0.7 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:36 PM PDT 24
Peak memory 200460 kb
Host smart-8eafb15d-2bc1-445a-81b9-ff5259357a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599667286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.599667286
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2532097617
Short name T201
Test name
Test status
Simulation time 1226297073 ps
CPU time 6.19 seconds
Started Aug 17 06:37:39 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 221916 kb
Host smart-9b4f747d-b3f4-4d2a-94ca-afbefacdc65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532097617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2532097617
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.869627455
Short name T146
Test name
Test status
Simulation time 243915032 ps
CPU time 1.07 seconds
Started Aug 17 06:37:36 PM PDT 24
Finished Aug 17 06:37:37 PM PDT 24
Peak memory 217716 kb
Host smart-69577241-4f79-41a8-bab8-5af8493275df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869627455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.869627455
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.892389013
Short name T13
Test name
Test status
Simulation time 113955136 ps
CPU time 0.78 seconds
Started Aug 17 06:37:17 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 200480 kb
Host smart-0167214e-8d3d-4fe1-bd7d-ecf596ceea63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892389013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.892389013
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.1364041232
Short name T128
Test name
Test status
Simulation time 2092882248 ps
CPU time 8.56 seconds
Started Aug 17 06:37:31 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 200820 kb
Host smart-ccf0c361-2d1d-4521-bf5b-1b686d562f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364041232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1364041232
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2923285333
Short name T450
Test name
Test status
Simulation time 174357959 ps
CPU time 1.24 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 200636 kb
Host smart-48426394-e09e-4022-bafa-963dd1ea0767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923285333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2923285333
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3690405075
Short name T449
Test name
Test status
Simulation time 119022150 ps
CPU time 1.19 seconds
Started Aug 17 06:37:27 PM PDT 24
Finished Aug 17 06:37:28 PM PDT 24
Peak memory 200692 kb
Host smart-b4592f31-e809-4973-a7af-6fbbcb90ec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690405075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3690405075
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.2372521653
Short name T456
Test name
Test status
Simulation time 11268201450 ps
CPU time 37.97 seconds
Started Aug 17 06:37:36 PM PDT 24
Finished Aug 17 06:38:14 PM PDT 24
Peak memory 209108 kb
Host smart-0684bd61-ceeb-471d-9a70-d6cff09412bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372521653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.2372521653
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3054783474
Short name T361
Test name
Test status
Simulation time 123607292 ps
CPU time 1.01 seconds
Started Aug 17 06:37:37 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200644 kb
Host smart-61fae889-7cb1-4ca0-9f69-c509c3b8f720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054783474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3054783474
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4104017154
Short name T349
Test name
Test status
Simulation time 68373410 ps
CPU time 0.77 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:35 PM PDT 24
Peak memory 200512 kb
Host smart-939e5799-ef78-43c7-a0e0-cdc2bac4e585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104017154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4104017154
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.530729906
Short name T306
Test name
Test status
Simulation time 1219914471 ps
CPU time 5.5 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 217700 kb
Host smart-c51f2987-10b5-4647-8983-d896d8e6620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530729906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.530729906
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.431101528
Short name T189
Test name
Test status
Simulation time 244409731 ps
CPU time 1.12 seconds
Started Aug 17 06:37:40 PM PDT 24
Finished Aug 17 06:37:41 PM PDT 24
Peak memory 217864 kb
Host smart-bcc3a5f5-1605-495c-bcf5-89a67e36fde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431101528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.431101528
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.2883248494
Short name T21
Test name
Test status
Simulation time 208607731 ps
CPU time 0.94 seconds
Started Aug 17 06:37:37 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200448 kb
Host smart-91ee18d6-73b7-4e9b-9d62-a613bf3ff2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883248494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2883248494
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.2139347677
Short name T531
Test name
Test status
Simulation time 1247745917 ps
CPU time 5.69 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 200820 kb
Host smart-3bc2af32-dbc2-4ce6-919c-fc7d1ac4f12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139347677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2139347677
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1332840082
Short name T537
Test name
Test status
Simulation time 160746349 ps
CPU time 1.29 seconds
Started Aug 17 06:37:39 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 200648 kb
Host smart-c8eaa54b-7f4d-4fc3-bce4-c0cb03f61e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332840082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1332840082
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.3987112001
Short name T475
Test name
Test status
Simulation time 195984060 ps
CPU time 1.41 seconds
Started Aug 17 06:37:32 PM PDT 24
Finished Aug 17 06:37:34 PM PDT 24
Peak memory 200808 kb
Host smart-93916e3a-0c35-4196-b463-5b54a8da7615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987112001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3987112001
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.3706359876
Short name T486
Test name
Test status
Simulation time 328072889 ps
CPU time 1.66 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:43 PM PDT 24
Peak memory 200740 kb
Host smart-b1bd772c-b8e6-423d-91a2-128248920b28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706359876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3706359876
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3244060939
Short name T303
Test name
Test status
Simulation time 122316491 ps
CPU time 1.71 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 208724 kb
Host smart-812ded8a-a05c-4c44-b7cb-83732699d9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244060939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3244060939
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.198114260
Short name T514
Test name
Test status
Simulation time 1902258580 ps
CPU time 8.04 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:43 PM PDT 24
Peak memory 217960 kb
Host smart-4831b179-b0ad-4f98-b94d-33da0566e477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198114260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.198114260
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3468367335
Short name T160
Test name
Test status
Simulation time 244705372 ps
CPU time 1.1 seconds
Started Aug 17 06:37:38 PM PDT 24
Finished Aug 17 06:37:39 PM PDT 24
Peak memory 217844 kb
Host smart-f7605c7a-f298-42f2-a11b-ba2c227f7f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468367335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3468367335
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.1310058148
Short name T312
Test name
Test status
Simulation time 210656543 ps
CPU time 0.96 seconds
Started Aug 17 06:37:37 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200440 kb
Host smart-813178bf-6a0c-4f51-855e-cb89264e5017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310058148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1310058148
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2480919525
Short name T177
Test name
Test status
Simulation time 1497574950 ps
CPU time 6.55 seconds
Started Aug 17 06:37:36 PM PDT 24
Finished Aug 17 06:37:43 PM PDT 24
Peak memory 200804 kb
Host smart-23ac93d2-652b-421e-8d0a-36ee7d8df84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480919525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2480919525
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3185829776
Short name T182
Test name
Test status
Simulation time 103776882 ps
CPU time 0.98 seconds
Started Aug 17 06:37:39 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 200588 kb
Host smart-33135fba-9c1c-4afe-9fe9-90333b1818a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185829776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3185829776
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3024399959
Short name T260
Test name
Test status
Simulation time 247535208 ps
CPU time 1.68 seconds
Started Aug 17 06:37:37 PM PDT 24
Finished Aug 17 06:37:39 PM PDT 24
Peak memory 200788 kb
Host smart-4e68ced4-ec3f-410e-bdb0-21a87b26d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024399959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3024399959
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.901475876
Short name T274
Test name
Test status
Simulation time 1365372562 ps
CPU time 6.61 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200744 kb
Host smart-751ec628-6f2c-49e1-a083-98a4a9e6b94f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901475876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.901475876
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.734181599
Short name T203
Test name
Test status
Simulation time 151777566 ps
CPU time 2.04 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200560 kb
Host smart-c7145d5f-9104-4357-9162-a8c83869ed11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734181599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.734181599
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.4189395345
Short name T342
Test name
Test status
Simulation time 217361610 ps
CPU time 1.4 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200644 kb
Host smart-fb8cca75-1350-4a31-89f9-1e4a21edae30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189395345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4189395345
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2879256059
Short name T387
Test name
Test status
Simulation time 66824408 ps
CPU time 0.74 seconds
Started Aug 17 06:37:36 PM PDT 24
Finished Aug 17 06:37:37 PM PDT 24
Peak memory 200508 kb
Host smart-57321da8-2722-4e29-9090-c7fa5f94cddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879256059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2879256059
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.2022946434
Short name T474
Test name
Test status
Simulation time 2181796167 ps
CPU time 7.62 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 221876 kb
Host smart-373b33b1-6f69-49cc-8ce9-4825953beb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022946434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2022946434
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.4286620642
Short name T215
Test name
Test status
Simulation time 245375544 ps
CPU time 1.02 seconds
Started Aug 17 06:37:40 PM PDT 24
Finished Aug 17 06:37:41 PM PDT 24
Peak memory 217828 kb
Host smart-0f694530-334e-4632-8304-68ad40418b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286620642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.4286620642
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3902368434
Short name T368
Test name
Test status
Simulation time 162191566 ps
CPU time 0.84 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200452 kb
Host smart-281d31c1-caac-4797-ae17-2f7fbd03a857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902368434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3902368434
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.390162338
Short name T158
Test name
Test status
Simulation time 713450992 ps
CPU time 3.88 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200816 kb
Host smart-f84d5ab5-1bf0-4c76-aff2-d7e7c0d8f3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390162338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.390162338
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2360214875
Short name T206
Test name
Test status
Simulation time 103374798 ps
CPU time 0.96 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 200604 kb
Host smart-f48ce7d8-c7ac-476a-9d33-354c4c4a4801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360214875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2360214875
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.1825431614
Short name T180
Test name
Test status
Simulation time 107701324 ps
CPU time 1.12 seconds
Started Aug 17 06:37:33 PM PDT 24
Finished Aug 17 06:37:35 PM PDT 24
Peak memory 200756 kb
Host smart-28a7a0a9-1c8d-4187-b805-4d9c16d2ba1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825431614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1825431614
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.2159765023
Short name T233
Test name
Test status
Simulation time 4193935532 ps
CPU time 19.74 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 209056 kb
Host smart-0d49e8cf-9990-473b-8e76-820407567d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159765023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2159765023
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.3534116600
Short name T143
Test name
Test status
Simulation time 511818193 ps
CPU time 2.68 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200548 kb
Host smart-1ea4f75e-e121-41ad-a0e5-aed12ab97536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534116600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3534116600
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.900778708
Short name T535
Test name
Test status
Simulation time 66328817 ps
CPU time 0.75 seconds
Started Aug 17 06:37:40 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 200640 kb
Host smart-f8ca9072-9f38-48e6-8745-2c449221c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900778708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.900778708
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1714081207
Short name T399
Test name
Test status
Simulation time 73952411 ps
CPU time 0.83 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 200524 kb
Host smart-3310011c-ae03-49cc-aa70-684dc6bb9d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714081207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1714081207
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2621468180
Short name T53
Test name
Test status
Simulation time 1222115658 ps
CPU time 5.36 seconds
Started Aug 17 06:37:39 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 217232 kb
Host smart-cedd6b65-50b5-461f-bad0-769618590e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621468180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2621468180
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2278368859
Short name T261
Test name
Test status
Simulation time 244360385 ps
CPU time 1.12 seconds
Started Aug 17 06:37:38 PM PDT 24
Finished Aug 17 06:37:39 PM PDT 24
Peak memory 217848 kb
Host smart-613fe743-5e0e-427e-9547-486e16bc71a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278368859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2278368859
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1701614398
Short name T452
Test name
Test status
Simulation time 117250010 ps
CPU time 0.8 seconds
Started Aug 17 06:37:37 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200500 kb
Host smart-a4e2b074-40a5-4f25-85c2-d45f0eeaa5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701614398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1701614398
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3892888959
Short name T193
Test name
Test status
Simulation time 722876790 ps
CPU time 4.14 seconds
Started Aug 17 06:37:36 PM PDT 24
Finished Aug 17 06:37:40 PM PDT 24
Peak memory 200744 kb
Host smart-09f7ab81-ab83-4c79-bca0-1c8a518cf57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892888959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3892888959
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.4229770338
Short name T62
Test name
Test status
Simulation time 152818762 ps
CPU time 1.18 seconds
Started Aug 17 06:37:32 PM PDT 24
Finished Aug 17 06:37:33 PM PDT 24
Peak memory 200640 kb
Host smart-0eb1e8c7-16b7-4776-b872-f98a029d08b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229770338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.4229770338
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.122895847
Short name T314
Test name
Test status
Simulation time 205155033 ps
CPU time 1.46 seconds
Started Aug 17 06:37:36 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200804 kb
Host smart-7fa832fe-ac3c-4104-85ad-2a07d65ea2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122895847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.122895847
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3450860085
Short name T118
Test name
Test status
Simulation time 6594336924 ps
CPU time 28.68 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:38:13 PM PDT 24
Peak memory 209076 kb
Host smart-063a0f4f-e327-4eba-b45a-4b4ecac24cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450860085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3450860085
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.1716519630
Short name T447
Test name
Test status
Simulation time 364708705 ps
CPU time 2.42 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200532 kb
Host smart-e3a27d95-55b4-4277-abb6-5718dc855a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716519630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1716519630
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2033000363
Short name T534
Test name
Test status
Simulation time 233073345 ps
CPU time 1.39 seconds
Started Aug 17 06:37:28 PM PDT 24
Finished Aug 17 06:37:30 PM PDT 24
Peak memory 200732 kb
Host smart-b94b17ed-11f2-40c7-96bc-a8afe480798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033000363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2033000363
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1575690223
Short name T372
Test name
Test status
Simulation time 76021959 ps
CPU time 0.75 seconds
Started Aug 17 06:37:00 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 200468 kb
Host smart-8a5167cc-cbeb-4985-98db-66e5d3312c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575690223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1575690223
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.4114913518
Short name T281
Test name
Test status
Simulation time 1896170845 ps
CPU time 7.59 seconds
Started Aug 17 06:37:27 PM PDT 24
Finished Aug 17 06:37:35 PM PDT 24
Peak memory 221984 kb
Host smart-0d566365-263e-4db9-9636-0304bde1d931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114913518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.4114913518
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3987539796
Short name T437
Test name
Test status
Simulation time 243775811 ps
CPU time 1.12 seconds
Started Aug 17 06:37:01 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 217868 kb
Host smart-172f6b60-bd0a-4181-b3ff-565061643bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987539796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3987539796
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1489131340
Short name T393
Test name
Test status
Simulation time 107192804 ps
CPU time 0.79 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:11 PM PDT 24
Peak memory 200472 kb
Host smart-ffe41688-7409-4950-bac2-1a16b743e94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489131340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1489131340
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3978816757
Short name T432
Test name
Test status
Simulation time 1566537343 ps
CPU time 5.85 seconds
Started Aug 17 06:37:08 PM PDT 24
Finished Aug 17 06:37:14 PM PDT 24
Peak memory 200800 kb
Host smart-65a6dfa4-fbc2-42e9-af1b-3c0ebc99770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978816757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3978816757
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.4010333692
Short name T80
Test name
Test status
Simulation time 16824113839 ps
CPU time 25.08 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:23 PM PDT 24
Peak memory 217536 kb
Host smart-dfb8026c-2ce3-40cc-88ea-ee763c393936
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010333692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.4010333692
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1218171374
Short name T235
Test name
Test status
Simulation time 180657297 ps
CPU time 1.23 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 200644 kb
Host smart-913824ec-2e57-4f72-bfbd-7eeb1c931e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218171374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1218171374
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2268338635
Short name T426
Test name
Test status
Simulation time 125735812 ps
CPU time 1.15 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 200708 kb
Host smart-b9abc31f-2687-4523-8cd4-affba155224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268338635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2268338635
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.4263369818
Short name T271
Test name
Test status
Simulation time 388501387 ps
CPU time 2.81 seconds
Started Aug 17 06:37:13 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 208848 kb
Host smart-ed96aa49-6872-4dbd-95ba-29053852e350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263369818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.4263369818
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2059540200
Short name T467
Test name
Test status
Simulation time 369572909 ps
CPU time 2.28 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 200508 kb
Host smart-fd4c2715-28bc-42dc-8643-9dde6873851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059540200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2059540200
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.2755755209
Short name T364
Test name
Test status
Simulation time 94363782 ps
CPU time 0.85 seconds
Started Aug 17 06:37:06 PM PDT 24
Finished Aug 17 06:37:07 PM PDT 24
Peak memory 200588 kb
Host smart-d8a103d8-4e7a-4778-af39-8b86a0b36561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755755209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2755755209
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.427528572
Short name T339
Test name
Test status
Simulation time 65527754 ps
CPU time 0.79 seconds
Started Aug 17 06:37:49 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 200500 kb
Host smart-362dbf4b-30d8-4d4e-a373-6a932e2c4c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427528572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.427528572
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3597883484
Short name T473
Test name
Test status
Simulation time 1225493127 ps
CPU time 6.03 seconds
Started Aug 17 06:37:42 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 221920 kb
Host smart-b09ac789-cc29-428f-a155-509253861982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597883484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3597883484
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.158209834
Short name T435
Test name
Test status
Simulation time 244249525 ps
CPU time 1.17 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 217824 kb
Host smart-7f136cd9-620e-4413-98c7-91cc294cf98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158209834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.158209834
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2631545293
Short name T293
Test name
Test status
Simulation time 155444247 ps
CPU time 0.84 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 200444 kb
Host smart-3d934a30-2181-46cb-a8fe-37f3b1be878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631545293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2631545293
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.239155751
Short name T341
Test name
Test status
Simulation time 1453956445 ps
CPU time 5.9 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 200864 kb
Host smart-0ed6f0a2-66e4-4f1f-9930-a24bf9f55650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239155751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.239155751
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2057224542
Short name T186
Test name
Test status
Simulation time 98406085 ps
CPU time 0.97 seconds
Started Aug 17 06:37:38 PM PDT 24
Finished Aug 17 06:37:39 PM PDT 24
Peak memory 200548 kb
Host smart-71483393-bfc6-4937-bcc9-896775cee6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057224542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2057224542
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.897692461
Short name T444
Test name
Test status
Simulation time 225824352 ps
CPU time 1.51 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 200744 kb
Host smart-e058bed2-42f3-4a00-a9a3-9478efecefaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897692461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.897692461
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.259247973
Short name T223
Test name
Test status
Simulation time 386376394 ps
CPU time 2.39 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200544 kb
Host smart-554a1dd0-471e-4a0c-8b49-a139aac0e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259247973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.259247973
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.3213998053
Short name T179
Test name
Test status
Simulation time 280573277 ps
CPU time 1.56 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 200908 kb
Host smart-90fa37e2-9a85-47e2-9cee-092c61ebd008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213998053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3213998053
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.2448267363
Short name T375
Test name
Test status
Simulation time 83871562 ps
CPU time 0.87 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200516 kb
Host smart-09b49ba9-e12f-4a24-8818-2fd1052e588b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448267363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.2448267363
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.287363305
Short name T65
Test name
Test status
Simulation time 1218449772 ps
CPU time 5.5 seconds
Started Aug 17 06:37:42 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 221928 kb
Host smart-e04dda39-e02c-4738-afc5-11c513036920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287363305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.287363305
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.164390249
Short name T524
Test name
Test status
Simulation time 244458684 ps
CPU time 1.16 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 217728 kb
Host smart-cc7cfc83-6cc9-4bc3-98ce-3906dabeb4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164390249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.164390249
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3420806655
Short name T465
Test name
Test status
Simulation time 90244565 ps
CPU time 0.79 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 200444 kb
Host smart-1dba6b2c-5965-43b0-bbc3-887fb8a2d58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420806655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3420806655
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2548853935
Short name T248
Test name
Test status
Simulation time 961919107 ps
CPU time 5.13 seconds
Started Aug 17 06:37:42 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200756 kb
Host smart-f5c9fcb0-2182-42fe-adbf-68d6370ac578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548853935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2548853935
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.570278175
Short name T195
Test name
Test status
Simulation time 108983251 ps
CPU time 1.04 seconds
Started Aug 17 06:37:37 PM PDT 24
Finished Aug 17 06:37:39 PM PDT 24
Peak memory 200636 kb
Host smart-96281e99-0d3c-4b81-9007-da4ee0d6546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570278175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.570278175
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.150179056
Short name T340
Test name
Test status
Simulation time 209830755 ps
CPU time 1.37 seconds
Started Aug 17 06:37:52 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200740 kb
Host smart-e6d101bd-ece4-4350-86f2-c7636fa53cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150179056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.150179056
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3255203497
Short name T422
Test name
Test status
Simulation time 5504709377 ps
CPU time 19.4 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:38:08 PM PDT 24
Peak memory 208964 kb
Host smart-96af372b-846a-4981-87fe-13936f4dd60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255203497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3255203497
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1746313938
Short name T291
Test name
Test status
Simulation time 444697212 ps
CPU time 2.31 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200532 kb
Host smart-9d13e2ac-74ac-4565-b399-494ad0267483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746313938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1746313938
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2022742333
Short name T43
Test name
Test status
Simulation time 135235855 ps
CPU time 1.15 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200604 kb
Host smart-2a8fb3ed-908a-4f40-bce6-6365a97f6800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022742333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2022742333
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.175380344
Short name T308
Test name
Test status
Simulation time 93147917 ps
CPU time 0.81 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200524 kb
Host smart-170ab94d-211c-4530-a1be-ee5f9c70bc14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175380344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.175380344
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.727498506
Short name T63
Test name
Test status
Simulation time 1224880211 ps
CPU time 5.35 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 221912 kb
Host smart-097d8373-c674-4fac-80d1-31b9ca65909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727498506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.727498506
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3897018873
Short name T483
Test name
Test status
Simulation time 244367176 ps
CPU time 1.02 seconds
Started Aug 17 06:37:40 PM PDT 24
Finished Aug 17 06:37:41 PM PDT 24
Peak memory 217904 kb
Host smart-3085e0ac-3830-492e-babe-7c1132994f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897018873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3897018873
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.2391126537
Short name T395
Test name
Test status
Simulation time 161285450 ps
CPU time 0.88 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200444 kb
Host smart-bb3acf40-7c8e-4e7e-92c3-bef452b00fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391126537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2391126537
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3711763940
Short name T290
Test name
Test status
Simulation time 1260168245 ps
CPU time 5.57 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 200816 kb
Host smart-6c36e27f-0d67-4a0f-b301-ada68720e481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711763940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3711763940
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3275942123
Short name T354
Test name
Test status
Simulation time 156898217 ps
CPU time 1.18 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200676 kb
Host smart-373b67a4-d656-41df-b552-1bbc0eea22e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275942123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3275942123
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.3271161150
Short name T253
Test name
Test status
Simulation time 241036197 ps
CPU time 1.49 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200756 kb
Host smart-484d3819-05d8-4495-bb26-cebb50e81f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271161150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3271161150
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1664112413
Short name T380
Test name
Test status
Simulation time 6237120014 ps
CPU time 27.79 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 200856 kb
Host smart-9c4da015-f064-4748-b30e-5e062dcc6f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664112413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1664112413
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.334379016
Short name T199
Test name
Test status
Simulation time 298788598 ps
CPU time 1.97 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 208704 kb
Host smart-af675a23-34cd-4415-a051-c447c6ef8ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334379016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.334379016
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.1827889734
Short name T145
Test name
Test status
Simulation time 231776169 ps
CPU time 1.23 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 200636 kb
Host smart-00e4a94e-3329-4fd8-90f0-a21da3477abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827889734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1827889734
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1793353332
Short name T25
Test name
Test status
Simulation time 73407663 ps
CPU time 0.81 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 200480 kb
Host smart-4835527a-67d8-419b-94db-13cae38a3471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793353332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1793353332
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3058780841
Short name T30
Test name
Test status
Simulation time 1219868139 ps
CPU time 5.73 seconds
Started Aug 17 06:37:39 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 217952 kb
Host smart-40692de6-998d-4bfc-ae9a-d812d88d6014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058780841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3058780841
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2219855206
Short name T529
Test name
Test status
Simulation time 245401102 ps
CPU time 1.04 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 217864 kb
Host smart-c5de969f-bfbf-4c78-88c1-6cfc1b4c4ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219855206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2219855206
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.3260556204
Short name T16
Test name
Test status
Simulation time 92164384 ps
CPU time 0.73 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200488 kb
Host smart-4dca3238-e50c-4fd9-acaa-44900e376a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260556204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3260556204
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1918035214
Short name T131
Test name
Test status
Simulation time 1779135061 ps
CPU time 6.59 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 200744 kb
Host smart-753b49bf-c682-4bea-b325-047a7bf848d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918035214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1918035214
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.483774430
Short name T421
Test name
Test status
Simulation time 183659835 ps
CPU time 1.25 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200640 kb
Host smart-08bc086c-7e18-4576-9089-41345a675c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483774430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.483774430
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.3929475945
Short name T200
Test name
Test status
Simulation time 128148152 ps
CPU time 1.25 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200692 kb
Host smart-287b165c-101c-4e46-ba59-cdffb2211d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929475945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3929475945
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.2110934050
Short name T523
Test name
Test status
Simulation time 3838432079 ps
CPU time 15.93 seconds
Started Aug 17 06:37:39 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 200820 kb
Host smart-216c476e-5fdb-45d1-914f-ba57affb92c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110934050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2110934050
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3588831924
Short name T45
Test name
Test status
Simulation time 333697859 ps
CPU time 2.35 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 200540 kb
Host smart-80fc57f8-5cd3-4251-b3fc-c0b75f57930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588831924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3588831924
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.2878646943
Short name T272
Test name
Test status
Simulation time 135246775 ps
CPU time 1.02 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200604 kb
Host smart-805452c3-0b16-4ce9-a724-1e781d2e4908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878646943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.2878646943
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.3118250970
Short name T300
Test name
Test status
Simulation time 74081517 ps
CPU time 0.81 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200532 kb
Host smart-6c51614a-30c3-4356-90cf-aaef9a0d881b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118250970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.3118250970
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.3671229598
Short name T32
Test name
Test status
Simulation time 1897968052 ps
CPU time 6.79 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 217980 kb
Host smart-bbdeb1fb-0d5c-4115-924a-ebdeb16eb8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671229598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3671229598
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.3890652481
Short name T365
Test name
Test status
Simulation time 244033289 ps
CPU time 1.12 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 217784 kb
Host smart-2446e400-d944-4760-969e-9c440fe71802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890652481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.3890652481
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.1660675546
Short name T275
Test name
Test status
Simulation time 153498299 ps
CPU time 0.82 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 200388 kb
Host smart-82a24a60-f5c3-4225-8932-ca9e49ecd7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660675546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1660675546
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2758832754
Short name T152
Test name
Test status
Simulation time 823571370 ps
CPU time 4.27 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200844 kb
Host smart-7cfed029-0d4f-4bcb-9f8b-409fdb804211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758832754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2758832754
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3092103498
Short name T360
Test name
Test status
Simulation time 95779144 ps
CPU time 1.03 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200600 kb
Host smart-e7394c94-f147-4b78-98c4-f26b61160534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092103498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3092103498
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.2358258391
Short name T326
Test name
Test status
Simulation time 120036099 ps
CPU time 1.22 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200636 kb
Host smart-9848605e-daf0-479f-801c-1385a0b8954c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358258391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2358258391
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.755618639
Short name T168
Test name
Test status
Simulation time 5366416397 ps
CPU time 18.29 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 200852 kb
Host smart-5a6ce8e4-6273-469d-98a2-7634307dd3d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755618639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.755618639
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3489752759
Short name T498
Test name
Test status
Simulation time 147272687 ps
CPU time 1.83 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:43 PM PDT 24
Peak memory 200536 kb
Host smart-f9dae301-5ea4-410d-b503-aebface5cf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489752759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3489752759
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3907445
Short name T6
Test name
Test status
Simulation time 153528710 ps
CPU time 1.16 seconds
Started Aug 17 06:37:35 PM PDT 24
Finished Aug 17 06:37:36 PM PDT 24
Peak memory 200596 kb
Host smart-a3be458e-0947-4bea-b52c-599ca9942ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3907445
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1456210568
Short name T278
Test name
Test status
Simulation time 65999227 ps
CPU time 0.77 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 200508 kb
Host smart-a6d00e1c-5079-4177-b908-761b0dda4a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456210568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1456210568
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.93982310
Short name T35
Test name
Test status
Simulation time 1227201467 ps
CPU time 5.38 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 217900 kb
Host smart-6fa039d2-96d3-4e8c-a5ed-0c72e10b77f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93982310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.93982310
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4176259684
Short name T105
Test name
Test status
Simulation time 244066869 ps
CPU time 1.19 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 217696 kb
Host smart-98b50045-7802-483e-a252-9afccc537206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176259684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4176259684
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.1813052701
Short name T284
Test name
Test status
Simulation time 159456668 ps
CPU time 0.88 seconds
Started Aug 17 06:37:49 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 200420 kb
Host smart-99f59014-8eea-4f71-a3fa-94ae1177787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813052701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1813052701
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1231792181
Short name T27
Test name
Test status
Simulation time 1836259555 ps
CPU time 7.77 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200800 kb
Host smart-87a11452-b3b3-4466-b2c8-ab6823df5017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231792181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1231792181
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1561202998
Short name T351
Test name
Test status
Simulation time 102196200 ps
CPU time 0.98 seconds
Started Aug 17 06:37:37 PM PDT 24
Finished Aug 17 06:37:38 PM PDT 24
Peak memory 200636 kb
Host smart-cfaad415-4939-44aa-a49f-866427bd05d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561202998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1561202998
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.1901791483
Short name T413
Test name
Test status
Simulation time 196947838 ps
CPU time 1.44 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200780 kb
Host smart-b68a66f9-b0e0-41ba-b3b3-ed07d12871dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901791483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1901791483
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3001251774
Short name T441
Test name
Test status
Simulation time 18250419470 ps
CPU time 64.24 seconds
Started Aug 17 06:37:49 PM PDT 24
Finished Aug 17 06:38:53 PM PDT 24
Peak memory 209028 kb
Host smart-0eeb5b21-ac53-463d-8106-c754c1b276aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001251774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3001251774
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.1240118795
Short name T254
Test name
Test status
Simulation time 519942014 ps
CPU time 2.72 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 200540 kb
Host smart-08af24c8-9df0-4866-97ef-01920ba79052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240118795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.1240118795
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3731216281
Short name T461
Test name
Test status
Simulation time 283526614 ps
CPU time 1.58 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200688 kb
Host smart-374429da-702a-410f-b6ce-be3c5ae3b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731216281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3731216281
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.4009820831
Short name T7
Test name
Test status
Simulation time 60189424 ps
CPU time 0.89 seconds
Started Aug 17 06:37:49 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 200504 kb
Host smart-625e04c8-9eae-4d7b-b9c9-71eb9f815b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009820831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4009820831
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.928273539
Short name T37
Test name
Test status
Simulation time 2186505340 ps
CPU time 8.55 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 217832 kb
Host smart-c38e7145-777b-4358-aea7-ff988112f2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928273539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.928273539
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.139645135
Short name T155
Test name
Test status
Simulation time 246900464 ps
CPU time 1.07 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 217864 kb
Host smart-7cdd8721-bb07-41b4-8023-040bc03a2d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139645135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.139645135
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3881883583
Short name T381
Test name
Test status
Simulation time 114899570 ps
CPU time 0.78 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200444 kb
Host smart-87ef33c2-04ea-401e-b9e2-ea72b63bb3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881883583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3881883583
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.1046244223
Short name T268
Test name
Test status
Simulation time 1428628086 ps
CPU time 6.65 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200796 kb
Host smart-7020476c-1e29-479d-91d1-63db00c7e89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046244223 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1046244223
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2818889073
Short name T471
Test name
Test status
Simulation time 144035255 ps
CPU time 1.1 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 200616 kb
Host smart-0eedf028-d5c0-48c8-bd72-9a468bcb4c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818889073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2818889073
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3268234970
Short name T294
Test name
Test status
Simulation time 116864481 ps
CPU time 1.29 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200656 kb
Host smart-d896db75-c552-4f68-934f-d540ac66fc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268234970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3268234970
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.2013835491
Short name T490
Test name
Test status
Simulation time 265525548 ps
CPU time 1.81 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200536 kb
Host smart-e76d925d-6b6c-443c-8381-3731beafd78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013835491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2013835491
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.247882823
Short name T106
Test name
Test status
Simulation time 112365710 ps
CPU time 1 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200636 kb
Host smart-bc10e1f9-5ad8-4fc6-bc6f-6fd522314b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247882823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.247882823
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2204492681
Short name T197
Test name
Test status
Simulation time 72372415 ps
CPU time 0.89 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200512 kb
Host smart-abbe85cf-c0e4-43bd-9c68-732420a3f6e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204492681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2204492681
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3463200215
Short name T504
Test name
Test status
Simulation time 1229657910 ps
CPU time 5.47 seconds
Started Aug 17 06:37:42 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 221924 kb
Host smart-726b7385-c264-4c62-84cc-3f2691d8de9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463200215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3463200215
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1855018703
Short name T162
Test name
Test status
Simulation time 249448845 ps
CPU time 1.02 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 217780 kb
Host smart-fac63e70-a6a6-40e7-abef-f47aad7983b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855018703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1855018703
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.4094884299
Short name T510
Test name
Test status
Simulation time 131822292 ps
CPU time 0.84 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 200404 kb
Host smart-94dc18fa-5fa1-4422-9e35-0122fc9b36dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094884299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.4094884299
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.254622318
Short name T5
Test name
Test status
Simulation time 916123134 ps
CPU time 4.88 seconds
Started Aug 17 06:37:55 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200808 kb
Host smart-c9e19bd5-736d-4c7d-9d24-768b43962af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254622318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.254622318
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.164427896
Short name T169
Test name
Test status
Simulation time 172614505 ps
CPU time 1.33 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200604 kb
Host smart-025c0a10-c0d6-4469-9b0b-cb8fbcb0a83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164427896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.164427896
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.2627287230
Short name T462
Test name
Test status
Simulation time 204572689 ps
CPU time 1.38 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200784 kb
Host smart-9024bb33-6a2c-48b8-8e61-b1b1e5e07fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627287230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2627287230
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.592017325
Short name T334
Test name
Test status
Simulation time 1607791546 ps
CPU time 7.4 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 209052 kb
Host smart-26faf57d-2fca-4879-bd35-c5e4fc907e26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592017325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.592017325
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.3475888535
Short name T400
Test name
Test status
Simulation time 157495359 ps
CPU time 1.91 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200492 kb
Host smart-76f6caf2-a8c4-4cb1-ac6e-0fe5d91e20d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475888535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.3475888535
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.2768559554
Short name T296
Test name
Test status
Simulation time 99741817 ps
CPU time 0.95 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 200648 kb
Host smart-5a949ed9-539d-4abd-bef4-826a6ab96afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768559554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2768559554
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.3072896062
Short name T325
Test name
Test status
Simulation time 67873087 ps
CPU time 0.77 seconds
Started Aug 17 06:37:58 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 200536 kb
Host smart-39a07ddd-6b2c-4cbe-86ca-e275590d0c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072896062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3072896062
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.633572129
Short name T52
Test name
Test status
Simulation time 2361753774 ps
CPU time 8.28 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:56 PM PDT 24
Peak memory 222000 kb
Host smart-541843db-b905-4ab8-9c1b-78d82bdd1976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633572129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.633572129
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.1885632644
Short name T496
Test name
Test status
Simulation time 244450676 ps
CPU time 1 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 217784 kb
Host smart-b21784bd-4c71-4f00-b75f-cc8431cd0f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885632644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.1885632644
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.331888795
Short name T320
Test name
Test status
Simulation time 188118856 ps
CPU time 0.87 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 200456 kb
Host smart-656601f8-c3dd-41bd-856a-5698e1978dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331888795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.331888795
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.1038295509
Short name T129
Test name
Test status
Simulation time 1146044159 ps
CPU time 5.27 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200728 kb
Host smart-96c78189-8ef3-4ea7-bb38-6ec5ef5f8a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038295509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1038295509
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3275457794
Short name T184
Test name
Test status
Simulation time 152040652 ps
CPU time 1.13 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 200628 kb
Host smart-06659d74-bd11-4447-9e0e-8549c9abc354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275457794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3275457794
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.2990092874
Short name T84
Test name
Test status
Simulation time 249946982 ps
CPU time 1.58 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200684 kb
Host smart-bd4dfec8-241a-4ffb-a108-6d4948df0ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990092874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2990092874
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.4187634694
Short name T359
Test name
Test status
Simulation time 6695161696 ps
CPU time 21.87 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:38:15 PM PDT 24
Peak memory 200908 kb
Host smart-a0f0f41b-d307-4f2b-8c81-9e3be4ed6d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187634694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.4187634694
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.707570041
Short name T436
Test name
Test status
Simulation time 333412897 ps
CPU time 2 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 200504 kb
Host smart-106d409b-4ef7-49f4-811d-0fd5e413e603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707570041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.707570041
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1745020129
Short name T244
Test name
Test status
Simulation time 193401398 ps
CPU time 1.24 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 200668 kb
Host smart-bf63aca6-ac2d-4b3e-8511-231448c4b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745020129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1745020129
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.764658604
Short name T270
Test name
Test status
Simulation time 60191369 ps
CPU time 0.72 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 200512 kb
Host smart-77343979-293e-4053-86ea-b15965d30829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764658604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.764658604
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2550305087
Short name T39
Test name
Test status
Simulation time 2344216855 ps
CPU time 8.13 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 218120 kb
Host smart-fc43cad6-2050-43ca-93a3-5a23fb434f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550305087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2550305087
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.465845376
Short name T157
Test name
Test status
Simulation time 243414080 ps
CPU time 1.07 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 217800 kb
Host smart-d444a186-9de6-47d4-ba9f-6c0836c2f2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465845376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.465845376
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3905876235
Short name T17
Test name
Test status
Simulation time 207318591 ps
CPU time 0.93 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 200460 kb
Host smart-28f3ec44-12e6-4fe5-8dca-13f01643f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905876235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3905876235
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.658925809
Short name T453
Test name
Test status
Simulation time 741830234 ps
CPU time 4.05 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 200780 kb
Host smart-71360b5d-4e75-4401-ab72-8a088d1ac984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658925809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.658925809
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1541566669
Short name T59
Test name
Test status
Simulation time 139657133 ps
CPU time 1.2 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 200636 kb
Host smart-14e62bea-0164-428f-9046-7fce66033eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541566669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1541566669
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.3831252790
Short name T15
Test name
Test status
Simulation time 110153809 ps
CPU time 1.24 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200636 kb
Host smart-97078cd5-4742-42a7-8eef-7f41d744ed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831252790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3831252790
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1016536257
Short name T116
Test name
Test status
Simulation time 3358756494 ps
CPU time 14.98 seconds
Started Aug 17 06:38:06 PM PDT 24
Finished Aug 17 06:38:21 PM PDT 24
Peak memory 209060 kb
Host smart-2493985b-a97b-4923-8480-b69d50c1021d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016536257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1016536257
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2234670419
Short name T133
Test name
Test status
Simulation time 533781042 ps
CPU time 2.71 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 200504 kb
Host smart-cb172d0d-f5c7-48ec-bcc2-08017a3001c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234670419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2234670419
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.216911581
Short name T83
Test name
Test status
Simulation time 200154380 ps
CPU time 1.3 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:37:56 PM PDT 24
Peak memory 200656 kb
Host smart-7863aa25-9097-47fd-8f34-703d75ad2886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216911581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.216911581
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.2682601416
Short name T477
Test name
Test status
Simulation time 93232276 ps
CPU time 0.81 seconds
Started Aug 17 06:37:26 PM PDT 24
Finished Aug 17 06:37:27 PM PDT 24
Peak memory 200464 kb
Host smart-40ccef83-ed74-435f-980a-7149f60bf4fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682601416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2682601416
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.2812623978
Short name T425
Test name
Test status
Simulation time 2370639675 ps
CPU time 8.52 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 230196 kb
Host smart-4b72c9a3-0fb5-4f59-816e-a1ff6b63c569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812623978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2812623978
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2914030737
Short name T309
Test name
Test status
Simulation time 245024776 ps
CPU time 1.03 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 217860 kb
Host smart-6a24f197-5b47-4472-89fe-aa14d7cda1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914030737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2914030737
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2754604746
Short name T22
Test name
Test status
Simulation time 202700106 ps
CPU time 0.94 seconds
Started Aug 17 06:37:01 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 200444 kb
Host smart-0af73a27-9f45-47a7-a5f3-83b7b0d89378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754604746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2754604746
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4081544676
Short name T234
Test name
Test status
Simulation time 794335308 ps
CPU time 4.11 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:03 PM PDT 24
Peak memory 200796 kb
Host smart-3ce800b3-7ffd-4b36-b0da-4e8665d47fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081544676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4081544676
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2560830760
Short name T77
Test name
Test status
Simulation time 16509917559 ps
CPU time 30.27 seconds
Started Aug 17 06:36:59 PM PDT 24
Finished Aug 17 06:37:29 PM PDT 24
Peak memory 218460 kb
Host smart-4fa7d308-a755-4507-874c-5e63e9a43b3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560830760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2560830760
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2850422667
Short name T214
Test name
Test status
Simulation time 173785698 ps
CPU time 1.21 seconds
Started Aug 17 06:36:56 PM PDT 24
Finished Aug 17 06:36:58 PM PDT 24
Peak memory 200640 kb
Host smart-f72d2a09-52b2-4f69-ae23-759b1a372b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850422667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2850422667
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.4128477380
Short name T175
Test name
Test status
Simulation time 256246819 ps
CPU time 1.65 seconds
Started Aug 17 06:37:07 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 200716 kb
Host smart-ed6ee9cd-616b-4b4a-884c-2a087774d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128477380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.4128477380
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.3017719055
Short name T506
Test name
Test status
Simulation time 4936449613 ps
CPU time 21.88 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:25 PM PDT 24
Peak memory 200836 kb
Host smart-c75bc266-5a6a-422e-bb0a-3e0870e270b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017719055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3017719055
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1995919799
Short name T321
Test name
Test status
Simulation time 137276651 ps
CPU time 1.6 seconds
Started Aug 17 06:37:11 PM PDT 24
Finished Aug 17 06:37:13 PM PDT 24
Peak memory 208744 kb
Host smart-ff935783-a282-420c-9e10-776aeff756fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995919799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1995919799
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3719655078
Short name T335
Test name
Test status
Simulation time 87404205 ps
CPU time 0.87 seconds
Started Aug 17 06:37:01 PM PDT 24
Finished Aug 17 06:37:02 PM PDT 24
Peak memory 200644 kb
Host smart-31b62699-6dc1-4c23-a81e-591fb4607162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719655078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3719655078
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1994894056
Short name T383
Test name
Test status
Simulation time 67449873 ps
CPU time 0.76 seconds
Started Aug 17 06:37:41 PM PDT 24
Finished Aug 17 06:37:42 PM PDT 24
Peak memory 200504 kb
Host smart-96b70cab-e891-4c71-9032-94c82fe54a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994894056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1994894056
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.337959889
Short name T49
Test name
Test status
Simulation time 1886675589 ps
CPU time 7.11 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 221884 kb
Host smart-55632f21-df01-4ad3-b276-0a34c2bf83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337959889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.337959889
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2705067902
Short name T282
Test name
Test status
Simulation time 244737153 ps
CPU time 1.1 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 217864 kb
Host smart-f1286714-2503-4e56-8068-8e2682f64f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705067902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2705067902
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1851338277
Short name T533
Test name
Test status
Simulation time 134319679 ps
CPU time 0.84 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200420 kb
Host smart-201056ee-0798-47c9-878f-8bcf5f340706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851338277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1851338277
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3279576912
Short name T479
Test name
Test status
Simulation time 1642049572 ps
CPU time 6.33 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 200784 kb
Host smart-65511bfc-0d0d-499f-ab41-d16c019ad0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279576912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3279576912
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.4077808677
Short name T170
Test name
Test status
Simulation time 171331505 ps
CPU time 1.18 seconds
Started Aug 17 06:37:52 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 200540 kb
Host smart-55d33e22-a538-415c-82b9-0c85db0df692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077808677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.4077808677
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.4205233569
Short name T353
Test name
Test status
Simulation time 110987743 ps
CPU time 1.21 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 200712 kb
Host smart-97fb7b5b-73f7-4998-b290-66fe6e13d855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205233569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4205233569
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1847233542
Short name T391
Test name
Test status
Simulation time 4941535445 ps
CPU time 18.7 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 210376 kb
Host smart-d0028e2c-3492-43ca-92e3-613d05da776b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847233542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1847233542
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3629177572
Short name T330
Test name
Test status
Simulation time 496409419 ps
CPU time 2.53 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200540 kb
Host smart-4965e54d-361a-4d7d-8b34-76bec1966cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629177572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3629177572
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.1737670480
Short name T528
Test name
Test status
Simulation time 177580730 ps
CPU time 1.21 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 200612 kb
Host smart-6fce87fe-a4b3-49ca-b9be-95e937571d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737670480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1737670480
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.2776360491
Short name T82
Test name
Test status
Simulation time 67160041 ps
CPU time 0.76 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200504 kb
Host smart-71edf7a4-442b-461d-a40f-8198515dff32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776360491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2776360491
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2464486932
Short name T64
Test name
Test status
Simulation time 1870585814 ps
CPU time 6.96 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:56 PM PDT 24
Peak memory 217608 kb
Host smart-06f0a62e-014d-45f3-bb01-a2a9e33d3f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464486932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2464486932
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.862586737
Short name T458
Test name
Test status
Simulation time 243618158 ps
CPU time 1.1 seconds
Started Aug 17 06:37:49 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 217824 kb
Host smart-5de062b8-d8b3-43eb-a97b-778cc09b2e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862586737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.862586737
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1213258222
Short name T243
Test name
Test status
Simulation time 156650888 ps
CPU time 0.83 seconds
Started Aug 17 06:37:52 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200436 kb
Host smart-2448525a-fc33-4b51-ba44-d44d82b11ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213258222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1213258222
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.3045032245
Short name T104
Test name
Test status
Simulation time 1420965846 ps
CPU time 5.47 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 200828 kb
Host smart-66c73564-5f59-417e-b499-879fe98da087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045032245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3045032245
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1670883926
Short name T522
Test name
Test status
Simulation time 103863733 ps
CPU time 0.97 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:44 PM PDT 24
Peak memory 200604 kb
Host smart-a8e1237a-a84d-4850-a9f1-6e65fdb1e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670883926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1670883926
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.877482775
Short name T213
Test name
Test status
Simulation time 245000163 ps
CPU time 1.62 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200808 kb
Host smart-2c9524f1-f45a-4cb9-9978-745c683f5b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877482775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.877482775
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3162574569
Short name T69
Test name
Test status
Simulation time 137731574 ps
CPU time 1.71 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200496 kb
Host smart-d43941b4-8e96-4bb6-ba57-c9b46bca6a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162574569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3162574569
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2181498109
Short name T147
Test name
Test status
Simulation time 125487787 ps
CPU time 1.14 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200608 kb
Host smart-02acb698-5d92-4b6d-b11f-e780e4289bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181498109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2181498109
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.3721598026
Short name T139
Test name
Test status
Simulation time 98482680 ps
CPU time 0.84 seconds
Started Aug 17 06:37:52 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200516 kb
Host smart-a55e6bf3-ee92-42d1-ac9a-ae5e74d19f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721598026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3721598026
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1653483066
Short name T134
Test name
Test status
Simulation time 2370599400 ps
CPU time 9.57 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 218148 kb
Host smart-8a85d825-10a4-4a21-8b45-81853f62e7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653483066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1653483066
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1840921708
Short name T513
Test name
Test status
Simulation time 244783156 ps
CPU time 1.03 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 217864 kb
Host smart-ea5afe0b-92e5-4736-b200-960a8c858ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840921708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1840921708
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1157164752
Short name T250
Test name
Test status
Simulation time 94613517 ps
CPU time 0.75 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:47 PM PDT 24
Peak memory 200452 kb
Host smart-df6641b2-5f68-4054-98b6-bd26f1b137f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157164752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1157164752
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2685119896
Short name T336
Test name
Test status
Simulation time 1466117696 ps
CPU time 5.41 seconds
Started Aug 17 06:37:43 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200868 kb
Host smart-dedb0559-bc00-4a0b-ab58-97a04f94fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685119896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2685119896
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.4034204720
Short name T459
Test name
Test status
Simulation time 147453784 ps
CPU time 1.14 seconds
Started Aug 17 06:38:05 PM PDT 24
Finished Aug 17 06:38:06 PM PDT 24
Peak memory 200640 kb
Host smart-4cc711c7-373a-4ff8-afe6-d5ac29a9f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034204720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.4034204720
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2284381707
Short name T208
Test name
Test status
Simulation time 195625046 ps
CPU time 1.42 seconds
Started Aug 17 06:38:05 PM PDT 24
Finished Aug 17 06:38:06 PM PDT 24
Peak memory 200760 kb
Host smart-c7c325c8-fc29-49e0-9876-b4a1334e8950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284381707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2284381707
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.4284041309
Short name T287
Test name
Test status
Simulation time 3257302856 ps
CPU time 12.76 seconds
Started Aug 17 06:37:52 PM PDT 24
Finished Aug 17 06:38:05 PM PDT 24
Peak memory 200864 kb
Host smart-26a233dc-3d51-4967-9a3f-d6ca5a216dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284041309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.4284041309
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1621958373
Short name T318
Test name
Test status
Simulation time 377248161 ps
CPU time 2.53 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 200540 kb
Host smart-802cacd9-fa0d-414b-b9f4-62a5133642d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621958373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1621958373
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.3064133299
Short name T408
Test name
Test status
Simulation time 121577151 ps
CPU time 1.18 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 200656 kb
Host smart-4274cac5-1b7e-4d13-a4f4-ecc0f2ae2381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064133299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3064133299
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.446462079
Short name T256
Test name
Test status
Simulation time 72316172 ps
CPU time 0.77 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200440 kb
Host smart-503f0ed3-62de-4535-b419-060e2f597a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446462079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.446462079
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.461108799
Short name T416
Test name
Test status
Simulation time 1234542378 ps
CPU time 6.42 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 221928 kb
Host smart-5cc15b11-1a6a-49b6-a31b-1d234bbb4adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461108799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.461108799
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.944873708
Short name T501
Test name
Test status
Simulation time 243405869 ps
CPU time 1.02 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 217796 kb
Host smart-b7f554c2-891d-45fe-979c-0fd237bf90c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944873708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.944873708
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.2579709138
Short name T442
Test name
Test status
Simulation time 94916542 ps
CPU time 0.73 seconds
Started Aug 17 06:37:44 PM PDT 24
Finished Aug 17 06:37:45 PM PDT 24
Peak memory 200368 kb
Host smart-638876eb-fe5d-424f-88f2-53f7b238c4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579709138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2579709138
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.3731373113
Short name T370
Test name
Test status
Simulation time 777318808 ps
CPU time 3.65 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 200708 kb
Host smart-e51ad976-fb25-4369-81ee-978ea8fcbab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731373113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3731373113
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2717184541
Short name T165
Test name
Test status
Simulation time 109816653 ps
CPU time 1.04 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200812 kb
Host smart-30e0ef11-404c-4bed-9eaa-75fe272bfe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717184541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2717184541
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1029088234
Short name T329
Test name
Test status
Simulation time 244030077 ps
CPU time 1.38 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200696 kb
Host smart-e654e1d0-8b83-4402-8bcd-3b7e35957201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029088234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1029088234
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.641095408
Short name T495
Test name
Test status
Simulation time 1964579521 ps
CPU time 7.57 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200788 kb
Host smart-fc3074a6-2f43-40a4-8a05-dd5b57b24134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641095408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.641095408
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3241169617
Short name T148
Test name
Test status
Simulation time 114577950 ps
CPU time 0.97 seconds
Started Aug 17 06:37:45 PM PDT 24
Finished Aug 17 06:37:46 PM PDT 24
Peak memory 200636 kb
Host smart-4e32e9b0-bea6-4326-b566-ce50ac0d0614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241169617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3241169617
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.3570840918
Short name T411
Test name
Test status
Simulation time 69652886 ps
CPU time 0.77 seconds
Started Aug 17 06:37:57 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 200524 kb
Host smart-eb00b62b-708c-4b71-88b7-e517eb3cc759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570840918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3570840918
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1938468577
Short name T33
Test name
Test status
Simulation time 2371223967 ps
CPU time 7.83 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:56 PM PDT 24
Peak memory 222004 kb
Host smart-c3e38c96-7533-43a5-99f2-09543874f2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938468577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1938468577
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1372357274
Short name T331
Test name
Test status
Simulation time 243898066 ps
CPU time 1.14 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 217772 kb
Host smart-7c1abed2-9664-424a-a172-1996163650ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372357274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1372357274
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2759689659
Short name T468
Test name
Test status
Simulation time 90033733 ps
CPU time 0.78 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200376 kb
Host smart-504c1a38-5cb7-4f10-900e-979266fc793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759689659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2759689659
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2031196635
Short name T517
Test name
Test status
Simulation time 986212776 ps
CPU time 4.75 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 200808 kb
Host smart-1a894c31-8a87-46e6-b1f9-1e019ec89166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031196635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2031196635
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3090886966
Short name T149
Test name
Test status
Simulation time 151916328 ps
CPU time 1.18 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200812 kb
Host smart-7156e1a0-9027-4d94-8651-679ec5387477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090886966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3090886966
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.2141485248
Short name T217
Test name
Test status
Simulation time 193948903 ps
CPU time 1.37 seconds
Started Aug 17 06:37:57 PM PDT 24
Finished Aug 17 06:37:59 PM PDT 24
Peak memory 200700 kb
Host smart-c474532b-c315-4d90-b3b0-8d18ad43b634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141485248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2141485248
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.2490841596
Short name T238
Test name
Test status
Simulation time 6651665769 ps
CPU time 31.52 seconds
Started Aug 17 06:37:55 PM PDT 24
Finished Aug 17 06:38:26 PM PDT 24
Peak memory 209088 kb
Host smart-cd8ccfc6-2902-40d6-bba0-2f3cc3b77bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490841596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.2490841596
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.4172004249
Short name T269
Test name
Test status
Simulation time 382071237 ps
CPU time 2.09 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200552 kb
Host smart-60e11df7-38d5-435b-8d8e-b3aded7f6bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172004249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4172004249
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3669449547
Short name T4
Test name
Test status
Simulation time 224610643 ps
CPU time 1.38 seconds
Started Aug 17 06:38:02 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 200640 kb
Host smart-39d96c9e-2aa0-4a5a-8733-051614b9a193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669449547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3669449547
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1444083895
Short name T443
Test name
Test status
Simulation time 77239354 ps
CPU time 0.75 seconds
Started Aug 17 06:38:14 PM PDT 24
Finished Aug 17 06:38:15 PM PDT 24
Peak memory 200476 kb
Host smart-9378ab22-05c8-416b-9604-b2e2d2fc6553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444083895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1444083895
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3268653517
Short name T255
Test name
Test status
Simulation time 1888748539 ps
CPU time 7.3 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 221892 kb
Host smart-66c1caff-0819-4e3e-993e-b0ac5ff42b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268653517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3268653517
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1188984740
Short name T464
Test name
Test status
Simulation time 244191072 ps
CPU time 1.18 seconds
Started Aug 17 06:37:56 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 217728 kb
Host smart-e9dc9a7c-9eec-4ff5-bbf9-d1c5158b0733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188984740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1188984740
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.1892535656
Short name T194
Test name
Test status
Simulation time 212782125 ps
CPU time 0.95 seconds
Started Aug 17 06:37:57 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 200472 kb
Host smart-a466fa92-bd57-4a1e-8f0e-12848454d678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892535656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.1892535656
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2060710841
Short name T445
Test name
Test status
Simulation time 1261830557 ps
CPU time 5.13 seconds
Started Aug 17 06:38:09 PM PDT 24
Finished Aug 17 06:38:14 PM PDT 24
Peak memory 200808 kb
Host smart-11e5ff22-a2b8-446e-a762-6cf7e4dd98b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060710841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2060710841
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2139771367
Short name T402
Test name
Test status
Simulation time 108441720 ps
CPU time 0.99 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200640 kb
Host smart-70767dee-9bd7-49cb-a08e-028e8221ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139771367 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2139771367
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1623481629
Short name T164
Test name
Test status
Simulation time 203275908 ps
CPU time 1.49 seconds
Started Aug 17 06:37:55 PM PDT 24
Finished Aug 17 06:37:57 PM PDT 24
Peak memory 200784 kb
Host smart-fc7541df-df71-4af8-aafc-59326d3ceb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623481629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1623481629
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1429577139
Short name T111
Test name
Test status
Simulation time 6180788757 ps
CPU time 28.21 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:38:20 PM PDT 24
Peak memory 200920 kb
Host smart-3ee318d2-4f60-402c-a8c8-64e4f9a2f91e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429577139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1429577139
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.2901461517
Short name T171
Test name
Test status
Simulation time 319864751 ps
CPU time 2.28 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 208640 kb
Host smart-a3fedd86-9d4c-48a2-943f-c5c9bbb278c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901461517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2901461517
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.207664698
Short name T246
Test name
Test status
Simulation time 160859414 ps
CPU time 1.25 seconds
Started Aug 17 06:37:48 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200680 kb
Host smart-c874b47f-39a6-4e6c-aa3a-da81e5e7ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207664698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.207664698
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1007627243
Short name T9
Test name
Test status
Simulation time 53065660 ps
CPU time 0.71 seconds
Started Aug 17 06:37:49 PM PDT 24
Finished Aug 17 06:37:49 PM PDT 24
Peak memory 200496 kb
Host smart-2924cab6-998e-45ed-9d52-d3d80910ecbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007627243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1007627243
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2360841303
Short name T242
Test name
Test status
Simulation time 1881800576 ps
CPU time 6.88 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 217996 kb
Host smart-a73c0796-793d-465a-9839-d3ef192d8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360841303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2360841303
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2015662665
Short name T61
Test name
Test status
Simulation time 243832156 ps
CPU time 1.12 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 217792 kb
Host smart-82b9d939-3822-477d-b107-af05d7cbac84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015662665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2015662665
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3714728764
Short name T266
Test name
Test status
Simulation time 187240556 ps
CPU time 0.92 seconds
Started Aug 17 06:38:00 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 200456 kb
Host smart-9f266337-f699-4a8f-98e0-3ca07785ec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714728764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3714728764
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.2212646089
Short name T132
Test name
Test status
Simulation time 1337841515 ps
CPU time 5.06 seconds
Started Aug 17 06:37:55 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200832 kb
Host smart-bde965f7-7eb7-4a8d-8b43-5783f592dd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212646089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2212646089
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.427318728
Short name T218
Test name
Test status
Simulation time 106068674 ps
CPU time 0.98 seconds
Started Aug 17 06:38:03 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 200600 kb
Host smart-8d16eeab-d005-46d9-914d-731f6c61f4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427318728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.427318728
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2149310852
Short name T192
Test name
Test status
Simulation time 265245510 ps
CPU time 1.8 seconds
Started Aug 17 06:37:46 PM PDT 24
Finished Aug 17 06:37:48 PM PDT 24
Peak memory 200760 kb
Host smart-d5fc22c6-dd27-4783-a596-0a8c8a2da4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149310852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2149310852
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.1178492801
Short name T378
Test name
Test status
Simulation time 4578616029 ps
CPU time 15.7 seconds
Started Aug 17 06:38:00 PM PDT 24
Finished Aug 17 06:38:16 PM PDT 24
Peak memory 209076 kb
Host smart-63dda062-65b8-49f8-ab06-bf7d74ddd366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178492801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1178492801
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1638496416
Short name T153
Test name
Test status
Simulation time 340538394 ps
CPU time 2.48 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:02 PM PDT 24
Peak memory 200540 kb
Host smart-9ccccbe5-1257-4488-826b-146635af3cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638496416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1638496416
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.967564693
Short name T60
Test name
Test status
Simulation time 258694457 ps
CPU time 1.49 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200648 kb
Host smart-630313ae-8028-49f0-b8c0-90faea43730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967564693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.967564693
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2861548178
Short name T423
Test name
Test status
Simulation time 60523910 ps
CPU time 0.79 seconds
Started Aug 17 06:38:01 PM PDT 24
Finished Aug 17 06:38:02 PM PDT 24
Peak memory 200512 kb
Host smart-096e8c19-3dfb-487a-8979-46eb3ae8b7a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861548178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2861548178
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.1080971538
Short name T497
Test name
Test status
Simulation time 1224536235 ps
CPU time 5.45 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 217668 kb
Host smart-0233eb87-267a-49e9-afc2-60dd47b3934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080971538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1080971538
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2011320980
Short name T389
Test name
Test status
Simulation time 244913147 ps
CPU time 1.04 seconds
Started Aug 17 06:38:08 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 217636 kb
Host smart-06959689-6c8c-4968-89ef-893b3f513ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011320980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2011320980
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.1471804820
Short name T516
Test name
Test status
Simulation time 163898423 ps
CPU time 0.93 seconds
Started Aug 17 06:38:04 PM PDT 24
Finished Aug 17 06:38:05 PM PDT 24
Peak memory 200456 kb
Host smart-b0b364d6-d092-4651-85bd-7b9c233da0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471804820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1471804820
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2364771190
Short name T85
Test name
Test status
Simulation time 1157324208 ps
CPU time 4.57 seconds
Started Aug 17 06:38:08 PM PDT 24
Finished Aug 17 06:38:13 PM PDT 24
Peak memory 200820 kb
Host smart-098f5e51-aabb-4ce4-b5ae-e22d18f70df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364771190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2364771190
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.454387378
Short name T224
Test name
Test status
Simulation time 111284929 ps
CPU time 1.05 seconds
Started Aug 17 06:37:52 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200816 kb
Host smart-1eb536e4-8847-4b68-86e7-f0e20d7041b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454387378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.454387378
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.1040103505
Short name T406
Test name
Test status
Simulation time 197773105 ps
CPU time 1.39 seconds
Started Aug 17 06:37:52 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200784 kb
Host smart-72337450-2d99-4f5c-8c63-333381d58c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040103505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1040103505
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.4213358085
Short name T119
Test name
Test status
Simulation time 3117052109 ps
CPU time 14.33 seconds
Started Aug 17 06:38:13 PM PDT 24
Finished Aug 17 06:38:28 PM PDT 24
Peak memory 200844 kb
Host smart-f5dd62c2-50b4-4edc-adde-64150b1d130c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213358085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4213358085
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.831967798
Short name T230
Test name
Test status
Simulation time 490292105 ps
CPU time 2.8 seconds
Started Aug 17 06:38:06 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 200564 kb
Host smart-5dc1ef0d-1b5c-4f9d-a2ee-4fd769ae6764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831967798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.831967798
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1817235704
Short name T478
Test name
Test status
Simulation time 87522925 ps
CPU time 0.83 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 200660 kb
Host smart-f183a9f2-c96c-4339-bdc8-50658e3e39a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817235704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1817235704
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3078920567
Short name T397
Test name
Test status
Simulation time 69076446 ps
CPU time 0.75 seconds
Started Aug 17 06:37:58 PM PDT 24
Finished Aug 17 06:37:59 PM PDT 24
Peak memory 200460 kb
Host smart-39e06d0c-37fe-4210-98ee-952680f83da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078920567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3078920567
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2579908561
Short name T38
Test name
Test status
Simulation time 1225082907 ps
CPU time 5.9 seconds
Started Aug 17 06:37:55 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 218032 kb
Host smart-650a0a75-7858-4490-8c0f-60cc1c86ea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579908561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2579908561
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.345605409
Short name T26
Test name
Test status
Simulation time 243815531 ps
CPU time 1.11 seconds
Started Aug 17 06:38:16 PM PDT 24
Finished Aug 17 06:38:17 PM PDT 24
Peak memory 217840 kb
Host smart-d19a7932-cf7b-4394-bcce-b3b29da100bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345605409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.345605409
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.3187334439
Short name T196
Test name
Test status
Simulation time 133856469 ps
CPU time 0.79 seconds
Started Aug 17 06:38:08 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 200372 kb
Host smart-9d0836a4-5592-4d0b-be60-f0afeb60d493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187334439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3187334439
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.772905622
Short name T176
Test name
Test status
Simulation time 1007952111 ps
CPU time 5.1 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 200808 kb
Host smart-304d98f1-104c-40b5-96b0-1c792d7f7a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772905622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.772905622
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1780487560
Short name T144
Test name
Test status
Simulation time 138152708 ps
CPU time 1.14 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200644 kb
Host smart-0b404507-1462-4781-892d-aee4e7e407dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780487560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1780487560
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.2090106829
Short name T390
Test name
Test status
Simulation time 258991080 ps
CPU time 1.73 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 200736 kb
Host smart-4d3ff1e6-1926-4e85-a28e-6ccc727a456c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090106829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2090106829
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.543162340
Short name T398
Test name
Test status
Simulation time 11101328859 ps
CPU time 37.89 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:38:31 PM PDT 24
Peak memory 209008 kb
Host smart-51670484-faaa-4d2e-a2ba-3a30a8b51be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543162340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.543162340
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.2352707490
Short name T327
Test name
Test status
Simulation time 342243898 ps
CPU time 2.27 seconds
Started Aug 17 06:38:05 PM PDT 24
Finished Aug 17 06:38:07 PM PDT 24
Peak memory 200564 kb
Host smart-43d392d2-9bfe-4b97-a1b5-e5ece9424a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352707490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2352707490
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.3689729316
Short name T107
Test name
Test status
Simulation time 81699156 ps
CPU time 0.88 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 200644 kb
Host smart-47234932-d859-4d30-a228-a2fc7a570292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689729316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3689729316
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.2145878847
Short name T323
Test name
Test status
Simulation time 77525566 ps
CPU time 0.85 seconds
Started Aug 17 06:37:55 PM PDT 24
Finished Aug 17 06:37:56 PM PDT 24
Peak memory 200700 kb
Host smart-796def32-11f1-4321-a153-8c49111c0c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145878847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2145878847
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1029270304
Short name T316
Test name
Test status
Simulation time 1898206268 ps
CPU time 6.97 seconds
Started Aug 17 06:37:57 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 221944 kb
Host smart-62e2337b-7977-4c87-8b04-c0020ae7ef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029270304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1029270304
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2867885851
Short name T207
Test name
Test status
Simulation time 244372502 ps
CPU time 1.04 seconds
Started Aug 17 06:37:49 PM PDT 24
Finished Aug 17 06:37:50 PM PDT 24
Peak memory 217832 kb
Host smart-a8a3a77c-bf8c-4c37-ad55-f2b56dc8014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867885851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2867885851
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.2677338369
Short name T23
Test name
Test status
Simulation time 130953693 ps
CPU time 0.81 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:51 PM PDT 24
Peak memory 200448 kb
Host smart-4a51e9de-f90e-4725-846c-a2f70373bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677338369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2677338369
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1112551272
Short name T366
Test name
Test status
Simulation time 2187674958 ps
CPU time 8.5 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:08 PM PDT 24
Peak memory 200812 kb
Host smart-4cd28364-98c4-48d4-87d6-c1d258711e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112551272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1112551272
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3154465794
Short name T2
Test name
Test status
Simulation time 148822987 ps
CPU time 1.05 seconds
Started Aug 17 06:38:13 PM PDT 24
Finished Aug 17 06:38:15 PM PDT 24
Peak memory 200620 kb
Host smart-3fa67fae-1136-4d04-8377-eab712bc3309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154465794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3154465794
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1773189032
Short name T536
Test name
Test status
Simulation time 190615731 ps
CPU time 1.34 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 200664 kb
Host smart-a4b5e2f8-91a1-4ced-8241-f8b9b6af0c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773189032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1773189032
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.1422777515
Short name T108
Test name
Test status
Simulation time 9298393811 ps
CPU time 30.81 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:38:25 PM PDT 24
Peak memory 200880 kb
Host smart-e29e15ca-9f91-4dce-b662-2e5b2ef7c091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422777515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1422777515
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.4180764017
Short name T315
Test name
Test status
Simulation time 134279714 ps
CPU time 1.64 seconds
Started Aug 17 06:38:16 PM PDT 24
Finished Aug 17 06:38:18 PM PDT 24
Peak memory 200564 kb
Host smart-385f678a-7234-4418-bbd7-1b64b6c4eaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180764017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.4180764017
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.822732450
Short name T431
Test name
Test status
Simulation time 167647454 ps
CPU time 1.2 seconds
Started Aug 17 06:38:06 PM PDT 24
Finished Aug 17 06:38:07 PM PDT 24
Peak memory 200632 kb
Host smart-97f43180-3e06-4f53-b2e7-1293f9712ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822732450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.822732450
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.2758269417
Short name T142
Test name
Test status
Simulation time 77451454 ps
CPU time 0.82 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 200512 kb
Host smart-4dc67573-ab0b-45cc-afc0-57b57cdb0e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758269417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2758269417
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3717332836
Short name T324
Test name
Test status
Simulation time 1894247979 ps
CPU time 7.5 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 216984 kb
Host smart-d9718ecf-2a01-452b-aa32-e2d8eae44ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717332836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3717332836
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3265757873
Short name T277
Test name
Test status
Simulation time 244538935 ps
CPU time 1.06 seconds
Started Aug 17 06:37:08 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 217840 kb
Host smart-6b17b929-81f1-41bb-b4f1-b01aa5073740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265757873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3265757873
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.3458327447
Short name T405
Test name
Test status
Simulation time 117371917 ps
CPU time 0.8 seconds
Started Aug 17 06:37:07 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 200444 kb
Host smart-b292bfd9-d34c-48ec-8a24-5d0da0ce1901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458327447 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3458327447
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4206000571
Short name T463
Test name
Test status
Simulation time 1287842484 ps
CPU time 5.45 seconds
Started Aug 17 06:37:02 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 200812 kb
Host smart-76eb9809-fde9-4e47-956e-990b4494e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206000571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4206000571
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.3867351372
Short name T78
Test name
Test status
Simulation time 16512285661 ps
CPU time 30.4 seconds
Started Aug 17 06:36:57 PM PDT 24
Finished Aug 17 06:37:27 PM PDT 24
Peak memory 217400 kb
Host smart-b3f3a856-31af-4cdd-8d0c-e133909e7db3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867351372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3867351372
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3646722230
Short name T322
Test name
Test status
Simulation time 137699027 ps
CPU time 1.03 seconds
Started Aug 17 06:37:16 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 200624 kb
Host smart-7c1467b6-5674-44d4-a90d-2e18db8f6d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646722230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3646722230
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1915636687
Short name T371
Test name
Test status
Simulation time 118207285 ps
CPU time 1.18 seconds
Started Aug 17 06:37:00 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 200732 kb
Host smart-6e35c934-a130-4805-8be4-61ad1fb62b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915636687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1915636687
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.550926879
Short name T346
Test name
Test status
Simulation time 1043791855 ps
CPU time 5.12 seconds
Started Aug 17 06:37:07 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 200812 kb
Host smart-b4ac6dc6-57c3-45dc-9c25-19bed2325569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550926879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.550926879
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.365596664
Short name T319
Test name
Test status
Simulation time 119915810 ps
CPU time 1.56 seconds
Started Aug 17 06:37:13 PM PDT 24
Finished Aug 17 06:37:15 PM PDT 24
Peak memory 200568 kb
Host smart-70c2b93e-4106-4c1e-87a3-a0ff6db986e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365596664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.365596664
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.2653861438
Short name T229
Test name
Test status
Simulation time 168650581 ps
CPU time 1.12 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 200620 kb
Host smart-8b3613d9-6b73-47cd-bf21-e2cd874ca3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653861438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2653861438
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.3596595273
Short name T491
Test name
Test status
Simulation time 64945085 ps
CPU time 0.72 seconds
Started Aug 17 06:38:06 PM PDT 24
Finished Aug 17 06:38:07 PM PDT 24
Peak memory 200488 kb
Host smart-67aaafc4-25be-4fff-acd7-6dc204f64a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596595273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3596595273
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.3337496381
Short name T518
Test name
Test status
Simulation time 1875626234 ps
CPU time 7.08 seconds
Started Aug 17 06:37:47 PM PDT 24
Finished Aug 17 06:37:54 PM PDT 24
Peak memory 217976 kb
Host smart-639047da-6325-444d-97bf-7b8d30f1aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337496381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3337496381
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1854342122
Short name T344
Test name
Test status
Simulation time 244278674 ps
CPU time 1.13 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 217756 kb
Host smart-dccf5fa2-9b15-4e6b-8800-0859a70528e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854342122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1854342122
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.3952380915
Short name T237
Test name
Test status
Simulation time 141076687 ps
CPU time 0.84 seconds
Started Aug 17 06:38:16 PM PDT 24
Finished Aug 17 06:38:17 PM PDT 24
Peak memory 200432 kb
Host smart-4c9e67cf-ab09-46d8-b4b8-4d6ab2f62a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952380915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3952380915
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.2005576499
Short name T403
Test name
Test status
Simulation time 689044556 ps
CPU time 3.63 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 200812 kb
Host smart-971f074e-27d8-444c-b1fc-566a5a15b734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005576499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2005576499
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1629964364
Short name T220
Test name
Test status
Simulation time 113037206 ps
CPU time 0.97 seconds
Started Aug 17 06:38:08 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 200636 kb
Host smart-2e0e6e55-3067-4f21-b77d-d331a4579f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629964364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1629964364
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3711053087
Short name T209
Test name
Test status
Simulation time 257693973 ps
CPU time 1.46 seconds
Started Aug 17 06:37:56 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 199384 kb
Host smart-70493c0f-b414-44da-bb6d-da70a0accd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711053087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3711053087
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3356410946
Short name T115
Test name
Test status
Simulation time 14941395593 ps
CPU time 48.38 seconds
Started Aug 17 06:38:07 PM PDT 24
Finished Aug 17 06:38:56 PM PDT 24
Peak memory 209060 kb
Host smart-936f302a-1c45-45fd-bc7a-6f858a1fdc69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356410946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3356410946
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.2394002909
Short name T110
Test name
Test status
Simulation time 287079271 ps
CPU time 1.92 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 200532 kb
Host smart-66191112-3194-4d7b-92d9-011f1057b1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394002909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2394002909
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.204571952
Short name T222
Test name
Test status
Simulation time 233499128 ps
CPU time 1.37 seconds
Started Aug 17 06:37:56 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 200572 kb
Host smart-60ff0b87-5ffd-4503-9230-4e5b3c611d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204571952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.204571952
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1480674428
Short name T488
Test name
Test status
Simulation time 73950408 ps
CPU time 0.79 seconds
Started Aug 17 06:37:52 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200516 kb
Host smart-141b1e4e-b5cc-4849-85d7-64153d42995c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480674428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1480674428
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2751390464
Short name T502
Test name
Test status
Simulation time 243734064 ps
CPU time 1.11 seconds
Started Aug 17 06:38:06 PM PDT 24
Finished Aug 17 06:38:08 PM PDT 24
Peak memory 217800 kb
Host smart-8d8c9095-3726-4d0d-8f8b-33169749d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751390464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2751390464
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.3081384707
Short name T205
Test name
Test status
Simulation time 183493542 ps
CPU time 0.85 seconds
Started Aug 17 06:38:19 PM PDT 24
Finished Aug 17 06:38:20 PM PDT 24
Peak memory 200436 kb
Host smart-dc1792d2-ca7c-46be-bb5a-b8304ab52e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081384707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3081384707
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3256542381
Short name T512
Test name
Test status
Simulation time 700448075 ps
CPU time 3.95 seconds
Started Aug 17 06:37:57 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 200744 kb
Host smart-78f06a24-2f55-4d54-a649-6d150f7422f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256542381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3256542381
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2174960305
Short name T377
Test name
Test status
Simulation time 177291861 ps
CPU time 1.22 seconds
Started Aug 17 06:38:16 PM PDT 24
Finished Aug 17 06:38:17 PM PDT 24
Peak memory 200620 kb
Host smart-9ea00fb8-e490-44bb-b5b1-b459fb236151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174960305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2174960305
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2723450635
Short name T249
Test name
Test status
Simulation time 248068729 ps
CPU time 1.51 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:37:52 PM PDT 24
Peak memory 200728 kb
Host smart-cce6f99a-8035-4b74-8e37-51018d8ac817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723450635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2723450635
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.3550457849
Short name T469
Test name
Test status
Simulation time 4851235947 ps
CPU time 17.98 seconds
Started Aug 17 06:37:50 PM PDT 24
Finished Aug 17 06:38:08 PM PDT 24
Peak memory 200812 kb
Host smart-16840078-734d-4b85-8978-ce1875a3a6a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550457849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.3550457849
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1830260304
Short name T151
Test name
Test status
Simulation time 251875227 ps
CPU time 1.87 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 200540 kb
Host smart-af914b5b-489a-4d76-b900-1e5862a347b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830260304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1830260304
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.974912633
Short name T376
Test name
Test status
Simulation time 168083147 ps
CPU time 1.18 seconds
Started Aug 17 06:38:04 PM PDT 24
Finished Aug 17 06:38:06 PM PDT 24
Peak memory 200568 kb
Host smart-efa1a696-8d67-40ac-82e6-17fadd511802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974912633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.974912633
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.1366407477
Short name T219
Test name
Test status
Simulation time 71815952 ps
CPU time 0.75 seconds
Started Aug 17 06:38:15 PM PDT 24
Finished Aug 17 06:38:16 PM PDT 24
Peak memory 200488 kb
Host smart-47bf2d8b-2d90-4b1d-8912-c3e955274fa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366407477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1366407477
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.4225491218
Short name T66
Test name
Test status
Simulation time 1903297819 ps
CPU time 7.2 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 217936 kb
Host smart-ce674cfd-70bc-4d87-be2e-dfae363259ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225491218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4225491218
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2920604122
Short name T357
Test name
Test status
Simulation time 243781107 ps
CPU time 1.08 seconds
Started Aug 17 06:38:07 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 217808 kb
Host smart-0c99c40e-7a72-4166-a6fd-13346b389291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920604122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2920604122
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.1708592725
Short name T347
Test name
Test status
Simulation time 121410742 ps
CPU time 0.8 seconds
Started Aug 17 06:38:03 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 200428 kb
Host smart-748224ae-d329-4533-a4ab-aa71a625befd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708592725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1708592725
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2333848718
Short name T420
Test name
Test status
Simulation time 2135306606 ps
CPU time 7.68 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 200812 kb
Host smart-2b749ab8-78e7-4734-9dac-8e9929501151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333848718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2333848718
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2214806915
Short name T429
Test name
Test status
Simulation time 177027125 ps
CPU time 1.27 seconds
Started Aug 17 06:37:53 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 200644 kb
Host smart-703478b2-5608-42d0-aa1c-0f6730eae2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214806915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2214806915
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1446651579
Short name T42
Test name
Test status
Simulation time 124605432 ps
CPU time 1.2 seconds
Started Aug 17 06:38:06 PM PDT 24
Finished Aug 17 06:38:07 PM PDT 24
Peak memory 200752 kb
Host smart-d65d99d3-49c2-4394-a5a9-3df7f2139271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446651579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1446651579
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.1033181598
Short name T29
Test name
Test status
Simulation time 4148684094 ps
CPU time 15.44 seconds
Started Aug 17 06:37:58 PM PDT 24
Finished Aug 17 06:38:13 PM PDT 24
Peak memory 209136 kb
Host smart-1c52efbe-4003-492b-9584-8e945dfee7d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033181598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.1033181598
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.2219177657
Short name T305
Test name
Test status
Simulation time 148289531 ps
CPU time 1.91 seconds
Started Aug 17 06:37:51 PM PDT 24
Finished Aug 17 06:37:53 PM PDT 24
Peak memory 200244 kb
Host smart-5df37c79-7c18-40e9-80a2-3a0fa6b6ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219177657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2219177657
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.381345535
Short name T434
Test name
Test status
Simulation time 137235441 ps
CPU time 1.14 seconds
Started Aug 17 06:37:54 PM PDT 24
Finished Aug 17 06:37:55 PM PDT 24
Peak memory 200640 kb
Host smart-895e9279-6487-47ab-9a0f-fb8bd0bc53b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381345535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.381345535
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.3641239442
Short name T55
Test name
Test status
Simulation time 92815040 ps
CPU time 0.87 seconds
Started Aug 17 06:38:15 PM PDT 24
Finished Aug 17 06:38:16 PM PDT 24
Peak memory 200460 kb
Host smart-d99aff12-b00f-4824-b911-76f6ddda591a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641239442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3641239442
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.1374328279
Short name T54
Test name
Test status
Simulation time 2358752582 ps
CPU time 8.04 seconds
Started Aug 17 06:38:00 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 218148 kb
Host smart-5efc4d05-e735-4829-9650-d65339c47154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374328279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1374328279
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1568879758
Short name T56
Test name
Test status
Simulation time 245739099 ps
CPU time 1.05 seconds
Started Aug 17 06:37:57 PM PDT 24
Finished Aug 17 06:37:58 PM PDT 24
Peak memory 217760 kb
Host smart-f716559b-26e6-42a3-b7be-aaf26dbb344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568879758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1568879758
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.175594104
Short name T328
Test name
Test status
Simulation time 228664670 ps
CPU time 0.91 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200408 kb
Host smart-6fedaa29-e5a2-4687-b566-70c9480dd788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175594104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.175594104
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2970679543
Short name T407
Test name
Test status
Simulation time 797956710 ps
CPU time 4.04 seconds
Started Aug 17 06:38:08 PM PDT 24
Finished Aug 17 06:38:12 PM PDT 24
Peak memory 200864 kb
Host smart-c2c0fcd7-85d7-4b71-ba02-cca3176f387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970679543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2970679543
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3608965779
Short name T231
Test name
Test status
Simulation time 104455598 ps
CPU time 0.98 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200596 kb
Host smart-e906ff0e-8c9f-427e-baad-6b4ba4f3d6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608965779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3608965779
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1505873759
Short name T307
Test name
Test status
Simulation time 120492647 ps
CPU time 1.25 seconds
Started Aug 17 06:38:08 PM PDT 24
Finished Aug 17 06:38:09 PM PDT 24
Peak memory 200752 kb
Host smart-1e982bb7-2bb0-45b2-b099-339239127cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505873759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1505873759
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.191900582
Short name T414
Test name
Test status
Simulation time 6869546717 ps
CPU time 24.59 seconds
Started Aug 17 06:38:05 PM PDT 24
Finished Aug 17 06:38:30 PM PDT 24
Peak memory 200864 kb
Host smart-85c78cd3-ed0e-41d1-98e0-b1f2b4cf1dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191900582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.191900582
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3280043028
Short name T198
Test name
Test status
Simulation time 122653000 ps
CPU time 1.54 seconds
Started Aug 17 06:38:07 PM PDT 24
Finished Aug 17 06:38:19 PM PDT 24
Peak memory 200524 kb
Host smart-ed1625e4-1861-4c07-b751-4e8682963d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280043028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3280043028
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3492031686
Short name T313
Test name
Test status
Simulation time 168448702 ps
CPU time 1.12 seconds
Started Aug 17 06:38:03 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 200640 kb
Host smart-80b399af-c470-4e05-b796-a28a785d763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492031686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3492031686
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2430498661
Short name T508
Test name
Test status
Simulation time 83786599 ps
CPU time 0.81 seconds
Started Aug 17 06:38:30 PM PDT 24
Finished Aug 17 06:38:31 PM PDT 24
Peak memory 200500 kb
Host smart-dbc909a2-e925-481d-a8f0-b59d13dd29f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430498661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2430498661
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.3687430007
Short name T519
Test name
Test status
Simulation time 2342640684 ps
CPU time 7.95 seconds
Started Aug 17 06:38:26 PM PDT 24
Finished Aug 17 06:38:34 PM PDT 24
Peak memory 222040 kb
Host smart-fa767db8-64b5-44ce-8193-a33eb120f876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687430007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3687430007
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.854804306
Short name T480
Test name
Test status
Simulation time 242982086 ps
CPU time 1.11 seconds
Started Aug 17 06:38:03 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 217724 kb
Host smart-eaf04435-fe5a-4321-9e45-67d6c00acb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854804306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.854804306
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.4116736155
Short name T440
Test name
Test status
Simulation time 126074036 ps
CPU time 0.78 seconds
Started Aug 17 06:38:26 PM PDT 24
Finished Aug 17 06:38:27 PM PDT 24
Peak memory 200424 kb
Host smart-c8eac658-7754-46a1-9fb5-af4678935499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116736155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4116736155
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2288876011
Short name T295
Test name
Test status
Simulation time 1632379100 ps
CPU time 6.41 seconds
Started Aug 17 06:38:26 PM PDT 24
Finished Aug 17 06:38:33 PM PDT 24
Peak memory 200820 kb
Host smart-fbacd088-e94d-4f31-a62c-a71465762269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288876011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2288876011
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3315664438
Short name T40
Test name
Test status
Simulation time 106564637 ps
CPU time 1.01 seconds
Started Aug 17 06:38:04 PM PDT 24
Finished Aug 17 06:38:05 PM PDT 24
Peak memory 200644 kb
Host smart-1110d9ac-25b4-44ad-9a34-7f6d35099e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315664438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3315664438
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.227275959
Short name T257
Test name
Test status
Simulation time 112037299 ps
CPU time 1.25 seconds
Started Aug 17 06:38:23 PM PDT 24
Finished Aug 17 06:38:25 PM PDT 24
Peak memory 200768 kb
Host smart-03891e9f-8060-4075-8e24-71bdfc475fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227275959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.227275959
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1840202927
Short name T526
Test name
Test status
Simulation time 4024685823 ps
CPU time 15.24 seconds
Started Aug 17 06:38:10 PM PDT 24
Finished Aug 17 06:38:25 PM PDT 24
Peak memory 209056 kb
Host smart-7f5424e1-f847-4356-b6c0-0944da4be665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840202927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1840202927
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3397243052
Short name T188
Test name
Test status
Simulation time 265371238 ps
CPU time 2.02 seconds
Started Aug 17 06:38:01 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 200496 kb
Host smart-c09ae082-8ba0-4ebc-8414-c8e533e3af28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397243052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3397243052
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.2490183690
Short name T525
Test name
Test status
Simulation time 124148154 ps
CPU time 0.96 seconds
Started Aug 17 06:38:12 PM PDT 24
Finished Aug 17 06:38:13 PM PDT 24
Peak memory 200644 kb
Host smart-5eceff0d-813a-47f6-bc07-912d9b1f28a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490183690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2490183690
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.286920909
Short name T367
Test name
Test status
Simulation time 74647904 ps
CPU time 0.81 seconds
Started Aug 17 06:38:01 PM PDT 24
Finished Aug 17 06:38:02 PM PDT 24
Peak memory 200692 kb
Host smart-1199d951-2379-4ff5-ba17-d0716f22c126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286920909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.286920909
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.3388953504
Short name T34
Test name
Test status
Simulation time 1895961590 ps
CPU time 8.28 seconds
Started Aug 17 06:38:00 PM PDT 24
Finished Aug 17 06:38:08 PM PDT 24
Peak memory 230160 kb
Host smart-535dac2a-a186-4e10-b270-ef37853f64c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388953504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3388953504
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3975372867
Short name T419
Test name
Test status
Simulation time 247483608 ps
CPU time 1.02 seconds
Started Aug 17 06:38:25 PM PDT 24
Finished Aug 17 06:38:26 PM PDT 24
Peak memory 217832 kb
Host smart-f39cd64c-9b07-4e44-ae84-0b3b64ec81ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975372867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3975372867
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.298292095
Short name T19
Test name
Test status
Simulation time 233565708 ps
CPU time 0.95 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200476 kb
Host smart-bd83ddbe-0011-4094-b9a6-1f04156c0156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298292095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.298292095
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.650467312
Short name T289
Test name
Test status
Simulation time 1283881438 ps
CPU time 5.34 seconds
Started Aug 17 06:38:07 PM PDT 24
Finished Aug 17 06:38:13 PM PDT 24
Peak memory 200804 kb
Host smart-8997c749-1520-4cfb-b472-051a8d17a854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650467312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.650467312
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.252376256
Short name T384
Test name
Test status
Simulation time 110689315 ps
CPU time 0.98 seconds
Started Aug 17 06:38:11 PM PDT 24
Finished Aug 17 06:38:12 PM PDT 24
Peak memory 200568 kb
Host smart-4d266d97-1432-4f9f-9887-f3c0296eaed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252376256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.252376256
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.4137143304
Short name T500
Test name
Test status
Simulation time 238948152 ps
CPU time 1.49 seconds
Started Aug 17 06:38:06 PM PDT 24
Finished Aug 17 06:38:08 PM PDT 24
Peak memory 200740 kb
Host smart-2b4e946f-160c-4a1b-9554-b2c9c646fa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137143304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.4137143304
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.1912948382
Short name T418
Test name
Test status
Simulation time 6922505366 ps
CPU time 25.07 seconds
Started Aug 17 06:38:00 PM PDT 24
Finished Aug 17 06:38:25 PM PDT 24
Peak memory 209036 kb
Host smart-391e3d77-12d5-4784-8b64-6a2d37879f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912948382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1912948382
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.4023327458
Short name T417
Test name
Test status
Simulation time 347609140 ps
CPU time 2.35 seconds
Started Aug 17 06:38:19 PM PDT 24
Finished Aug 17 06:38:21 PM PDT 24
Peak memory 200564 kb
Host smart-78459a76-c3c9-4f06-abcd-7392b1ddd571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023327458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.4023327458
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1451965463
Short name T356
Test name
Test status
Simulation time 138452270 ps
CPU time 1.16 seconds
Started Aug 17 06:38:03 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 200644 kb
Host smart-359a600f-dbd8-4f59-8d3c-d3013720694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451965463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1451965463
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2901009954
Short name T44
Test name
Test status
Simulation time 85278886 ps
CPU time 0.79 seconds
Started Aug 17 06:38:33 PM PDT 24
Finished Aug 17 06:38:34 PM PDT 24
Peak memory 200512 kb
Host smart-203ee4e9-908a-456c-b530-2e67cd1de567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901009954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2901009954
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.139849205
Short name T345
Test name
Test status
Simulation time 2375850477 ps
CPU time 9.09 seconds
Started Aug 17 06:38:04 PM PDT 24
Finished Aug 17 06:38:14 PM PDT 24
Peak memory 222004 kb
Host smart-923aa3c0-7cd6-4953-b629-7ba3a1d5f460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139849205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.139849205
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2309779071
Short name T404
Test name
Test status
Simulation time 243535846 ps
CPU time 1.07 seconds
Started Aug 17 06:38:04 PM PDT 24
Finished Aug 17 06:38:05 PM PDT 24
Peak memory 217804 kb
Host smart-f8c32cea-775b-46bf-a7ad-d13c27523a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309779071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2309779071
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.433636380
Short name T24
Test name
Test status
Simulation time 129164993 ps
CPU time 0.84 seconds
Started Aug 17 06:38:02 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 200356 kb
Host smart-73a341a4-7470-49a3-b229-b1355009c6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433636380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.433636380
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2590996417
Short name T343
Test name
Test status
Simulation time 863121040 ps
CPU time 4.46 seconds
Started Aug 17 06:37:58 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 200772 kb
Host smart-15cbdaa3-3713-4b4a-8ebe-d4d1b328a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590996417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2590996417
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.2379082256
Short name T46
Test name
Test status
Simulation time 105621734 ps
CPU time 1.06 seconds
Started Aug 17 06:38:25 PM PDT 24
Finished Aug 17 06:38:26 PM PDT 24
Peak memory 200636 kb
Host smart-c343c926-3de9-40d8-8d4f-3f55cd39a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379082256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.2379082256
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.662696609
Short name T333
Test name
Test status
Simulation time 117954783 ps
CPU time 1.19 seconds
Started Aug 17 06:38:03 PM PDT 24
Finished Aug 17 06:38:05 PM PDT 24
Peak memory 200740 kb
Host smart-58acf624-d2e7-46f0-b250-075953e6ae19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662696609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.662696609
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3021036823
Short name T484
Test name
Test status
Simulation time 1012571536 ps
CPU time 4.95 seconds
Started Aug 17 06:38:12 PM PDT 24
Finished Aug 17 06:38:18 PM PDT 24
Peak memory 208928 kb
Host smart-3159079f-302f-4f06-b8e5-a6c8ebd99e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021036823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3021036823
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1374064654
Short name T492
Test name
Test status
Simulation time 465163238 ps
CPU time 2.51 seconds
Started Aug 17 06:38:12 PM PDT 24
Finished Aug 17 06:38:15 PM PDT 24
Peak memory 208688 kb
Host smart-761546a6-7baa-474e-b401-359c0aaf4ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374064654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1374064654
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.459412106
Short name T433
Test name
Test status
Simulation time 82021954 ps
CPU time 0.87 seconds
Started Aug 17 06:38:02 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 200544 kb
Host smart-30ebed05-1aaf-4759-92ae-4b9da7030166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459412106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.459412106
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.2861734900
Short name T191
Test name
Test status
Simulation time 77899749 ps
CPU time 0.78 seconds
Started Aug 17 06:38:02 PM PDT 24
Finished Aug 17 06:38:03 PM PDT 24
Peak memory 200472 kb
Host smart-f60875bf-7f49-4e95-9d74-55487ab05964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861734900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2861734900
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.600122756
Short name T392
Test name
Test status
Simulation time 2367428439 ps
CPU time 8.89 seconds
Started Aug 17 06:38:06 PM PDT 24
Finished Aug 17 06:38:15 PM PDT 24
Peak memory 217964 kb
Host smart-7b73c87a-86c5-40d2-b110-bc8a1f345f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600122756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.600122756
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1946880048
Short name T240
Test name
Test status
Simulation time 244364957 ps
CPU time 1.11 seconds
Started Aug 17 06:38:03 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 217780 kb
Host smart-f42b7fd2-4023-465f-bc17-c7748087c5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946880048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1946880048
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.4244278622
Short name T379
Test name
Test status
Simulation time 87079351 ps
CPU time 0.75 seconds
Started Aug 17 06:38:01 PM PDT 24
Finished Aug 17 06:38:02 PM PDT 24
Peak memory 200444 kb
Host smart-8f3cd65a-438e-4117-b9b0-555f7e7cfe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244278622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4244278622
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.2038791515
Short name T130
Test name
Test status
Simulation time 1460875608 ps
CPU time 6.1 seconds
Started Aug 17 06:38:07 PM PDT 24
Finished Aug 17 06:38:13 PM PDT 24
Peak memory 200784 kb
Host smart-e96dcdbb-4c27-4a8b-b0e7-329cbf1acbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038791515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2038791515
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2348051684
Short name T236
Test name
Test status
Simulation time 155623769 ps
CPU time 1.16 seconds
Started Aug 17 06:38:01 PM PDT 24
Finished Aug 17 06:38:02 PM PDT 24
Peak memory 200576 kb
Host smart-6e7771c6-6408-4403-a85f-ba94744f2699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348051684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2348051684
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1962737262
Short name T348
Test name
Test status
Simulation time 196912966 ps
CPU time 1.33 seconds
Started Aug 17 06:38:01 PM PDT 24
Finished Aug 17 06:38:02 PM PDT 24
Peak memory 200736 kb
Host smart-33027bd4-8ae0-40a5-bba8-ba3d5d5a7319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962737262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1962737262
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1543355795
Short name T267
Test name
Test status
Simulation time 2476762628 ps
CPU time 12.28 seconds
Started Aug 17 06:38:31 PM PDT 24
Finished Aug 17 06:38:44 PM PDT 24
Peak memory 209052 kb
Host smart-dfb13bb8-485f-4e94-8038-878d0f58deb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543355795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1543355795
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.1291092163
Short name T382
Test name
Test status
Simulation time 494790005 ps
CPU time 2.58 seconds
Started Aug 17 06:38:14 PM PDT 24
Finished Aug 17 06:38:17 PM PDT 24
Peak memory 200612 kb
Host smart-48790593-4f7b-4793-afb8-1f769f72b37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291092163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1291092163
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.827537610
Short name T451
Test name
Test status
Simulation time 127827928 ps
CPU time 1.05 seconds
Started Aug 17 06:38:11 PM PDT 24
Finished Aug 17 06:38:12 PM PDT 24
Peak memory 200440 kb
Host smart-d8e89992-d5b6-4aec-bfde-caee2ef2fbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827537610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.827537610
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.985285885
Short name T298
Test name
Test status
Simulation time 66235185 ps
CPU time 0.76 seconds
Started Aug 17 06:38:43 PM PDT 24
Finished Aug 17 06:38:44 PM PDT 24
Peak memory 200480 kb
Host smart-eda738b2-75a4-4032-9b01-fb65a45754c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985285885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.985285885
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2367926911
Short name T362
Test name
Test status
Simulation time 2338930451 ps
CPU time 8.88 seconds
Started Aug 17 06:38:12 PM PDT 24
Finished Aug 17 06:38:22 PM PDT 24
Peak memory 218132 kb
Host smart-ba4b68fb-63e0-4344-a25a-65d45a358d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367926911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2367926911
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3488673958
Short name T494
Test name
Test status
Simulation time 244158734 ps
CPU time 1.2 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:01 PM PDT 24
Peak memory 217728 kb
Host smart-5a2cbfde-b891-4dfc-9601-204236e55b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488673958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3488673958
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1407723063
Short name T210
Test name
Test status
Simulation time 72530013 ps
CPU time 0.72 seconds
Started Aug 17 06:38:01 PM PDT 24
Finished Aug 17 06:38:02 PM PDT 24
Peak memory 200384 kb
Host smart-7fb843ad-f2e7-44c7-aee6-886bea036951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407723063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1407723063
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.589184800
Short name T150
Test name
Test status
Simulation time 1397078363 ps
CPU time 5.59 seconds
Started Aug 17 06:38:02 PM PDT 24
Finished Aug 17 06:38:08 PM PDT 24
Peak memory 200804 kb
Host smart-81949bdb-36bc-453a-9cf4-15424c61d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589184800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.589184800
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.4218452723
Short name T137
Test name
Test status
Simulation time 104822440 ps
CPU time 0.99 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200588 kb
Host smart-776dc8be-8635-4110-976a-82c6c7410627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218452723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.4218452723
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2702549191
Short name T355
Test name
Test status
Simulation time 191115748 ps
CPU time 1.41 seconds
Started Aug 17 06:38:35 PM PDT 24
Finished Aug 17 06:38:36 PM PDT 24
Peak memory 200772 kb
Host smart-7419f65b-74fa-41ab-b4d3-b138c2e586f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702549191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2702549191
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.3745980459
Short name T430
Test name
Test status
Simulation time 683410180 ps
CPU time 3.55 seconds
Started Aug 17 06:38:34 PM PDT 24
Finished Aug 17 06:38:37 PM PDT 24
Peak memory 200660 kb
Host smart-5cb88b53-6f94-449a-9bbd-051f5d9e5d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745980459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3745980459
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.61444687
Short name T415
Test name
Test status
Simulation time 387291777 ps
CPU time 2.52 seconds
Started Aug 17 06:38:39 PM PDT 24
Finished Aug 17 06:38:41 PM PDT 24
Peak memory 200528 kb
Host smart-84f73568-775f-4030-8229-614da83e2554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61444687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.61444687
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2845421160
Short name T232
Test name
Test status
Simulation time 119155657 ps
CPU time 0.99 seconds
Started Aug 17 06:38:14 PM PDT 24
Finished Aug 17 06:38:15 PM PDT 24
Peak memory 200644 kb
Host smart-704249ca-35f7-42fb-a4d3-6310c6b8384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845421160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2845421160
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.717492174
Short name T204
Test name
Test status
Simulation time 66454671 ps
CPU time 0.77 seconds
Started Aug 17 06:38:28 PM PDT 24
Finished Aug 17 06:38:29 PM PDT 24
Peak memory 200512 kb
Host smart-5d8afacb-f38d-44b6-9667-c2e52e3d2e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717492174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.717492174
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2540578827
Short name T67
Test name
Test status
Simulation time 1225083203 ps
CPU time 5.62 seconds
Started Aug 17 06:38:36 PM PDT 24
Finished Aug 17 06:38:42 PM PDT 24
Peak memory 221884 kb
Host smart-98152df1-10dd-487b-928a-9b459b44b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540578827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2540578827
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1545648371
Short name T288
Test name
Test status
Simulation time 244815393 ps
CPU time 1.09 seconds
Started Aug 17 06:38:04 PM PDT 24
Finished Aug 17 06:38:05 PM PDT 24
Peak memory 217860 kb
Host smart-fd8c2e36-8b80-4a7d-8130-6cb4ad240757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545648371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1545648371
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.3606154271
Short name T264
Test name
Test status
Simulation time 182523764 ps
CPU time 0.88 seconds
Started Aug 17 06:38:13 PM PDT 24
Finished Aug 17 06:38:14 PM PDT 24
Peak memory 200452 kb
Host smart-f07567df-16cd-43f2-9241-358d3f41522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606154271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3606154271
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.3855429001
Short name T332
Test name
Test status
Simulation time 1608136577 ps
CPU time 5.67 seconds
Started Aug 17 06:38:00 PM PDT 24
Finished Aug 17 06:38:06 PM PDT 24
Peak memory 200756 kb
Host smart-3c359c6d-da95-4db8-b2d9-4f3573a31458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855429001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3855429001
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1464485343
Short name T174
Test name
Test status
Simulation time 182981977 ps
CPU time 1.23 seconds
Started Aug 17 06:37:59 PM PDT 24
Finished Aug 17 06:38:00 PM PDT 24
Peak memory 200596 kb
Host smart-0b47f363-a99e-4dfd-93cd-759a5c2bc75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464485343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1464485343
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.756918810
Short name T350
Test name
Test status
Simulation time 253119821 ps
CPU time 1.44 seconds
Started Aug 17 06:38:21 PM PDT 24
Finished Aug 17 06:38:22 PM PDT 24
Peak memory 200800 kb
Host smart-e6a6f7b1-8450-48ad-95cf-41003378511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756918810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.756918810
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3666342920
Short name T239
Test name
Test status
Simulation time 337565985 ps
CPU time 2.06 seconds
Started Aug 17 06:38:02 PM PDT 24
Finished Aug 17 06:38:04 PM PDT 24
Peak memory 200772 kb
Host smart-1c6a92a2-d895-4cec-b803-aca530ee7ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666342920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3666342920
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3241766407
Short name T515
Test name
Test status
Simulation time 117315007 ps
CPU time 1.55 seconds
Started Aug 17 06:38:11 PM PDT 24
Finished Aug 17 06:38:12 PM PDT 24
Peak memory 200380 kb
Host smart-cdd3066f-c198-424d-a968-c1ff7ae077d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241766407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3241766407
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1594999972
Short name T505
Test name
Test status
Simulation time 182777043 ps
CPU time 1.17 seconds
Started Aug 17 06:38:09 PM PDT 24
Finished Aug 17 06:38:10 PM PDT 24
Peak memory 200644 kb
Host smart-9b162083-19d4-4ae2-983e-764b2be4288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594999972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1594999972
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2452634402
Short name T369
Test name
Test status
Simulation time 67234017 ps
CPU time 0.74 seconds
Started Aug 17 06:37:08 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 200508 kb
Host smart-06ed3dff-3c6b-43fa-9b94-248bc5cbb2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452634402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2452634402
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2254130472
Short name T190
Test name
Test status
Simulation time 2362679627 ps
CPU time 8.22 seconds
Started Aug 17 06:37:07 PM PDT 24
Finished Aug 17 06:37:15 PM PDT 24
Peak memory 221960 kb
Host smart-8bf3b127-2aca-4d2a-a4b7-9d28caa9710e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254130472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2254130472
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3674919708
Short name T172
Test name
Test status
Simulation time 244997338 ps
CPU time 1.05 seconds
Started Aug 17 06:37:00 PM PDT 24
Finished Aug 17 06:37:01 PM PDT 24
Peak memory 217860 kb
Host smart-47553a36-3e69-415c-9304-d47a4edfcc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674919708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3674919708
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.778249042
Short name T373
Test name
Test status
Simulation time 154031839 ps
CPU time 0.85 seconds
Started Aug 17 06:36:59 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 200432 kb
Host smart-709f3a6a-b54c-4bce-8cfd-4fcef6cb83e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778249042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.778249042
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.2106705376
Short name T396
Test name
Test status
Simulation time 1298787323 ps
CPU time 5.13 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 200760 kb
Host smart-d3493c2b-2d49-4bc0-87d6-51fc05f84233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106705376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2106705376
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2185308766
Short name T424
Test name
Test status
Simulation time 98447956 ps
CPU time 0.96 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:36:59 PM PDT 24
Peak memory 200624 kb
Host smart-8b85d141-59f2-4d27-b664-1cda1777eac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185308766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2185308766
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.4267196083
Short name T527
Test name
Test status
Simulation time 129703166 ps
CPU time 1.2 seconds
Started Aug 17 06:36:58 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 200656 kb
Host smart-9ba00366-de42-4aaa-9a32-212fb3766572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267196083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.4267196083
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.1989797829
Short name T12
Test name
Test status
Simulation time 3586636197 ps
CPU time 14.29 seconds
Started Aug 17 06:37:11 PM PDT 24
Finished Aug 17 06:37:25 PM PDT 24
Peak memory 209064 kb
Host smart-a7c0e11e-8cf1-4850-bba1-2cfa50875fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989797829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1989797829
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3211030981
Short name T163
Test name
Test status
Simulation time 122862696 ps
CPU time 1.62 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 208732 kb
Host smart-9f7be82f-1818-43d4-9ab6-7e1435700e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211030981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3211030981
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1941072766
Short name T166
Test name
Test status
Simulation time 77081972 ps
CPU time 0.83 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 200640 kb
Host smart-01eb669a-0f25-4159-aa67-935f6bb48275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941072766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1941072766
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.4206153665
Short name T457
Test name
Test status
Simulation time 65026992 ps
CPU time 0.74 seconds
Started Aug 17 06:37:04 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 200508 kb
Host smart-73ed60ce-e0b4-4a25-8496-e3757f7de5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206153665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4206153665
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.140363165
Short name T499
Test name
Test status
Simulation time 2344715519 ps
CPU time 8.44 seconds
Started Aug 17 06:37:13 PM PDT 24
Finished Aug 17 06:37:21 PM PDT 24
Peak memory 218040 kb
Host smart-da16167c-b6fa-481b-838a-a0ad4a40f301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140363165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.140363165
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.29308787
Short name T454
Test name
Test status
Simulation time 245873831 ps
CPU time 1.11 seconds
Started Aug 17 06:37:11 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 217816 kb
Host smart-aeacba63-16a2-47dd-afb7-f7315e8b5654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29308787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.29308787
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3242697338
Short name T476
Test name
Test status
Simulation time 130457612 ps
CPU time 0.78 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:11 PM PDT 24
Peak memory 200412 kb
Host smart-e346aadd-3e0a-47fb-af98-06c1bc57afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242697338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3242697338
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2159541952
Short name T286
Test name
Test status
Simulation time 1750291716 ps
CPU time 5.86 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:15 PM PDT 24
Peak memory 200752 kb
Host smart-077a0c51-c64a-4e0f-a1dd-f20801aee04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159541952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2159541952
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2157612508
Short name T221
Test name
Test status
Simulation time 174648791 ps
CPU time 1.16 seconds
Started Aug 17 06:37:06 PM PDT 24
Finished Aug 17 06:37:07 PM PDT 24
Peak memory 200596 kb
Host smart-d2548249-6b34-42f9-b52d-1344e67e3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157612508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2157612508
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1076991207
Short name T140
Test name
Test status
Simulation time 114243988 ps
CPU time 1.22 seconds
Started Aug 17 06:37:04 PM PDT 24
Finished Aug 17 06:37:05 PM PDT 24
Peak memory 200724 kb
Host smart-a8a532a3-ad29-4b81-81ed-f9b077589707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076991207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1076991207
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.229084839
Short name T509
Test name
Test status
Simulation time 12269042862 ps
CPU time 47.83 seconds
Started Aug 17 06:37:19 PM PDT 24
Finished Aug 17 06:38:06 PM PDT 24
Peak memory 209904 kb
Host smart-592c2440-81d6-4eb9-85cb-c6bc94a8f20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229084839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.229084839
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.1563569281
Short name T388
Test name
Test status
Simulation time 350069117 ps
CPU time 2.22 seconds
Started Aug 17 06:37:16 PM PDT 24
Finished Aug 17 06:37:18 PM PDT 24
Peak memory 200520 kb
Host smart-8aa4304d-6be5-492a-bef5-ec08d7d433f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563569281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1563569281
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3209577931
Short name T317
Test name
Test status
Simulation time 69739900 ps
CPU time 0.9 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:11 PM PDT 24
Peak memory 200592 kb
Host smart-7b1bdbee-611a-4868-a727-018d5332d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209577931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3209577931
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.860145365
Short name T245
Test name
Test status
Simulation time 65699048 ps
CPU time 0.77 seconds
Started Aug 17 06:37:06 PM PDT 24
Finished Aug 17 06:37:07 PM PDT 24
Peak memory 200360 kb
Host smart-b9d3df56-b5fb-4e76-b35a-af71a300eba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860145365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.860145365
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.1085371154
Short name T185
Test name
Test status
Simulation time 2357303156 ps
CPU time 7.88 seconds
Started Aug 17 06:37:06 PM PDT 24
Finished Aug 17 06:37:14 PM PDT 24
Peak memory 218024 kb
Host smart-1fc0f714-4bda-4bb9-b2af-75bbbb1af938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085371154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1085371154
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3945257293
Short name T258
Test name
Test status
Simulation time 245415310 ps
CPU time 1.09 seconds
Started Aug 17 06:37:03 PM PDT 24
Finished Aug 17 06:37:04 PM PDT 24
Peak memory 217772 kb
Host smart-7da35d82-8abd-41e7-831c-d02441e2cfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945257293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3945257293
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.1847846225
Short name T259
Test name
Test status
Simulation time 94246686 ps
CPU time 0.77 seconds
Started Aug 17 06:37:16 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 200400 kb
Host smart-216d51ca-3305-4984-bf62-57d1d1c97eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847846225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.1847846225
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.1150102318
Short name T225
Test name
Test status
Simulation time 801405867 ps
CPU time 4.6 seconds
Started Aug 17 06:37:12 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 200768 kb
Host smart-a32cada6-a41b-4e0c-8950-9e59c2a159f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150102318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1150102318
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.714579114
Short name T211
Test name
Test status
Simulation time 147987242 ps
CPU time 1.13 seconds
Started Aug 17 06:37:07 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 200576 kb
Host smart-bacc94f4-c225-44a1-8120-49efed0e714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714579114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.714579114
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3187244535
Short name T301
Test name
Test status
Simulation time 111618585 ps
CPU time 1.14 seconds
Started Aug 17 06:37:18 PM PDT 24
Finished Aug 17 06:37:20 PM PDT 24
Peak memory 200744 kb
Host smart-dd0ebbf0-f649-46b6-b911-95e4bfde0536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187244535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3187244535
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2114961334
Short name T427
Test name
Test status
Simulation time 4715231532 ps
CPU time 18.46 seconds
Started Aug 17 06:37:11 PM PDT 24
Finished Aug 17 06:37:30 PM PDT 24
Peak memory 209060 kb
Host smart-9668c140-90dc-4f9b-8a26-b24f230adbff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114961334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2114961334
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.2352562060
Short name T466
Test name
Test status
Simulation time 455779590 ps
CPU time 2.55 seconds
Started Aug 17 06:37:17 PM PDT 24
Finished Aug 17 06:37:19 PM PDT 24
Peak memory 200500 kb
Host smart-c6be6327-a7da-4939-8aaa-9dbf586d9c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352562060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.2352562060
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2887859003
Short name T338
Test name
Test status
Simulation time 260067584 ps
CPU time 1.37 seconds
Started Aug 17 06:37:07 PM PDT 24
Finished Aug 17 06:37:09 PM PDT 24
Peak memory 200572 kb
Host smart-07e5006d-3fd6-49cf-bc0e-b223c4585c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887859003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2887859003
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.1093661959
Short name T28
Test name
Test status
Simulation time 79706308 ps
CPU time 0.79 seconds
Started Aug 17 06:37:11 PM PDT 24
Finished Aug 17 06:37:12 PM PDT 24
Peak memory 200504 kb
Host smart-6f7f32eb-44b8-4ce6-961b-b8bdf87b7fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093661959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1093661959
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1836895643
Short name T227
Test name
Test status
Simulation time 244483043 ps
CPU time 1.11 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:11 PM PDT 24
Peak memory 217660 kb
Host smart-e6d1812f-c29a-455e-a99c-8daa337e80fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836895643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1836895643
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1173706233
Short name T409
Test name
Test status
Simulation time 97280364 ps
CPU time 0.76 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:11 PM PDT 24
Peak memory 200472 kb
Host smart-5ad1ef47-7492-4ebb-938c-b20299cdd61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173706233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1173706233
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2560494309
Short name T181
Test name
Test status
Simulation time 745909324 ps
CPU time 3.84 seconds
Started Aug 17 06:37:10 PM PDT 24
Finished Aug 17 06:37:14 PM PDT 24
Peak memory 200744 kb
Host smart-17174b34-5100-49cf-8922-1f8d9b6241d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560494309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2560494309
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1014522326
Short name T41
Test name
Test status
Simulation time 181950762 ps
CPU time 1.18 seconds
Started Aug 17 06:37:15 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 200652 kb
Host smart-eebe26ed-ed3f-4775-92e6-3572dc898b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014522326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1014522326
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.497224826
Short name T310
Test name
Test status
Simulation time 194245736 ps
CPU time 1.33 seconds
Started Aug 17 06:37:08 PM PDT 24
Finished Aug 17 06:37:10 PM PDT 24
Peak memory 200784 kb
Host smart-4db40e3e-5e1b-4b67-9c6c-96eab4310b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497224826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.497224826
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.882174637
Short name T520
Test name
Test status
Simulation time 14499944157 ps
CPU time 48.69 seconds
Started Aug 17 06:37:16 PM PDT 24
Finished Aug 17 06:38:05 PM PDT 24
Peak memory 209112 kb
Host smart-ef3073d2-d462-40bd-aacf-8b2ca649f3e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882174637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.882174637
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.367153884
Short name T485
Test name
Test status
Simulation time 507452718 ps
CPU time 2.72 seconds
Started Aug 17 06:37:14 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 200568 kb
Host smart-766f3e15-e1c3-4250-a520-c3d58b98c88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367153884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.367153884
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3168733493
Short name T530
Test name
Test status
Simulation time 159082318 ps
CPU time 1.26 seconds
Started Aug 17 06:37:14 PM PDT 24
Finished Aug 17 06:37:15 PM PDT 24
Peak memory 200792 kb
Host smart-8054ca67-1eff-4ee7-b1a0-ad95185de96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168733493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3168733493
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1224840508
Short name T167
Test name
Test status
Simulation time 80900227 ps
CPU time 0.83 seconds
Started Aug 17 06:37:16 PM PDT 24
Finished Aug 17 06:37:17 PM PDT 24
Peak memory 200476 kb
Host smart-a023f791-d938-4bfa-86c9-0ca3fd5f45a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224840508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1224840508
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.3548969266
Short name T446
Test name
Test status
Simulation time 1228950286 ps
CPU time 5.08 seconds
Started Aug 17 06:37:18 PM PDT 24
Finished Aug 17 06:37:23 PM PDT 24
Peak memory 217972 kb
Host smart-c824a93d-8e80-49d0-8040-3750dae654ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548969266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3548969266
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.807039486
Short name T538
Test name
Test status
Simulation time 243948878 ps
CPU time 1.08 seconds
Started Aug 17 06:37:05 PM PDT 24
Finished Aug 17 06:37:06 PM PDT 24
Peak memory 217884 kb
Host smart-6d5fc5e0-15ea-40ac-bbf9-4dc748a66984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807039486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.807039486
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2670559130
Short name T385
Test name
Test status
Simulation time 212482034 ps
CPU time 0.92 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:10 PM PDT 24
Peak memory 200404 kb
Host smart-c376f160-d7ae-4171-ba5a-c907adc971b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670559130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2670559130
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.3308623213
Short name T265
Test name
Test status
Simulation time 826127209 ps
CPU time 3.97 seconds
Started Aug 17 06:37:17 PM PDT 24
Finished Aug 17 06:37:21 PM PDT 24
Peak memory 200616 kb
Host smart-1a35a0e3-98f0-4aac-a16a-f5e2c3fca976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308623213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3308623213
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.654737545
Short name T487
Test name
Test status
Simulation time 157999270 ps
CPU time 1.17 seconds
Started Aug 17 06:37:06 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 200660 kb
Host smart-18817da0-c280-48c2-b970-65a3c523437e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654737545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.654737545
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.52147745
Short name T276
Test name
Test status
Simulation time 113281718 ps
CPU time 1.23 seconds
Started Aug 17 06:37:07 PM PDT 24
Finished Aug 17 06:37:08 PM PDT 24
Peak memory 200724 kb
Host smart-22f010f6-2ded-4147-bdab-216d598c26e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52147745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.52147745
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1824125512
Short name T187
Test name
Test status
Simulation time 2545221245 ps
CPU time 10.31 seconds
Started Aug 17 06:37:12 PM PDT 24
Finished Aug 17 06:37:22 PM PDT 24
Peak memory 200796 kb
Host smart-37e4da1c-f3da-4fc4-af69-1877ea90d4e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824125512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1824125512
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2364250611
Short name T285
Test name
Test status
Simulation time 106987517 ps
CPU time 1.48 seconds
Started Aug 17 06:37:09 PM PDT 24
Finished Aug 17 06:37:11 PM PDT 24
Peak memory 200484 kb
Host smart-f0cd8247-f3c6-4e45-a756-d0b296e6c29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364250611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2364250611
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.977868424
Short name T532
Test name
Test status
Simulation time 90035205 ps
CPU time 0.81 seconds
Started Aug 17 06:37:06 PM PDT 24
Finished Aug 17 06:37:07 PM PDT 24
Peak memory 200600 kb
Host smart-d9e9cb13-9450-4319-8823-eb9b1f43a1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977868424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.977868424
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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