Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8667

1

T1

180

T2

28

T3

32

auto[1]

11498

1

T1

189

T2

22

T3

24

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6189	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6821	1			T1	115		T2	16		T3	19
reset_info_cp[2]	3060	1			T1	56		T2	7		T3	10
reset_info_cp[4]	4137	1			T1	90		T2	11		T3	11
reset_info_cp[8]	113	1			T1	2		T5	1		T23	2
reset_info_cp[16]	110	1			T1	3		T3	2		T7	2
reset_info_cp[32]	129	1			T1	1		T5	1		T7	1
reset_info_cp[64]	104	1			T2	1		T3	1		T5	1
reset_info_cp[128]	122	1			T1	1		T2	1		T9	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3286	1			T1	50		T2	7		T3	11
reset_info_cp[1]	auto[1]	2915	1			T1	64		T2	8		T3	7
reset_info_cp[2]	auto[0]	991	1			T1	21		T2	5		T3	3
reset_info_cp[2]	auto[1]	2069	1			T1	35		T2	2		T3	7
reset_info_cp[4]	auto[0]	1476	1			T1	46		T2	6		T3	7
reset_info_cp[4]	auto[1]	2661	1			T1	44		T2	5		T3	4
reset_info_cp[8]	auto[0]	35	1			T1	2		T34	4		T73	1
reset_info_cp[8]	auto[1]	78	1			T5	1		T23	2		T34	1
reset_info_cp[16]	auto[0]	41	1			T3	1		T7	2		T9	1
reset_info_cp[16]	auto[1]	69	1			T1	3		T3	1		T23	1
reset_info_cp[32]	auto[0]	55	1			T1	1		T5	1		T7	1
reset_info_cp[32]	auto[1]	74	1			T11	1		T72	1		T76	1
reset_info_cp[64]	auto[0]	38	1			T2	1		T3	1		T75	3
reset_info_cp[64]	auto[1]	66	1			T5	1		T11	2		T23	4
reset_info_cp[128]	auto[0]	55	1			T1	1		T9	1		T72	1
reset_info_cp[128]	auto[1]	67	1			T2	1		T34	1		T73	2