Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
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T536 /workspace/coverage/default/33.rstmgr_por_stretcher.3427805944 Aug 18 05:26:09 PM PDT 24 Aug 18 05:26:10 PM PDT 24 237996936 ps
T537 /workspace/coverage/default/13.rstmgr_smoke.1579221316 Aug 18 05:25:22 PM PDT 24 Aug 18 05:25:24 PM PDT 24 248990797 ps
T538 /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2483112224 Aug 18 05:25:30 PM PDT 24 Aug 18 05:25:31 PM PDT 24 106942121 ps
T539 /workspace/coverage/default/26.rstmgr_stress_all.71846422 Aug 18 05:25:50 PM PDT 24 Aug 18 05:26:13 PM PDT 24 6087492716 ps
T540 /workspace/coverage/default/41.rstmgr_stress_all.2493582932 Aug 18 05:26:19 PM PDT 24 Aug 18 05:26:45 PM PDT 24 7739928567 ps
T52 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4083753372 Aug 18 05:47:37 PM PDT 24 Aug 18 05:47:38 PM PDT 24 205539961 ps
T53 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1643579686 Aug 18 05:47:45 PM PDT 24 Aug 18 05:47:46 PM PDT 24 62529958 ps
T54 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3256503006 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:49 PM PDT 24 889754392 ps
T55 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3107176489 Aug 18 05:47:57 PM PDT 24 Aug 18 05:47:59 PM PDT 24 416158393 ps
T56 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.625817799 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:55 PM PDT 24 214236188 ps
T86 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1474827931 Aug 18 05:47:42 PM PDT 24 Aug 18 05:47:43 PM PDT 24 135491579 ps
T57 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2783282790 Aug 18 05:47:34 PM PDT 24 Aug 18 05:47:36 PM PDT 24 113700790 ps
T58 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.798257603 Aug 18 05:47:34 PM PDT 24 Aug 18 05:47:37 PM PDT 24 298826762 ps
T87 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4238006278 Aug 18 05:47:55 PM PDT 24 Aug 18 05:47:56 PM PDT 24 140988317 ps
T77 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3965250996 Aug 18 05:47:52 PM PDT 24 Aug 18 05:47:55 PM PDT 24 161080313 ps
T63 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.322519831 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:56 PM PDT 24 937657717 ps
T541 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1669229230 Aug 18 05:47:34 PM PDT 24 Aug 18 05:47:40 PM PDT 24 487317103 ps
T78 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2182410477 Aug 18 05:47:33 PM PDT 24 Aug 18 05:47:35 PM PDT 24 189164061 ps
T79 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1735872297 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:48 PM PDT 24 194451881 ps
T88 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2155793769 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:56 PM PDT 24 148319298 ps
T80 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.878559098 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:44 PM PDT 24 110950014 ps
T89 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4152425283 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:44 PM PDT 24 81530683 ps
T542 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.713412423 Aug 18 05:47:36 PM PDT 24 Aug 18 05:47:37 PM PDT 24 69456728 ps
T543 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1447373051 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:54 PM PDT 24 68155956 ps
T90 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2585852088 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:55 PM PDT 24 60992157 ps
T91 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3477045570 Aug 18 05:47:41 PM PDT 24 Aug 18 05:47:43 PM PDT 24 119411208 ps
T92 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.58234504 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:55 PM PDT 24 124318561 ps
T81 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1079791216 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:45 PM PDT 24 116532460 ps
T100 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3992432239 Aug 18 05:47:42 PM PDT 24 Aug 18 05:47:44 PM PDT 24 408289905 ps
T82 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3498448508 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:58 PM PDT 24 919243283 ps
T544 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2207932485 Aug 18 05:47:57 PM PDT 24 Aug 18 05:47:58 PM PDT 24 83482761 ps
T93 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1658938019 Aug 18 05:47:57 PM PDT 24 Aug 18 05:47:59 PM PDT 24 129982464 ps
T102 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4214010319 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:56 PM PDT 24 203610582 ps
T545 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1090113216 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:47 PM PDT 24 182205757 ps
T96 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.511030437 Aug 18 05:47:41 PM PDT 24 Aug 18 05:47:45 PM PDT 24 449111336 ps
T546 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2136078221 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:54 PM PDT 24 82397446 ps
T547 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1399748296 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:44 PM PDT 24 128157935 ps
T97 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3102887686 Aug 18 05:47:35 PM PDT 24 Aug 18 05:47:37 PM PDT 24 529002665 ps
T548 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1001543476 Aug 18 05:47:35 PM PDT 24 Aug 18 05:47:43 PM PDT 24 2030380384 ps
T549 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2302986640 Aug 18 05:47:59 PM PDT 24 Aug 18 05:48:01 PM PDT 24 178075531 ps
T94 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.893478135 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:55 PM PDT 24 95495688 ps
T550 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4268705282 Aug 18 05:47:39 PM PDT 24 Aug 18 05:47:40 PM PDT 24 77240846 ps
T98 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2549172787 Aug 18 05:47:42 PM PDT 24 Aug 18 05:47:45 PM PDT 24 431942338 ps
T95 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2114808463 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:45 PM PDT 24 86832295 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.967494480 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:45 PM PDT 24 498617055 ps
T552 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.561479741 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:55 PM PDT 24 73785078 ps
T103 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1478215846 Aug 18 05:47:57 PM PDT 24 Aug 18 05:48:00 PM PDT 24 422411017 ps
T553 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.199737867 Aug 18 05:47:33 PM PDT 24 Aug 18 05:47:35 PM PDT 24 184367416 ps
T554 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3983265685 Aug 18 05:47:34 PM PDT 24 Aug 18 05:47:36 PM PDT 24 524865906 ps
T555 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2280291512 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:47 PM PDT 24 64665100 ps
T556 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3637854898 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:56 PM PDT 24 208899698 ps
T101 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.247476340 Aug 18 05:47:55 PM PDT 24 Aug 18 05:47:58 PM PDT 24 202538795 ps
T557 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.505136485 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:46 PM PDT 24 509695454 ps
T558 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4194030156 Aug 18 05:47:34 PM PDT 24 Aug 18 05:47:36 PM PDT 24 505946391 ps
T559 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1956242467 Aug 18 05:47:59 PM PDT 24 Aug 18 05:48:02 PM PDT 24 453363017 ps
T560 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2346426880 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:47 PM PDT 24 182249694 ps
T561 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1668167320 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:54 PM PDT 24 275034126 ps
T562 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2922496990 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:45 PM PDT 24 81873362 ps
T563 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3265485909 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:45 PM PDT 24 196449100 ps
T564 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1265119624 Aug 18 05:47:37 PM PDT 24 Aug 18 05:47:38 PM PDT 24 219064868 ps
T565 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1384437609 Aug 18 05:47:36 PM PDT 24 Aug 18 05:47:37 PM PDT 24 136563579 ps
T566 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1381118729 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:46 PM PDT 24 324289157 ps
T113 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1548064546 Aug 18 05:47:56 PM PDT 24 Aug 18 05:47:58 PM PDT 24 469114687 ps
T99 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3055416602 Aug 18 05:47:54 PM PDT 24 Aug 18 05:47:57 PM PDT 24 772287754 ps
T567 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.186982994 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:44 PM PDT 24 134484836 ps
T568 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3061012648 Aug 18 05:47:42 PM PDT 24 Aug 18 05:47:44 PM PDT 24 221369661 ps
T569 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4258224700 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:44 PM PDT 24 71830828 ps
T570 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4213685739 Aug 18 05:47:41 PM PDT 24 Aug 18 05:47:43 PM PDT 24 211992800 ps
T571 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3603630916 Aug 18 05:47:34 PM PDT 24 Aug 18 05:47:36 PM PDT 24 485404698 ps
T572 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2724575469 Aug 18 05:48:04 PM PDT 24 Aug 18 05:48:06 PM PDT 24 174951574 ps
T573 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2588351993 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:44 PM PDT 24 65907858 ps
T574 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3082129593 Aug 18 05:47:55 PM PDT 24 Aug 18 05:47:58 PM PDT 24 448280693 ps
T115 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3515555748 Aug 18 05:47:52 PM PDT 24 Aug 18 05:47:56 PM PDT 24 1307003858 ps
T575 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4037307322 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:46 PM PDT 24 120903203 ps
T576 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.273665033 Aug 18 05:47:42 PM PDT 24 Aug 18 05:47:43 PM PDT 24 74233781 ps
T577 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2511227022 Aug 18 05:47:41 PM PDT 24 Aug 18 05:47:42 PM PDT 24 54540617 ps
T578 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3688899230 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:46 PM PDT 24 428815894 ps
T579 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1273020202 Aug 18 05:47:56 PM PDT 24 Aug 18 05:47:59 PM PDT 24 419193421 ps
T580 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3734263185 Aug 18 05:47:36 PM PDT 24 Aug 18 05:47:38 PM PDT 24 211690422 ps
T581 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3081897973 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:46 PM PDT 24 131940547 ps
T582 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3342286244 Aug 18 05:47:35 PM PDT 24 Aug 18 05:47:36 PM PDT 24 103482060 ps
T583 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3356685472 Aug 18 05:47:48 PM PDT 24 Aug 18 05:47:51 PM PDT 24 884578505 ps
T584 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4079144916 Aug 18 05:47:42 PM PDT 24 Aug 18 05:47:43 PM PDT 24 118208368 ps
T585 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.521684796 Aug 18 05:47:35 PM PDT 24 Aug 18 05:47:36 PM PDT 24 128571631 ps
T586 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1668529066 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:55 PM PDT 24 162195982 ps
T587 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3984032028 Aug 18 05:47:52 PM PDT 24 Aug 18 05:47:53 PM PDT 24 108658409 ps
T588 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1945120648 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:48 PM PDT 24 203407779 ps
T589 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3412854523 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:46 PM PDT 24 204244285 ps
T590 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1579712293 Aug 18 05:47:35 PM PDT 24 Aug 18 05:47:37 PM PDT 24 117941402 ps
T591 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2740967157 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:46 PM PDT 24 425828065 ps
T592 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1522104291 Aug 18 05:47:55 PM PDT 24 Aug 18 05:47:57 PM PDT 24 103864453 ps
T593 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2878120971 Aug 18 05:47:45 PM PDT 24 Aug 18 05:47:46 PM PDT 24 113484278 ps
T594 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2079708680 Aug 18 05:47:52 PM PDT 24 Aug 18 05:47:54 PM PDT 24 137538080 ps
T595 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3802319394 Aug 18 05:47:49 PM PDT 24 Aug 18 05:47:50 PM PDT 24 78691828 ps
T596 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3575477214 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:49 PM PDT 24 875653649 ps
T597 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.774917433 Aug 18 05:47:55 PM PDT 24 Aug 18 05:47:56 PM PDT 24 69070656 ps
T598 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4095696520 Aug 18 05:47:55 PM PDT 24 Aug 18 05:47:57 PM PDT 24 401400906 ps
T599 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3593763109 Aug 18 05:47:36 PM PDT 24 Aug 18 05:47:37 PM PDT 24 88444724 ps
T600 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.580639335 Aug 18 05:47:52 PM PDT 24 Aug 18 05:47:54 PM PDT 24 125778008 ps
T601 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1396714799 Aug 18 05:47:41 PM PDT 24 Aug 18 05:47:45 PM PDT 24 481151387 ps
T114 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.755449179 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:49 PM PDT 24 779291753 ps
T602 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4101909019 Aug 18 05:47:35 PM PDT 24 Aug 18 05:47:37 PM PDT 24 118490848 ps
T603 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3992140977 Aug 18 05:47:48 PM PDT 24 Aug 18 05:47:49 PM PDT 24 89856330 ps
T604 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.160773818 Aug 18 05:47:43 PM PDT 24 Aug 18 05:47:45 PM PDT 24 212623423 ps
T605 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.934008519 Aug 18 05:47:37 PM PDT 24 Aug 18 05:47:38 PM PDT 24 103449227 ps
T606 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3322564865 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:54 PM PDT 24 101905400 ps
T607 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3140610898 Aug 18 05:47:59 PM PDT 24 Aug 18 05:48:01 PM PDT 24 255083403 ps
T608 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2527426600 Aug 18 05:47:46 PM PDT 24 Aug 18 05:47:51 PM PDT 24 808197095 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.846974166 Aug 18 05:47:42 PM PDT 24 Aug 18 05:47:48 PM PDT 24 493211392 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.327276013 Aug 18 05:47:41 PM PDT 24 Aug 18 05:47:42 PM PDT 24 74781308 ps
T611 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.673794618 Aug 18 05:47:59 PM PDT 24 Aug 18 05:48:02 PM PDT 24 955074679 ps
T612 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4073040089 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:45 PM PDT 24 124574125 ps
T613 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2032389831 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:54 PM PDT 24 70032476 ps
T614 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.243571565 Aug 18 05:47:55 PM PDT 24 Aug 18 05:47:58 PM PDT 24 487195402 ps
T615 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3313187685 Aug 18 05:47:39 PM PDT 24 Aug 18 05:47:40 PM PDT 24 238654391 ps
T616 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1193660584 Aug 18 05:47:34 PM PDT 24 Aug 18 05:47:37 PM PDT 24 267030961 ps
T617 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1519157032 Aug 18 05:47:42 PM PDT 24 Aug 18 05:47:45 PM PDT 24 427192766 ps
T618 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3348074083 Aug 18 05:47:51 PM PDT 24 Aug 18 05:47:52 PM PDT 24 188995508 ps
T619 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.116446200 Aug 18 05:47:44 PM PDT 24 Aug 18 05:47:45 PM PDT 24 63699826 ps
T620 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1552710583 Aug 18 05:47:55 PM PDT 24 Aug 18 05:47:56 PM PDT 24 58410903 ps

Test location /workspace/coverage/default/9.rstmgr_stress_all.368284563
Short name T1
Test name
Test status
Simulation time 12727085039 ps
CPU time 44.2 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:57 PM PDT 24
Peak memory 200748 kb
Host smart-bcf48488-f9fc-45cb-9092-003187c882ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368284563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.368284563
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2155443052
Short name T50
Test name
Test status
Simulation time 259834246 ps
CPU time 1.77 seconds
Started Aug 18 05:25:56 PM PDT 24
Finished Aug 18 05:25:58 PM PDT 24
Peak memory 200520 kb
Host smart-202db1c8-044c-4af2-a3d5-6457db499308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155443052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2155443052
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3256503006
Short name T54
Test name
Test status
Simulation time 889754392 ps
CPU time 3.24 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:49 PM PDT 24
Peak memory 200916 kb
Host smart-39d8741c-db72-400f-bb4d-e3e69cd77843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256503006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3256503006
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.1093152478
Short name T59
Test name
Test status
Simulation time 8276010884 ps
CPU time 15.32 seconds
Started Aug 18 05:24:44 PM PDT 24
Finished Aug 18 05:24:59 PM PDT 24
Peak memory 217744 kb
Host smart-4b550b9f-559c-4279-b30d-f0a0022d3614
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093152478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1093152478
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.2419093414
Short name T23
Test name
Test status
Simulation time 1228459630 ps
CPU time 5.61 seconds
Started Aug 18 05:25:01 PM PDT 24
Finished Aug 18 05:25:07 PM PDT 24
Peak memory 220928 kb
Host smart-78d70b45-b26e-40f3-8329-271cfd381692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419093414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2419093414
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3965250996
Short name T77
Test name
Test status
Simulation time 161080313 ps
CPU time 2.38 seconds
Started Aug 18 05:47:52 PM PDT 24
Finished Aug 18 05:47:55 PM PDT 24
Peak memory 212884 kb
Host smart-ab5590df-13f8-4bb1-bd41-c5046a3c6467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965250996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3965250996
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.3774956983
Short name T42
Test name
Test status
Simulation time 1894968437 ps
CPU time 7.96 seconds
Started Aug 18 05:26:26 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 217472 kb
Host smart-d8bc685b-df4f-4a93-a06f-ba6d491754aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774956983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.3774956983
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.1199086349
Short name T117
Test name
Test status
Simulation time 218490559 ps
CPU time 1.35 seconds
Started Aug 18 05:25:30 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 200584 kb
Host smart-0cc3e055-4b43-481d-a566-8a4a00e37d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199086349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1199086349
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.438380644
Short name T130
Test name
Test status
Simulation time 171951356 ps
CPU time 1.22 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:23 PM PDT 24
Peak memory 200624 kb
Host smart-9b024ee4-51f7-4cb1-b181-130e8768167e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438380644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.438380644
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.2578944549
Short name T62
Test name
Test status
Simulation time 87396853 ps
CPU time 0.77 seconds
Started Aug 18 05:24:44 PM PDT 24
Finished Aug 18 05:24:45 PM PDT 24
Peak memory 200396 kb
Host smart-003b558f-8bcd-4244-ac96-1cc99855cccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578944549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2578944549
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1548064546
Short name T113
Test name
Test status
Simulation time 469114687 ps
CPU time 1.84 seconds
Started Aug 18 05:47:56 PM PDT 24
Finished Aug 18 05:47:58 PM PDT 24
Peak memory 200964 kb
Host smart-76d36704-2391-4242-97b4-a279e960134d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548064546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.1548064546
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.4289526885
Short name T85
Test name
Test status
Simulation time 5463955634 ps
CPU time 23.78 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:57 PM PDT 24
Peak memory 200856 kb
Host smart-e335948b-ff92-4785-9835-7b657286d6cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289526885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4289526885
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3102887686
Short name T97
Test name
Test status
Simulation time 529002665 ps
CPU time 1.99 seconds
Started Aug 18 05:47:35 PM PDT 24
Finished Aug 18 05:47:37 PM PDT 24
Peak memory 201072 kb
Host smart-c866fa4d-0d94-41b4-a120-f0102f7fa165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102887686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.3102887686
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3477045570
Short name T91
Test name
Test status
Simulation time 119411208 ps
CPU time 1.07 seconds
Started Aug 18 05:47:41 PM PDT 24
Finished Aug 18 05:47:43 PM PDT 24
Peak memory 200832 kb
Host smart-f8852e04-e1da-46ec-b856-f744582b86ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477045570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3477045570
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3898336362
Short name T19
Test name
Test status
Simulation time 178611518 ps
CPU time 0.87 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200436 kb
Host smart-ce353178-2a00-422c-8d48-16d78363073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898336362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3898336362
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.798257603
Short name T58
Test name
Test status
Simulation time 298826762 ps
CPU time 2.1 seconds
Started Aug 18 05:47:34 PM PDT 24
Finished Aug 18 05:47:37 PM PDT 24
Peak memory 209128 kb
Host smart-cf5446aa-68da-4b27-9d0c-dff3b7e89b12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798257603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.798257603
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4083753372
Short name T52
Test name
Test status
Simulation time 205539961 ps
CPU time 1.56 seconds
Started Aug 18 05:47:37 PM PDT 24
Finished Aug 18 05:47:38 PM PDT 24
Peak memory 200880 kb
Host smart-e5406619-eccb-496c-9fb6-06e496237c5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083753372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
083753372
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1193660584
Short name T616
Test name
Test status
Simulation time 267030961 ps
CPU time 3.09 seconds
Started Aug 18 05:47:34 PM PDT 24
Finished Aug 18 05:47:37 PM PDT 24
Peak memory 201004 kb
Host smart-dc47c426-3b8a-4c1c-99d6-90846698dd89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193660584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1
193660584
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3342286244
Short name T582
Test name
Test status
Simulation time 103482060 ps
CPU time 0.82 seconds
Started Aug 18 05:47:35 PM PDT 24
Finished Aug 18 05:47:36 PM PDT 24
Peak memory 200948 kb
Host smart-102e3da5-7ffe-49dc-af24-1c901fc65080
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342286244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3
342286244
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.199737867
Short name T553
Test name
Test status
Simulation time 184367416 ps
CPU time 1.71 seconds
Started Aug 18 05:47:33 PM PDT 24
Finished Aug 18 05:47:35 PM PDT 24
Peak memory 209164 kb
Host smart-90f9f0ee-4be6-4ed6-8ad3-629b5a67a010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199737867 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.199737867
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.713412423
Short name T542
Test name
Test status
Simulation time 69456728 ps
CPU time 0.76 seconds
Started Aug 18 05:47:36 PM PDT 24
Finished Aug 18 05:47:37 PM PDT 24
Peak memory 200740 kb
Host smart-db0e1754-dce6-49f9-9aee-35b7828c1d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713412423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.713412423
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.4213685739
Short name T570
Test name
Test status
Simulation time 211992800 ps
CPU time 1.39 seconds
Started Aug 18 05:47:41 PM PDT 24
Finished Aug 18 05:47:43 PM PDT 24
Peak memory 201008 kb
Host smart-f14c1c2e-0f30-4cef-87c0-46be85fa4f7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213685739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.4213685739
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.2783282790
Short name T57
Test name
Test status
Simulation time 113700790 ps
CPU time 1.66 seconds
Started Aug 18 05:47:34 PM PDT 24
Finished Aug 18 05:47:36 PM PDT 24
Peak memory 211860 kb
Host smart-46774420-127e-4a06-bbbf-e5d151918c61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783282790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2783282790
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4194030156
Short name T558
Test name
Test status
Simulation time 505946391 ps
CPU time 2.02 seconds
Started Aug 18 05:47:34 PM PDT 24
Finished Aug 18 05:47:36 PM PDT 24
Peak memory 200968 kb
Host smart-ada386b8-341c-47bc-b71c-4fc6437d10d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194030156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.4194030156
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3734263185
Short name T580
Test name
Test status
Simulation time 211690422 ps
CPU time 1.61 seconds
Started Aug 18 05:47:36 PM PDT 24
Finished Aug 18 05:47:38 PM PDT 24
Peak memory 200956 kb
Host smart-012cc7ee-62ad-4a41-903e-7b986a8db5b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734263185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3
734263185
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1669229230
Short name T541
Test name
Test status
Simulation time 487317103 ps
CPU time 5.88 seconds
Started Aug 18 05:47:34 PM PDT 24
Finished Aug 18 05:47:40 PM PDT 24
Peak memory 200996 kb
Host smart-bd67bd4f-dad2-406b-9488-db524ecd50be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669229230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1
669229230
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.934008519
Short name T605
Test name
Test status
Simulation time 103449227 ps
CPU time 0.83 seconds
Started Aug 18 05:47:37 PM PDT 24
Finished Aug 18 05:47:38 PM PDT 24
Peak memory 200772 kb
Host smart-a7d445ea-eccb-4a66-90e1-83180784752f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934008519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.934008519
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2182410477
Short name T78
Test name
Test status
Simulation time 189164061 ps
CPU time 1.85 seconds
Started Aug 18 05:47:33 PM PDT 24
Finished Aug 18 05:47:35 PM PDT 24
Peak memory 209280 kb
Host smart-700b1894-ab01-4951-a886-2f76658f3220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182410477 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2182410477
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.2511227022
Short name T577
Test name
Test status
Simulation time 54540617 ps
CPU time 0.74 seconds
Started Aug 18 05:47:41 PM PDT 24
Finished Aug 18 05:47:42 PM PDT 24
Peak memory 200768 kb
Host smart-6af2ff52-13e5-4aa3-a489-458b90fe129d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511227022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2511227022
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1384437609
Short name T565
Test name
Test status
Simulation time 136563579 ps
CPU time 1.11 seconds
Started Aug 18 05:47:36 PM PDT 24
Finished Aug 18 05:47:37 PM PDT 24
Peak memory 200868 kb
Host smart-573b04ca-79cd-4ab8-ab26-7b52476cd9a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384437609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.1384437609
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2878120971
Short name T593
Test name
Test status
Simulation time 113484278 ps
CPU time 0.98 seconds
Started Aug 18 05:47:45 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 200928 kb
Host smart-2d49bc23-67ef-4f3c-bc70-f56269f37a7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878120971 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.2878120971
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2922496990
Short name T562
Test name
Test status
Simulation time 81873362 ps
CPU time 0.9 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 200732 kb
Host smart-115bb43a-c668-41d6-a0a6-9a1031d3b2fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922496990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2922496990
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.3081897973
Short name T581
Test name
Test status
Simulation time 131940547 ps
CPU time 1.83 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 209196 kb
Host smart-482e0f15-942e-44f2-98e6-ea34c77d948e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081897973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3081897973
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.505136485
Short name T557
Test name
Test status
Simulation time 509695454 ps
CPU time 2.11 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 201020 kb
Host smart-4cc4ecc1-21f1-4241-a825-ae57ee63828f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505136485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err
.505136485
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3984032028
Short name T587
Test name
Test status
Simulation time 108658409 ps
CPU time 0.9 seconds
Started Aug 18 05:47:52 PM PDT 24
Finished Aug 18 05:47:53 PM PDT 24
Peak memory 200928 kb
Host smart-8120fe30-22e0-4196-8334-1284d3f7f650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984032028 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.3984032028
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2280291512
Short name T555
Test name
Test status
Simulation time 64665100 ps
CPU time 0.82 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:47 PM PDT 24
Peak memory 200788 kb
Host smart-3eba264d-b850-4633-aaf0-79564dfa5584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280291512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2280291512
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2079708680
Short name T594
Test name
Test status
Simulation time 137538080 ps
CPU time 1.11 seconds
Started Aug 18 05:47:52 PM PDT 24
Finished Aug 18 05:47:54 PM PDT 24
Peak memory 200848 kb
Host smart-503c8e3d-e705-4619-b73d-e0f9d96bf6c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079708680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2079708680
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.511030437
Short name T96
Test name
Test status
Simulation time 449111336 ps
CPU time 3.17 seconds
Started Aug 18 05:47:41 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 209196 kb
Host smart-e517c3d4-6f96-49d8-a855-54f50a17de5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511030437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.511030437
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3356685472
Short name T583
Test name
Test status
Simulation time 884578505 ps
CPU time 3.01 seconds
Started Aug 18 05:47:48 PM PDT 24
Finished Aug 18 05:47:51 PM PDT 24
Peak memory 201004 kb
Host smart-36a21ed0-7df4-4c0d-8af0-e3175f5f42f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356685472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.3356685472
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.580639335
Short name T600
Test name
Test status
Simulation time 125778008 ps
CPU time 0.97 seconds
Started Aug 18 05:47:52 PM PDT 24
Finished Aug 18 05:47:54 PM PDT 24
Peak memory 200816 kb
Host smart-7b3cee51-e109-48a0-a368-2ee82092cd20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580639335 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.580639335
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.2585852088
Short name T90
Test name
Test status
Simulation time 60992157 ps
CPU time 0.78 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:55 PM PDT 24
Peak memory 200780 kb
Host smart-88f4c5bf-5fb7-42bd-ad1d-9604ec7c8f43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585852088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2585852088
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1522104291
Short name T592
Test name
Test status
Simulation time 103864453 ps
CPU time 1.33 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:57 PM PDT 24
Peak memory 200920 kb
Host smart-97c190ba-1f42-463f-b6aa-0bbdf53b0da1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522104291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.1522104291
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3082129593
Short name T574
Test name
Test status
Simulation time 448280693 ps
CPU time 3.27 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:58 PM PDT 24
Peak memory 209132 kb
Host smart-2451d693-b1ed-4e4f-b877-87cb682ec7f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082129593 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3082129593
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.673794618
Short name T611
Test name
Test status
Simulation time 955074679 ps
CPU time 3.16 seconds
Started Aug 18 05:47:59 PM PDT 24
Finished Aug 18 05:48:02 PM PDT 24
Peak memory 201024 kb
Host smart-252ae5c9-adba-497b-a259-d9853fb94736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673794618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err
.673794618
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3322564865
Short name T606
Test name
Test status
Simulation time 101905400 ps
CPU time 0.95 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:54 PM PDT 24
Peak memory 200904 kb
Host smart-84cfd566-e1b2-4ff5-90d0-3645c2525372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322564865 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3322564865
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2207932485
Short name T544
Test name
Test status
Simulation time 83482761 ps
CPU time 0.92 seconds
Started Aug 18 05:47:57 PM PDT 24
Finished Aug 18 05:47:58 PM PDT 24
Peak memory 200712 kb
Host smart-db1c4c65-cda8-4fcc-85ac-8b3366fb873a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207932485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2207932485
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4238006278
Short name T87
Test name
Test status
Simulation time 140988317 ps
CPU time 1.4 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 200972 kb
Host smart-cef550e6-113d-40c6-9a83-3b29e4f941d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238006278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.4238006278
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3498448508
Short name T82
Test name
Test status
Simulation time 919243283 ps
CPU time 3.27 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:58 PM PDT 24
Peak memory 200880 kb
Host smart-dd9d171b-6f95-4856-89fb-cdc25f3fea39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498448508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.3498448508
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2724575469
Short name T572
Test name
Test status
Simulation time 174951574 ps
CPU time 1.12 seconds
Started Aug 18 05:48:04 PM PDT 24
Finished Aug 18 05:48:06 PM PDT 24
Peak memory 209032 kb
Host smart-303dd65d-b6d8-43bc-9425-549e343872cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724575469 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2724575469
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.893478135
Short name T94
Test name
Test status
Simulation time 95495688 ps
CPU time 0.87 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:55 PM PDT 24
Peak memory 200772 kb
Host smart-67211a01-cdd6-4242-a550-98339c246b6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893478135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.893478135
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2032389831
Short name T613
Test name
Test status
Simulation time 70032476 ps
CPU time 0.96 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:54 PM PDT 24
Peak memory 200832 kb
Host smart-ee20093c-2840-45b5-9bb6-bfe9b389dcc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032389831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.2032389831
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.247476340
Short name T101
Test name
Test status
Simulation time 202538795 ps
CPU time 2.89 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:58 PM PDT 24
Peak memory 209212 kb
Host smart-eb7c6755-944a-4c19-af45-978b5ca9a5b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247476340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.247476340
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.3055416602
Short name T99
Test name
Test status
Simulation time 772287754 ps
CPU time 2.75 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:57 PM PDT 24
Peak memory 200908 kb
Host smart-d26c03dd-f3de-457d-b83b-2ec5a3c2bb4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055416602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.3055416602
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3637854898
Short name T556
Test name
Test status
Simulation time 208899698 ps
CPU time 1.29 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 209052 kb
Host smart-f2421a3f-791d-4109-9f5a-85e8009e6440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637854898 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3637854898
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2136078221
Short name T546
Test name
Test status
Simulation time 82397446 ps
CPU time 0.89 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:54 PM PDT 24
Peak memory 200776 kb
Host smart-d39171c5-2a0f-4317-a506-e3cc8e48fe04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136078221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2136078221
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2155793769
Short name T88
Test name
Test status
Simulation time 148319298 ps
CPU time 1.17 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 200844 kb
Host smart-33e843f7-e73d-48cb-aad6-8ff02751eecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155793769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2155793769
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1478215846
Short name T103
Test name
Test status
Simulation time 422411017 ps
CPU time 3.13 seconds
Started Aug 18 05:47:57 PM PDT 24
Finished Aug 18 05:48:00 PM PDT 24
Peak memory 212976 kb
Host smart-b67bb5b8-1988-44e2-b297-a38a94b6d193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478215846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1478215846
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3515555748
Short name T115
Test name
Test status
Simulation time 1307003858 ps
CPU time 3.61 seconds
Started Aug 18 05:47:52 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 201048 kb
Host smart-bb4af977-7922-4572-a66f-6bce9283df15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515555748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3515555748
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1668529066
Short name T586
Test name
Test status
Simulation time 162195982 ps
CPU time 1.54 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:55 PM PDT 24
Peak memory 209264 kb
Host smart-503f56f8-db40-4c02-8f6a-53d41ab4401f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668529066 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1668529066
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.1447373051
Short name T543
Test name
Test status
Simulation time 68155956 ps
CPU time 0.75 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:54 PM PDT 24
Peak memory 200788 kb
Host smart-00027b50-fe34-42cb-99bf-dcd0bc09afec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447373051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1447373051
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.58234504
Short name T92
Test name
Test status
Simulation time 124318561 ps
CPU time 1.04 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:55 PM PDT 24
Peak memory 200860 kb
Host smart-35cebff7-78a5-4e69-a404-c8675645d62a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58234504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sam
e_csr_outstanding.58234504
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.243571565
Short name T614
Test name
Test status
Simulation time 487195402 ps
CPU time 3.38 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:58 PM PDT 24
Peak memory 209212 kb
Host smart-595918a1-e456-4cfb-bc7d-7687b672808a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243571565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.243571565
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3107176489
Short name T55
Test name
Test status
Simulation time 416158393 ps
CPU time 1.73 seconds
Started Aug 18 05:47:57 PM PDT 24
Finished Aug 18 05:47:59 PM PDT 24
Peak memory 200960 kb
Host smart-bfe1c37c-2855-403d-8d48-597a8ce124e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107176489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_er
r.3107176489
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3348074083
Short name T618
Test name
Test status
Simulation time 188995508 ps
CPU time 1.14 seconds
Started Aug 18 05:47:51 PM PDT 24
Finished Aug 18 05:47:52 PM PDT 24
Peak memory 200988 kb
Host smart-a70493ce-f6d6-489c-8b7b-503aee4fc42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348074083 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.3348074083
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.561479741
Short name T552
Test name
Test status
Simulation time 73785078 ps
CPU time 0.82 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:55 PM PDT 24
Peak memory 200780 kb
Host smart-62050f71-cd34-4e75-a56b-f58fb03326b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561479741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.561479741
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3140610898
Short name T607
Test name
Test status
Simulation time 255083403 ps
CPU time 1.65 seconds
Started Aug 18 05:47:59 PM PDT 24
Finished Aug 18 05:48:01 PM PDT 24
Peak memory 200980 kb
Host smart-88ed5288-6763-4423-a41a-17102ac8406c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140610898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.3140610898
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.1273020202
Short name T579
Test name
Test status
Simulation time 419193421 ps
CPU time 3.04 seconds
Started Aug 18 05:47:56 PM PDT 24
Finished Aug 18 05:47:59 PM PDT 24
Peak memory 209172 kb
Host smart-ffe3d105-925a-4e20-82a7-cf9b1220fca2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273020202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1273020202
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.4095696520
Short name T598
Test name
Test status
Simulation time 401400906 ps
CPU time 1.67 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:57 PM PDT 24
Peak memory 201008 kb
Host smart-495d21ae-2289-4857-9f08-11aefab61f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095696520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.4095696520
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4214010319
Short name T102
Test name
Test status
Simulation time 203610582 ps
CPU time 1.4 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 209116 kb
Host smart-93ac357d-bb00-425d-ba32-05c015e09133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214010319 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.4214010319
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.1552710583
Short name T620
Test name
Test status
Simulation time 58410903 ps
CPU time 0.8 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 200780 kb
Host smart-20c0890a-c59f-43e3-95d4-0bdd1c65e5aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552710583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1552710583
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1658938019
Short name T93
Test name
Test status
Simulation time 129982464 ps
CPU time 1.18 seconds
Started Aug 18 05:47:57 PM PDT 24
Finished Aug 18 05:47:59 PM PDT 24
Peak memory 200740 kb
Host smart-8d102b21-14b4-4919-aa11-9c452872a453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658938019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1658938019
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.625817799
Short name T56
Test name
Test status
Simulation time 214236188 ps
CPU time 1.81 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:55 PM PDT 24
Peak memory 209200 kb
Host smart-6ad74873-880d-42b2-9c35-cf5a3bd0146c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625817799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.625817799
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2302986640
Short name T549
Test name
Test status
Simulation time 178075531 ps
CPU time 1.31 seconds
Started Aug 18 05:47:59 PM PDT 24
Finished Aug 18 05:48:01 PM PDT 24
Peak memory 209092 kb
Host smart-8990470e-9ce2-45b5-9ddf-8125607dcc57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302986640 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.2302986640
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.774917433
Short name T597
Test name
Test status
Simulation time 69070656 ps
CPU time 0.83 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 200744 kb
Host smart-13398d44-6939-46a4-98e5-483b5a4fc722
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774917433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.774917433
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1668167320
Short name T561
Test name
Test status
Simulation time 275034126 ps
CPU time 1.58 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:54 PM PDT 24
Peak memory 201072 kb
Host smart-30ddfe9e-f816-4aa9-af1d-d481c7af1455
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668167320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.1668167320
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.1956242467
Short name T559
Test name
Test status
Simulation time 453363017 ps
CPU time 2.93 seconds
Started Aug 18 05:47:59 PM PDT 24
Finished Aug 18 05:48:02 PM PDT 24
Peak memory 212624 kb
Host smart-85996fd5-f5ab-46ad-9e00-46de31f5f0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956242467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1956242467
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.322519831
Short name T63
Test name
Test status
Simulation time 937657717 ps
CPU time 2.99 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 201024 kb
Host smart-69c5bcf4-681d-4979-8538-fc37c36c5bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322519831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err
.322519831
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3313187685
Short name T615
Test name
Test status
Simulation time 238654391 ps
CPU time 1.65 seconds
Started Aug 18 05:47:39 PM PDT 24
Finished Aug 18 05:47:40 PM PDT 24
Peak memory 200928 kb
Host smart-9e123973-9c3d-4170-b40e-3518e2b3dae5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313187685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
313187685
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1001543476
Short name T548
Test name
Test status
Simulation time 2030380384 ps
CPU time 8.75 seconds
Started Aug 18 05:47:35 PM PDT 24
Finished Aug 18 05:47:43 PM PDT 24
Peak memory 200944 kb
Host smart-58997613-29d1-4415-88e0-389ecadf9f0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001543476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
001543476
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.521684796
Short name T585
Test name
Test status
Simulation time 128571631 ps
CPU time 0.91 seconds
Started Aug 18 05:47:35 PM PDT 24
Finished Aug 18 05:47:36 PM PDT 24
Peak memory 200776 kb
Host smart-32eddb73-dc83-413a-b85e-ecd6308aaaed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521684796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.521684796
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.4101909019
Short name T602
Test name
Test status
Simulation time 118490848 ps
CPU time 0.98 seconds
Started Aug 18 05:47:35 PM PDT 24
Finished Aug 18 05:47:37 PM PDT 24
Peak memory 200820 kb
Host smart-48638ea2-60e7-4ecf-a984-41a69695711f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101909019 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.4101909019
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4268705282
Short name T550
Test name
Test status
Simulation time 77240846 ps
CPU time 0.87 seconds
Started Aug 18 05:47:39 PM PDT 24
Finished Aug 18 05:47:40 PM PDT 24
Peak memory 200748 kb
Host smart-25728913-f971-45b4-b3d2-d471907271ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268705282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4268705282
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1265119624
Short name T564
Test name
Test status
Simulation time 219064868 ps
CPU time 1.45 seconds
Started Aug 18 05:47:37 PM PDT 24
Finished Aug 18 05:47:38 PM PDT 24
Peak memory 201008 kb
Host smart-9ccf39a5-58a6-427f-82f6-c4189ee51584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265119624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.1265119624
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.1396714799
Short name T601
Test name
Test status
Simulation time 481151387 ps
CPU time 3.69 seconds
Started Aug 18 05:47:41 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 209192 kb
Host smart-91b2b8de-ee21-4ad0-af54-a3b510e99b29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396714799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1396714799
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3603630916
Short name T571
Test name
Test status
Simulation time 485404698 ps
CPU time 1.99 seconds
Started Aug 18 05:47:34 PM PDT 24
Finished Aug 18 05:47:36 PM PDT 24
Peak memory 201140 kb
Host smart-3a2f7d8d-5dc9-4ede-9efd-af0f19d13553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603630916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.3603630916
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1519157032
Short name T617
Test name
Test status
Simulation time 427192766 ps
CPU time 2.59 seconds
Started Aug 18 05:47:42 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 200896 kb
Host smart-421ee447-595a-4c95-96cd-c1e3bdac84a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519157032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1
519157032
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.846974166
Short name T609
Test name
Test status
Simulation time 493211392 ps
CPU time 5.87 seconds
Started Aug 18 05:47:42 PM PDT 24
Finished Aug 18 05:47:48 PM PDT 24
Peak memory 200960 kb
Host smart-c1b534d7-8285-4f7f-812e-60998f84f084
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846974166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.846974166
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3593763109
Short name T599
Test name
Test status
Simulation time 88444724 ps
CPU time 0.77 seconds
Started Aug 18 05:47:36 PM PDT 24
Finished Aug 18 05:47:37 PM PDT 24
Peak memory 200716 kb
Host smart-02ba2456-1a56-45dd-b05b-36ca6194744e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593763109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
593763109
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2346426880
Short name T560
Test name
Test status
Simulation time 182249694 ps
CPU time 1.18 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:47 PM PDT 24
Peak memory 200896 kb
Host smart-a6621662-7b98-4a42-9581-b27ea4d4dcb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346426880 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.2346426880
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.327276013
Short name T610
Test name
Test status
Simulation time 74781308 ps
CPU time 0.81 seconds
Started Aug 18 05:47:41 PM PDT 24
Finished Aug 18 05:47:42 PM PDT 24
Peak memory 200684 kb
Host smart-f6fbc77b-aa5f-4893-95dc-d8f10a7a360f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327276013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.327276013
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1474827931
Short name T86
Test name
Test status
Simulation time 135491579 ps
CPU time 1.08 seconds
Started Aug 18 05:47:42 PM PDT 24
Finished Aug 18 05:47:43 PM PDT 24
Peak memory 200748 kb
Host smart-cf952cbe-13b5-472c-856f-2b13cb394eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474827931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1474827931
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1579712293
Short name T590
Test name
Test status
Simulation time 117941402 ps
CPU time 1.56 seconds
Started Aug 18 05:47:35 PM PDT 24
Finished Aug 18 05:47:37 PM PDT 24
Peak memory 217264 kb
Host smart-fde8616a-5638-404f-967f-1972835144d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579712293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1579712293
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3983265685
Short name T554
Test name
Test status
Simulation time 524865906 ps
CPU time 1.89 seconds
Started Aug 18 05:47:34 PM PDT 24
Finished Aug 18 05:47:36 PM PDT 24
Peak memory 200944 kb
Host smart-337de1c9-4eb9-4d2d-a452-3a97f1194d66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983265685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.3983265685
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.3412854523
Short name T589
Test name
Test status
Simulation time 204244285 ps
CPU time 1.44 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 200912 kb
Host smart-f033fc59-7bc5-4b3d-8d2c-5d99221d3b4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412854523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.3
412854523
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2527426600
Short name T608
Test name
Test status
Simulation time 808197095 ps
CPU time 4.5 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:51 PM PDT 24
Peak memory 209148 kb
Host smart-44d8ef98-d2e4-43bb-b719-e2dd265e4765
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527426600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
527426600
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1399748296
Short name T547
Test name
Test status
Simulation time 128157935 ps
CPU time 0.94 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 200800 kb
Host smart-ac0faa72-fe2b-4fa0-a269-cc5f4ac929f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399748296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1
399748296
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1735872297
Short name T79
Test name
Test status
Simulation time 194451881 ps
CPU time 1.18 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:48 PM PDT 24
Peak memory 209136 kb
Host smart-9b3d8ed3-f46a-4880-9a90-16e79c03f174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735872297 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1735872297
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1643579686
Short name T53
Test name
Test status
Simulation time 62529958 ps
CPU time 0.78 seconds
Started Aug 18 05:47:45 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 200680 kb
Host smart-1a691ffb-9b39-4c5f-9cef-28aab0d369c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643579686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1643579686
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.160773818
Short name T604
Test name
Test status
Simulation time 212623423 ps
CPU time 1.54 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 201020 kb
Host smart-5e5e5796-1823-4410-aced-7fc6ff0e1393
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160773818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.160773818
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3061012648
Short name T568
Test name
Test status
Simulation time 221369661 ps
CPU time 1.68 seconds
Started Aug 18 05:47:42 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 209252 kb
Host smart-cbc480b8-047f-4d65-8e3a-23f9905dbbad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061012648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3061012648
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.967494480
Short name T551
Test name
Test status
Simulation time 498617055 ps
CPU time 1.81 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 201052 kb
Host smart-9d22da17-8edd-438d-8a8c-bb96e37f6417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967494480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.
967494480
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3265485909
Short name T563
Test name
Test status
Simulation time 196449100 ps
CPU time 1.23 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 209092 kb
Host smart-6075105b-71e0-4c0c-a66b-61a5be989496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265485909 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3265485909
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2588351993
Short name T573
Test name
Test status
Simulation time 65907858 ps
CPU time 0.79 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 200728 kb
Host smart-57a64ac3-82ca-4b72-9247-4f55c79c65a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588351993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2588351993
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2114808463
Short name T95
Test name
Test status
Simulation time 86832295 ps
CPU time 1.08 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 200804 kb
Host smart-7a592895-b8f5-4ec7-96b0-03f520b44030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114808463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.2114808463
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.3688899230
Short name T578
Test name
Test status
Simulation time 428815894 ps
CPU time 3.12 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 212612 kb
Host smart-01fb2167-c969-4d36-9765-67add9204a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688899230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.3688899230
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.3575477214
Short name T596
Test name
Test status
Simulation time 875653649 ps
CPU time 2.98 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:49 PM PDT 24
Peak memory 200996 kb
Host smart-9d19a4ef-ed2f-4bc9-83df-58075c97fa15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575477214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.3575477214
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.4079144916
Short name T584
Test name
Test status
Simulation time 118208368 ps
CPU time 0.93 seconds
Started Aug 18 05:47:42 PM PDT 24
Finished Aug 18 05:47:43 PM PDT 24
Peak memory 200788 kb
Host smart-4b88a4d5-a247-4446-b54f-391c09349b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079144916 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.4079144916
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.4258224700
Short name T569
Test name
Test status
Simulation time 71830828 ps
CPU time 0.74 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 200760 kb
Host smart-b44c6658-2524-4429-9298-94c1647852da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258224700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.4258224700
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.186982994
Short name T567
Test name
Test status
Simulation time 134484836 ps
CPU time 1.11 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 200848 kb
Host smart-408d41cc-04c5-46cb-9401-da20fb58a8e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186982994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.186982994
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.878559098
Short name T80
Test name
Test status
Simulation time 110950014 ps
CPU time 1.42 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 209260 kb
Host smart-e1effb54-8eda-4007-8bc0-38075ee119e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878559098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.878559098
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3992432239
Short name T100
Test name
Test status
Simulation time 408289905 ps
CPU time 1.75 seconds
Started Aug 18 05:47:42 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 200992 kb
Host smart-ee448fe8-573b-4234-8fa1-b24312e5c4dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992432239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3992432239
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1079791216
Short name T81
Test name
Test status
Simulation time 116532460 ps
CPU time 1.12 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 209092 kb
Host smart-a7ffcda1-08b3-43aa-af13-411d672f2de2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079791216 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.1079791216
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.116446200
Short name T619
Test name
Test status
Simulation time 63699826 ps
CPU time 0.76 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 200888 kb
Host smart-fd7e7c79-5fab-4de4-95ea-21ed2e0186a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116446200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.116446200
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4152425283
Short name T89
Test name
Test status
Simulation time 81530683 ps
CPU time 0.98 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:44 PM PDT 24
Peak memory 200864 kb
Host smart-210152f3-c28a-4ae5-a660-d447e1e6b355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152425283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.4152425283
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.4037307322
Short name T575
Test name
Test status
Simulation time 120903203 ps
CPU time 1.58 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 217304 kb
Host smart-de055169-606f-4711-b851-4e2e8421d8ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037307322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4037307322
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2740967157
Short name T591
Test name
Test status
Simulation time 425828065 ps
CPU time 1.9 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 201044 kb
Host smart-300fbb97-ae9b-4cf7-b439-8a1350897225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740967157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.2740967157
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4073040089
Short name T612
Test name
Test status
Simulation time 124574125 ps
CPU time 0.92 seconds
Started Aug 18 05:47:44 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 200924 kb
Host smart-3a406679-26c5-4e0e-8bb4-7e89374768e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073040089 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4073040089
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3992140977
Short name T603
Test name
Test status
Simulation time 89856330 ps
CPU time 0.93 seconds
Started Aug 18 05:47:48 PM PDT 24
Finished Aug 18 05:47:49 PM PDT 24
Peak memory 200776 kb
Host smart-6f210946-39ec-4ba8-a40f-e6f420c6c8fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992140977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3992140977
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3802319394
Short name T595
Test name
Test status
Simulation time 78691828 ps
CPU time 0.95 seconds
Started Aug 18 05:47:49 PM PDT 24
Finished Aug 18 05:47:50 PM PDT 24
Peak memory 200860 kb
Host smart-bcbec7ea-cb7a-4177-8920-01bb2a653f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802319394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3802319394
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2549172787
Short name T98
Test name
Test status
Simulation time 431942338 ps
CPU time 3.03 seconds
Started Aug 18 05:47:42 PM PDT 24
Finished Aug 18 05:47:45 PM PDT 24
Peak memory 212924 kb
Host smart-aca05da0-ad5e-4304-a36b-c04e64defaec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549172787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2549172787
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.755449179
Short name T114
Test name
Test status
Simulation time 779291753 ps
CPU time 2.76 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:49 PM PDT 24
Peak memory 201088 kb
Host smart-0cb76644-2a3f-482e-a9e1-99e3fe190c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755449179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
755449179
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1090113216
Short name T545
Test name
Test status
Simulation time 182205757 ps
CPU time 1.24 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:47 PM PDT 24
Peak memory 209092 kb
Host smart-3fe91d7b-f5bd-4b1d-85a3-91572f3498f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090113216 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.1090113216
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.273665033
Short name T576
Test name
Test status
Simulation time 74233781 ps
CPU time 0.83 seconds
Started Aug 18 05:47:42 PM PDT 24
Finished Aug 18 05:47:43 PM PDT 24
Peak memory 200784 kb
Host smart-928ec504-53cb-41e6-a52a-54e0d208af53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273665033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.273665033
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1945120648
Short name T588
Test name
Test status
Simulation time 203407779 ps
CPU time 1.49 seconds
Started Aug 18 05:47:46 PM PDT 24
Finished Aug 18 05:47:48 PM PDT 24
Peak memory 201080 kb
Host smart-7f1dc96b-6e2c-411a-9c29-e9ba2202abca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945120648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1945120648
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1381118729
Short name T566
Test name
Test status
Simulation time 324289157 ps
CPU time 2.44 seconds
Started Aug 18 05:47:43 PM PDT 24
Finished Aug 18 05:47:46 PM PDT 24
Peak memory 201088 kb
Host smart-f35daf53-c122-4d28-aeda-78f802525118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381118729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1381118729
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.96552130
Short name T40
Test name
Test status
Simulation time 1221408074 ps
CPU time 5.6 seconds
Started Aug 18 05:24:35 PM PDT 24
Finished Aug 18 05:24:41 PM PDT 24
Peak memory 221912 kb
Host smart-849fcd45-b45c-4723-ae02-d66d3e86ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96552130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.96552130
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.3281237823
Short name T330
Test name
Test status
Simulation time 243745807 ps
CPU time 1.04 seconds
Started Aug 18 05:24:34 PM PDT 24
Finished Aug 18 05:24:35 PM PDT 24
Peak memory 217788 kb
Host smart-59e9814b-c9fe-4b76-934d-177b6e6b095e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281237823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.3281237823
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.428483577
Short name T401
Test name
Test status
Simulation time 139499533 ps
CPU time 0.78 seconds
Started Aug 18 05:24:36 PM PDT 24
Finished Aug 18 05:24:36 PM PDT 24
Peak memory 200404 kb
Host smart-c60961c3-4fa8-4f46-bd5c-d1aa7a9c40e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428483577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.428483577
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.4054210209
Short name T482
Test name
Test status
Simulation time 1580042376 ps
CPU time 6.29 seconds
Started Aug 18 05:24:34 PM PDT 24
Finished Aug 18 05:24:40 PM PDT 24
Peak memory 200804 kb
Host smart-c549bef5-f415-4472-956b-d2553b62482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054210209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.4054210209
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3646821757
Short name T196
Test name
Test status
Simulation time 98195633 ps
CPU time 0.94 seconds
Started Aug 18 05:24:33 PM PDT 24
Finished Aug 18 05:24:34 PM PDT 24
Peak memory 200620 kb
Host smart-977243ff-a965-48a5-86e5-b9e900a9200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646821757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3646821757
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.140402094
Short name T338
Test name
Test status
Simulation time 197577194 ps
CPU time 1.38 seconds
Started Aug 18 05:24:34 PM PDT 24
Finished Aug 18 05:24:36 PM PDT 24
Peak memory 200736 kb
Host smart-13b8b686-26fc-4e8d-acb0-0bb2438bfdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140402094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.140402094
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.663864977
Short name T261
Test name
Test status
Simulation time 8505353380 ps
CPU time 32.71 seconds
Started Aug 18 05:24:36 PM PDT 24
Finished Aug 18 05:25:09 PM PDT 24
Peak memory 200848 kb
Host smart-00b20003-4c30-404c-8347-74fd5d418acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663864977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.663864977
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3987280758
Short name T49
Test name
Test status
Simulation time 340117978 ps
CPU time 2.15 seconds
Started Aug 18 05:24:34 PM PDT 24
Finished Aug 18 05:24:36 PM PDT 24
Peak memory 200552 kb
Host smart-99700992-6fe3-4fb0-b6ab-6d8a4cb361fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987280758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3987280758
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2669323119
Short name T178
Test name
Test status
Simulation time 154781344 ps
CPU time 1.12 seconds
Started Aug 18 05:24:32 PM PDT 24
Finished Aug 18 05:24:33 PM PDT 24
Peak memory 200588 kb
Host smart-aae3c7d6-f762-429b-8797-46570940de1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669323119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2669323119
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.164932411
Short name T204
Test name
Test status
Simulation time 67580487 ps
CPU time 0.73 seconds
Started Aug 18 05:24:41 PM PDT 24
Finished Aug 18 05:24:42 PM PDT 24
Peak memory 200456 kb
Host smart-1f5f8579-8eb8-41c3-98d2-8ddb421b4825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164932411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.164932411
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.3555939876
Short name T11
Test name
Test status
Simulation time 2350173900 ps
CPU time 8.1 seconds
Started Aug 18 05:24:44 PM PDT 24
Finished Aug 18 05:24:52 PM PDT 24
Peak memory 221892 kb
Host smart-7ef117a7-453c-49d6-aea5-6038647aa01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555939876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3555939876
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3130344196
Short name T260
Test name
Test status
Simulation time 244700128 ps
CPU time 1.1 seconds
Started Aug 18 05:24:43 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 217732 kb
Host smart-5890c0da-9111-430c-91ff-72e42468596e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130344196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3130344196
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.2466624636
Short name T526
Test name
Test status
Simulation time 162446902 ps
CPU time 0.92 seconds
Started Aug 18 05:24:42 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 200432 kb
Host smart-6891a194-1e25-4ac4-badc-a674b4b9061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466624636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2466624636
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.2776896600
Short name T33
Test name
Test status
Simulation time 2485124933 ps
CPU time 8.7 seconds
Started Aug 18 05:24:40 PM PDT 24
Finished Aug 18 05:24:49 PM PDT 24
Peak memory 200840 kb
Host smart-98fd5d55-96c8-4b31-8e07-771b6a956f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776896600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2776896600
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.2021264074
Short name T65
Test name
Test status
Simulation time 8335809719 ps
CPU time 12.9 seconds
Started Aug 18 05:24:41 PM PDT 24
Finished Aug 18 05:24:54 PM PDT 24
Peak memory 217292 kb
Host smart-a78c6a0b-3f01-438d-a12d-94b9375f5ce7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021264074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2021264074
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3389051754
Short name T447
Test name
Test status
Simulation time 152332886 ps
CPU time 1.12 seconds
Started Aug 18 05:24:45 PM PDT 24
Finished Aug 18 05:24:46 PM PDT 24
Peak memory 200608 kb
Host smart-fb9bb4cb-1dde-41df-8712-193cc0cf199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389051754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3389051754
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.2517749932
Short name T506
Test name
Test status
Simulation time 188077145 ps
CPU time 1.42 seconds
Started Aug 18 05:24:43 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 200620 kb
Host smart-6e391cbb-8725-4e48-afb1-a49bc5473165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517749932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2517749932
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.3441885576
Short name T313
Test name
Test status
Simulation time 7839683059 ps
CPU time 26.75 seconds
Started Aug 18 05:24:43 PM PDT 24
Finished Aug 18 05:25:10 PM PDT 24
Peak memory 200748 kb
Host smart-36ea4d33-e8f9-43b3-86e2-09079fa9266c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441885576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3441885576
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.1572563752
Short name T230
Test name
Test status
Simulation time 499404593 ps
CPU time 2.51 seconds
Started Aug 18 05:24:40 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 200516 kb
Host smart-805cc5f2-a6bf-48aa-be82-c057a14b0bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572563752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1572563752
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2787398125
Short name T334
Test name
Test status
Simulation time 89040590 ps
CPU time 0.81 seconds
Started Aug 18 05:24:40 PM PDT 24
Finished Aug 18 05:24:41 PM PDT 24
Peak memory 200528 kb
Host smart-d7fdbddf-8768-435b-abcf-a4e843e04884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787398125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2787398125
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.1370836849
Short name T369
Test name
Test status
Simulation time 67941476 ps
CPU time 0.74 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 200492 kb
Host smart-a4ffae69-bd61-4512-82d3-e7ac6768ee45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370836849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1370836849
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.1495306425
Short name T377
Test name
Test status
Simulation time 2368215642 ps
CPU time 8.38 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 221924 kb
Host smart-1513c9f7-45e5-4497-87f7-1324014535c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495306425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1495306425
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.290775881
Short name T486
Test name
Test status
Simulation time 243316905 ps
CPU time 1.17 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 217780 kb
Host smart-9fe49732-b349-411a-9ee9-7edfabdafd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290775881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.290775881
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.534880105
Short name T479
Test name
Test status
Simulation time 165372359 ps
CPU time 0.88 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:14 PM PDT 24
Peak memory 200396 kb
Host smart-de624909-f2b4-498f-890a-c843072dfad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534880105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.534880105
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1045825514
Short name T222
Test name
Test status
Simulation time 1772677525 ps
CPU time 7.54 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200800 kb
Host smart-a731b7c7-30a4-428a-a83d-b40fada66254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045825514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1045825514
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3772728729
Short name T189
Test name
Test status
Simulation time 103741785 ps
CPU time 1.03 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:14 PM PDT 24
Peak memory 200628 kb
Host smart-1dee01ad-5c7c-4f6f-9256-eff7e47c96ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772728729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3772728729
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.4097722049
Short name T187
Test name
Test status
Simulation time 189533408 ps
CPU time 1.36 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:14 PM PDT 24
Peak memory 200788 kb
Host smart-32cf9ad3-db4f-421d-b42f-dd587c0e57ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097722049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4097722049
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.1934989401
Short name T397
Test name
Test status
Simulation time 1921085319 ps
CPU time 7.52 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:21 PM PDT 24
Peak memory 200784 kb
Host smart-d63ae3da-72ab-478a-a441-447b2df6cc31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934989401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1934989401
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2153695964
Short name T475
Test name
Test status
Simulation time 512656762 ps
CPU time 2.74 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:17 PM PDT 24
Peak memory 200520 kb
Host smart-5f7d33a3-70d7-41d2-aa73-9326a5bdb23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153695964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2153695964
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.3799596350
Short name T218
Test name
Test status
Simulation time 139743853 ps
CPU time 1 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:16 PM PDT 24
Peak memory 200612 kb
Host smart-eee6a17c-ed26-455f-8c7d-1968d95f8293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799596350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3799596350
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1178072356
Short name T278
Test name
Test status
Simulation time 79406588 ps
CPU time 0.84 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200500 kb
Host smart-913c493f-4f38-4707-8c0a-12ec6e42cbcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178072356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1178072356
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.545431299
Short name T419
Test name
Test status
Simulation time 1224951929 ps
CPU time 5.98 seconds
Started Aug 18 05:25:20 PM PDT 24
Finished Aug 18 05:25:26 PM PDT 24
Peak memory 216988 kb
Host smart-469bd29c-4e59-4fa8-a993-d30c130b7c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545431299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.545431299
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1066587533
Short name T294
Test name
Test status
Simulation time 243871888 ps
CPU time 1.11 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 217848 kb
Host smart-08458498-d6a5-4f79-97b6-14904d7cff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066587533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1066587533
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.1888727477
Short name T483
Test name
Test status
Simulation time 118827585 ps
CPU time 0.82 seconds
Started Aug 18 05:25:23 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200428 kb
Host smart-436bd537-363a-488b-9c45-161739de0f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888727477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1888727477
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.1096805721
Short name T153
Test name
Test status
Simulation time 759212887 ps
CPU time 3.87 seconds
Started Aug 18 05:25:22 PM PDT 24
Finished Aug 18 05:25:26 PM PDT 24
Peak memory 200700 kb
Host smart-b7880b4d-e187-42b7-ae7a-0b17ee8d1bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096805721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1096805721
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1066659210
Short name T518
Test name
Test status
Simulation time 261367917 ps
CPU time 1.48 seconds
Started Aug 18 05:25:22 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200712 kb
Host smart-146a6ea6-90b4-4924-9755-20da15dd2d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066659210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1066659210
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.3507510086
Short name T167
Test name
Test status
Simulation time 815497056 ps
CPU time 4.34 seconds
Started Aug 18 05:25:23 PM PDT 24
Finished Aug 18 05:25:27 PM PDT 24
Peak memory 200752 kb
Host smart-ef655564-6299-44a1-92e7-5b9aa3d56cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507510086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3507510086
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.1907407876
Short name T298
Test name
Test status
Simulation time 500246234 ps
CPU time 2.76 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200532 kb
Host smart-73853bf9-2606-4ee9-92ac-2439e0674e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907407876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1907407876
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1883679578
Short name T7
Test name
Test status
Simulation time 231531431 ps
CPU time 1.34 seconds
Started Aug 18 05:25:25 PM PDT 24
Finished Aug 18 05:25:26 PM PDT 24
Peak memory 200580 kb
Host smart-5e7013f8-d957-4567-817a-058a360474c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883679578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1883679578
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1060928768
Short name T242
Test name
Test status
Simulation time 80455724 ps
CPU time 0.84 seconds
Started Aug 18 05:25:19 PM PDT 24
Finished Aug 18 05:25:20 PM PDT 24
Peak memory 200488 kb
Host smart-478f9976-efe5-4fae-acb5-5ef15adb71f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060928768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1060928768
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3674375642
Short name T533
Test name
Test status
Simulation time 2347132753 ps
CPU time 8.3 seconds
Started Aug 18 05:25:19 PM PDT 24
Finished Aug 18 05:25:28 PM PDT 24
Peak memory 217392 kb
Host smart-14d14c4d-aea2-44b1-bdae-1ea10cef11d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674375642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3674375642
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1301976649
Short name T534
Test name
Test status
Simulation time 243749088 ps
CPU time 1.12 seconds
Started Aug 18 05:25:20 PM PDT 24
Finished Aug 18 05:25:21 PM PDT 24
Peak memory 217840 kb
Host smart-1657351a-2dac-49bc-abdc-96f63360709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301976649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1301976649
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.3278019814
Short name T532
Test name
Test status
Simulation time 203704863 ps
CPU time 0.95 seconds
Started Aug 18 05:25:23 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200352 kb
Host smart-ef939e93-8647-4024-8b80-24e45e18cef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278019814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3278019814
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.1948643378
Short name T468
Test name
Test status
Simulation time 1069618045 ps
CPU time 4.97 seconds
Started Aug 18 05:25:19 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200776 kb
Host smart-28421587-fd3f-4462-9fd7-1002e676265e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948643378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1948643378
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2968710460
Short name T503
Test name
Test status
Simulation time 101118698 ps
CPU time 1 seconds
Started Aug 18 05:25:23 PM PDT 24
Finished Aug 18 05:25:25 PM PDT 24
Peak memory 200584 kb
Host smart-eaf1a2a6-aafb-4830-9bb6-506ecae6a445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968710460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2968710460
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.3110193931
Short name T522
Test name
Test status
Simulation time 124740056 ps
CPU time 1.21 seconds
Started Aug 18 05:25:20 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200744 kb
Host smart-d847c5e8-0081-4b6d-baa0-77189d714822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110193931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3110193931
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.3598495365
Short name T321
Test name
Test status
Simulation time 1683582469 ps
CPU time 7.82 seconds
Started Aug 18 05:25:23 PM PDT 24
Finished Aug 18 05:25:31 PM PDT 24
Peak memory 200760 kb
Host smart-fb0c1082-5451-490f-876f-817ffdf7804e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598495365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3598495365
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.3883393140
Short name T504
Test name
Test status
Simulation time 444067016 ps
CPU time 2.41 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200756 kb
Host smart-94180186-7e30-4c81-a4f0-d42e3570810c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883393140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3883393140
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.2067388025
Short name T476
Test name
Test status
Simulation time 146025874 ps
CPU time 1.08 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200528 kb
Host smart-3172248a-02f0-4d22-a965-4a3d1dce7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067388025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2067388025
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.32827883
Short name T128
Test name
Test status
Simulation time 70024742 ps
CPU time 0.75 seconds
Started Aug 18 05:25:20 PM PDT 24
Finished Aug 18 05:25:20 PM PDT 24
Peak memory 200444 kb
Host smart-4b190f85-bcb4-49f2-845d-a437f55cd22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32827883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.32827883
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.2019751661
Short name T374
Test name
Test status
Simulation time 1231748158 ps
CPU time 5.82 seconds
Started Aug 18 05:25:19 PM PDT 24
Finished Aug 18 05:25:25 PM PDT 24
Peak memory 217048 kb
Host smart-26d9b7ac-1ef7-4bea-8afa-cc93ac77ea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019751661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2019751661
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.962019766
Short name T375
Test name
Test status
Simulation time 244982409 ps
CPU time 1.05 seconds
Started Aug 18 05:25:22 PM PDT 24
Finished Aug 18 05:25:23 PM PDT 24
Peak memory 217792 kb
Host smart-c9fde25d-bde2-4b07-af52-132143a75b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962019766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.962019766
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_reset.918702424
Short name T266
Test name
Test status
Simulation time 1253455378 ps
CPU time 5.17 seconds
Started Aug 18 05:25:24 PM PDT 24
Finished Aug 18 05:25:29 PM PDT 24
Peak memory 200700 kb
Host smart-ad9de124-6004-42ed-8d21-e13e1dbbc7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918702424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.918702424
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.214104102
Short name T368
Test name
Test status
Simulation time 152660470 ps
CPU time 1.14 seconds
Started Aug 18 05:25:20 PM PDT 24
Finished Aug 18 05:25:21 PM PDT 24
Peak memory 200480 kb
Host smart-93dabfc9-11b2-494d-a0fa-085544514fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214104102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.214104102
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1579221316
Short name T537
Test name
Test status
Simulation time 248990797 ps
CPU time 1.52 seconds
Started Aug 18 05:25:22 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200680 kb
Host smart-4edb210f-a993-452e-a74c-c0595d66f4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579221316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1579221316
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.4134065944
Short name T234
Test name
Test status
Simulation time 9502150225 ps
CPU time 32.4 seconds
Started Aug 18 05:25:25 PM PDT 24
Finished Aug 18 05:25:57 PM PDT 24
Peak memory 200788 kb
Host smart-91b41d52-cdea-4a18-95e2-103fa7770777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134065944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.4134065944
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1314883719
Short name T383
Test name
Test status
Simulation time 293569022 ps
CPU time 1.92 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:23 PM PDT 24
Peak memory 200516 kb
Host smart-a37ecc52-cc67-49b2-8081-6ccf8380fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314883719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1314883719
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.2103003819
Short name T425
Test name
Test status
Simulation time 283071661 ps
CPU time 1.61 seconds
Started Aug 18 05:25:23 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200712 kb
Host smart-751da30b-2530-41a2-ab8a-3216d1a5e95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103003819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2103003819
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.1189178333
Short name T158
Test name
Test status
Simulation time 70656648 ps
CPU time 0.79 seconds
Started Aug 18 05:25:24 PM PDT 24
Finished Aug 18 05:25:25 PM PDT 24
Peak memory 200388 kb
Host smart-904313ac-967c-46a7-9b5d-864f2c40b1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189178333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1189178333
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2111605579
Short name T524
Test name
Test status
Simulation time 2170596106 ps
CPU time 7.91 seconds
Started Aug 18 05:25:20 PM PDT 24
Finished Aug 18 05:25:28 PM PDT 24
Peak memory 218032 kb
Host smart-83d6a5c7-d4e2-4812-b76e-d9ca04f33fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111605579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2111605579
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2420492395
Short name T407
Test name
Test status
Simulation time 244026828 ps
CPU time 1.12 seconds
Started Aug 18 05:25:20 PM PDT 24
Finished Aug 18 05:25:21 PM PDT 24
Peak memory 217712 kb
Host smart-8346f00a-14c5-4789-9261-540ecfbb3af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420492395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2420492395
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1156324109
Short name T201
Test name
Test status
Simulation time 144109803 ps
CPU time 0.8 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200336 kb
Host smart-7cbea37b-8305-42fc-945c-69a4ddaf8f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156324109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1156324109
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.870602431
Short name T354
Test name
Test status
Simulation time 1438291427 ps
CPU time 5.32 seconds
Started Aug 18 05:25:18 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200776 kb
Host smart-6924b06f-e07f-4b85-9757-467e7175766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870602431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.870602431
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2863901487
Short name T244
Test name
Test status
Simulation time 101987982 ps
CPU time 0.98 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200608 kb
Host smart-6df96630-fb6f-4cc3-928b-74ea1d09ec4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863901487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2863901487
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.326853790
Short name T149
Test name
Test status
Simulation time 209448715 ps
CPU time 1.39 seconds
Started Aug 18 05:25:24 PM PDT 24
Finished Aug 18 05:25:25 PM PDT 24
Peak memory 200688 kb
Host smart-ab0a5f6f-7b4e-445e-9965-e877295ffa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326853790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.326853790
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.1016116084
Short name T194
Test name
Test status
Simulation time 2868463960 ps
CPU time 11.75 seconds
Started Aug 18 05:25:20 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 209016 kb
Host smart-2d3f832a-3d00-44a0-b80e-2399ab458ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016116084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1016116084
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.2394387311
Short name T409
Test name
Test status
Simulation time 143160080 ps
CPU time 1.82 seconds
Started Aug 18 05:25:25 PM PDT 24
Finished Aug 18 05:25:26 PM PDT 24
Peak memory 208716 kb
Host smart-470187cc-a645-45bf-adc6-c973b928bae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394387311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2394387311
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.3397255506
Short name T351
Test name
Test status
Simulation time 97901217 ps
CPU time 0.99 seconds
Started Aug 18 05:25:23 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200624 kb
Host smart-2bd962f5-9629-4cfa-91f5-24039be724cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397255506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3397255506
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.1479571178
Short name T403
Test name
Test status
Simulation time 85193624 ps
CPU time 0.81 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 200468 kb
Host smart-69092de3-9c60-4022-9977-facd141d40ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479571178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1479571178
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.1525962105
Short name T212
Test name
Test status
Simulation time 1892096354 ps
CPU time 6.92 seconds
Started Aug 18 05:25:22 PM PDT 24
Finished Aug 18 05:25:29 PM PDT 24
Peak memory 217892 kb
Host smart-35bdeef6-3391-49fe-9c6b-17f19247836f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525962105 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1525962105
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1350028308
Short name T231
Test name
Test status
Simulation time 245565074 ps
CPU time 1.06 seconds
Started Aug 18 05:25:24 PM PDT 24
Finished Aug 18 05:25:25 PM PDT 24
Peak memory 217780 kb
Host smart-41b057fc-ed5d-4b13-b75e-c6d1b2d71a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350028308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1350028308
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2560533062
Short name T301
Test name
Test status
Simulation time 133416038 ps
CPU time 0.78 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200412 kb
Host smart-7b47eb83-65fc-4d8f-9a58-38cb7758c589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560533062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2560533062
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.707446626
Short name T284
Test name
Test status
Simulation time 1498088977 ps
CPU time 6.29 seconds
Started Aug 18 05:25:22 PM PDT 24
Finished Aug 18 05:25:29 PM PDT 24
Peak memory 200696 kb
Host smart-a335760b-0a32-4aef-b3f2-078c6fef0bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707446626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.707446626
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1924664719
Short name T255
Test name
Test status
Simulation time 180943926 ps
CPU time 1.22 seconds
Started Aug 18 05:25:22 PM PDT 24
Finished Aug 18 05:25:23 PM PDT 24
Peak memory 200568 kb
Host smart-7eee875a-44e0-4007-b915-40c14540f02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924664719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1924664719
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3145239412
Short name T258
Test name
Test status
Simulation time 249281344 ps
CPU time 1.57 seconds
Started Aug 18 05:25:24 PM PDT 24
Finished Aug 18 05:25:25 PM PDT 24
Peak memory 200720 kb
Host smart-c36ec03c-52aa-4c41-a36e-86cc1aeb5226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145239412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3145239412
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3622570421
Short name T308
Test name
Test status
Simulation time 1730301773 ps
CPU time 6.35 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:37 PM PDT 24
Peak memory 200828 kb
Host smart-62da5d00-4642-4ff1-b016-3803c2cbbeaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622570421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3622570421
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.4144470102
Short name T180
Test name
Test status
Simulation time 476497114 ps
CPU time 2.45 seconds
Started Aug 18 05:25:22 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 200468 kb
Host smart-ad6b8be4-0569-47ef-8fe5-1d7472d21468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144470102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.4144470102
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.3219215102
Short name T265
Test name
Test status
Simulation time 189814346 ps
CPU time 1.21 seconds
Started Aug 18 05:25:21 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 200596 kb
Host smart-5ad4dbf5-1b2b-4083-814a-c76b29dcca11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219215102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3219215102
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.4174961137
Short name T304
Test name
Test status
Simulation time 73899522 ps
CPU time 0.82 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:33 PM PDT 24
Peak memory 200460 kb
Host smart-6c62cfa1-cfe5-46ad-b685-8f1719760b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174961137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4174961137
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.1223297100
Short name T417
Test name
Test status
Simulation time 1228739114 ps
CPU time 5.35 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:38 PM PDT 24
Peak memory 221920 kb
Host smart-a77e9842-a957-45f6-955c-d9d0754ebb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223297100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1223297100
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.280300026
Short name T297
Test name
Test status
Simulation time 247572579 ps
CPU time 1.05 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 217744 kb
Host smart-f65ccc74-dfef-468c-bb8b-2241db546be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280300026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.280300026
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.967070222
Short name T396
Test name
Test status
Simulation time 164450260 ps
CPU time 0.88 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 200448 kb
Host smart-0e3d7253-a338-4734-9fc0-cfbac95c2864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967070222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.967070222
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.4272689555
Short name T371
Test name
Test status
Simulation time 920795531 ps
CPU time 4.51 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:37 PM PDT 24
Peak memory 201012 kb
Host smart-7442e361-6b48-4355-8945-d6e9d1b31f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272689555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.4272689555
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1203035676
Short name T141
Test name
Test status
Simulation time 105247574 ps
CPU time 1 seconds
Started Aug 18 05:25:30 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 200604 kb
Host smart-675233f8-5f30-4fb1-bb05-bd71cef0825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203035676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1203035676
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.774272744
Short name T140
Test name
Test status
Simulation time 203288751 ps
CPU time 1.34 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:33 PM PDT 24
Peak memory 200684 kb
Host smart-3ecfd523-3432-45a5-a23c-b34e1874602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774272744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.774272744
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.2100191807
Short name T502
Test name
Test status
Simulation time 7711415830 ps
CPU time 29.52 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 200896 kb
Host smart-4fccc0eb-1124-4cf5-abe4-1a3879a69f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100191807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2100191807
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.1878425984
Short name T132
Test name
Test status
Simulation time 358996579 ps
CPU time 2.27 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:35 PM PDT 24
Peak memory 200508 kb
Host smart-c616b069-a42e-4f02-a60f-a56b0dcd5ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878425984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1878425984
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3923866477
Short name T238
Test name
Test status
Simulation time 92354971 ps
CPU time 0.86 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 200476 kb
Host smart-224ffd8b-bfe1-4d9c-a93c-e4e9666a947e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923866477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3923866477
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.4264352038
Short name T310
Test name
Test status
Simulation time 1884084765 ps
CPU time 6.96 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:38 PM PDT 24
Peak memory 217932 kb
Host smart-cb6c8629-b2c0-48ea-a699-bf9f76970112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264352038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.4264352038
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3299696090
Short name T283
Test name
Test status
Simulation time 244040496 ps
CPU time 1.13 seconds
Started Aug 18 05:25:29 PM PDT 24
Finished Aug 18 05:25:31 PM PDT 24
Peak memory 217720 kb
Host smart-c4d669bd-701c-4d53-8134-7aece3c9f875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299696090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3299696090
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.951673972
Short name T412
Test name
Test status
Simulation time 176652791 ps
CPU time 0.86 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:33 PM PDT 24
Peak memory 200420 kb
Host smart-0daa9001-c30e-4656-8610-6cf3cde96035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951673972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.951673972
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.776278738
Short name T394
Test name
Test status
Simulation time 880125531 ps
CPU time 4.25 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:36 PM PDT 24
Peak memory 200820 kb
Host smart-4835343a-ad15-48ba-9db8-1c350c638e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776278738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.776278738
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.2483112224
Short name T538
Test name
Test status
Simulation time 106942121 ps
CPU time 0.99 seconds
Started Aug 18 05:25:30 PM PDT 24
Finished Aug 18 05:25:31 PM PDT 24
Peak memory 200624 kb
Host smart-35d307ea-5dc0-420d-942b-392500b24de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483112224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.2483112224
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.3842963539
Short name T127
Test name
Test status
Simulation time 198490222 ps
CPU time 1.42 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 200744 kb
Host smart-d9506f6e-7d11-4259-906f-85975d25cee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842963539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3842963539
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.27786591
Short name T323
Test name
Test status
Simulation time 5187237724 ps
CPU time 23.85 seconds
Started Aug 18 05:25:34 PM PDT 24
Finished Aug 18 05:25:58 PM PDT 24
Peak memory 200840 kb
Host smart-7429aa8f-2b04-4231-939b-d42daf5ccecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27786591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.27786591
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.1260243635
Short name T262
Test name
Test status
Simulation time 337985443 ps
CPU time 2.29 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 208756 kb
Host smart-c4f0458d-256e-407a-afb0-90fd1a71c5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260243635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1260243635
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.2784218210
Short name T137
Test name
Test status
Simulation time 115606114 ps
CPU time 0.93 seconds
Started Aug 18 05:25:34 PM PDT 24
Finished Aug 18 05:25:35 PM PDT 24
Peak memory 200604 kb
Host smart-7666a108-a717-4fe8-8b1f-fab038dd196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784218210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2784218210
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.77854089
Short name T246
Test name
Test status
Simulation time 76496504 ps
CPU time 0.8 seconds
Started Aug 18 05:25:35 PM PDT 24
Finished Aug 18 05:25:35 PM PDT 24
Peak memory 200496 kb
Host smart-1c65722b-90de-4f75-8a62-d32f8863c2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77854089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.77854089
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.4282819289
Short name T43
Test name
Test status
Simulation time 1899578807 ps
CPU time 7.59 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:40 PM PDT 24
Peak memory 221632 kb
Host smart-6f572eb0-d944-40be-b638-6b489507a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282819289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.4282819289
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1524763446
Short name T432
Test name
Test status
Simulation time 244334223 ps
CPU time 1.07 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 217788 kb
Host smart-1f60dd3f-7c1f-4059-9017-102c3035590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524763446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1524763446
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.3302857144
Short name T463
Test name
Test status
Simulation time 207202497 ps
CPU time 0.98 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:33 PM PDT 24
Peak memory 200380 kb
Host smart-3e0d50a0-6e02-4bc6-91af-a21f574ced91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302857144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3302857144
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2757491355
Short name T104
Test name
Test status
Simulation time 2063846415 ps
CPU time 7.95 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:41 PM PDT 24
Peak memory 200824 kb
Host smart-1a5ac71d-44eb-493e-8ab8-12d463373d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757491355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2757491355
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2111762148
Short name T473
Test name
Test status
Simulation time 167621955 ps
CPU time 1.31 seconds
Started Aug 18 05:25:35 PM PDT 24
Finished Aug 18 05:25:36 PM PDT 24
Peak memory 200588 kb
Host smart-1cfdedfc-527c-4add-9e12-350d905d1b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111762148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2111762148
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.647526356
Short name T176
Test name
Test status
Simulation time 202695625 ps
CPU time 1.4 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:33 PM PDT 24
Peak memory 200636 kb
Host smart-d04ba209-26ba-4002-8696-bd4e77c3d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647526356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.647526356
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1680461189
Short name T422
Test name
Test status
Simulation time 382457897 ps
CPU time 2.23 seconds
Started Aug 18 05:25:34 PM PDT 24
Finished Aug 18 05:25:36 PM PDT 24
Peak memory 208712 kb
Host smart-497b078f-7d8f-4edb-8fab-4879f6a23a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680461189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1680461189
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.584648783
Short name T172
Test name
Test status
Simulation time 102995319 ps
CPU time 0.99 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:33 PM PDT 24
Peak memory 200584 kb
Host smart-7e8fd5ec-41c4-4b5c-82d8-a943cdc3e59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584648783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.584648783
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.2641320718
Short name T213
Test name
Test status
Simulation time 70580001 ps
CPU time 0.76 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:33 PM PDT 24
Peak memory 200472 kb
Host smart-2cefbcab-787a-4302-bfa8-3bb21010580e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641320718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2641320718
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.3573095048
Short name T45
Test name
Test status
Simulation time 1885467978 ps
CPU time 7.02 seconds
Started Aug 18 05:25:37 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 217708 kb
Host smart-a82af54e-6502-4152-9395-296d443f2593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573095048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3573095048
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4171229131
Short name T8
Test name
Test status
Simulation time 243991168 ps
CPU time 1.14 seconds
Started Aug 18 05:25:36 PM PDT 24
Finished Aug 18 05:25:37 PM PDT 24
Peak memory 217728 kb
Host smart-96538f48-ecb8-4dd3-9a13-5393ab0cd5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171229131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4171229131
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.3595545065
Short name T291
Test name
Test status
Simulation time 88986405 ps
CPU time 0.75 seconds
Started Aug 18 05:25:36 PM PDT 24
Finished Aug 18 05:25:37 PM PDT 24
Peak memory 200400 kb
Host smart-103d4ae1-aa64-471a-a619-0b597262d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595545065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3595545065
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3895171703
Short name T315
Test name
Test status
Simulation time 959084728 ps
CPU time 4.56 seconds
Started Aug 18 05:25:31 PM PDT 24
Finished Aug 18 05:25:36 PM PDT 24
Peak memory 200760 kb
Host smart-df4d7eba-ddbc-4b34-be26-d95608874a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895171703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3895171703
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3468306692
Short name T161
Test name
Test status
Simulation time 168528478 ps
CPU time 1.18 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:35 PM PDT 24
Peak memory 200628 kb
Host smart-03ba365c-06b8-44a9-9da4-f688beb722ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468306692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3468306692
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.1664632850
Short name T164
Test name
Test status
Simulation time 232541584 ps
CPU time 1.55 seconds
Started Aug 18 05:25:36 PM PDT 24
Finished Aug 18 05:25:37 PM PDT 24
Peak memory 200788 kb
Host smart-ec242e95-fe81-4ce8-a69e-01740c747d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664632850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1664632850
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.4028680171
Short name T325
Test name
Test status
Simulation time 183487101 ps
CPU time 1.25 seconds
Started Aug 18 05:25:36 PM PDT 24
Finished Aug 18 05:25:38 PM PDT 24
Peak memory 200608 kb
Host smart-e2df8759-7a98-49ae-84ed-9fd585f3d959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028680171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.4028680171
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2127178087
Short name T456
Test name
Test status
Simulation time 496994115 ps
CPU time 2.71 seconds
Started Aug 18 05:25:34 PM PDT 24
Finished Aug 18 05:25:37 PM PDT 24
Peak memory 200568 kb
Host smart-054c3648-6beb-4453-b36d-bb571bb1db7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127178087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2127178087
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.289969465
Short name T491
Test name
Test status
Simulation time 233743444 ps
CPU time 1.43 seconds
Started Aug 18 05:25:30 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 200624 kb
Host smart-5b0f9e7f-df92-4201-9344-21cea825f1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289969465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.289969465
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.1442718419
Short name T391
Test name
Test status
Simulation time 71147936 ps
CPU time 0.8 seconds
Started Aug 18 05:24:43 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 200432 kb
Host smart-e6822570-11f9-492b-840f-8bd94d1ff845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442718419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1442718419
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.3100035445
Short name T273
Test name
Test status
Simulation time 2185841819 ps
CPU time 7.75 seconds
Started Aug 18 05:24:42 PM PDT 24
Finished Aug 18 05:24:50 PM PDT 24
Peak memory 221976 kb
Host smart-643aa014-7cb0-4897-8181-b0223bd7e001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100035445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3100035445
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.350709797
Short name T228
Test name
Test status
Simulation time 244861064 ps
CPU time 1.03 seconds
Started Aug 18 05:24:42 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 217676 kb
Host smart-10ea9c38-f168-4649-b0e2-958c2b18dd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350709797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.350709797
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3471383087
Short name T241
Test name
Test status
Simulation time 158248484 ps
CPU time 0.89 seconds
Started Aug 18 05:24:43 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 200440 kb
Host smart-1ada2301-41ae-4877-a4b7-d370f4aaa126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471383087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3471383087
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1227246295
Short name T171
Test name
Test status
Simulation time 1878673307 ps
CPU time 7.42 seconds
Started Aug 18 05:24:43 PM PDT 24
Finished Aug 18 05:24:50 PM PDT 24
Peak memory 200744 kb
Host smart-6bcecdbc-2b6c-46d0-aed6-12254087d0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227246295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1227246295
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2642182680
Short name T61
Test name
Test status
Simulation time 17596418348 ps
CPU time 25.4 seconds
Started Aug 18 05:24:44 PM PDT 24
Finished Aug 18 05:25:09 PM PDT 24
Peak memory 217696 kb
Host smart-761f62ba-11a7-4613-b59f-324df0d6f401
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642182680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2642182680
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1432765698
Short name T344
Test name
Test status
Simulation time 176082621 ps
CPU time 1.18 seconds
Started Aug 18 05:24:41 PM PDT 24
Finished Aug 18 05:24:42 PM PDT 24
Peak memory 200588 kb
Host smart-bf8db0e2-ab31-4ae8-9525-dad522ded216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432765698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1432765698
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.1272517649
Short name T125
Test name
Test status
Simulation time 121608747 ps
CPU time 1.18 seconds
Started Aug 18 05:24:41 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 200712 kb
Host smart-dceee778-31db-4311-9bcb-f13360724c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272517649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1272517649
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.2552040506
Short name T314
Test name
Test status
Simulation time 200330485 ps
CPU time 1.33 seconds
Started Aug 18 05:24:42 PM PDT 24
Finished Aug 18 05:24:44 PM PDT 24
Peak memory 200324 kb
Host smart-bc74dbcf-b73f-4625-926c-93760cdf3286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552040506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2552040506
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.2679046635
Short name T215
Test name
Test status
Simulation time 532288669 ps
CPU time 2.61 seconds
Started Aug 18 05:24:41 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 200500 kb
Host smart-a2a67db5-3172-43db-8afe-b5473f6b92a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679046635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2679046635
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1433717878
Short name T168
Test name
Test status
Simulation time 144904926 ps
CPU time 1.18 seconds
Started Aug 18 05:24:45 PM PDT 24
Finished Aug 18 05:24:46 PM PDT 24
Peak memory 200528 kb
Host smart-988c3da6-f2de-496c-9cc9-224db28b619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433717878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1433717878
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.1246684735
Short name T136
Test name
Test status
Simulation time 54577413 ps
CPU time 0.74 seconds
Started Aug 18 05:25:34 PM PDT 24
Finished Aug 18 05:25:35 PM PDT 24
Peak memory 200388 kb
Host smart-d4de961a-45ab-488d-804e-d5f1168813ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246684735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1246684735
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.1814239789
Short name T243
Test name
Test status
Simulation time 1240535560 ps
CPU time 5.7 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:38 PM PDT 24
Peak memory 221896 kb
Host smart-46bfdcc5-cca3-4839-be3b-3367dfcd14c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814239789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1814239789
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1392752104
Short name T386
Test name
Test status
Simulation time 244485385 ps
CPU time 1.06 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 217792 kb
Host smart-280cddfc-a892-4048-813d-0aefb5207f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392752104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1392752104
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.3571235352
Short name T490
Test name
Test status
Simulation time 101480415 ps
CPU time 0.79 seconds
Started Aug 18 05:25:37 PM PDT 24
Finished Aug 18 05:25:38 PM PDT 24
Peak memory 200420 kb
Host smart-360ecc0d-7d66-4d9a-9887-170d106a9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571235352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3571235352
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1952395060
Short name T129
Test name
Test status
Simulation time 701539985 ps
CPU time 3.71 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:37 PM PDT 24
Peak memory 200708 kb
Host smart-e35d772f-07b2-4426-9d9a-c4cd3bde1b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952395060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1952395060
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3345284796
Short name T488
Test name
Test status
Simulation time 93107728 ps
CPU time 0.98 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 200620 kb
Host smart-c76c1d8e-a875-425a-b43d-8c6e5674b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345284796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3345284796
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.758398035
Short name T307
Test name
Test status
Simulation time 120083385 ps
CPU time 1.18 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 200696 kb
Host smart-c6bd0cdc-5562-4c24-917e-831125dcf9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758398035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.758398035
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.4199354650
Short name T76
Test name
Test status
Simulation time 2680761642 ps
CPU time 13.37 seconds
Started Aug 18 05:25:34 PM PDT 24
Finished Aug 18 05:25:48 PM PDT 24
Peak memory 200848 kb
Host smart-38e56e1a-e1f3-45c2-adf7-926302224af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199354650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.4199354650
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.781354125
Short name T177
Test name
Test status
Simulation time 128372094 ps
CPU time 1.65 seconds
Started Aug 18 05:25:32 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 200516 kb
Host smart-2bc7f0c2-b5d2-4ecc-9b08-b446215f1204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781354125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.781354125
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1995268913
Short name T10
Test name
Test status
Simulation time 85273333 ps
CPU time 0.81 seconds
Started Aug 18 05:25:33 PM PDT 24
Finished Aug 18 05:25:34 PM PDT 24
Peak memory 200624 kb
Host smart-fb09b874-4980-4928-b18c-ba0b6102d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995268913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1995268913
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.3234809489
Short name T398
Test name
Test status
Simulation time 67283806 ps
CPU time 0.74 seconds
Started Aug 18 05:25:38 PM PDT 24
Finished Aug 18 05:25:39 PM PDT 24
Peak memory 200496 kb
Host smart-25297cd4-3d29-47ba-a5cc-7d027c112c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234809489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3234809489
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1737480582
Short name T276
Test name
Test status
Simulation time 1885623364 ps
CPU time 7.25 seconds
Started Aug 18 05:25:39 PM PDT 24
Finished Aug 18 05:25:46 PM PDT 24
Peak memory 217728 kb
Host smart-d4caba16-6813-4806-96f8-f1f25b4f05e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737480582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1737480582
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2684765778
Short name T399
Test name
Test status
Simulation time 243866659 ps
CPU time 1.09 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:45 PM PDT 24
Peak memory 217840 kb
Host smart-ff974a57-2799-43fa-ad59-3b5cd9a7f83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684765778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2684765778
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.3469847904
Short name T192
Test name
Test status
Simulation time 165327142 ps
CPU time 0.87 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:41 PM PDT 24
Peak memory 200420 kb
Host smart-a5ec4186-15a6-4fc3-b8e3-29b93b100352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469847904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3469847904
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.3569051125
Short name T444
Test name
Test status
Simulation time 976085784 ps
CPU time 4.82 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:45 PM PDT 24
Peak memory 200748 kb
Host smart-1b030572-62d4-4d53-9be7-34460bb8a6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569051125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3569051125
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1258549343
Short name T186
Test name
Test status
Simulation time 101858876 ps
CPU time 1.08 seconds
Started Aug 18 05:25:45 PM PDT 24
Finished Aug 18 05:25:46 PM PDT 24
Peak memory 200624 kb
Host smart-a14be3ea-efe7-4349-b07e-dc6b39460767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258549343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1258549343
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2744143150
Short name T123
Test name
Test status
Simulation time 206403969 ps
CPU time 1.36 seconds
Started Aug 18 05:25:34 PM PDT 24
Finished Aug 18 05:25:35 PM PDT 24
Peak memory 200680 kb
Host smart-46d930db-1a95-46da-a34a-8aebc5484cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744143150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2744143150
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.2953814709
Short name T68
Test name
Test status
Simulation time 2360636775 ps
CPU time 8.99 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:49 PM PDT 24
Peak memory 200820 kb
Host smart-812b9a05-4131-46a3-a9ed-c0d5ab333ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953814709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2953814709
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.1672947622
Short name T332
Test name
Test status
Simulation time 433361711 ps
CPU time 2.4 seconds
Started Aug 18 05:25:45 PM PDT 24
Finished Aug 18 05:25:48 PM PDT 24
Peak memory 208700 kb
Host smart-d7c0fd97-bb1e-4133-8ef2-53c44be1cbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672947622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1672947622
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.2326230442
Short name T438
Test name
Test status
Simulation time 230945989 ps
CPU time 1.35 seconds
Started Aug 18 05:25:41 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 200592 kb
Host smart-d232aecd-ebd1-4f80-a68e-3c3c87ba85b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326230442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2326230442
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3631040643
Short name T516
Test name
Test status
Simulation time 60912243 ps
CPU time 0.77 seconds
Started Aug 18 05:25:43 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 200500 kb
Host smart-2c38b65b-5654-4f6d-aa77-400ba3d638c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631040643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3631040643
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2819789283
Short name T406
Test name
Test status
Simulation time 2356092410 ps
CPU time 8.96 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:53 PM PDT 24
Peak memory 217980 kb
Host smart-dd525f53-3724-4c7b-a8bf-9ace0d6b1917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819789283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2819789283
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3445156006
Short name T346
Test name
Test status
Simulation time 249858557 ps
CPU time 1.09 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:41 PM PDT 24
Peak memory 217792 kb
Host smart-0fb14ae5-e89a-4d8c-9a9e-822449879447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445156006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3445156006
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.343030674
Short name T449
Test name
Test status
Simulation time 127694075 ps
CPU time 0.81 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:49 PM PDT 24
Peak memory 200440 kb
Host smart-4400e89f-aa85-4c0d-82fd-575ca3f82837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343030674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.343030674
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.3807388088
Short name T514
Test name
Test status
Simulation time 758318690 ps
CPU time 4.11 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 200632 kb
Host smart-3e40aedb-a05c-4f2e-ba4b-bf53859bac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807388088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3807388088
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.77370882
Short name T236
Test name
Test status
Simulation time 144452782 ps
CPU time 1.17 seconds
Started Aug 18 05:25:41 PM PDT 24
Finished Aug 18 05:25:43 PM PDT 24
Peak memory 200524 kb
Host smart-be651896-6bee-4aff-bb9c-3f4e899049e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77370882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.77370882
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.4254413725
Short name T156
Test name
Test status
Simulation time 107363971 ps
CPU time 1.12 seconds
Started Aug 18 05:25:38 PM PDT 24
Finished Aug 18 05:25:40 PM PDT 24
Peak memory 200604 kb
Host smart-5fcb4110-29b6-4f93-90de-48f7c21e333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254413725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4254413725
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.1633342006
Short name T240
Test name
Test status
Simulation time 8689050665 ps
CPU time 31.68 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:26:12 PM PDT 24
Peak memory 209044 kb
Host smart-5dd09961-f2ce-4c83-8dc8-45430fc1f529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633342006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1633342006
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1410903669
Short name T146
Test name
Test status
Simulation time 119230969 ps
CPU time 1.57 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:41 PM PDT 24
Peak memory 200480 kb
Host smart-ca0a28c6-3c0a-4251-89ae-5cac4bd4ed47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410903669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1410903669
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.894851737
Short name T22
Test name
Test status
Simulation time 68874116 ps
CPU time 0.77 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:45 PM PDT 24
Peak memory 200600 kb
Host smart-fde017b3-8920-4e02-9d86-8bda07af5ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894851737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.894851737
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.3450716665
Short name T36
Test name
Test status
Simulation time 91742248 ps
CPU time 0.84 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:49 PM PDT 24
Peak memory 200504 kb
Host smart-4bfaa7f9-c231-4914-8671-23890608b434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450716665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3450716665
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.239834801
Short name T513
Test name
Test status
Simulation time 1222123560 ps
CPU time 5.65 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:50 PM PDT 24
Peak memory 221052 kb
Host smart-083844a9-8c8d-433e-90df-f31842e7f5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239834801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.239834801
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3171397956
Short name T481
Test name
Test status
Simulation time 243652271 ps
CPU time 1.17 seconds
Started Aug 18 05:25:41 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 217800 kb
Host smart-971b856e-9fc5-40e0-b327-9049c161bb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171397956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3171397956
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.877135451
Short name T361
Test name
Test status
Simulation time 205496029 ps
CPU time 0.94 seconds
Started Aug 18 05:25:50 PM PDT 24
Finished Aug 18 05:25:51 PM PDT 24
Peak memory 200464 kb
Host smart-d1c4e3f8-36c2-4b8d-a454-43295d381370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877135451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.877135451
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.1449416877
Short name T199
Test name
Test status
Simulation time 1435999512 ps
CPU time 5.53 seconds
Started Aug 18 05:25:42 PM PDT 24
Finished Aug 18 05:25:47 PM PDT 24
Peak memory 200700 kb
Host smart-123e006b-fc6a-4add-a6d9-93745f622ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449416877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1449416877
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1131725218
Short name T267
Test name
Test status
Simulation time 151494564 ps
CPU time 1.19 seconds
Started Aug 18 05:25:43 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 200616 kb
Host smart-d09d85d5-6651-4c1c-b7aa-030356de173a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131725218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1131725218
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1181508641
Short name T181
Test name
Test status
Simulation time 112896856 ps
CPU time 1.23 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:49 PM PDT 24
Peak memory 200720 kb
Host smart-ae891b31-d5c5-40c2-83f9-aefced3ec892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181508641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1181508641
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3939916151
Short name T337
Test name
Test status
Simulation time 7452960688 ps
CPU time 31.38 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 209044 kb
Host smart-c06a3ffd-9f29-4efe-8e7d-a3e36d671ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939916151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3939916151
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3044511714
Short name T470
Test name
Test status
Simulation time 123659930 ps
CPU time 1.56 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 200464 kb
Host smart-d3e24b34-9109-4a93-93e3-b5db1255ac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044511714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3044511714
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.3220900178
Short name T257
Test name
Test status
Simulation time 116857498 ps
CPU time 1 seconds
Started Aug 18 05:25:45 PM PDT 24
Finished Aug 18 05:25:46 PM PDT 24
Peak memory 200628 kb
Host smart-a8b9491a-5c8c-42a3-b67a-d3f32e76d3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220900178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3220900178
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.2776338479
Short name T227
Test name
Test status
Simulation time 71830747 ps
CPU time 0.75 seconds
Started Aug 18 05:25:46 PM PDT 24
Finished Aug 18 05:25:47 PM PDT 24
Peak memory 200488 kb
Host smart-2bf0dfec-132c-48b4-ba83-e33369c404d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776338479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2776338479
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.97779735
Short name T48
Test name
Test status
Simulation time 2357053026 ps
CPU time 9.28 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:57 PM PDT 24
Peak memory 221984 kb
Host smart-a7099ad6-caeb-4e80-8b1a-5db6cb2f5f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97779735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.97779735
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.2382028561
Short name T259
Test name
Test status
Simulation time 244820481 ps
CPU time 1.12 seconds
Started Aug 18 05:25:43 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 217792 kb
Host smart-bc2a774d-b3f1-445a-9486-0e2dbbd715c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382028561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.2382028561
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.26316655
Short name T225
Test name
Test status
Simulation time 187703385 ps
CPU time 0.94 seconds
Started Aug 18 05:25:41 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 200428 kb
Host smart-19e76eb3-e15f-40e0-9a32-6c3a3a0cae94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26316655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.26316655
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.430410024
Short name T66
Test name
Test status
Simulation time 1047673224 ps
CPU time 4.81 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:45 PM PDT 24
Peak memory 200764 kb
Host smart-2e42af7c-f582-4daf-9148-938005c2bed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430410024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.430410024
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.1221092953
Short name T293
Test name
Test status
Simulation time 106664924 ps
CPU time 0.98 seconds
Started Aug 18 05:25:41 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 200824 kb
Host smart-26be75f8-a480-4601-932a-6ac7c54a0709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221092953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.1221092953
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3089567833
Short name T37
Test name
Test status
Simulation time 190116339 ps
CPU time 1.39 seconds
Started Aug 18 05:25:47 PM PDT 24
Finished Aug 18 05:25:48 PM PDT 24
Peak memory 200788 kb
Host smart-d89ba20e-8622-4df6-bbd4-1e897d850488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089567833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3089567833
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.892688051
Short name T320
Test name
Test status
Simulation time 1976635014 ps
CPU time 10.52 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:54 PM PDT 24
Peak memory 200764 kb
Host smart-239141fa-30bf-4854-9303-77fe018dd013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892688051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.892688051
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.850070813
Short name T207
Test name
Test status
Simulation time 287956756 ps
CPU time 1.91 seconds
Started Aug 18 05:25:42 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 200420 kb
Host smart-0c6d1091-9139-4bf0-9dbb-2d81d2f0e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850070813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.850070813
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.466972692
Short name T328
Test name
Test status
Simulation time 83453789 ps
CPU time 0.86 seconds
Started Aug 18 05:25:43 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 200616 kb
Host smart-3eeb90a2-3be3-42df-a642-ecbf14c0939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466972692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.466972692
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1532875753
Short name T303
Test name
Test status
Simulation time 66869047 ps
CPU time 0.83 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:45 PM PDT 24
Peak memory 200408 kb
Host smart-a51c2a80-c73e-4929-9303-4c29b7257548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532875753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1532875753
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3974914277
Short name T31
Test name
Test status
Simulation time 1227369540 ps
CPU time 5.55 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:50 PM PDT 24
Peak memory 217948 kb
Host smart-8ab0c0cd-6557-49bb-bdf1-fd0c6adbbe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974914277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3974914277
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3469116005
Short name T193
Test name
Test status
Simulation time 244234663 ps
CPU time 1.09 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:25:41 PM PDT 24
Peak memory 217796 kb
Host smart-1fdafba8-28c9-44e3-a45d-0ab0d07ce926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469116005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3469116005
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.3050131609
Short name T376
Test name
Test status
Simulation time 142327935 ps
CPU time 0.82 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:45 PM PDT 24
Peak memory 200416 kb
Host smart-7a152949-5c4d-4aa9-b9b6-8a817c01a7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050131609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3050131609
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3427095848
Short name T492
Test name
Test status
Simulation time 1370708401 ps
CPU time 5.54 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:50 PM PDT 24
Peak memory 200688 kb
Host smart-698882dd-6a42-426e-8f63-ac9f88e4d50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427095848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3427095848
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.473346008
Short name T362
Test name
Test status
Simulation time 168992579 ps
CPU time 1.13 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:46 PM PDT 24
Peak memory 200612 kb
Host smart-c94ce3b2-f3e3-4418-8d8a-a9f20fdc5f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473346008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.473346008
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.2522149482
Short name T163
Test name
Test status
Simulation time 244950849 ps
CPU time 1.53 seconds
Started Aug 18 05:25:39 PM PDT 24
Finished Aug 18 05:25:40 PM PDT 24
Peak memory 200716 kb
Host smart-117f21da-bafb-47f4-ba72-536cd893504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522149482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2522149482
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.3200549430
Short name T34
Test name
Test status
Simulation time 7385080638 ps
CPU time 35.38 seconds
Started Aug 18 05:25:40 PM PDT 24
Finished Aug 18 05:26:15 PM PDT 24
Peak memory 200852 kb
Host smart-e6800cae-b883-46b6-80cc-a6673dc259e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200549430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3200549430
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.3694116149
Short name T420
Test name
Test status
Simulation time 334448325 ps
CPU time 1.9 seconds
Started Aug 18 05:25:43 PM PDT 24
Finished Aug 18 05:25:45 PM PDT 24
Peak memory 200524 kb
Host smart-13449026-1137-439d-8aa9-c4a73cb3ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694116149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3694116149
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.1804915334
Short name T119
Test name
Test status
Simulation time 187952957 ps
CPU time 1.21 seconds
Started Aug 18 05:25:44 PM PDT 24
Finished Aug 18 05:25:45 PM PDT 24
Peak memory 200536 kb
Host smart-12d3900f-3867-4c41-b4e9-cfecc2b8f3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804915334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1804915334
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2515778675
Short name T296
Test name
Test status
Simulation time 70118548 ps
CPU time 0.81 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:49 PM PDT 24
Peak memory 200500 kb
Host smart-e3521211-5cb1-46d3-8f84-4d68bd193b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515778675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2515778675
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.506693427
Short name T26
Test name
Test status
Simulation time 1896587656 ps
CPU time 7.86 seconds
Started Aug 18 05:25:49 PM PDT 24
Finished Aug 18 05:25:57 PM PDT 24
Peak memory 221932 kb
Host smart-13bb05c1-f0af-4319-83d7-fb1109008910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506693427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.506693427
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3566497589
Short name T302
Test name
Test status
Simulation time 245326121 ps
CPU time 1.04 seconds
Started Aug 18 05:25:49 PM PDT 24
Finished Aug 18 05:25:50 PM PDT 24
Peak memory 217736 kb
Host smart-6ffd8b99-01e8-4f54-a69e-757ea79da9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566497589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3566497589
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3781441059
Short name T245
Test name
Test status
Simulation time 120958158 ps
CPU time 0.8 seconds
Started Aug 18 05:25:42 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 200440 kb
Host smart-8701a553-b7c0-4b55-9424-e60ea7d04fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781441059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3781441059
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.4147612167
Short name T421
Test name
Test status
Simulation time 1848920278 ps
CPU time 6.58 seconds
Started Aug 18 05:25:46 PM PDT 24
Finished Aug 18 05:25:53 PM PDT 24
Peak memory 200800 kb
Host smart-ffeb1f35-1a3f-4834-adb5-618affeb6b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147612167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4147612167
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.4017923018
Short name T474
Test name
Test status
Simulation time 106913862 ps
CPU time 1.06 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:49 PM PDT 24
Peak memory 200628 kb
Host smart-2d3929ec-1fec-4c13-9841-c8ed5b7fbd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017923018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.4017923018
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.639899581
Short name T455
Test name
Test status
Simulation time 122991780 ps
CPU time 1.2 seconds
Started Aug 18 05:25:46 PM PDT 24
Finished Aug 18 05:25:47 PM PDT 24
Peak memory 200700 kb
Host smart-7af8ebc7-d727-46ac-bd80-9b9f84109ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639899581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.639899581
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.71846422
Short name T539
Test name
Test status
Simulation time 6087492716 ps
CPU time 22.98 seconds
Started Aug 18 05:25:50 PM PDT 24
Finished Aug 18 05:26:13 PM PDT 24
Peak memory 199612 kb
Host smart-003f78af-413b-49fd-9295-52a394e3b142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71846422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.71846422
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.1504779860
Short name T464
Test name
Test status
Simulation time 408914699 ps
CPU time 2.34 seconds
Started Aug 18 05:25:41 PM PDT 24
Finished Aug 18 05:25:44 PM PDT 24
Peak memory 208620 kb
Host smart-1411ae12-11fa-4b8e-a2ee-406a59236f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504779860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1504779860
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2555386464
Short name T135
Test name
Test status
Simulation time 141397157 ps
CPU time 1.2 seconds
Started Aug 18 05:25:42 PM PDT 24
Finished Aug 18 05:25:43 PM PDT 24
Peak memory 200524 kb
Host smart-c1f77f9f-1dd7-4acf-ac88-f7dea1215b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555386464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2555386464
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.3091430762
Short name T457
Test name
Test status
Simulation time 56538081 ps
CPU time 0.73 seconds
Started Aug 18 05:25:49 PM PDT 24
Finished Aug 18 05:25:49 PM PDT 24
Peak memory 200392 kb
Host smart-c6074f09-e648-4064-be1c-c0ec3676eccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091430762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3091430762
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.3987666748
Short name T443
Test name
Test status
Simulation time 1889884278 ps
CPU time 7.16 seconds
Started Aug 18 05:25:49 PM PDT 24
Finished Aug 18 05:25:56 PM PDT 24
Peak memory 217708 kb
Host smart-e0793959-962e-4879-9a82-436a11300c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987666748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.3987666748
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.278017493
Short name T316
Test name
Test status
Simulation time 244202958 ps
CPU time 1.08 seconds
Started Aug 18 05:25:50 PM PDT 24
Finished Aug 18 05:25:51 PM PDT 24
Peak memory 217812 kb
Host smart-26332de6-0f5c-4cd4-911f-94d7f72c859e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278017493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.278017493
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3882613771
Short name T13
Test name
Test status
Simulation time 135279264 ps
CPU time 0.86 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:49 PM PDT 24
Peak memory 200432 kb
Host smart-cab4de8f-8514-486d-a0d2-f2cdfdee631c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882613771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3882613771
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.2967101480
Short name T38
Test name
Test status
Simulation time 1816081178 ps
CPU time 6.83 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:55 PM PDT 24
Peak memory 200812 kb
Host smart-be1726e9-c6bc-4f6a-bce0-49f450ed71b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967101480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2967101480
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.730554405
Short name T450
Test name
Test status
Simulation time 96623319 ps
CPU time 1.05 seconds
Started Aug 18 05:25:50 PM PDT 24
Finished Aug 18 05:25:51 PM PDT 24
Peak memory 199420 kb
Host smart-51008430-f1d0-44c5-9081-5747c4090c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730554405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.730554405
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.1884405499
Short name T331
Test name
Test status
Simulation time 117580190 ps
CPU time 1.22 seconds
Started Aug 18 05:25:50 PM PDT 24
Finished Aug 18 05:25:51 PM PDT 24
Peak memory 200684 kb
Host smart-1c98bda7-6735-4f71-b81e-2ed43bbc6ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884405499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1884405499
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3199665225
Short name T485
Test name
Test status
Simulation time 9729274257 ps
CPU time 35.76 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 209040 kb
Host smart-33148417-309e-41a7-9366-95c27c72919b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199665225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3199665225
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.4208875639
Short name T223
Test name
Test status
Simulation time 155490945 ps
CPU time 1.88 seconds
Started Aug 18 05:25:52 PM PDT 24
Finished Aug 18 05:25:54 PM PDT 24
Peak memory 200520 kb
Host smart-95e2da13-7666-4df1-a48c-e363f829dca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208875639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4208875639
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.3783876726
Short name T198
Test name
Test status
Simulation time 100108856 ps
CPU time 0.95 seconds
Started Aug 18 05:25:50 PM PDT 24
Finished Aug 18 05:25:51 PM PDT 24
Peak memory 200592 kb
Host smart-9ed620cb-7ae6-4bcb-9748-8cb091909a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783876726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3783876726
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.2326143912
Short name T360
Test name
Test status
Simulation time 61612117 ps
CPU time 0.75 seconds
Started Aug 18 05:26:01 PM PDT 24
Finished Aug 18 05:26:02 PM PDT 24
Peak memory 200492 kb
Host smart-0d3a6a14-4910-45f6-a656-688e20524c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326143912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2326143912
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1304944541
Short name T24
Test name
Test status
Simulation time 1883002690 ps
CPU time 7.12 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:26:05 PM PDT 24
Peak memory 217984 kb
Host smart-45349025-2efe-4d97-a3fe-95d34082c65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304944541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1304944541
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3183473816
Short name T529
Test name
Test status
Simulation time 244039265 ps
CPU time 1.15 seconds
Started Aug 18 05:26:02 PM PDT 24
Finished Aug 18 05:26:03 PM PDT 24
Peak memory 217876 kb
Host smart-6b7dc0d3-665e-48ab-a388-c33759f1a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183473816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3183473816
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2284897465
Short name T15
Test name
Test status
Simulation time 166249159 ps
CPU time 0.9 seconds
Started Aug 18 05:25:50 PM PDT 24
Finished Aug 18 05:25:51 PM PDT 24
Peak memory 200400 kb
Host smart-f71d6b2c-e616-4e0b-a307-050cc3b64d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284897465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2284897465
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3304959660
Short name T410
Test name
Test status
Simulation time 927451847 ps
CPU time 4.85 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:04 PM PDT 24
Peak memory 200800 kb
Host smart-5c6402ca-5447-40cd-8ebe-53bf7d1fa6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304959660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3304959660
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3236758256
Short name T440
Test name
Test status
Simulation time 192650769 ps
CPU time 1.18 seconds
Started Aug 18 05:26:02 PM PDT 24
Finished Aug 18 05:26:03 PM PDT 24
Peak memory 200628 kb
Host smart-df9a3cab-1a39-4db0-8f18-308349ab13c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236758256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3236758256
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.651533337
Short name T471
Test name
Test status
Simulation time 197286481 ps
CPU time 1.46 seconds
Started Aug 18 05:25:48 PM PDT 24
Finished Aug 18 05:25:50 PM PDT 24
Peak memory 200576 kb
Host smart-1a8d8b6d-cbac-449e-a497-afeaf9e4a5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651533337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.651533337
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.299285265
Short name T496
Test name
Test status
Simulation time 4144971628 ps
CPU time 17.97 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 209100 kb
Host smart-1b3bf3b4-4a9a-41e9-a30b-bbf7764bade1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299285265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.299285265
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.1371032837
Short name T429
Test name
Test status
Simulation time 172355871 ps
CPU time 1.41 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 200700 kb
Host smart-bfb90d11-bde5-41f5-81e4-7b8f31bfb4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371032837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1371032837
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.908874594
Short name T384
Test name
Test status
Simulation time 73399848 ps
CPU time 0.81 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:25:59 PM PDT 24
Peak memory 200468 kb
Host smart-83f794ed-ebc2-4105-81e8-3b8452130163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908874594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.908874594
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.1820082314
Short name T41
Test name
Test status
Simulation time 1233581702 ps
CPU time 5.48 seconds
Started Aug 18 05:26:00 PM PDT 24
Finished Aug 18 05:26:05 PM PDT 24
Peak memory 217016 kb
Host smart-82332ce2-f8d5-4a1b-9f86-84de41aeba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820082314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1820082314
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2209715549
Short name T500
Test name
Test status
Simulation time 244572036 ps
CPU time 1.05 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:25:59 PM PDT 24
Peak memory 217820 kb
Host smart-8de381d6-59bd-4d63-a8f5-b41221de172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209715549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2209715549
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1616718675
Short name T200
Test name
Test status
Simulation time 179404347 ps
CPU time 0.94 seconds
Started Aug 18 05:26:00 PM PDT 24
Finished Aug 18 05:26:01 PM PDT 24
Peak memory 200384 kb
Host smart-a0cbf0d3-842e-4bbb-8ca6-ef1084bbb81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616718675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1616718675
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.4201558002
Short name T389
Test name
Test status
Simulation time 1721500155 ps
CPU time 6.31 seconds
Started Aug 18 05:26:00 PM PDT 24
Finished Aug 18 05:26:07 PM PDT 24
Peak memory 200800 kb
Host smart-45679cee-9f7e-40b1-adc7-6810f87e41b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201558002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4201558002
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1563321597
Short name T428
Test name
Test status
Simulation time 174828185 ps
CPU time 1.16 seconds
Started Aug 18 05:25:56 PM PDT 24
Finished Aug 18 05:25:57 PM PDT 24
Peak memory 200620 kb
Host smart-69b438e7-a998-4923-ba0a-145a1eb662de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563321597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1563321597
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.1914212597
Short name T466
Test name
Test status
Simulation time 111946302 ps
CPU time 1.21 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 200700 kb
Host smart-23de732b-fde4-49ea-aa60-831a1dca0ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914212597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1914212597
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.4201505194
Short name T288
Test name
Test status
Simulation time 1835790194 ps
CPU time 6.97 seconds
Started Aug 18 05:25:57 PM PDT 24
Finished Aug 18 05:26:04 PM PDT 24
Peak memory 200716 kb
Host smart-b7d092a1-c69b-4616-bf06-798e2f01e8d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201505194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.4201505194
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3025846745
Short name T461
Test name
Test status
Simulation time 129195701 ps
CPU time 1.66 seconds
Started Aug 18 05:25:57 PM PDT 24
Finished Aug 18 05:25:59 PM PDT 24
Peak memory 200512 kb
Host smart-886d1d09-0ceb-4799-a0b2-2370b8ec7bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025846745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3025846745
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1272112267
Short name T109
Test name
Test status
Simulation time 118327666 ps
CPU time 0.94 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 200616 kb
Host smart-63dcee4f-a7c2-479a-9cd4-c203c1e99751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272112267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1272112267
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1326471568
Short name T147
Test name
Test status
Simulation time 75372299 ps
CPU time 0.8 seconds
Started Aug 18 05:24:49 PM PDT 24
Finished Aug 18 05:24:50 PM PDT 24
Peak memory 200492 kb
Host smart-0d8641eb-3895-40e2-8f41-251a6070c89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326471568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1326471568
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.3030141027
Short name T423
Test name
Test status
Simulation time 1882540657 ps
CPU time 7.16 seconds
Started Aug 18 05:24:49 PM PDT 24
Finished Aug 18 05:24:57 PM PDT 24
Peak memory 217908 kb
Host smart-a3b938cb-8138-42e1-b9f6-9569cc38fcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030141027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3030141027
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2982917192
Short name T535
Test name
Test status
Simulation time 244322842 ps
CPU time 1.04 seconds
Started Aug 18 05:24:52 PM PDT 24
Finished Aug 18 05:24:54 PM PDT 24
Peak memory 217780 kb
Host smart-c417a1b5-b9e2-48d1-b796-3184a23e6d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982917192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2982917192
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.289730417
Short name T286
Test name
Test status
Simulation time 146861517 ps
CPU time 0.85 seconds
Started Aug 18 05:24:53 PM PDT 24
Finished Aug 18 05:24:54 PM PDT 24
Peak memory 200336 kb
Host smart-78dce00f-fe3a-49b3-863d-9ab120d63dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289730417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.289730417
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.301253401
Short name T324
Test name
Test status
Simulation time 1619415248 ps
CPU time 5.88 seconds
Started Aug 18 05:24:55 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 200716 kb
Host smart-a0c9beb8-0061-430c-91c1-825224dfde6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301253401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.301253401
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.2563009386
Short name T64
Test name
Test status
Simulation time 8312189330 ps
CPU time 13.35 seconds
Started Aug 18 05:24:50 PM PDT 24
Finished Aug 18 05:25:03 PM PDT 24
Peak memory 217396 kb
Host smart-7f01628e-a7a6-4d34-b653-99de890809f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563009386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2563009386
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3849973719
Short name T191
Test name
Test status
Simulation time 116163494 ps
CPU time 1.04 seconds
Started Aug 18 05:24:51 PM PDT 24
Finished Aug 18 05:24:53 PM PDT 24
Peak memory 200624 kb
Host smart-dd4d7e16-c60f-4cbc-98d8-c142c620b29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849973719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3849973719
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.1073417982
Short name T523
Test name
Test status
Simulation time 251445457 ps
CPU time 1.54 seconds
Started Aug 18 05:24:50 PM PDT 24
Finished Aug 18 05:24:52 PM PDT 24
Peak memory 200788 kb
Host smart-5a29cb70-f082-41b0-9b32-3b8615047bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073417982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1073417982
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1309400372
Short name T329
Test name
Test status
Simulation time 2893715625 ps
CPU time 11.35 seconds
Started Aug 18 05:24:51 PM PDT 24
Finished Aug 18 05:25:02 PM PDT 24
Peak memory 200756 kb
Host smart-8aac7125-4659-47dc-92e2-9296f9cdbf1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309400372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1309400372
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.1805341503
Short name T411
Test name
Test status
Simulation time 123110324 ps
CPU time 1.44 seconds
Started Aug 18 05:24:50 PM PDT 24
Finished Aug 18 05:24:52 PM PDT 24
Peak memory 200532 kb
Host smart-d2cd437f-e624-4096-82ba-358bc9a6fa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805341503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1805341503
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.2411243993
Short name T190
Test name
Test status
Simulation time 110607997 ps
CPU time 0.95 seconds
Started Aug 18 05:24:50 PM PDT 24
Finished Aug 18 05:24:51 PM PDT 24
Peak memory 200528 kb
Host smart-84e7df8a-0302-4cc1-8c3c-f3744f5b5eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411243993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2411243993
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.3400506347
Short name T326
Test name
Test status
Simulation time 64530468 ps
CPU time 0.79 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 200476 kb
Host smart-07b23359-fb11-470d-b9bd-c8593122b66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400506347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3400506347
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1743819016
Short name T28
Test name
Test status
Simulation time 1227337164 ps
CPU time 5.67 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:05 PM PDT 24
Peak memory 221788 kb
Host smart-166c7eb6-34c8-4cbf-8fd8-50798807915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743819016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1743819016
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3752827395
Short name T472
Test name
Test status
Simulation time 244290621 ps
CPU time 1.04 seconds
Started Aug 18 05:26:01 PM PDT 24
Finished Aug 18 05:26:02 PM PDT 24
Peak memory 217844 kb
Host smart-7b3b9044-3982-439d-be47-94d00e39cf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752827395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3752827395
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.1740198231
Short name T319
Test name
Test status
Simulation time 241065150 ps
CPU time 0.96 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 200328 kb
Host smart-8f46d06f-728e-458b-af6c-fad37d53fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740198231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1740198231
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.2555966628
Short name T197
Test name
Test status
Simulation time 1178126058 ps
CPU time 4.81 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:26:03 PM PDT 24
Peak memory 200800 kb
Host smart-c8f2c6fa-dec3-4936-b6bd-25618c6f4c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555966628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2555966628
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1612022732
Short name T217
Test name
Test status
Simulation time 145947888 ps
CPU time 1.14 seconds
Started Aug 18 05:26:01 PM PDT 24
Finished Aug 18 05:26:03 PM PDT 24
Peak memory 200620 kb
Host smart-351ebc7a-5049-4fa2-b208-2bcc6fecd581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612022732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1612022732
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.2745578273
Short name T289
Test name
Test status
Simulation time 249414985 ps
CPU time 1.51 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:01 PM PDT 24
Peak memory 200728 kb
Host smart-22197992-540b-44f8-8cbe-de9863b38a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745578273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2745578273
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.1947014910
Short name T107
Test name
Test status
Simulation time 10913665513 ps
CPU time 37.31 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:26:35 PM PDT 24
Peak memory 200864 kb
Host smart-8a7b66e2-b599-4795-a3d1-ac45e381561f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947014910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1947014910
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3179559045
Short name T162
Test name
Test status
Simulation time 120190179 ps
CPU time 1.49 seconds
Started Aug 18 05:26:00 PM PDT 24
Finished Aug 18 05:26:02 PM PDT 24
Peak memory 200480 kb
Host smart-f8da5efd-3f0b-40e5-ac04-d154cb937b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179559045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3179559045
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.3116800474
Short name T499
Test name
Test status
Simulation time 200700475 ps
CPU time 1.26 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:25:59 PM PDT 24
Peak memory 200484 kb
Host smart-51009651-ec31-43a7-9aea-aa5cba3bf148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116800474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3116800474
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.18486837
Short name T263
Test name
Test status
Simulation time 80243721 ps
CPU time 0.83 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 200480 kb
Host smart-9c94bfcf-f608-418f-927b-ab373a25981a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18486837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.18486837
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.3549031456
Short name T32
Test name
Test status
Simulation time 1890375768 ps
CPU time 7.2 seconds
Started Aug 18 05:25:57 PM PDT 24
Finished Aug 18 05:26:05 PM PDT 24
Peak memory 217216 kb
Host smart-de615668-7d60-4b2e-81c5-e02e88050cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549031456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3549031456
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.73292008
Short name T131
Test name
Test status
Simulation time 249276805 ps
CPU time 1.09 seconds
Started Aug 18 05:25:58 PM PDT 24
Finished Aug 18 05:25:59 PM PDT 24
Peak memory 217736 kb
Host smart-503221bb-f405-4615-8c94-153acbada09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73292008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.73292008
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1340259296
Short name T18
Test name
Test status
Simulation time 199941666 ps
CPU time 0.9 seconds
Started Aug 18 05:26:01 PM PDT 24
Finished Aug 18 05:26:02 PM PDT 24
Peak memory 200436 kb
Host smart-37cd3a70-1778-4eb2-84bf-bb2936a35174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340259296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1340259296
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.2087848923
Short name T3
Test name
Test status
Simulation time 899168835 ps
CPU time 4.75 seconds
Started Aug 18 05:26:02 PM PDT 24
Finished Aug 18 05:26:07 PM PDT 24
Peak memory 200812 kb
Host smart-29fcafd4-96b1-408e-aa66-08515d6f585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087848923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.2087848923
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.887997045
Short name T226
Test name
Test status
Simulation time 102734678 ps
CPU time 0.96 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 200568 kb
Host smart-c4936f22-c023-4f93-8d3d-edd7f27c3928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887997045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.887997045
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.1588638823
Short name T179
Test name
Test status
Simulation time 115783387 ps
CPU time 1.17 seconds
Started Aug 18 05:25:59 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 200752 kb
Host smart-4fa3eaad-f7ba-4e26-a3b5-c07e184199d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588638823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1588638823
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.2887708169
Short name T495
Test name
Test status
Simulation time 7133671478 ps
CPU time 33.98 seconds
Started Aug 18 05:26:00 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 200864 kb
Host smart-53a6b724-b731-4442-a6cc-f1cd58b77f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887708169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2887708169
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.561627304
Short name T110
Test name
Test status
Simulation time 478957958 ps
CPU time 2.76 seconds
Started Aug 18 05:26:00 PM PDT 24
Finished Aug 18 05:26:03 PM PDT 24
Peak memory 200492 kb
Host smart-a3519e4a-0c82-4ed1-95d8-658e8dc6f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561627304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.561627304
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.2108401949
Short name T269
Test name
Test status
Simulation time 235481978 ps
CPU time 1.5 seconds
Started Aug 18 05:26:01 PM PDT 24
Finished Aug 18 05:26:03 PM PDT 24
Peak memory 200716 kb
Host smart-4b87c799-ea82-4c77-ae6b-4919ccc6ae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108401949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2108401949
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.598153894
Short name T415
Test name
Test status
Simulation time 61412615 ps
CPU time 0.79 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:09 PM PDT 24
Peak memory 200464 kb
Host smart-7af1d38f-4d5d-4f7d-987d-f2761562ad3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598153894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.598153894
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.2280590279
Short name T390
Test name
Test status
Simulation time 1221256337 ps
CPU time 5.38 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:14 PM PDT 24
Peak memory 220252 kb
Host smart-63f80936-e394-4907-a947-7b7346393add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280590279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2280590279
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2064670554
Short name T152
Test name
Test status
Simulation time 244578131 ps
CPU time 1.09 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 216396 kb
Host smart-d47aa665-0e78-4df9-bea1-cc35ae87a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064670554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2064670554
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3428279477
Short name T20
Test name
Test status
Simulation time 180114520 ps
CPU time 0.97 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200432 kb
Host smart-747064aa-e061-4b46-8e48-b0b49e990ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428279477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3428279477
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.2069029347
Short name T70
Test name
Test status
Simulation time 735985254 ps
CPU time 3.91 seconds
Started Aug 18 05:26:05 PM PDT 24
Finished Aug 18 05:26:09 PM PDT 24
Peak memory 200772 kb
Host smart-c8ac366a-ce8b-4d87-92a4-b70d7be473b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069029347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2069029347
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2556727524
Short name T133
Test name
Test status
Simulation time 104913179 ps
CPU time 1.02 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200540 kb
Host smart-06d91721-eea1-4144-80de-375b5fcf4384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556727524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2556727524
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.1660531383
Short name T208
Test name
Test status
Simulation time 117163907 ps
CPU time 1.16 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:09 PM PDT 24
Peak memory 200720 kb
Host smart-aaa9e3cd-b663-4c79-a523-8a910bbf2d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660531383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.1660531383
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.3867421415
Short name T339
Test name
Test status
Simulation time 8351059573 ps
CPU time 38.16 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:46 PM PDT 24
Peak memory 200832 kb
Host smart-1d158919-8251-47d8-8d79-089782f641a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867421415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3867421415
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1318872333
Short name T512
Test name
Test status
Simulation time 363957101 ps
CPU time 2.31 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200484 kb
Host smart-ca0202c7-2a37-4083-ac40-9a69999654dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318872333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1318872333
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.2138943936
Short name T154
Test name
Test status
Simulation time 185372906 ps
CPU time 1.16 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200604 kb
Host smart-12a46433-c17a-4745-805d-094400fcd90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138943936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2138943936
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.190461085
Short name T445
Test name
Test status
Simulation time 86412525 ps
CPU time 0.89 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:09 PM PDT 24
Peak memory 200444 kb
Host smart-5976bccf-9524-422b-af53-6fcd48592b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190461085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.190461085
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.170005110
Short name T349
Test name
Test status
Simulation time 1876888151 ps
CPU time 7.82 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 217588 kb
Host smart-a06f82e9-c093-41c4-afb4-5c8ca7e25183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170005110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.170005110
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3422073406
Short name T501
Test name
Test status
Simulation time 244032119 ps
CPU time 1.11 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:09 PM PDT 24
Peak memory 217656 kb
Host smart-7d22f16f-7a82-4b8c-94ac-2176184cc51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422073406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3422073406
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3427805944
Short name T536
Test name
Test status
Simulation time 237996936 ps
CPU time 0.94 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200396 kb
Host smart-3b2cdef2-630f-4d2a-a2a9-25b384afb938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427805944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3427805944
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1474567112
Short name T175
Test name
Test status
Simulation time 923629458 ps
CPU time 5.35 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:14 PM PDT 24
Peak memory 200812 kb
Host smart-4d4c5fff-28cc-4644-bb71-c1183615d4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474567112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1474567112
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3422053766
Short name T264
Test name
Test status
Simulation time 145693903 ps
CPU time 1.1 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 200588 kb
Host smart-0b009997-cb7c-4f91-8663-a1e1ae830ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422053766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3422053766
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.620860958
Short name T509
Test name
Test status
Simulation time 199196704 ps
CPU time 1.38 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200788 kb
Host smart-1a3512dd-a5e2-4d1c-a9b8-dd1fb10804a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620860958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.620860958
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1136958716
Short name T73
Test name
Test status
Simulation time 14556651323 ps
CPU time 46.51 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:54 PM PDT 24
Peak memory 201036 kb
Host smart-bd554952-f015-4e40-b5bc-f021a51af3e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136958716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1136958716
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.3147116057
Short name T126
Test name
Test status
Simulation time 142791103 ps
CPU time 1.98 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:11 PM PDT 24
Peak memory 200524 kb
Host smart-620c6b9e-eea3-43c1-8205-ae8cbb984dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147116057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.3147116057
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.2903746501
Short name T528
Test name
Test status
Simulation time 80204847 ps
CPU time 0.86 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 200632 kb
Host smart-477a6b07-27f0-48e4-abb7-ad2011794bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903746501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.2903746501
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2863372344
Short name T300
Test name
Test status
Simulation time 70108265 ps
CPU time 0.74 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200472 kb
Host smart-4ad80b34-a95e-4921-8e70-31f741eb5b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863372344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2863372344
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.4044089525
Short name T387
Test name
Test status
Simulation time 1218578752 ps
CPU time 5.29 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:12 PM PDT 24
Peak memory 217504 kb
Host smart-f3ed2d42-e3a1-4b1e-a1c9-00619be01276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044089525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.4044089525
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3690534358
Short name T335
Test name
Test status
Simulation time 244787028 ps
CPU time 1.1 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 217828 kb
Host smart-5b0b87f5-0e57-4b16-a656-5e2f7cf4d224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690534358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3690534358
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2917908117
Short name T480
Test name
Test status
Simulation time 71912345 ps
CPU time 0.72 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200384 kb
Host smart-bd3d040e-0fd2-437f-8342-2feeaf60049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917908117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2917908117
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2607482711
Short name T414
Test name
Test status
Simulation time 837245185 ps
CPU time 4.46 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:12 PM PDT 24
Peak memory 200736 kb
Host smart-8348070c-3a67-45bc-ad36-52ee4d0146c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607482711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2607482711
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.743684800
Short name T116
Test name
Test status
Simulation time 101912093 ps
CPU time 1 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200584 kb
Host smart-a46c3640-303c-402c-81bf-a3a0d8207d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743684800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.743684800
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.463186535
Short name T454
Test name
Test status
Simulation time 261708584 ps
CPU time 1.52 seconds
Started Aug 18 05:26:10 PM PDT 24
Finished Aug 18 05:26:11 PM PDT 24
Peak memory 200708 kb
Host smart-2dd046b5-d748-48b4-a1aa-13da30be84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463186535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.463186535
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1814365257
Short name T203
Test name
Test status
Simulation time 7616383723 ps
CPU time 27.76 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:36 PM PDT 24
Peak memory 209060 kb
Host smart-091cd7da-b0a1-4be6-9ff6-c783917709d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814365257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1814365257
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1462186901
Short name T418
Test name
Test status
Simulation time 123953364 ps
CPU time 1.59 seconds
Started Aug 18 05:26:10 PM PDT 24
Finished Aug 18 05:26:12 PM PDT 24
Peak memory 208680 kb
Host smart-55ebec85-312e-4b6e-a6ba-7d2e281acf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462186901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1462186901
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1599032041
Short name T322
Test name
Test status
Simulation time 85745893 ps
CPU time 0.77 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 200624 kb
Host smart-898c2f55-69e0-4891-a78c-4deedda337bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599032041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1599032041
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.1642321736
Short name T188
Test name
Test status
Simulation time 80026252 ps
CPU time 0.83 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 200480 kb
Host smart-7eb08734-6afa-4829-b30e-8d26f18b3dd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642321736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1642321736
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.1919267626
Short name T347
Test name
Test status
Simulation time 1899545008 ps
CPU time 7.29 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 221888 kb
Host smart-85c717ac-1d72-4f7e-8e6d-19eb7d5a64d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919267626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.1919267626
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2024011622
Short name T358
Test name
Test status
Simulation time 243745944 ps
CPU time 1.16 seconds
Started Aug 18 05:26:10 PM PDT 24
Finished Aug 18 05:26:12 PM PDT 24
Peak memory 217832 kb
Host smart-24138634-9639-45b2-8704-4810278d9799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024011622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2024011622
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.2784026521
Short name T282
Test name
Test status
Simulation time 115533954 ps
CPU time 0.76 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:09 PM PDT 24
Peak memory 200404 kb
Host smart-45c19efb-5e47-47c4-9e9f-62e3f5168475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784026521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2784026521
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.3428372143
Short name T487
Test name
Test status
Simulation time 950252290 ps
CPU time 4.51 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:13 PM PDT 24
Peak memory 200760 kb
Host smart-e2d0db5b-1ef4-4e96-a19c-a093517663a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428372143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3428372143
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.648130289
Short name T317
Test name
Test status
Simulation time 155276698 ps
CPU time 1.19 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200592 kb
Host smart-a01ef93b-639c-42a3-8daa-3fd0bbc61ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648130289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.648130289
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1715578200
Short name T216
Test name
Test status
Simulation time 235154444 ps
CPU time 1.57 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:11 PM PDT 24
Peak memory 200744 kb
Host smart-49d0bd9d-5959-4af2-a223-a9768abf418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715578200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1715578200
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.3475958310
Short name T527
Test name
Test status
Simulation time 8953524508 ps
CPU time 31.63 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:40 PM PDT 24
Peak memory 200748 kb
Host smart-bcf86786-694f-4841-93ca-0a39622f4173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475958310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3475958310
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3629213348
Short name T381
Test name
Test status
Simulation time 118456726 ps
CPU time 1.5 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:11 PM PDT 24
Peak memory 200520 kb
Host smart-491e3477-ee5f-4dc5-a5e6-f3f990a72868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629213348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3629213348
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.1832877066
Short name T209
Test name
Test status
Simulation time 172703125 ps
CPU time 1.23 seconds
Started Aug 18 05:26:12 PM PDT 24
Finished Aug 18 05:26:13 PM PDT 24
Peak memory 200524 kb
Host smart-31bf883e-d4d4-47b6-bd8a-a4c15afbd941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832877066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1832877066
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1549573919
Short name T124
Test name
Test status
Simulation time 70356596 ps
CPU time 0.84 seconds
Started Aug 18 05:26:12 PM PDT 24
Finished Aug 18 05:26:12 PM PDT 24
Peak memory 200388 kb
Host smart-d4fa2e04-6f45-4f36-bf2d-99cefe97e193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549573919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1549573919
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1881675189
Short name T44
Test name
Test status
Simulation time 1227452437 ps
CPU time 5.87 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:15 PM PDT 24
Peak memory 217644 kb
Host smart-4454365b-1a52-49d5-aa0f-64a4bea780ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881675189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1881675189
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1225236843
Short name T272
Test name
Test status
Simulation time 244027286 ps
CPU time 1.09 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:09 PM PDT 24
Peak memory 217728 kb
Host smart-20159919-580b-4935-90ca-f8aec6023505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225236843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1225236843
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.968177502
Short name T519
Test name
Test status
Simulation time 156829356 ps
CPU time 0.85 seconds
Started Aug 18 05:26:10 PM PDT 24
Finished Aug 18 05:26:11 PM PDT 24
Peak memory 200464 kb
Host smart-8cab1c37-9e9d-4b7a-a615-0f667ab9c958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968177502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.968177502
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1718941725
Short name T402
Test name
Test status
Simulation time 840862876 ps
CPU time 3.96 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:13 PM PDT 24
Peak memory 200800 kb
Host smart-61f8aa0c-d2fa-4a39-bf5a-be6a8701681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718941725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1718941725
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2434730916
Short name T318
Test name
Test status
Simulation time 139355533 ps
CPU time 1.1 seconds
Started Aug 18 05:26:10 PM PDT 24
Finished Aug 18 05:26:12 PM PDT 24
Peak memory 200572 kb
Host smart-29550c86-09e2-4826-a9b4-04d3e81236bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434730916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2434730916
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.2620421370
Short name T436
Test name
Test status
Simulation time 202949365 ps
CPU time 1.34 seconds
Started Aug 18 05:26:07 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 200712 kb
Host smart-9d5fbabe-819e-4aae-ab72-a23b00e0952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620421370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2620421370
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3960005805
Short name T366
Test name
Test status
Simulation time 5090205464 ps
CPU time 20.05 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:29 PM PDT 24
Peak memory 200796 kb
Host smart-192b0a2f-646f-49af-8fa9-c4190ff39fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960005805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3960005805
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.2721670961
Short name T111
Test name
Test status
Simulation time 375986392 ps
CPU time 2.24 seconds
Started Aug 18 05:26:12 PM PDT 24
Finished Aug 18 05:26:14 PM PDT 24
Peak memory 200420 kb
Host smart-598decf3-a288-42fa-9f03-6a168404275a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721670961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2721670961
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.72018489
Short name T71
Test name
Test status
Simulation time 85749123 ps
CPU time 0.9 seconds
Started Aug 18 05:26:10 PM PDT 24
Finished Aug 18 05:26:11 PM PDT 24
Peak memory 200628 kb
Host smart-440dd430-c797-4532-b608-c29dcd7ad9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72018489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.72018489
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.968416430
Short name T312
Test name
Test status
Simulation time 57237451 ps
CPU time 0.7 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 200476 kb
Host smart-247b5041-7a3d-4e0d-81b7-e9ae0146c070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968416430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.968416430
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3678532632
Short name T340
Test name
Test status
Simulation time 1914626909 ps
CPU time 6.79 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:15 PM PDT 24
Peak memory 221920 kb
Host smart-ad188a1f-17b0-4b9f-a5cd-56f96ad40423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678532632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3678532632
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2536491198
Short name T434
Test name
Test status
Simulation time 244236954 ps
CPU time 1.09 seconds
Started Aug 18 05:26:11 PM PDT 24
Finished Aug 18 05:26:13 PM PDT 24
Peak memory 217700 kb
Host smart-9e550fba-f7a7-4a41-b1c0-a8e69cf3455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536491198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2536491198
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2890473028
Short name T17
Test name
Test status
Simulation time 204743509 ps
CPU time 0.9 seconds
Started Aug 18 05:26:06 PM PDT 24
Finished Aug 18 05:26:07 PM PDT 24
Peak memory 200412 kb
Host smart-eb857a5d-908e-49d3-bee4-400b7062a019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890473028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2890473028
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.1601481068
Short name T379
Test name
Test status
Simulation time 964036223 ps
CPU time 4.48 seconds
Started Aug 18 05:26:09 PM PDT 24
Finished Aug 18 05:26:14 PM PDT 24
Peak memory 200780 kb
Host smart-36998ffe-e04c-4298-8ceb-53922fd1f518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601481068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.1601481068
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1218603686
Short name T270
Test name
Test status
Simulation time 137738400 ps
CPU time 1.09 seconds
Started Aug 18 05:26:12 PM PDT 24
Finished Aug 18 05:26:13 PM PDT 24
Peak memory 200604 kb
Host smart-b1975f1f-593e-44c4-8d32-adecfdfc98d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218603686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1218603686
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.2284964002
Short name T183
Test name
Test status
Simulation time 117030966 ps
CPU time 1.18 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200636 kb
Host smart-2166a724-fc63-4807-9ccc-61d62d2cdd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284964002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2284964002
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.3177800512
Short name T84
Test name
Test status
Simulation time 6218244220 ps
CPU time 22.31 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:38 PM PDT 24
Peak memory 209020 kb
Host smart-8dbd5cdc-1678-416f-b410-abc4f46ae293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177800512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3177800512
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.2508781633
Short name T256
Test name
Test status
Simulation time 371362650 ps
CPU time 2.11 seconds
Started Aug 18 05:26:08 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 200524 kb
Host smart-0e8dc56a-3f14-4690-898a-185eae7d39f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508781633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2508781633
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.595165841
Short name T395
Test name
Test status
Simulation time 84113139 ps
CPU time 0.84 seconds
Started Aug 18 05:26:06 PM PDT 24
Finished Aug 18 05:26:07 PM PDT 24
Peak memory 200632 kb
Host smart-dff76c85-a70a-4c29-9333-36125aceed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595165841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.595165841
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.4261823629
Short name T220
Test name
Test status
Simulation time 62374544 ps
CPU time 0.74 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 200456 kb
Host smart-08281548-deaf-4763-b1d6-aaad3ecbc19b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261823629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.4261823629
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.437755870
Short name T27
Test name
Test status
Simulation time 2370806498 ps
CPU time 8 seconds
Started Aug 18 05:26:14 PM PDT 24
Finished Aug 18 05:26:22 PM PDT 24
Peak memory 218032 kb
Host smart-aa13a23d-1f42-454f-b8e6-57ee17f2c588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437755870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.437755870
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.303634705
Short name T521
Test name
Test status
Simulation time 244743527 ps
CPU time 1.12 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 218688 kb
Host smart-53e608a7-d713-4f0e-9c97-152e44044b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303634705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.303634705
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2989530106
Short name T299
Test name
Test status
Simulation time 152828278 ps
CPU time 0.88 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 200420 kb
Host smart-8a428434-4dd0-42be-a312-412eb950fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989530106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2989530106
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3460411372
Short name T505
Test name
Test status
Simulation time 1560326629 ps
CPU time 6.98 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:23 PM PDT 24
Peak memory 200800 kb
Host smart-1b2e92e8-1643-40dd-bf23-8fc4b5267eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460411372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3460411372
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.268949802
Short name T517
Test name
Test status
Simulation time 146981181 ps
CPU time 1.13 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 200624 kb
Host smart-9221a0bc-62b6-4788-ada7-0380470376ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268949802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.268949802
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1773997818
Short name T155
Test name
Test status
Simulation time 192746585 ps
CPU time 1.42 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 200740 kb
Host smart-4798315c-ea48-4fab-8468-d19f008cd6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773997818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1773997818
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.4105936674
Short name T508
Test name
Test status
Simulation time 7180259435 ps
CPU time 25 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:42 PM PDT 24
Peak memory 210916 kb
Host smart-d6bc06a3-77eb-4dbb-b2b3-ee1dad66dddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105936674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.4105936674
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.608024396
Short name T165
Test name
Test status
Simulation time 350816636 ps
CPU time 2.17 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 200508 kb
Host smart-5c111559-10d5-4013-898d-0a471c0677ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608024396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.608024396
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.389322547
Short name T460
Test name
Test status
Simulation time 61577971 ps
CPU time 0.78 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 200628 kb
Host smart-910ef645-0dae-41d4-9170-063adbd1b882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389322547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.389322547
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1328140397
Short name T336
Test name
Test status
Simulation time 59814178 ps
CPU time 0.79 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 200500 kb
Host smart-b6635782-c085-4689-be1e-8bf327aefa9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328140397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1328140397
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1106527827
Short name T311
Test name
Test status
Simulation time 1229503868 ps
CPU time 6.22 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:22 PM PDT 24
Peak memory 221656 kb
Host smart-366c3499-a5e9-4762-86d4-89c5d19a3602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106527827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1106527827
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.736334288
Short name T214
Test name
Test status
Simulation time 244485817 ps
CPU time 0.99 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 217776 kb
Host smart-c21c2b55-50ad-4d42-97a1-cebb67ef6a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736334288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.736334288
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1674474638
Short name T14
Test name
Test status
Simulation time 89399899 ps
CPU time 0.76 seconds
Started Aug 18 05:26:14 PM PDT 24
Finished Aug 18 05:26:15 PM PDT 24
Peak memory 200396 kb
Host smart-675b837f-ed5b-472b-a9f0-90e0678d5d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674474638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1674474638
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1357347009
Short name T424
Test name
Test status
Simulation time 1723082577 ps
CPU time 6.92 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:23 PM PDT 24
Peak memory 200768 kb
Host smart-7127538c-5462-431d-967e-f8b5b3e246c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357347009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1357347009
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2121948940
Short name T142
Test name
Test status
Simulation time 148776945 ps
CPU time 1.07 seconds
Started Aug 18 05:26:18 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 200528 kb
Host smart-e7911002-f73c-45c3-a918-6c3487557105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121948940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2121948940
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1247056414
Short name T237
Test name
Test status
Simulation time 257940938 ps
CPU time 1.6 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 200728 kb
Host smart-f71e106a-1bd6-43b2-ba9a-12bfd316aac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247056414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1247056414
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.881040264
Short name T219
Test name
Test status
Simulation time 2749386741 ps
CPU time 10.41 seconds
Started Aug 18 05:26:19 PM PDT 24
Finished Aug 18 05:26:29 PM PDT 24
Peak memory 209240 kb
Host smart-2b779e18-e0e0-4655-abbc-457ca0bf8829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881040264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.881040264
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.726894435
Short name T350
Test name
Test status
Simulation time 281661579 ps
CPU time 1.86 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 200456 kb
Host smart-178c1050-2682-418a-9a15-226447a5ac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726894435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.726894435
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.296784463
Short name T206
Test name
Test status
Simulation time 240858967 ps
CPU time 1.42 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 200652 kb
Host smart-67af8f22-f05a-44f1-b7aa-ec00d35ff1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296784463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.296784463
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.3636924402
Short name T448
Test name
Test status
Simulation time 66903327 ps
CPU time 0.79 seconds
Started Aug 18 05:24:51 PM PDT 24
Finished Aug 18 05:24:52 PM PDT 24
Peak memory 200516 kb
Host smart-39dc28a6-0398-4c8b-a2e1-4fed2a11a58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636924402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3636924402
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.3035840258
Short name T478
Test name
Test status
Simulation time 2381381694 ps
CPU time 9.62 seconds
Started Aug 18 05:24:49 PM PDT 24
Finished Aug 18 05:24:59 PM PDT 24
Peak memory 217992 kb
Host smart-1723d2f2-3200-43ad-93de-c0eff81adc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035840258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3035840258
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.184209742
Short name T525
Test name
Test status
Simulation time 243826028 ps
CPU time 1.16 seconds
Started Aug 18 05:24:49 PM PDT 24
Finished Aug 18 05:24:50 PM PDT 24
Peak memory 217784 kb
Host smart-7c838e8f-f68e-4699-945d-97a5d0e30aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184209742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.184209742
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2752676830
Short name T232
Test name
Test status
Simulation time 94279487 ps
CPU time 0.76 seconds
Started Aug 18 05:24:49 PM PDT 24
Finished Aug 18 05:24:49 PM PDT 24
Peak memory 200328 kb
Host smart-bf4409e1-fd52-4ec1-9c11-0a55f6ecb03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752676830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2752676830
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.2392149811
Short name T400
Test name
Test status
Simulation time 1546872827 ps
CPU time 5.4 seconds
Started Aug 18 05:24:51 PM PDT 24
Finished Aug 18 05:24:57 PM PDT 24
Peak memory 200784 kb
Host smart-96068526-8785-4cd8-a51c-137d961a3768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392149811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2392149811
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.1282026390
Short name T60
Test name
Test status
Simulation time 16514463778 ps
CPU time 28.8 seconds
Started Aug 18 05:24:52 PM PDT 24
Finished Aug 18 05:25:21 PM PDT 24
Peak memory 217776 kb
Host smart-e27a9d6c-e147-48a8-ab6a-a9e97089a9ee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282026390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1282026390
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.2119567830
Short name T160
Test name
Test status
Simulation time 171694470 ps
CPU time 1.16 seconds
Started Aug 18 05:24:50 PM PDT 24
Finished Aug 18 05:24:51 PM PDT 24
Peak memory 200584 kb
Host smart-aa5b6a6a-5497-45cf-95ce-77e1541979d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119567830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.2119567830
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.310005669
Short name T453
Test name
Test status
Simulation time 250408709 ps
CPU time 1.5 seconds
Started Aug 18 05:24:49 PM PDT 24
Finished Aug 18 05:24:51 PM PDT 24
Peak memory 200740 kb
Host smart-5e1018f9-feea-480b-914e-9d1b75680444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310005669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.310005669
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.2846113510
Short name T35
Test name
Test status
Simulation time 1786677934 ps
CPU time 7.86 seconds
Started Aug 18 05:24:50 PM PDT 24
Finished Aug 18 05:24:58 PM PDT 24
Peak memory 209100 kb
Host smart-852bd46b-03ee-42e1-b823-44ba8eecf44f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846113510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2846113510
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3103501183
Short name T385
Test name
Test status
Simulation time 267785710 ps
CPU time 1.84 seconds
Started Aug 18 05:24:50 PM PDT 24
Finished Aug 18 05:24:52 PM PDT 24
Peak memory 200516 kb
Host smart-e34a7d83-c3c0-454e-934a-7e06f9b42654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103501183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3103501183
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.4290469153
Short name T451
Test name
Test status
Simulation time 235691159 ps
CPU time 1.44 seconds
Started Aug 18 05:24:48 PM PDT 24
Finished Aug 18 05:24:50 PM PDT 24
Peak memory 200532 kb
Host smart-7070896d-b093-4097-bf56-db976a55a310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290469153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.4290469153
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.109506394
Short name T139
Test name
Test status
Simulation time 67649090 ps
CPU time 0.73 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 200480 kb
Host smart-ef1cdb64-3767-4dd7-82c9-e6dc1755598b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109506394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.109506394
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.733969000
Short name T30
Test name
Test status
Simulation time 2353375487 ps
CPU time 7.99 seconds
Started Aug 18 05:26:14 PM PDT 24
Finished Aug 18 05:26:22 PM PDT 24
Peak memory 221964 kb
Host smart-88129b55-5f8e-4b14-a0f4-e7520fbebc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733969000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.733969000
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3046279
Short name T144
Test name
Test status
Simulation time 244200442 ps
CPU time 1.1 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 217812 kb
Host smart-4c91da6e-3743-4102-9bbd-a551d217f851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3046279
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.441281356
Short name T497
Test name
Test status
Simulation time 224988456 ps
CPU time 0.94 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 200452 kb
Host smart-ec2ffa4c-c0ff-4fa4-bdfe-e46233513477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441281356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.441281356
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.737793887
Short name T83
Test name
Test status
Simulation time 1038320995 ps
CPU time 4.95 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:22 PM PDT 24
Peak memory 200800 kb
Host smart-ddfe70df-4cdd-45c1-a737-617cec5d5da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737793887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.737793887
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1842141126
Short name T67
Test name
Test status
Simulation time 99535226 ps
CPU time 0.97 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 200600 kb
Host smart-74a0a438-709f-49e1-9127-ba509c4872ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842141126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1842141126
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.2177231918
Short name T182
Test name
Test status
Simulation time 206537756 ps
CPU time 1.44 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 200684 kb
Host smart-62a32d40-8fc2-4e69-b35b-b3c9a26648bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177231918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.2177231918
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.2417169646
Short name T74
Test name
Test status
Simulation time 1354881158 ps
CPU time 6.71 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:23 PM PDT 24
Peak memory 200788 kb
Host smart-2a5f7a13-5cb1-43a4-8cfa-1b0e91503b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417169646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2417169646
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.621247457
Short name T250
Test name
Test status
Simulation time 148411608 ps
CPU time 1.73 seconds
Started Aug 18 05:26:14 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 200420 kb
Host smart-91ce39fa-fdcb-40d4-88ff-a5791d01558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621247457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.621247457
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.1110874947
Short name T348
Test name
Test status
Simulation time 201200911 ps
CPU time 1.25 seconds
Started Aug 18 05:26:18 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 200624 kb
Host smart-c4dd0091-abe6-41fb-9d58-d311c8d54e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110874947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1110874947
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1161651953
Short name T121
Test name
Test status
Simulation time 69277189 ps
CPU time 0.74 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 200468 kb
Host smart-cfd2d669-5bbc-44c3-9f6b-4b9c360700ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161651953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1161651953
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.3275730426
Short name T333
Test name
Test status
Simulation time 2373801517 ps
CPU time 7.91 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:23 PM PDT 24
Peak memory 222008 kb
Host smart-46499ad9-ebf7-4046-a340-48bb4c6c2333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275730426 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3275730426
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.928669230
Short name T392
Test name
Test status
Simulation time 245235282 ps
CPU time 1.03 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 217816 kb
Host smart-421777b2-9544-4b30-98e0-e9fa5e665986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928669230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.928669230
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2449497276
Short name T12
Test name
Test status
Simulation time 208068819 ps
CPU time 0.88 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 200412 kb
Host smart-19497a8b-c001-4c16-97ee-94aa28dde596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449497276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2449497276
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1627485520
Short name T108
Test name
Test status
Simulation time 1631589635 ps
CPU time 6.63 seconds
Started Aug 18 05:26:19 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 200964 kb
Host smart-622a42ab-aa1e-4ebd-bbd5-1b7a08c0396f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627485520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1627485520
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.960401469
Short name T405
Test name
Test status
Simulation time 140079655 ps
CPU time 1.16 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 200620 kb
Host smart-cfeee62c-6b34-41c2-8855-64a7fd3a8f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960401469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.960401469
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.1299717497
Short name T356
Test name
Test status
Simulation time 197775603 ps
CPU time 1.34 seconds
Started Aug 18 05:26:18 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 200780 kb
Host smart-2243d06a-8a4f-4ea8-b4de-b02311e2568d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299717497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1299717497
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.2493582932
Short name T540
Test name
Test status
Simulation time 7739928567 ps
CPU time 26.74 seconds
Started Aug 18 05:26:19 PM PDT 24
Finished Aug 18 05:26:45 PM PDT 24
Peak memory 200908 kb
Host smart-4423c0a3-7b1a-445b-b538-d04d527f9b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493582932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2493582932
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.892517636
Short name T274
Test name
Test status
Simulation time 117448255 ps
CPU time 1.48 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:19 PM PDT 24
Peak memory 200516 kb
Host smart-0caf7bc5-3d32-437f-8b92-6322b01e90a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892517636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.892517636
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3817595402
Short name T345
Test name
Test status
Simulation time 287737641 ps
CPU time 1.49 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 200664 kb
Host smart-fe39f1ba-86ad-46b3-a631-44b4d4b5946a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817595402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3817595402
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.795431462
Short name T484
Test name
Test status
Simulation time 68950332 ps
CPU time 0.74 seconds
Started Aug 18 05:26:15 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 200392 kb
Host smart-4f515390-7740-4fbc-b986-5ed2bbd9bcf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795431462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.795431462
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.2807782538
Short name T277
Test name
Test status
Simulation time 1903248789 ps
CPU time 7.26 seconds
Started Aug 18 05:26:18 PM PDT 24
Finished Aug 18 05:26:25 PM PDT 24
Peak memory 218004 kb
Host smart-7f5ff39c-6733-427f-864e-bd90bac907f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807782538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.2807782538
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3918713557
Short name T365
Test name
Test status
Simulation time 244159210 ps
CPU time 1.03 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 217736 kb
Host smart-b457fe85-6404-4343-8b14-eba6ed43b43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918713557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3918713557
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.133002679
Short name T442
Test name
Test status
Simulation time 187863773 ps
CPU time 0.98 seconds
Started Aug 18 05:26:19 PM PDT 24
Finished Aug 18 05:26:21 PM PDT 24
Peak memory 200336 kb
Host smart-52f35520-032a-4cf1-ad30-596d53a26717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133002679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.133002679
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3381956345
Short name T248
Test name
Test status
Simulation time 1686123723 ps
CPU time 6.19 seconds
Started Aug 18 05:26:19 PM PDT 24
Finished Aug 18 05:26:25 PM PDT 24
Peak memory 200772 kb
Host smart-be1e5479-3000-44ce-8dc0-6f73d831ca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381956345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3381956345
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3986046352
Short name T430
Test name
Test status
Simulation time 155446260 ps
CPU time 1.16 seconds
Started Aug 18 05:26:17 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 200620 kb
Host smart-0c0d04c9-3e6b-49d7-8b2f-7ad3d764f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986046352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3986046352
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.2446523749
Short name T252
Test name
Test status
Simulation time 123408320 ps
CPU time 1.18 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 200680 kb
Host smart-2c0cfe88-5e89-4eca-9735-09234a029495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446523749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2446523749
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2587193723
Short name T352
Test name
Test status
Simulation time 7174123743 ps
CPU time 29.31 seconds
Started Aug 18 05:26:18 PM PDT 24
Finished Aug 18 05:26:48 PM PDT 24
Peak memory 210872 kb
Host smart-b39b029c-c2dc-4614-99ed-60d013817ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587193723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2587193723
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.3567118996
Short name T441
Test name
Test status
Simulation time 150825229 ps
CPU time 1.73 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:18 PM PDT 24
Peak memory 200520 kb
Host smart-a7a03ff8-27c2-4a71-a5a2-bfe9a658d90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567118996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3567118996
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.2337042489
Short name T515
Test name
Test status
Simulation time 114491016 ps
CPU time 1.05 seconds
Started Aug 18 05:26:16 PM PDT 24
Finished Aug 18 05:26:17 PM PDT 24
Peak memory 200616 kb
Host smart-a5cb2f7e-aec4-420a-80fc-0b30e0d17527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337042489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.2337042489
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.4194155884
Short name T431
Test name
Test status
Simulation time 71247970 ps
CPU time 0.79 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 200456 kb
Host smart-982ec011-cb37-4703-865f-5cdb8b2414f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194155884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.4194155884
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3782645861
Short name T39
Test name
Test status
Simulation time 243529621 ps
CPU time 1.08 seconds
Started Aug 18 05:26:21 PM PDT 24
Finished Aug 18 05:26:23 PM PDT 24
Peak memory 217832 kb
Host smart-df950db1-9693-4827-95c2-c389ef41cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782645861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3782645861
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.984818251
Short name T327
Test name
Test status
Simulation time 75165614 ps
CPU time 0.84 seconds
Started Aug 18 05:26:23 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 200396 kb
Host smart-d5e4f828-2061-4497-9755-c42fbed15b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984818251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.984818251
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.2848046402
Short name T120
Test name
Test status
Simulation time 1639052869 ps
CPU time 6.7 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:32 PM PDT 24
Peak memory 200136 kb
Host smart-9e0553f9-2cc3-4018-8a7c-0133daa8e6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848046402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2848046402
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2165316240
Short name T195
Test name
Test status
Simulation time 108367985 ps
CPU time 1.04 seconds
Started Aug 18 05:26:22 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 200480 kb
Host smart-166b9533-f887-43cb-a9a1-ae5ba3b6fdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165316240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2165316240
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.1636459396
Short name T249
Test name
Test status
Simulation time 126737651 ps
CPU time 1.2 seconds
Started Aug 18 05:26:18 PM PDT 24
Finished Aug 18 05:26:20 PM PDT 24
Peak memory 200616 kb
Host smart-d650d56e-266e-43bc-9823-9a5f7446bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636459396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1636459396
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.772791822
Short name T247
Test name
Test status
Simulation time 10282699207 ps
CPU time 40.13 seconds
Started Aug 18 05:26:24 PM PDT 24
Finished Aug 18 05:27:04 PM PDT 24
Peak memory 209052 kb
Host smart-402a5c31-cd35-41cb-9f08-5d31f5187cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772791822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.772791822
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3732851445
Short name T229
Test name
Test status
Simulation time 376902609 ps
CPU time 2.04 seconds
Started Aug 18 05:26:33 PM PDT 24
Finished Aug 18 05:26:35 PM PDT 24
Peak memory 200504 kb
Host smart-113b112e-a6aa-40ce-80d9-1a100ffe9be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732851445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3732851445
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3215854850
Short name T148
Test name
Test status
Simulation time 240906815 ps
CPU time 1.37 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:27 PM PDT 24
Peak memory 200676 kb
Host smart-f1eb4524-b9d8-4dc3-9eee-b306b850df09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215854850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3215854850
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.492849974
Short name T150
Test name
Test status
Simulation time 83188459 ps
CPU time 0.83 seconds
Started Aug 18 05:26:26 PM PDT 24
Finished Aug 18 05:26:27 PM PDT 24
Peak memory 200400 kb
Host smart-13a7913e-cb78-4ef5-b14a-4f41aaf3a564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492849974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.492849974
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.4161739757
Short name T413
Test name
Test status
Simulation time 1893888753 ps
CPU time 7.3 seconds
Started Aug 18 05:26:24 PM PDT 24
Finished Aug 18 05:26:32 PM PDT 24
Peak memory 217108 kb
Host smart-7f06c4ba-2e6a-4685-bde4-9be50f4b7d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161739757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.4161739757
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1919418462
Short name T305
Test name
Test status
Simulation time 255158598 ps
CPU time 1.03 seconds
Started Aug 18 05:26:23 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 217784 kb
Host smart-06655c11-da23-4019-a1ae-7054efa7489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919418462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1919418462
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2227153085
Short name T393
Test name
Test status
Simulation time 206739476 ps
CPU time 0.97 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 199792 kb
Host smart-2c464291-5522-4b52-a89c-990bba320bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227153085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2227153085
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.2977494592
Short name T105
Test name
Test status
Simulation time 1521175086 ps
CPU time 6 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:31 PM PDT 24
Peak memory 200732 kb
Host smart-aaf5c3d4-4f42-41cd-9b7e-25cd361480cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977494592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2977494592
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.4286589943
Short name T510
Test name
Test status
Simulation time 163373622 ps
CPU time 1.23 seconds
Started Aug 18 05:26:22 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 200584 kb
Host smart-e9cfe6aa-fdc5-4be8-b86c-e3f9efde517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286589943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.4286589943
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2052976814
Short name T446
Test name
Test status
Simulation time 207539092 ps
CPU time 1.45 seconds
Started Aug 18 05:26:24 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 200684 kb
Host smart-016df184-56c1-4b6e-8b77-5f28c7f5e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052976814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2052976814
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.421881770
Short name T5
Test name
Test status
Simulation time 2498925382 ps
CPU time 10.04 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:35 PM PDT 24
Peak memory 209240 kb
Host smart-bf52d4c1-9d10-4660-8891-70170c35af16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421881770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.421881770
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.3148468746
Short name T367
Test name
Test status
Simulation time 265243822 ps
CPU time 1.72 seconds
Started Aug 18 05:26:24 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 200512 kb
Host smart-ca1c725d-f3b7-4a0e-ac11-911d7ea8bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148468746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3148468746
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.760374008
Short name T364
Test name
Test status
Simulation time 74277663 ps
CPU time 0.79 seconds
Started Aug 18 05:26:23 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 200616 kb
Host smart-cf9b873e-c1ba-492c-8c5b-bf1def676b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760374008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.760374008
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.1779700933
Short name T290
Test name
Test status
Simulation time 60984034 ps
CPU time 0.79 seconds
Started Aug 18 05:26:23 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 200480 kb
Host smart-d277135f-7874-4a52-9fe7-6cb5d970ea28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779700933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1779700933
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.907892847
Short name T370
Test name
Test status
Simulation time 1890748183 ps
CPU time 6.83 seconds
Started Aug 18 05:26:26 PM PDT 24
Finished Aug 18 05:26:33 PM PDT 24
Peak memory 221924 kb
Host smart-64f856ae-1f0e-4ad1-8c98-b90f60f270be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907892847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.907892847
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3927155008
Short name T251
Test name
Test status
Simulation time 243748679 ps
CPU time 1.09 seconds
Started Aug 18 05:26:24 PM PDT 24
Finished Aug 18 05:26:25 PM PDT 24
Peak memory 217784 kb
Host smart-d46d6472-d596-424f-8d59-bbdb459bc757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927155008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3927155008
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.1180799683
Short name T211
Test name
Test status
Simulation time 91032689 ps
CPU time 0.8 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 200440 kb
Host smart-f731051d-a579-482d-b5cf-1710f03fe087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180799683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1180799683
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1097507147
Short name T493
Test name
Test status
Simulation time 1906335314 ps
CPU time 6.51 seconds
Started Aug 18 05:26:23 PM PDT 24
Finished Aug 18 05:26:30 PM PDT 24
Peak memory 200748 kb
Host smart-53a37691-dc3e-4e09-856d-333cf558b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097507147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1097507147
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.592729894
Short name T271
Test name
Test status
Simulation time 151401739 ps
CPU time 1.12 seconds
Started Aug 18 05:26:26 PM PDT 24
Finished Aug 18 05:26:27 PM PDT 24
Peak memory 200620 kb
Host smart-73ec6a20-c98d-48cd-974c-b243cc284970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592729894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.592729894
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.700519408
Short name T353
Test name
Test status
Simulation time 114202315 ps
CPU time 1.2 seconds
Started Aug 18 05:26:22 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 200732 kb
Host smart-f168e6c0-27e8-4623-b26e-e1bd85790438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700519408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.700519408
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.4151449398
Short name T477
Test name
Test status
Simulation time 9068812904 ps
CPU time 31.9 seconds
Started Aug 18 05:26:22 PM PDT 24
Finished Aug 18 05:26:54 PM PDT 24
Peak memory 200892 kb
Host smart-16118fc9-9f4b-4289-9112-166b0db45cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151449398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.4151449398
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.2167235021
Short name T275
Test name
Test status
Simulation time 535905210 ps
CPU time 2.78 seconds
Started Aug 18 05:26:29 PM PDT 24
Finished Aug 18 05:26:32 PM PDT 24
Peak memory 200504 kb
Host smart-a2c779bb-7797-4f09-a9cc-4700ddc0fed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167235021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2167235021
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.1164807386
Short name T118
Test name
Test status
Simulation time 161741912 ps
CPU time 1.13 seconds
Started Aug 18 05:26:28 PM PDT 24
Finished Aug 18 05:26:29 PM PDT 24
Peak memory 200604 kb
Host smart-57e6ae80-588d-475c-b425-ed8b5e6c5dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164807386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1164807386
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.2650322040
Short name T439
Test name
Test status
Simulation time 71402134 ps
CPU time 0.8 seconds
Started Aug 18 05:26:33 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 200484 kb
Host smart-c476390d-0643-4bd6-8912-51918eb003f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650322040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2650322040
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.2746771229
Short name T25
Test name
Test status
Simulation time 1894336096 ps
CPU time 7.75 seconds
Started Aug 18 05:26:27 PM PDT 24
Finished Aug 18 05:26:35 PM PDT 24
Peak memory 217948 kb
Host smart-8af7d599-eaff-4552-8f07-440e320bf808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746771229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2746771229
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.1634774989
Short name T404
Test name
Test status
Simulation time 244661822 ps
CPU time 1.18 seconds
Started Aug 18 05:26:26 PM PDT 24
Finished Aug 18 05:26:28 PM PDT 24
Peak memory 217856 kb
Host smart-490fb3ba-f59e-42e4-96b0-445bd7fe2d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634774989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.1634774989
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.1117520251
Short name T185
Test name
Test status
Simulation time 164316952 ps
CPU time 0.83 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 200432 kb
Host smart-29e5985f-9160-4a08-97a5-76dcffbb7279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117520251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1117520251
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.2551890863
Short name T159
Test name
Test status
Simulation time 721578910 ps
CPU time 3.67 seconds
Started Aug 18 05:26:24 PM PDT 24
Finished Aug 18 05:26:27 PM PDT 24
Peak memory 200784 kb
Host smart-564930d3-684f-42e7-8296-3d8ce485727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551890863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2551890863
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.919172784
Short name T4
Test name
Test status
Simulation time 156489838 ps
CPU time 1.08 seconds
Started Aug 18 05:26:27 PM PDT 24
Finished Aug 18 05:26:28 PM PDT 24
Peak memory 200620 kb
Host smart-3f48b1f7-87e9-45ee-96f9-57e403cf1ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919172784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.919172784
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2354399202
Short name T122
Test name
Test status
Simulation time 118107242 ps
CPU time 1.17 seconds
Started Aug 18 05:26:25 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 200708 kb
Host smart-1e54ba86-8c29-4f50-843f-f9c5d46e0143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354399202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2354399202
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.1828392473
Short name T138
Test name
Test status
Simulation time 332322779 ps
CPU time 1.67 seconds
Started Aug 18 05:26:26 PM PDT 24
Finished Aug 18 05:26:28 PM PDT 24
Peak memory 200676 kb
Host smart-db27d35c-d460-4a49-801c-52169e1602cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828392473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1828392473
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1465801259
Short name T157
Test name
Test status
Simulation time 353951205 ps
CPU time 2.34 seconds
Started Aug 18 05:26:23 PM PDT 24
Finished Aug 18 05:26:26 PM PDT 24
Peak memory 200424 kb
Host smart-1c6e06c4-accc-4d7a-bf0c-d7d774f2a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465801259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1465801259
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.581977639
Short name T145
Test name
Test status
Simulation time 82316727 ps
CPU time 0.81 seconds
Started Aug 18 05:26:23 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 200628 kb
Host smart-4adedb3a-7941-4b63-b1e9-46e9a39c13bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581977639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.581977639
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.4201127758
Short name T166
Test name
Test status
Simulation time 64080444 ps
CPU time 0.76 seconds
Started Aug 18 05:26:36 PM PDT 24
Finished Aug 18 05:26:37 PM PDT 24
Peak memory 200436 kb
Host smart-46510e80-faea-4884-92d1-e4953b0d6881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201127758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4201127758
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.3626279039
Short name T408
Test name
Test status
Simulation time 1903458406 ps
CPU time 7.08 seconds
Started Aug 18 05:26:33 PM PDT 24
Finished Aug 18 05:26:41 PM PDT 24
Peak memory 217060 kb
Host smart-05c6a227-0cca-4c3a-a767-2d4a1d648843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626279039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3626279039
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.1315008384
Short name T306
Test name
Test status
Simulation time 243861808 ps
CPU time 1.03 seconds
Started Aug 18 05:26:32 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 217832 kb
Host smart-c4b254d7-17d4-4596-8159-e0b427a75ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315008384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.1315008384
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2239627431
Short name T174
Test name
Test status
Simulation time 91241681 ps
CPU time 0.8 seconds
Started Aug 18 05:26:24 PM PDT 24
Finished Aug 18 05:26:25 PM PDT 24
Peak memory 200436 kb
Host smart-a00199be-842f-4917-bf56-034f36bb2e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239627431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2239627431
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.3456364364
Short name T2
Test name
Test status
Simulation time 1271079880 ps
CPU time 5.29 seconds
Started Aug 18 05:26:27 PM PDT 24
Finished Aug 18 05:26:33 PM PDT 24
Peak memory 200780 kb
Host smart-799921e2-f045-4c24-a0c8-4cecd7e2f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456364364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3456364364
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3629248417
Short name T224
Test name
Test status
Simulation time 153122245 ps
CPU time 1.17 seconds
Started Aug 18 05:26:23 PM PDT 24
Finished Aug 18 05:26:25 PM PDT 24
Peak memory 200620 kb
Host smart-7070d91b-8bc1-4ce1-93d8-40fcc289412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629248417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3629248417
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.233803329
Short name T170
Test name
Test status
Simulation time 111583105 ps
CPU time 1.17 seconds
Started Aug 18 05:26:24 PM PDT 24
Finished Aug 18 05:26:25 PM PDT 24
Peak memory 200720 kb
Host smart-e96924c9-9fa6-4e08-838e-c08503825e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233803329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.233803329
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1075870766
Short name T433
Test name
Test status
Simulation time 219119170 ps
CPU time 1.5 seconds
Started Aug 18 05:26:34 PM PDT 24
Finished Aug 18 05:26:36 PM PDT 24
Peak memory 200576 kb
Host smart-ad70f505-22e7-4021-b493-47af661e90e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075870766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1075870766
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2004747524
Short name T309
Test name
Test status
Simulation time 439872386 ps
CPU time 2.32 seconds
Started Aug 18 05:26:28 PM PDT 24
Finished Aug 18 05:26:30 PM PDT 24
Peak memory 200500 kb
Host smart-b27e6c67-4b00-4521-a571-1da6644b876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004747524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2004747524
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.1812527943
Short name T355
Test name
Test status
Simulation time 138110411 ps
CPU time 1.15 seconds
Started Aug 18 05:26:22 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 200528 kb
Host smart-65bf113e-6aef-41fa-a6ed-e7cddd63d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812527943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1812527943
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.282985750
Short name T202
Test name
Test status
Simulation time 109994722 ps
CPU time 0.92 seconds
Started Aug 18 05:26:35 PM PDT 24
Finished Aug 18 05:26:36 PM PDT 24
Peak memory 200440 kb
Host smart-b3e64bef-677b-4b4f-b2f3-e6ae81586d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282985750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.282985750
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.1173548810
Short name T530
Test name
Test status
Simulation time 2362374794 ps
CPU time 7.87 seconds
Started Aug 18 05:26:35 PM PDT 24
Finished Aug 18 05:26:43 PM PDT 24
Peak memory 221976 kb
Host smart-f5ca5476-4810-4e6a-b25a-ba35f0f3f960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173548810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1173548810
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1805818486
Short name T520
Test name
Test status
Simulation time 244154732 ps
CPU time 1.07 seconds
Started Aug 18 05:26:35 PM PDT 24
Finished Aug 18 05:26:36 PM PDT 24
Peak memory 217948 kb
Host smart-c34a8694-36c9-43fa-b988-c532681e7b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805818486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1805818486
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1989947489
Short name T6
Test name
Test status
Simulation time 102688438 ps
CPU time 0.74 seconds
Started Aug 18 05:26:33 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 200440 kb
Host smart-9e6aafba-333f-4656-bc0d-3ef4aac08b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989947489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1989947489
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.3216278935
Short name T426
Test name
Test status
Simulation time 2040637252 ps
CPU time 7.48 seconds
Started Aug 18 05:26:36 PM PDT 24
Finished Aug 18 05:26:44 PM PDT 24
Peak memory 200668 kb
Host smart-a2d9d5e3-5046-4b27-8b0a-4d871b376748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216278935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3216278935
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1763578970
Short name T221
Test name
Test status
Simulation time 140946743 ps
CPU time 1.14 seconds
Started Aug 18 05:26:35 PM PDT 24
Finished Aug 18 05:26:37 PM PDT 24
Peak memory 200628 kb
Host smart-160939f9-c620-46c1-a9e8-fa70324e1afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763578970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1763578970
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2032395997
Short name T382
Test name
Test status
Simulation time 119274318 ps
CPU time 1.27 seconds
Started Aug 18 05:26:38 PM PDT 24
Finished Aug 18 05:26:39 PM PDT 24
Peak memory 200700 kb
Host smart-cedaaa32-dfc3-4961-8a31-704b183218fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032395997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2032395997
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.2682157250
Short name T469
Test name
Test status
Simulation time 370736299 ps
CPU time 1.71 seconds
Started Aug 18 05:26:34 PM PDT 24
Finished Aug 18 05:26:36 PM PDT 24
Peak memory 200696 kb
Host smart-3fa9986e-2a66-4b36-ba90-3c8a31d1f632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682157250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2682157250
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3691499152
Short name T112
Test name
Test status
Simulation time 403032163 ps
CPU time 2.23 seconds
Started Aug 18 05:26:34 PM PDT 24
Finished Aug 18 05:26:36 PM PDT 24
Peak memory 208712 kb
Host smart-dc117c07-6b76-40c9-9001-fd5a61130303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691499152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3691499152
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.185848644
Short name T9
Test name
Test status
Simulation time 176622160 ps
CPU time 1.17 seconds
Started Aug 18 05:26:36 PM PDT 24
Finished Aug 18 05:26:37 PM PDT 24
Peak memory 200532 kb
Host smart-9d599006-67a8-45a8-9e39-c3d9a1b720a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185848644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.185848644
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.543835139
Short name T292
Test name
Test status
Simulation time 71730569 ps
CPU time 0.81 seconds
Started Aug 18 05:26:33 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 200496 kb
Host smart-266e2619-550b-477f-b2e9-dbe21815af85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543835139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.543835139
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.3834133581
Short name T29
Test name
Test status
Simulation time 1230413269 ps
CPU time 5.6 seconds
Started Aug 18 05:26:33 PM PDT 24
Finished Aug 18 05:26:39 PM PDT 24
Peak memory 221860 kb
Host smart-464f4c01-434c-4f25-a67e-166398f5f56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834133581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3834133581
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2457636297
Short name T205
Test name
Test status
Simulation time 244117578 ps
CPU time 1.05 seconds
Started Aug 18 05:26:35 PM PDT 24
Finished Aug 18 05:26:36 PM PDT 24
Peak memory 217844 kb
Host smart-3d99a7c1-f948-4467-9226-30e7dedba7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457636297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2457636297
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2968561225
Short name T437
Test name
Test status
Simulation time 134903026 ps
CPU time 0.84 seconds
Started Aug 18 05:26:33 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 200436 kb
Host smart-153939c7-ab64-4c35-ae28-fb0156f11908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968561225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2968561225
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.4205564438
Short name T416
Test name
Test status
Simulation time 951531917 ps
CPU time 4.71 seconds
Started Aug 18 05:26:34 PM PDT 24
Finished Aug 18 05:26:39 PM PDT 24
Peak memory 200784 kb
Host smart-0d3de1ce-312d-4de5-be59-f1047094fb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205564438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.4205564438
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3404943179
Short name T388
Test name
Test status
Simulation time 187946151 ps
CPU time 1.19 seconds
Started Aug 18 05:26:32 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 200620 kb
Host smart-d5355f81-16c6-4df7-8979-14740b2fc719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404943179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3404943179
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.3699533034
Short name T511
Test name
Test status
Simulation time 194033083 ps
CPU time 1.34 seconds
Started Aug 18 05:26:38 PM PDT 24
Finished Aug 18 05:26:40 PM PDT 24
Peak memory 200708 kb
Host smart-fe6f6ee0-1500-4eea-8f93-fc8827a47331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699533034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.3699533034
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.1344283728
Short name T341
Test name
Test status
Simulation time 8935310554 ps
CPU time 28.73 seconds
Started Aug 18 05:26:40 PM PDT 24
Finished Aug 18 05:27:08 PM PDT 24
Peak memory 209896 kb
Host smart-897866f0-5bc5-4922-8e75-d9786a1c12c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344283728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1344283728
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.2340785289
Short name T458
Test name
Test status
Simulation time 277705011 ps
CPU time 1.96 seconds
Started Aug 18 05:26:39 PM PDT 24
Finished Aug 18 05:26:41 PM PDT 24
Peak memory 200520 kb
Host smart-e12a7d0f-641c-4b1e-83ad-57a104a6c29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340785289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2340785289
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.1915836591
Short name T342
Test name
Test status
Simulation time 212450537 ps
CPU time 1.32 seconds
Started Aug 18 05:26:36 PM PDT 24
Finished Aug 18 05:26:37 PM PDT 24
Peak memory 200536 kb
Host smart-459b338b-5c84-4f17-a745-2a5813577b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915836591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1915836591
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.2842570758
Short name T459
Test name
Test status
Simulation time 64035233 ps
CPU time 0.77 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 200476 kb
Host smart-77e9fc73-344e-40b5-a4a9-13f8a1e54e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842570758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2842570758
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.638569646
Short name T359
Test name
Test status
Simulation time 243829743 ps
CPU time 1.15 seconds
Started Aug 18 05:25:01 PM PDT 24
Finished Aug 18 05:25:02 PM PDT 24
Peak memory 217740 kb
Host smart-b8ab88d1-c89f-414b-93c2-eec7b3b28f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638569646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.638569646
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.4283890514
Short name T16
Test name
Test status
Simulation time 106570961 ps
CPU time 0.75 seconds
Started Aug 18 05:24:51 PM PDT 24
Finished Aug 18 05:24:52 PM PDT 24
Peak memory 200432 kb
Host smart-295cf0e2-9092-4ffb-8a56-40c8429361b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283890514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.4283890514
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1785280208
Short name T285
Test name
Test status
Simulation time 1840500472 ps
CPU time 6.69 seconds
Started Aug 18 05:25:02 PM PDT 24
Finished Aug 18 05:25:09 PM PDT 24
Peak memory 200764 kb
Host smart-a89e89d4-a77d-4846-9507-e2ac31bb2e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785280208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1785280208
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4025579870
Short name T239
Test name
Test status
Simulation time 150703302 ps
CPU time 1.12 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 200820 kb
Host smart-d876e295-2651-45f4-b6c0-f72e4a8f429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025579870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4025579870
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.668188991
Short name T210
Test name
Test status
Simulation time 261327010 ps
CPU time 1.5 seconds
Started Aug 18 05:24:50 PM PDT 24
Finished Aug 18 05:24:51 PM PDT 24
Peak memory 200720 kb
Host smart-e4b6a57e-6330-4dae-bc2e-234eb1579199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668188991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.668188991
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.4116288422
Short name T233
Test name
Test status
Simulation time 8078261117 ps
CPU time 30.53 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:31 PM PDT 24
Peak memory 200824 kb
Host smart-4df80570-af26-47e3-8282-27eb48f10dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116288422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4116288422
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.2162346954
Short name T531
Test name
Test status
Simulation time 332238309 ps
CPU time 2.08 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:02 PM PDT 24
Peak memory 200484 kb
Host smart-d3d94417-4e56-42a0-9fa1-9a844f057626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162346954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2162346954
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.1992210880
Short name T151
Test name
Test status
Simulation time 220747258 ps
CPU time 1.4 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:02 PM PDT 24
Peak memory 200616 kb
Host smart-ebef6a84-c31b-40c5-ad7a-48677dc3400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992210880 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1992210880
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.2218614439
Short name T235
Test name
Test status
Simulation time 82615659 ps
CPU time 0.78 seconds
Started Aug 18 05:24:59 PM PDT 24
Finished Aug 18 05:25:00 PM PDT 24
Peak memory 200396 kb
Host smart-649285f9-70bf-4a6f-b1d7-28ba992604ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218614439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2218614439
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2933396267
Short name T47
Test name
Test status
Simulation time 1226170203 ps
CPU time 5.51 seconds
Started Aug 18 05:24:59 PM PDT 24
Finished Aug 18 05:25:04 PM PDT 24
Peak memory 217968 kb
Host smart-a61df607-63eb-40c6-bd0d-3ef894482f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933396267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2933396267
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3507424218
Short name T494
Test name
Test status
Simulation time 244167057 ps
CPU time 1.13 seconds
Started Aug 18 05:25:03 PM PDT 24
Finished Aug 18 05:25:04 PM PDT 24
Peak memory 217736 kb
Host smart-51b56d62-8b2f-42f1-89ce-646724375c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507424218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3507424218
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.2575033888
Short name T452
Test name
Test status
Simulation time 145079344 ps
CPU time 0.87 seconds
Started Aug 18 05:24:59 PM PDT 24
Finished Aug 18 05:25:00 PM PDT 24
Peak memory 200436 kb
Host smart-79a1c2a8-ae57-45e3-92b2-d38ac5e79938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575033888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2575033888
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.2492560412
Short name T380
Test name
Test status
Simulation time 994119135 ps
CPU time 4.73 seconds
Started Aug 18 05:25:01 PM PDT 24
Finished Aug 18 05:25:06 PM PDT 24
Peak memory 200708 kb
Host smart-08959d01-32bd-401c-a938-f9e52a86905c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492560412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2492560412
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3523894848
Short name T279
Test name
Test status
Simulation time 150037555 ps
CPU time 1.13 seconds
Started Aug 18 05:24:59 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 200620 kb
Host smart-929e5b92-fb24-4462-8168-b5520c2a6b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523894848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3523894848
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.1773089230
Short name T378
Test name
Test status
Simulation time 227815924 ps
CPU time 1.39 seconds
Started Aug 18 05:25:02 PM PDT 24
Finished Aug 18 05:25:03 PM PDT 24
Peak memory 200716 kb
Host smart-1c64709f-899c-4921-bfff-525e9f506695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773089230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1773089230
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2006783577
Short name T357
Test name
Test status
Simulation time 9670236741 ps
CPU time 42.58 seconds
Started Aug 18 05:24:59 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 200880 kb
Host smart-10bf6b95-028b-43d3-b007-40533da27e34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006783577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2006783577
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4099036334
Short name T465
Test name
Test status
Simulation time 145028548 ps
CPU time 1.9 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:02 PM PDT 24
Peak memory 200464 kb
Host smart-a13210b8-5aa8-4750-8dd2-15fe3290c13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099036334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4099036334
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.2661922608
Short name T254
Test name
Test status
Simulation time 96450640 ps
CPU time 0.86 seconds
Started Aug 18 05:24:59 PM PDT 24
Finished Aug 18 05:25:00 PM PDT 24
Peak memory 200520 kb
Host smart-c08afe54-9240-4b09-b940-d9771f14e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661922608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2661922608
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.2120009562
Short name T143
Test name
Test status
Simulation time 68648376 ps
CPU time 0.78 seconds
Started Aug 18 05:25:12 PM PDT 24
Finished Aug 18 05:25:13 PM PDT 24
Peak memory 200496 kb
Host smart-5ea66985-ab78-4843-8320-726fb4270a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120009562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2120009562
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.2237810909
Short name T498
Test name
Test status
Simulation time 2381208340 ps
CPU time 8.46 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:21 PM PDT 24
Peak memory 217852 kb
Host smart-4d8ad1f6-00f8-432e-97b1-e30024a15955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237810909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2237810909
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3243747861
Short name T69
Test name
Test status
Simulation time 243899190 ps
CPU time 1.02 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 217844 kb
Host smart-d64a7dac-a817-465d-bfab-0392005b3e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243747861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3243747861
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.460793997
Short name T173
Test name
Test status
Simulation time 198530744 ps
CPU time 0.87 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 200300 kb
Host smart-3974579e-d9b1-47f5-a53c-2c1610ecdaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460793997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.460793997
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.219775417
Short name T435
Test name
Test status
Simulation time 1521661028 ps
CPU time 5.82 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:06 PM PDT 24
Peak memory 200768 kb
Host smart-663abe6b-dc55-4ef8-a98d-b8e42b592817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219775417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.219775417
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2629655162
Short name T268
Test name
Test status
Simulation time 109291662 ps
CPU time 1.09 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 200584 kb
Host smart-906def5a-6a12-4534-aa4d-109ac2109c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629655162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2629655162
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3337915913
Short name T169
Test name
Test status
Simulation time 113482163 ps
CPU time 1.16 seconds
Started Aug 18 05:24:57 PM PDT 24
Finished Aug 18 05:24:59 PM PDT 24
Peak memory 200740 kb
Host smart-8d0103f0-afc7-4a87-918d-d1efd53447d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337915913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3337915913
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.2022568415
Short name T280
Test name
Test status
Simulation time 4133527525 ps
CPU time 18.08 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:32 PM PDT 24
Peak memory 200812 kb
Host smart-70fb047a-f61f-494b-a100-e58ae1d7dfa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022568415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.2022568415
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.4081494585
Short name T287
Test name
Test status
Simulation time 358865551 ps
CPU time 2.31 seconds
Started Aug 18 05:25:00 PM PDT 24
Finished Aug 18 05:25:02 PM PDT 24
Peak memory 200484 kb
Host smart-3ad737d6-c6f3-4c3e-bdde-9a226698ddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081494585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.4081494585
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.3267113245
Short name T72
Test name
Test status
Simulation time 96907997 ps
CPU time 0.86 seconds
Started Aug 18 05:24:58 PM PDT 24
Finished Aug 18 05:25:00 PM PDT 24
Peak memory 200628 kb
Host smart-01f6e6fe-af69-41ea-ad5b-cd1a075dd725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267113245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3267113245
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.3965705394
Short name T21
Test name
Test status
Simulation time 65361162 ps
CPU time 0.74 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 200484 kb
Host smart-d88807d4-5700-4333-8326-171dba32f10d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965705394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3965705394
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.859517244
Short name T372
Test name
Test status
Simulation time 1894377490 ps
CPU time 7.41 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:21 PM PDT 24
Peak memory 217940 kb
Host smart-50eae73f-5476-457c-b4cf-570d00747a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859517244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.859517244
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.371812297
Short name T281
Test name
Test status
Simulation time 244499637 ps
CPU time 1.06 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 217840 kb
Host smart-eaa95627-7116-49ea-80b2-a3419f6b001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371812297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.371812297
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.3412239256
Short name T507
Test name
Test status
Simulation time 157242688 ps
CPU time 0.86 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:14 PM PDT 24
Peak memory 200428 kb
Host smart-2b3cc50e-b312-4494-9be0-4656608c3896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412239256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3412239256
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.3787908219
Short name T373
Test name
Test status
Simulation time 1034697990 ps
CPU time 4.84 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:19 PM PDT 24
Peak memory 200804 kb
Host smart-190c9d3e-2fd6-45e9-805f-1125bae8ecbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787908219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3787908219
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2174653499
Short name T462
Test name
Test status
Simulation time 103453601 ps
CPU time 0.94 seconds
Started Aug 18 05:25:12 PM PDT 24
Finished Aug 18 05:25:13 PM PDT 24
Peak memory 200620 kb
Host smart-46c9418b-8513-4f79-836e-b0cde4323dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174653499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2174653499
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.3010679258
Short name T184
Test name
Test status
Simulation time 229074143 ps
CPU time 1.47 seconds
Started Aug 18 05:25:15 PM PDT 24
Finished Aug 18 05:25:16 PM PDT 24
Peak memory 200748 kb
Host smart-5d335f97-afcd-4be8-965e-4122552dbe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010679258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3010679258
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3119981137
Short name T106
Test name
Test status
Simulation time 14557980748 ps
CPU time 51.29 seconds
Started Aug 18 05:25:17 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 200840 kb
Host smart-1cc1716d-1a50-40fa-91d4-63fedad67033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119981137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3119981137
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.2808157308
Short name T51
Test name
Test status
Simulation time 545371073 ps
CPU time 2.6 seconds
Started Aug 18 05:25:17 PM PDT 24
Finished Aug 18 05:25:19 PM PDT 24
Peak memory 200516 kb
Host smart-436f78c0-42f4-41ae-85c8-9cdfb4683e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808157308 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.2808157308
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.4196317757
Short name T75
Test name
Test status
Simulation time 241566333 ps
CPU time 1.49 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:14 PM PDT 24
Peak memory 200764 kb
Host smart-2acf1e99-1346-458d-a3e7-d09f5e1aa811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196317757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.4196317757
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.1984461477
Short name T489
Test name
Test status
Simulation time 71955844 ps
CPU time 0.79 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:14 PM PDT 24
Peak memory 200436 kb
Host smart-561c238a-9c0a-43b4-b4d6-6e41a2c43068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984461477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1984461477
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2580703051
Short name T46
Test name
Test status
Simulation time 2170680934 ps
CPU time 8.48 seconds
Started Aug 18 05:25:15 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 217736 kb
Host smart-89542b84-2d9d-48f5-84fc-f126b963ad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580703051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2580703051
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1956741556
Short name T134
Test name
Test status
Simulation time 244568989 ps
CPU time 1.16 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 217804 kb
Host smart-520337b3-5b5c-4285-bb17-c1d5776f43e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956741556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1956741556
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2138315132
Short name T363
Test name
Test status
Simulation time 104993878 ps
CPU time 0.77 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 200428 kb
Host smart-ea38db49-6adb-4489-a3be-3838b3ee79e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138315132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2138315132
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.31945205
Short name T343
Test name
Test status
Simulation time 861045726 ps
CPU time 4.36 seconds
Started Aug 18 05:25:13 PM PDT 24
Finished Aug 18 05:25:18 PM PDT 24
Peak memory 200772 kb
Host smart-0dcd5d84-d3e1-4e2b-9eae-91c42582acde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31945205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.31945205
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.444138721
Short name T295
Test name
Test status
Simulation time 152616520 ps
CPU time 1.1 seconds
Started Aug 18 05:25:15 PM PDT 24
Finished Aug 18 05:25:16 PM PDT 24
Peak memory 200620 kb
Host smart-0810cfb4-3cf9-434e-8fc2-97f63906a0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444138721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.444138721
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.1269539781
Short name T467
Test name
Test status
Simulation time 115023129 ps
CPU time 1.23 seconds
Started Aug 18 05:25:12 PM PDT 24
Finished Aug 18 05:25:13 PM PDT 24
Peak memory 200696 kb
Host smart-65cec411-d82d-458f-98d0-b01b66227315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269539781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1269539781
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.1321892642
Short name T253
Test name
Test status
Simulation time 127658708 ps
CPU time 1.53 seconds
Started Aug 18 05:25:12 PM PDT 24
Finished Aug 18 05:25:14 PM PDT 24
Peak memory 200504 kb
Host smart-4a12ecb8-9baf-47be-a831-01b90df20506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321892642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.1321892642
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3077698458
Short name T427
Test name
Test status
Simulation time 168158149 ps
CPU time 1.3 seconds
Started Aug 18 05:25:14 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 200712 kb
Host smart-18016c2b-4908-4be7-a8e8-4eb451016c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077698458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3077698458
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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