Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7586

1

T2

2

T7

11

T8

17

auto[1]

10399

1

T2

1

T7

1

T8

84

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5537	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6104	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2763	1			T8	22		T11	6		T12	21
reset_info_cp[4]	3659	1			T8	12		T11	7		T12	18
reset_info_cp[8]	111	1			T2	1		T7	1		T17	1
reset_info_cp[16]	105	1			T8	1		T11	1		T30	1
reset_info_cp[32]	111	1			T7	2		T17	1		T30	1
reset_info_cp[64]	101	1			T13	1		T17	1		T30	1
reset_info_cp[128]	114	1			T12	1		T17	1		T30	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2945	1			T8	17		T11	9		T12	12
reset_info_cp[1]	auto[1]	2539	1			T8	9		T11	6		T12	14
reset_info_cp[2]	auto[0]	863	1			T11	3		T13	4		T17	7
reset_info_cp[2]	auto[1]	1900	1			T8	22		T11	3		T12	21
reset_info_cp[4]	auto[0]	1299	1			T11	3		T13	2		T17	12
reset_info_cp[4]	auto[1]	2360	1			T8	12		T11	4		T12	18
reset_info_cp[8]	auto[0]	41	1			T2	1		T30	1		T57	1
reset_info_cp[8]	auto[1]	70	1			T7	1		T17	1		T30	1
reset_info_cp[16]	auto[0]	42	1			T33	2		T62	1		T91	1
reset_info_cp[16]	auto[1]	63	1			T8	1		T11	1		T30	1
reset_info_cp[32]	auto[0]	48	1			T7	2		T17	1		T88	1
reset_info_cp[32]	auto[1]	63	1			T30	1		T32	1		T36	1
reset_info_cp[64]	auto[0]	39	1			T13	1		T30	1		T33	1
reset_info_cp[64]	auto[1]	62	1			T17	1		T63	1		T88	1
reset_info_cp[128]	auto[0]	45	1			T30	1		T33	1		T35	1
reset_info_cp[128]	auto[1]	69	1			T12	1		T17	1		T59	1