Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_access_cg
 
Summary for Group   rstmgr_env_pkg::rstmgr_env_cov::alert_info_access_cg
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
9 | 
0 | 
9 | 
100.00 | 
Variables for Group  rstmgr_env_pkg::rstmgr_env_cov::alert_info_access_cg
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| index_cp | 
9 | 
0 | 
9 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
 
Summary for Variable index_cp
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
9 | 
0 | 
9 | 
100.00 | 
User Defined Bins for index_cp
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
0 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| valid[0] | 
31544 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
| valid[1] | 
31544 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
| valid[2] | 
31544 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
| valid[3] | 
31544 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
| valid[4] | 
31544 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
| valid[5] | 
31544 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
| valid[6] | 
31544 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
| valid[7] | 
31544 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
| valid[8] | 
38240 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T3 | 
2 | 
 | 
T5 | 
2 | 
 
 
 
| 0% | 
10% | 
20% | 
30% | 
40% | 
50% | 
60% | 
70% | 
80% | 
90% | 
100% |