Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2706108042 Aug 19 04:34:07 PM PDT 24 Aug 19 04:34:08 PM PDT 24 245078906 ps
T541 /workspace/coverage/default/31.rstmgr_sw_rst.1540592449 Aug 19 04:34:24 PM PDT 24 Aug 19 04:34:26 PM PDT 24 372661811 ps
T542 /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.608150342 Aug 19 04:34:02 PM PDT 24 Aug 19 04:34:07 PM PDT 24 1220174439 ps
T543 /workspace/coverage/default/6.rstmgr_smoke.3664193920 Aug 19 04:33:45 PM PDT 24 Aug 19 04:33:46 PM PDT 24 194947462 ps
T544 /workspace/coverage/default/33.rstmgr_stress_all.145701868 Aug 19 04:34:30 PM PDT 24 Aug 19 04:34:37 PM PDT 24 1500423890 ps
T69 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.66446980 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:52 PM PDT 24 494501429 ps
T70 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1307004801 Aug 19 04:28:34 PM PDT 24 Aug 19 04:28:36 PM PDT 24 188280213 ps
T71 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2454031287 Aug 19 04:28:33 PM PDT 24 Aug 19 04:28:35 PM PDT 24 79863470 ps
T72 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.904421285 Aug 19 04:28:37 PM PDT 24 Aug 19 04:28:38 PM PDT 24 202532810 ps
T73 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2719704098 Aug 19 04:28:42 PM PDT 24 Aug 19 04:28:43 PM PDT 24 203815245 ps
T82 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4237514155 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:40 PM PDT 24 121660777 ps
T74 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4112491118 Aug 19 04:28:47 PM PDT 24 Aug 19 04:28:51 PM PDT 24 947370705 ps
T83 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1238057830 Aug 19 04:28:41 PM PDT 24 Aug 19 04:28:48 PM PDT 24 204742346 ps
T96 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3280008529 Aug 19 04:28:46 PM PDT 24 Aug 19 04:28:47 PM PDT 24 101322840 ps
T545 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2824494855 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:44 PM PDT 24 1555511435 ps
T97 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2311782026 Aug 19 04:29:00 PM PDT 24 Aug 19 04:29:01 PM PDT 24 59398327 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2891687055 Aug 19 04:28:46 PM PDT 24 Aug 19 04:28:56 PM PDT 24 2280004070 ps
T84 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1134537036 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:39 PM PDT 24 211408269 ps
T85 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2616683215 Aug 19 04:28:43 PM PDT 24 Aug 19 04:28:45 PM PDT 24 202036225 ps
T98 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1288429475 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:51 PM PDT 24 87207960 ps
T99 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3753722591 Aug 19 04:29:01 PM PDT 24 Aug 19 04:29:02 PM PDT 24 143249534 ps
T86 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1191593854 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:37 PM PDT 24 180327997 ps
T75 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1897915735 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:43 PM PDT 24 938832655 ps
T87 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.990929834 Aug 19 04:28:47 PM PDT 24 Aug 19 04:28:50 PM PDT 24 418406604 ps
T100 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2689246717 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:39 PM PDT 24 66663246 ps
T105 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4021306848 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:43 PM PDT 24 448368009 ps
T115 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3653531385 Aug 19 04:28:29 PM PDT 24 Aug 19 04:28:31 PM PDT 24 486776370 ps
T547 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3337342420 Aug 19 04:28:57 PM PDT 24 Aug 19 04:28:58 PM PDT 24 70398649 ps
T111 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3516879619 Aug 19 04:28:46 PM PDT 24 Aug 19 04:28:50 PM PDT 24 579249534 ps
T101 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1736110746 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:41 PM PDT 24 69653642 ps
T106 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4064989310 Aug 19 04:29:00 PM PDT 24 Aug 19 04:29:03 PM PDT 24 165403357 ps
T102 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1012263883 Aug 19 04:28:35 PM PDT 24 Aug 19 04:28:37 PM PDT 24 111952962 ps
T112 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1998268778 Aug 19 04:28:30 PM PDT 24 Aug 19 04:28:32 PM PDT 24 411033778 ps
T548 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2000156061 Aug 19 04:28:42 PM PDT 24 Aug 19 04:28:43 PM PDT 24 74941934 ps
T107 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1162032526 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:38 PM PDT 24 183116035 ps
T549 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.851661757 Aug 19 04:28:37 PM PDT 24 Aug 19 04:28:39 PM PDT 24 104856735 ps
T550 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2035955756 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:39 PM PDT 24 116541635 ps
T551 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.292666922 Aug 19 04:29:01 PM PDT 24 Aug 19 04:29:02 PM PDT 24 92160854 ps
T552 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.39628399 Aug 19 04:28:30 PM PDT 24 Aug 19 04:28:36 PM PDT 24 486708418 ps
T553 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3992484976 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:40 PM PDT 24 75984491 ps
T103 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2995921172 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:40 PM PDT 24 253149705 ps
T554 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3134683169 Aug 19 04:28:47 PM PDT 24 Aug 19 04:28:49 PM PDT 24 421243332 ps
T555 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1929143174 Aug 19 04:28:33 PM PDT 24 Aug 19 04:28:35 PM PDT 24 188833687 ps
T104 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4006629806 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:51 PM PDT 24 140859933 ps
T108 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3313606189 Aug 19 04:28:57 PM PDT 24 Aug 19 04:29:00 PM PDT 24 914991933 ps
T556 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4034415559 Aug 19 04:28:41 PM PDT 24 Aug 19 04:28:42 PM PDT 24 118537633 ps
T116 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1977205328 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:39 PM PDT 24 159870170 ps
T126 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1006385530 Aug 19 04:28:37 PM PDT 24 Aug 19 04:28:40 PM PDT 24 892319828 ps
T557 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1901932164 Aug 19 04:28:33 PM PDT 24 Aug 19 04:28:35 PM PDT 24 105952120 ps
T558 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2814957907 Aug 19 04:28:51 PM PDT 24 Aug 19 04:28:52 PM PDT 24 70624655 ps
T114 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2621857362 Aug 19 04:28:41 PM PDT 24 Aug 19 04:28:44 PM PDT 24 405323573 ps
T559 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1696093005 Aug 19 04:28:32 PM PDT 24 Aug 19 04:28:35 PM PDT 24 150161376 ps
T560 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.787938867 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:39 PM PDT 24 74194661 ps
T561 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1604759405 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:50 PM PDT 24 183481165 ps
T562 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2141452359 Aug 19 04:28:47 PM PDT 24 Aug 19 04:28:48 PM PDT 24 192741915 ps
T563 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2840828457 Aug 19 04:28:30 PM PDT 24 Aug 19 04:28:32 PM PDT 24 155412855 ps
T564 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4128163422 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:37 PM PDT 24 55363306 ps
T565 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3954112081 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:51 PM PDT 24 163363698 ps
T127 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4252999430 Aug 19 04:28:32 PM PDT 24 Aug 19 04:28:34 PM PDT 24 432079448 ps
T566 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2778117755 Aug 19 04:28:53 PM PDT 24 Aug 19 04:28:54 PM PDT 24 269332934 ps
T567 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4001150372 Aug 19 04:28:46 PM PDT 24 Aug 19 04:28:47 PM PDT 24 62781027 ps
T568 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1145710816 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:39 PM PDT 24 169914202 ps
T569 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1407530459 Aug 19 04:29:04 PM PDT 24 Aug 19 04:29:05 PM PDT 24 238540742 ps
T109 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3538303403 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:41 PM PDT 24 799153901 ps
T128 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.221096130 Aug 19 04:28:37 PM PDT 24 Aug 19 04:28:40 PM PDT 24 788044703 ps
T570 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4236340257 Aug 19 04:28:37 PM PDT 24 Aug 19 04:28:40 PM PDT 24 186666732 ps
T571 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3198876704 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:37 PM PDT 24 90157660 ps
T572 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1127540494 Aug 19 04:28:45 PM PDT 24 Aug 19 04:28:48 PM PDT 24 485952446 ps
T573 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3267691468 Aug 19 04:28:27 PM PDT 24 Aug 19 04:28:28 PM PDT 24 118985292 ps
T574 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1219410785 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:39 PM PDT 24 69331702 ps
T575 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4130374551 Aug 19 04:28:57 PM PDT 24 Aug 19 04:29:00 PM PDT 24 486025176 ps
T89 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2052274933 Aug 19 04:29:00 PM PDT 24 Aug 19 04:29:02 PM PDT 24 105316192 ps
T129 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1196484402 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:42 PM PDT 24 413409794 ps
T576 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3453754318 Aug 19 04:28:47 PM PDT 24 Aug 19 04:28:50 PM PDT 24 197360967 ps
T577 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3191306704 Aug 19 04:28:35 PM PDT 24 Aug 19 04:28:43 PM PDT 24 1541412387 ps
T578 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3564387553 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:42 PM PDT 24 226324564 ps
T579 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2171873954 Aug 19 04:28:51 PM PDT 24 Aug 19 04:28:52 PM PDT 24 116315524 ps
T580 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.655756169 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:39 PM PDT 24 90737103 ps
T581 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3478949913 Aug 19 04:28:41 PM PDT 24 Aug 19 04:28:44 PM PDT 24 209739408 ps
T582 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1049791883 Aug 19 04:28:37 PM PDT 24 Aug 19 04:28:38 PM PDT 24 71736116 ps
T583 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1468837384 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:41 PM PDT 24 147234105 ps
T584 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1679299230 Aug 19 04:28:44 PM PDT 24 Aug 19 04:28:45 PM PDT 24 84871965 ps
T585 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2647102273 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:40 PM PDT 24 232163981 ps
T586 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2276459947 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:40 PM PDT 24 101450256 ps
T587 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1731739141 Aug 19 04:28:30 PM PDT 24 Aug 19 04:28:36 PM PDT 24 479577138 ps
T588 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1216386694 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:39 PM PDT 24 438741576 ps
T589 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.105690877 Aug 19 04:28:35 PM PDT 24 Aug 19 04:28:36 PM PDT 24 56107908 ps
T590 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.974774246 Aug 19 04:28:53 PM PDT 24 Aug 19 04:28:56 PM PDT 24 496333583 ps
T113 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2064830557 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:43 PM PDT 24 795325166 ps
T591 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1467729752 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:50 PM PDT 24 134119891 ps
T592 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2603898020 Aug 19 04:28:45 PM PDT 24 Aug 19 04:28:46 PM PDT 24 69271567 ps
T593 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3664367382 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:50 PM PDT 24 73986082 ps
T594 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2298622581 Aug 19 04:28:44 PM PDT 24 Aug 19 04:28:45 PM PDT 24 68898991 ps
T595 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1301979866 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:42 PM PDT 24 120189540 ps
T596 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.714707899 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:41 PM PDT 24 88830657 ps
T597 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3337031292 Aug 19 04:28:47 PM PDT 24 Aug 19 04:28:49 PM PDT 24 187787183 ps
T598 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.203894700 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:42 PM PDT 24 890155946 ps
T599 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2550751953 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:39 PM PDT 24 95995011 ps
T600 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.240833807 Aug 19 04:28:47 PM PDT 24 Aug 19 04:28:48 PM PDT 24 117621104 ps
T601 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1371873139 Aug 19 04:28:48 PM PDT 24 Aug 19 04:28:49 PM PDT 24 103064424 ps
T602 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.56125432 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:43 PM PDT 24 901921238 ps
T603 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.685901836 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:52 PM PDT 24 223081996 ps
T604 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2571578825 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:12 PM PDT 24 142526690 ps
T605 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2246180041 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:40 PM PDT 24 434327332 ps
T606 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4093160525 Aug 19 04:28:51 PM PDT 24 Aug 19 04:28:52 PM PDT 24 112205445 ps
T110 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2821737481 Aug 19 04:28:52 PM PDT 24 Aug 19 04:28:54 PM PDT 24 513286658 ps
T607 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1407025182 Aug 19 04:28:52 PM PDT 24 Aug 19 04:28:55 PM PDT 24 516408571 ps
T608 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1653422220 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:41 PM PDT 24 115120902 ps
T609 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3629540968 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:40 PM PDT 24 130786525 ps
T610 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1603869728 Aug 19 04:28:39 PM PDT 24 Aug 19 04:28:41 PM PDT 24 430158008 ps
T611 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.478225606 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:40 PM PDT 24 196707673 ps
T612 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3980748815 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:51 PM PDT 24 66314387 ps
T613 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.425041988 Aug 19 04:28:27 PM PDT 24 Aug 19 04:28:29 PM PDT 24 99116027 ps
T614 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1905046842 Aug 19 04:28:38 PM PDT 24 Aug 19 04:28:39 PM PDT 24 156494924 ps
T615 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3305880531 Aug 19 04:28:57 PM PDT 24 Aug 19 04:28:58 PM PDT 24 89285624 ps
T616 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3750237464 Aug 19 04:28:40 PM PDT 24 Aug 19 04:28:42 PM PDT 24 132775945 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4251343695 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:37 PM PDT 24 115284921 ps
T618 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2428156001 Aug 19 04:28:36 PM PDT 24 Aug 19 04:28:39 PM PDT 24 890547465 ps
T619 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4214948914 Aug 19 04:28:37 PM PDT 24 Aug 19 04:28:39 PM PDT 24 114070900 ps
T620 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3190570786 Aug 19 04:28:37 PM PDT 24 Aug 19 04:28:38 PM PDT 24 99204197 ps

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.393884781
Short name T8
Test name
Test status
Simulation time 1896829775 ps
CPU time 6.89 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 217924 kb
Host smart-39b1c5f4-262f-4219-a693-38548827bd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393884781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.393884781
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.1263787908
Short name T14
Test name
Test status
Simulation time 121401266 ps
CPU time 1.21 seconds
Started Aug 19 04:33:38 PM PDT 24
Finished Aug 19 04:33:40 PM PDT 24
Peak memory 200556 kb
Host smart-51ac79a3-dba0-4259-8c0e-82a47a46cb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263787908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1263787908
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.4177293902
Short name T1
Test name
Test status
Simulation time 311706236 ps
CPU time 1.84 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 200532 kb
Host smart-0422a388-41a7-4906-89b5-9d869f57f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177293902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4177293902
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1238057830
Short name T83
Test name
Test status
Simulation time 204742346 ps
CPU time 1.33 seconds
Started Aug 19 04:28:41 PM PDT 24
Finished Aug 19 04:28:48 PM PDT 24
Peak memory 209016 kb
Host smart-8b3de327-0df8-4aa8-b5ba-fe1c42d8e4be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238057830 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.1238057830
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.1124933707
Short name T18
Test name
Test status
Simulation time 8300555114 ps
CPU time 13.19 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:13 PM PDT 24
Peak memory 217372 kb
Host smart-2665d844-f4f3-4572-bb6f-05a16fa5fdb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124933707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1124933707
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.1805390516
Short name T30
Test name
Test status
Simulation time 3428983694 ps
CPU time 15.03 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:41 PM PDT 24
Peak memory 200844 kb
Host smart-ccb2b4f8-8e92-4894-85c7-f1087edc0005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805390516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1805390516
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4112491118
Short name T74
Test name
Test status
Simulation time 947370705 ps
CPU time 3.19 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 201024 kb
Host smart-ee1537de-d7c4-4a64-a7fc-341272ea8c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112491118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4112491118
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.2149052518
Short name T56
Test name
Test status
Simulation time 83276513 ps
CPU time 0.79 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:00 PM PDT 24
Peak memory 200484 kb
Host smart-1cf9b0d3-0bdb-4b67-8b5c-9a23bca8dad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149052518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2149052518
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.2691868441
Short name T38
Test name
Test status
Simulation time 1879346409 ps
CPU time 7.02 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 217908 kb
Host smart-eaa99a78-057a-45a7-9039-d3b9eb251650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691868441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2691868441
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.3186150004
Short name T91
Test name
Test status
Simulation time 10887449783 ps
CPU time 34.62 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:35:23 PM PDT 24
Peak memory 200740 kb
Host smart-de236f4c-ed78-4028-8462-1d0fa83e3f96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186150004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3186150004
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.4067446725
Short name T16
Test name
Test status
Simulation time 169034176 ps
CPU time 1.15 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200444 kb
Host smart-bc055e7e-b704-448e-a241-ee44b416e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067446725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.4067446725
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.4064989310
Short name T106
Test name
Test status
Simulation time 165403357 ps
CPU time 2.39 seconds
Started Aug 19 04:29:00 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 207820 kb
Host smart-a9841f47-8c4b-49ac-bb1d-7420623e62c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064989310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4064989310
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.221096130
Short name T128
Test name
Test status
Simulation time 788044703 ps
CPU time 2.8 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 201032 kb
Host smart-7fba5c20-88b1-4b42-a513-177ff9b64ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221096130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.
221096130
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.2163218126
Short name T153
Test name
Test status
Simulation time 68490243 ps
CPU time 0.79 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:01 PM PDT 24
Peak memory 200616 kb
Host smart-bf9b30aa-8a74-4be2-8dd5-52632bacfa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163218126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.2163218126
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1943190030
Short name T64
Test name
Test status
Simulation time 2362969320 ps
CPU time 9.13 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:09 PM PDT 24
Peak memory 218112 kb
Host smart-c30886f5-1188-4c70-8fbb-eea27e3df513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943190030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1943190030
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.1972509055
Short name T231
Test name
Test status
Simulation time 150287129 ps
CPU time 1.22 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:17 PM PDT 24
Peak memory 200656 kb
Host smart-625a987c-50d3-47d6-a64f-f6978fea3535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972509055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1972509055
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.3954112081
Short name T565
Test name
Test status
Simulation time 163363698 ps
CPU time 2.23 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 209100 kb
Host smart-f8192c9e-1dda-4f90-9e12-bd71bca49903
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954112081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3954112081
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3753722591
Short name T99
Test name
Test status
Simulation time 143249534 ps
CPU time 1.14 seconds
Started Aug 19 04:29:01 PM PDT 24
Finished Aug 19 04:29:02 PM PDT 24
Peak memory 200832 kb
Host smart-fae9cee7-4671-4d85-a02c-8188a85bf45c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753722591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.3753722591
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.4130827825
Short name T25
Test name
Test status
Simulation time 122522672 ps
CPU time 0.81 seconds
Started Aug 19 04:34:04 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 200424 kb
Host smart-8196d285-ed59-4930-8934-a2209a43ad7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130827825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.4130827825
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.391981578
Short name T141
Test name
Test status
Simulation time 243995534 ps
CPU time 1.06 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:01 PM PDT 24
Peak memory 217744 kb
Host smart-6adf4b50-9e28-4d34-a541-6e539879e5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391981578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.391981578
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.95757188
Short name T36
Test name
Test status
Simulation time 2362219133 ps
CPU time 7.66 seconds
Started Aug 19 04:34:13 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 218088 kb
Host smart-fe2de02a-e17a-43e6-9ed9-7315d8f8eb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95757188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.95757188
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.66446980
Short name T69
Test name
Test status
Simulation time 494501429 ps
CPU time 2.03 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 201004 kb
Host smart-c9165d64-1f13-4666-b770-2288753854e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66446980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.66446980
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1468837384
Short name T583
Test name
Test status
Simulation time 147234105 ps
CPU time 1.98 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:41 PM PDT 24
Peak memory 200824 kb
Host smart-8d68c388-a92a-4f5f-869b-558ece1e62f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468837384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1
468837384
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.39628399
Short name T552
Test name
Test status
Simulation time 486708418 ps
CPU time 5.42 seconds
Started Aug 19 04:28:30 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 200924 kb
Host smart-2539f659-2245-475c-8014-cc11cd955a76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39628399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.39628399
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2571578825
Short name T604
Test name
Test status
Simulation time 142526690 ps
CPU time 0.98 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:12 PM PDT 24
Peak memory 200780 kb
Host smart-8f68e211-f6d1-4076-b241-53defec045d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571578825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
571578825
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3267691468
Short name T573
Test name
Test status
Simulation time 118985292 ps
CPU time 1.28 seconds
Started Aug 19 04:28:27 PM PDT 24
Finished Aug 19 04:28:28 PM PDT 24
Peak memory 208960 kb
Host smart-4e05066f-dc1e-4735-b58a-b101b7bd1307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267691468 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.3267691468
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.105690877
Short name T589
Test name
Test status
Simulation time 56107908 ps
CPU time 0.72 seconds
Started Aug 19 04:28:35 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 200768 kb
Host smart-7302986b-304d-403d-a280-f5db6b3f317a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105690877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.105690877
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1467729752
Short name T591
Test name
Test status
Simulation time 134119891 ps
CPU time 1.33 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 200964 kb
Host smart-b66781b0-f822-4ba3-b301-e0ee3be2f4a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467729752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sa
me_csr_outstanding.1467729752
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.1145710816
Short name T568
Test name
Test status
Simulation time 169914202 ps
CPU time 2.33 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 212248 kb
Host smart-8448799e-3855-4f52-9107-4d9784bb6278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145710816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.1145710816
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3653531385
Short name T115
Test name
Test status
Simulation time 486776370 ps
CPU time 1.83 seconds
Started Aug 19 04:28:29 PM PDT 24
Finished Aug 19 04:28:31 PM PDT 24
Peak memory 200896 kb
Host smart-a00a87dd-9cd0-431a-8611-cf246c733f10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653531385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.3653531385
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.425041988
Short name T613
Test name
Test status
Simulation time 99116027 ps
CPU time 1.35 seconds
Started Aug 19 04:28:27 PM PDT 24
Finished Aug 19 04:28:29 PM PDT 24
Peak memory 200784 kb
Host smart-146da86c-f930-488c-a574-d841ffd0e5c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425041988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.425041988
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2891687055
Short name T546
Test name
Test status
Simulation time 2280004070 ps
CPU time 9.86 seconds
Started Aug 19 04:28:46 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 217212 kb
Host smart-dfad889f-3e05-417b-9f52-c96f75eecacf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891687055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2
891687055
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3198876704
Short name T571
Test name
Test status
Simulation time 90157660 ps
CPU time 0.85 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 200692 kb
Host smart-ea99f78e-d843-43e3-9628-e0153d1f171c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198876704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
198876704
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2141452359
Short name T562
Test name
Test status
Simulation time 192741915 ps
CPU time 1.24 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:48 PM PDT 24
Peak memory 200820 kb
Host smart-9c2e39c0-581d-43de-9c57-388c44ee77d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141452359 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.2141452359
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.3992484976
Short name T553
Test name
Test status
Simulation time 75984491 ps
CPU time 0.91 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200720 kb
Host smart-09d86bf9-a5f9-437e-8e9f-efdaf2173ef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992484976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3992484976
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1696093005
Short name T559
Test name
Test status
Simulation time 150161376 ps
CPU time 2.19 seconds
Started Aug 19 04:28:32 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 209200 kb
Host smart-d9c7e4c6-fc90-4e60-aa23-fbee7c9cbb8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696093005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1696093005
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.2298622581
Short name T594
Test name
Test status
Simulation time 68898991 ps
CPU time 0.83 seconds
Started Aug 19 04:28:44 PM PDT 24
Finished Aug 19 04:28:45 PM PDT 24
Peak memory 200684 kb
Host smart-5e665d95-096c-416e-8f85-fc133163fb66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298622581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2298622581
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3337031292
Short name T597
Test name
Test status
Simulation time 187787183 ps
CPU time 1.53 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 200948 kb
Host smart-183a166a-7347-4e85-9a0e-19d5ae6f366d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337031292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3337031292
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.1653422220
Short name T608
Test name
Test status
Simulation time 115120902 ps
CPU time 1.49 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:41 PM PDT 24
Peak memory 209196 kb
Host smart-c704da20-1c4a-4156-bb9b-c2057e537502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653422220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1653422220
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2246180041
Short name T605
Test name
Test status
Simulation time 434327332 ps
CPU time 1.8 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200992 kb
Host smart-bca5df9a-eb07-45a6-b29c-b22626d7c6e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246180041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.2246180041
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.2035955756
Short name T550
Test name
Test status
Simulation time 116541635 ps
CPU time 1.07 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200820 kb
Host smart-87e4a011-b41e-49e7-9972-f11d3f3a7dfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035955756 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.2035955756
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.1049791883
Short name T582
Test name
Test status
Simulation time 71736116 ps
CPU time 0.79 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 200656 kb
Host smart-211ec65a-6b1b-433e-b045-106c2625a05f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049791883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1049791883
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2647102273
Short name T585
Test name
Test status
Simulation time 232163981 ps
CPU time 1.56 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 209012 kb
Host smart-961c7cd5-fc67-424e-a80a-72c295a8f5cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647102273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.2647102273
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.240833807
Short name T600
Test name
Test status
Simulation time 117621104 ps
CPU time 1.24 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:48 PM PDT 24
Peak memory 208952 kb
Host smart-8e6331c1-9b79-47b0-b333-86ff14deb5e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240833807 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.240833807
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.3337342420
Short name T547
Test name
Test status
Simulation time 70398649 ps
CPU time 0.8 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:28:58 PM PDT 24
Peak memory 200796 kb
Host smart-7ffc72b0-9e60-4f91-9595-261321324c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337342420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3337342420
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2276459947
Short name T586
Test name
Test status
Simulation time 101450256 ps
CPU time 1.26 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200948 kb
Host smart-1531ed58-deea-4b51-bc95-04625797eb17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276459947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2276459947
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.4021306848
Short name T105
Test name
Test status
Simulation time 448368009 ps
CPU time 2.93 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 209200 kb
Host smart-e3b70cec-61bb-4b1e-ac82-3e373e71eca4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021306848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4021306848
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2821737481
Short name T110
Test name
Test status
Simulation time 513286658 ps
CPU time 1.9 seconds
Started Aug 19 04:28:52 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 200924 kb
Host smart-81cb15ac-0b1e-4c32-9f93-caedc34328c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821737481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.2821737481
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4034415559
Short name T556
Test name
Test status
Simulation time 118537633 ps
CPU time 0.94 seconds
Started Aug 19 04:28:41 PM PDT 24
Finished Aug 19 04:28:42 PM PDT 24
Peak memory 200820 kb
Host smart-a9cf0719-8ccd-49d5-8046-b59a1a869bcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034415559 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.4034415559
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2454031287
Short name T71
Test name
Test status
Simulation time 79863470 ps
CPU time 0.81 seconds
Started Aug 19 04:28:33 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 200684 kb
Host smart-a60e145d-00ac-414f-9162-add72bc9929b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454031287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2454031287
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.655756169
Short name T580
Test name
Test status
Simulation time 90737103 ps
CPU time 1.01 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200756 kb
Host smart-a7b38681-24a4-4352-a959-74e6e7c5ccb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655756169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_sa
me_csr_outstanding.655756169
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.3453754318
Short name T576
Test name
Test status
Simulation time 197360967 ps
CPU time 2.86 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 209036 kb
Host smart-26c87248-c978-45da-afb5-5ce7460dc573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453754318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3453754318
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1897915735
Short name T75
Test name
Test status
Simulation time 938832655 ps
CPU time 2.63 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 201236 kb
Host smart-a8df4129-0ed0-4f3c-a0af-10a467a3989a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897915735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1897915735
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3190570786
Short name T620
Test name
Test status
Simulation time 99204197 ps
CPU time 0.92 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 200820 kb
Host smart-567a676c-799e-45c3-9378-3e1779bfa8dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190570786 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.3190570786
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.1736110746
Short name T101
Test name
Test status
Simulation time 69653642 ps
CPU time 0.84 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:41 PM PDT 24
Peak memory 200656 kb
Host smart-cfb92cc0-abe0-4985-aefc-78bdbce2e16e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736110746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1736110746
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3750237464
Short name T616
Test name
Test status
Simulation time 132775945 ps
CPU time 1.28 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:42 PM PDT 24
Peak memory 200980 kb
Host smart-01832ec4-eaa5-45e7-9713-7c6baf603f6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750237464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_s
ame_csr_outstanding.3750237464
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3478949913
Short name T581
Test name
Test status
Simulation time 209739408 ps
CPU time 2.97 seconds
Started Aug 19 04:28:41 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 209096 kb
Host smart-fad942b0-3829-4180-b17e-c420ff077420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478949913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3478949913
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2428156001
Short name T618
Test name
Test status
Simulation time 890547465 ps
CPU time 2.99 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 201052 kb
Host smart-72a3d667-9288-4b12-a516-c9a30222b965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428156001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2428156001
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.904421285
Short name T72
Test name
Test status
Simulation time 202532810 ps
CPU time 1.31 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 209064 kb
Host smart-73210249-45cc-4de7-b21d-561ca8f4771c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904421285 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.904421285
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2603898020
Short name T592
Test name
Test status
Simulation time 69271567 ps
CPU time 0.77 seconds
Started Aug 19 04:28:45 PM PDT 24
Finished Aug 19 04:28:46 PM PDT 24
Peak memory 200728 kb
Host smart-730d03a7-fb5b-40eb-b815-d454f0545cdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603898020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2603898020
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2995921172
Short name T103
Test name
Test status
Simulation time 253149705 ps
CPU time 1.53 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200976 kb
Host smart-46671c54-1158-4a81-8afd-b259f6529824
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995921172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.2995921172
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.1407025182
Short name T607
Test name
Test status
Simulation time 516408571 ps
CPU time 3.25 seconds
Started Aug 19 04:28:52 PM PDT 24
Finished Aug 19 04:28:55 PM PDT 24
Peak memory 211980 kb
Host smart-bf1cf7dd-7044-4113-8e1a-1b21757846e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407025182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.1407025182
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2064830557
Short name T113
Test name
Test status
Simulation time 795325166 ps
CPU time 3.08 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 201020 kb
Host smart-317880ce-1e0f-4cbc-af4f-c039e1ff08b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064830557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.2064830557
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3629540968
Short name T609
Test name
Test status
Simulation time 130786525 ps
CPU time 1 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200824 kb
Host smart-d409c016-9cf0-4f8f-98bc-a9b3e8ad2237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629540968 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.3629540968
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.2000156061
Short name T548
Test name
Test status
Simulation time 74941934 ps
CPU time 0.84 seconds
Started Aug 19 04:28:42 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 200672 kb
Host smart-d2c42ef4-f63f-4f2b-8c6a-9fbbd85653bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000156061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2000156061
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.685901836
Short name T603
Test name
Test status
Simulation time 223081996 ps
CPU time 1.5 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 200924 kb
Host smart-9beda4ed-215e-4185-92bd-ba4d21f0b30e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685901836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.685901836
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3516879619
Short name T111
Test name
Test status
Simulation time 579249534 ps
CPU time 3.54 seconds
Started Aug 19 04:28:46 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 209244 kb
Host smart-b20a9f38-a779-4087-afd8-ce603183168d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516879619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3516879619
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.203894700
Short name T598
Test name
Test status
Simulation time 890155946 ps
CPU time 2.85 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:42 PM PDT 24
Peak memory 200996 kb
Host smart-64ad045e-d9ed-45a2-8b77-88dbecdfefe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203894700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.203894700
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1134537036
Short name T84
Test name
Test status
Simulation time 211408269 ps
CPU time 1.33 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 209116 kb
Host smart-c0c8a2ba-66cf-4db8-9db9-938eee97799d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134537036 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.1134537036
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2689246717
Short name T100
Test name
Test status
Simulation time 66663246 ps
CPU time 0.77 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200672 kb
Host smart-40a27224-2106-43e6-962b-d9d6ac7e1b23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689246717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2689246717
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2550751953
Short name T599
Test name
Test status
Simulation time 95995011 ps
CPU time 1.16 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200980 kb
Host smart-76eae197-006e-4b84-b457-24a4dc93492a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550751953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.2550751953
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.4130374551
Short name T575
Test name
Test status
Simulation time 486025176 ps
CPU time 3.32 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 209112 kb
Host smart-f7107977-3862-424b-87b3-a1ddf170633e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130374551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4130374551
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3313606189
Short name T108
Test name
Test status
Simulation time 914991933 ps
CPU time 2.9 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 200900 kb
Host smart-54081eac-dffa-48dd-83d1-5cf1c0733917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313606189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.3313606189
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2719704098
Short name T73
Test name
Test status
Simulation time 203815245 ps
CPU time 1.39 seconds
Started Aug 19 04:28:42 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 209240 kb
Host smart-44f60fa5-c84c-4bf3-8c37-e12ce210d657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719704098 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.2719704098
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.3305880531
Short name T615
Test name
Test status
Simulation time 89285624 ps
CPU time 0.86 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:28:58 PM PDT 24
Peak memory 200668 kb
Host smart-097fcbaf-4c78-43d3-8c29-66309607880e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305880531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3305880531
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1288429475
Short name T98
Test name
Test status
Simulation time 87207960 ps
CPU time 0.99 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 200836 kb
Host smart-798ddca7-904b-4d3d-9628-519359f164ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288429475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1288429475
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.974774246
Short name T590
Test name
Test status
Simulation time 496333583 ps
CPU time 3.65 seconds
Started Aug 19 04:28:53 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 209056 kb
Host smart-6d54f413-446e-4ce6-8e82-9e3376349aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974774246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.974774246
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.56125432
Short name T602
Test name
Test status
Simulation time 901921238 ps
CPU time 2.99 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 201000 kb
Host smart-1bc4aa9c-49c0-4298-8396-fc2bf1d7c4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56125432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.56125432
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1604759405
Short name T561
Test name
Test status
Simulation time 183481165 ps
CPU time 1.76 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 209272 kb
Host smart-ec41607a-a18f-487f-b691-0c6ac43a26a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604759405 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1604759405
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.2814957907
Short name T558
Test name
Test status
Simulation time 70624655 ps
CPU time 0.78 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 200796 kb
Host smart-ccef3212-6691-4397-9420-28a98b423bc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814957907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2814957907
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2778117755
Short name T566
Test name
Test status
Simulation time 269332934 ps
CPU time 1.78 seconds
Started Aug 19 04:28:53 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 201036 kb
Host smart-85e8f973-0b44-4a80-8ffe-c92b9ba160c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778117755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_s
ame_csr_outstanding.2778117755
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.990929834
Short name T87
Test name
Test status
Simulation time 418406604 ps
CPU time 2.8 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 209052 kb
Host smart-fdb4b304-2a2d-433b-bf69-1413a330a70a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990929834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.990929834
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1216386694
Short name T588
Test name
Test status
Simulation time 438741576 ps
CPU time 1.74 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200972 kb
Host smart-e64ae611-cb1b-4a7f-ae2c-cc694e18358c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216386694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.1216386694
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2840828457
Short name T563
Test name
Test status
Simulation time 155412855 ps
CPU time 1.96 seconds
Started Aug 19 04:28:30 PM PDT 24
Finished Aug 19 04:28:32 PM PDT 24
Peak memory 200788 kb
Host smart-c50e4449-694a-4b69-a5c9-a2ab113dd986
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840828457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2
840828457
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1731739141
Short name T587
Test name
Test status
Simulation time 479577138 ps
CPU time 5.91 seconds
Started Aug 19 04:28:30 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 200800 kb
Host smart-28a656e1-7085-43d4-acc8-3cc365e1731e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731739141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
731739141
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2171873954
Short name T579
Test name
Test status
Simulation time 116315524 ps
CPU time 0.93 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 200676 kb
Host smart-01b9775c-8ebe-4e82-9766-a8c89a24a833
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171873954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
171873954
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1307004801
Short name T70
Test name
Test status
Simulation time 188280213 ps
CPU time 1.82 seconds
Started Aug 19 04:28:34 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 209200 kb
Host smart-5f1cf0a1-1be8-4c28-8b38-9b695ebd5964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307004801 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.1307004801
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.4001150372
Short name T567
Test name
Test status
Simulation time 62781027 ps
CPU time 0.77 seconds
Started Aug 19 04:28:46 PM PDT 24
Finished Aug 19 04:28:47 PM PDT 24
Peak memory 200796 kb
Host smart-6af88483-1032-4d44-9638-46ad59056ad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001150372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.4001150372
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4251343695
Short name T617
Test name
Test status
Simulation time 115284921 ps
CPU time 1 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 200828 kb
Host smart-a1ed09f9-0db2-4c70-830b-430a7a4fa103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251343695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.4251343695
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.4236340257
Short name T570
Test name
Test status
Simulation time 186666732 ps
CPU time 2.67 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 209200 kb
Host smart-587069a5-5a67-4148-b5d6-26aae8807041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236340257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.4236340257
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1196484402
Short name T129
Test name
Test status
Simulation time 413409794 ps
CPU time 1.7 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:42 PM PDT 24
Peak memory 201028 kb
Host smart-92dea0a9-b50b-426d-8d28-27773b6f3463
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196484402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.1196484402
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2052274933
Short name T89
Test name
Test status
Simulation time 105316192 ps
CPU time 1.38 seconds
Started Aug 19 04:29:00 PM PDT 24
Finished Aug 19 04:29:02 PM PDT 24
Peak memory 200996 kb
Host smart-4bbb1332-50fe-4cc3-9c48-cad151c40698
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052274933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2
052274933
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3191306704
Short name T577
Test name
Test status
Simulation time 1541412387 ps
CPU time 8.1 seconds
Started Aug 19 04:28:35 PM PDT 24
Finished Aug 19 04:28:43 PM PDT 24
Peak memory 217148 kb
Host smart-c3b0ad9f-95b5-41e1-8463-b2ec1562ae67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191306704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3
191306704
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.1905046842
Short name T614
Test name
Test status
Simulation time 156494924 ps
CPU time 0.94 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200792 kb
Host smart-ee4127cf-d7bb-4962-9ca7-140607ee54ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905046842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.1
905046842
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1162032526
Short name T107
Test name
Test status
Simulation time 183116035 ps
CPU time 1.65 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 209216 kb
Host smart-edd6c358-39e9-4d9d-a56c-87c35497af9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162032526 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.1162032526
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.2311782026
Short name T97
Test name
Test status
Simulation time 59398327 ps
CPU time 0.82 seconds
Started Aug 19 04:29:00 PM PDT 24
Finished Aug 19 04:29:01 PM PDT 24
Peak memory 200680 kb
Host smart-c481d4ea-1ec0-4fe3-9c02-21ebc08fa1ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311782026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2311782026
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1012263883
Short name T102
Test name
Test status
Simulation time 111952962 ps
CPU time 1.34 seconds
Started Aug 19 04:28:35 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 200896 kb
Host smart-8cb90eee-e812-4610-8b6e-bbce82ace57e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012263883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.1012263883
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1977205328
Short name T116
Test name
Test status
Simulation time 159870170 ps
CPU time 2.35 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 209216 kb
Host smart-d6da4c29-cc77-470d-90f3-1bf372cbdd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977205328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1977205328
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1603869728
Short name T610
Test name
Test status
Simulation time 430158008 ps
CPU time 1.76 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:41 PM PDT 24
Peak memory 201024 kb
Host smart-7984642c-925f-4b66-8806-8529b1094ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603869728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err
.1603869728
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1901932164
Short name T557
Test name
Test status
Simulation time 105952120 ps
CPU time 1.41 seconds
Started Aug 19 04:28:33 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 200948 kb
Host smart-b91b33d6-b34a-4df0-a852-05a1d0fc87c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901932164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1
901932164
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2824494855
Short name T545
Test name
Test status
Simulation time 1555511435 ps
CPU time 7.92 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 200864 kb
Host smart-6ac07645-e52a-42a9-92c4-d903a732ced0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824494855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2
824494855
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.292666922
Short name T551
Test name
Test status
Simulation time 92160854 ps
CPU time 0.84 seconds
Started Aug 19 04:29:01 PM PDT 24
Finished Aug 19 04:29:02 PM PDT 24
Peak memory 200788 kb
Host smart-1dff2f4f-45e7-4406-a634-6cff33c4174e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292666922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.292666922
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.4237514155
Short name T82
Test name
Test status
Simulation time 121660777 ps
CPU time 0.99 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200748 kb
Host smart-075ddfbd-0116-465b-9666-6ef4ef8ce2aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237514155 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.4237514155
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.1679299230
Short name T584
Test name
Test status
Simulation time 84871965 ps
CPU time 0.91 seconds
Started Aug 19 04:28:44 PM PDT 24
Finished Aug 19 04:28:45 PM PDT 24
Peak memory 200820 kb
Host smart-f977fae0-6ddf-407a-972d-658bd3b475ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679299230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1679299230
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.4214948914
Short name T619
Test name
Test status
Simulation time 114070900 ps
CPU time 1.02 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200860 kb
Host smart-951a67be-74f3-4dd8-9f29-7ae7b3de95aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214948914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sa
me_csr_outstanding.4214948914
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.1371873139
Short name T601
Test name
Test status
Simulation time 103064424 ps
CPU time 1.46 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 211148 kb
Host smart-ac0125af-fea1-48a2-80b9-37ad57082398
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371873139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1371873139
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.4252999430
Short name T127
Test name
Test status
Simulation time 432079448 ps
CPU time 1.75 seconds
Started Aug 19 04:28:32 PM PDT 24
Finished Aug 19 04:28:34 PM PDT 24
Peak memory 201032 kb
Host smart-30529903-e0c9-44db-94f7-64e9fd87ab32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252999430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.4252999430
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1191593854
Short name T86
Test name
Test status
Simulation time 180327997 ps
CPU time 1.14 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 200788 kb
Host smart-fef316ae-5d21-4064-b52e-269db0925986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191593854 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.1191593854
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.3980748815
Short name T612
Test name
Test status
Simulation time 66314387 ps
CPU time 0.76 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 201012 kb
Host smart-fb0d480d-d40d-4fbb-a6c8-13fe5d1d954d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980748815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3980748815
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1407530459
Short name T569
Test name
Test status
Simulation time 238540742 ps
CPU time 1.52 seconds
Started Aug 19 04:29:04 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 200964 kb
Host smart-c2d0e008-6574-4e8e-b8ac-164b8b911925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407530459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.1407530459
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1301979866
Short name T595
Test name
Test status
Simulation time 120189540 ps
CPU time 1.7 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:42 PM PDT 24
Peak memory 209184 kb
Host smart-de7bfa99-a5f2-4bd1-a829-b7282fe7a0e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301979866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1301979866
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1998268778
Short name T112
Test name
Test status
Simulation time 411033778 ps
CPU time 1.77 seconds
Started Aug 19 04:28:30 PM PDT 24
Finished Aug 19 04:28:32 PM PDT 24
Peak memory 200892 kb
Host smart-54f0b952-b069-4cbc-9f92-0f5cd0a20a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998268778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1998268778
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1929143174
Short name T555
Test name
Test status
Simulation time 188833687 ps
CPU time 1.32 seconds
Started Aug 19 04:28:33 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 208980 kb
Host smart-cc4995a4-d863-45af-9499-fcae25c25a6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929143174 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1929143174
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.1219410785
Short name T574
Test name
Test status
Simulation time 69331702 ps
CPU time 0.78 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200656 kb
Host smart-f7cc2a20-76f0-4f33-a831-92d44f56b019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219410785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1219410785
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.478225606
Short name T611
Test name
Test status
Simulation time 196707673 ps
CPU time 1.4 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200880 kb
Host smart-16901d29-c93c-4849-847d-823f4295adcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478225606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sam
e_csr_outstanding.478225606
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2616683215
Short name T85
Test name
Test status
Simulation time 202036225 ps
CPU time 1.9 seconds
Started Aug 19 04:28:43 PM PDT 24
Finished Aug 19 04:28:45 PM PDT 24
Peak memory 209260 kb
Host smart-0ef64a65-5f9e-4c26-9b77-74b0364fafe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616683215 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.2616683215
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.787938867
Short name T560
Test name
Test status
Simulation time 74194661 ps
CPU time 0.74 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200772 kb
Host smart-eff97be1-0135-42b2-9795-a659ea6b7831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787938867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.787938867
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4006629806
Short name T104
Test name
Test status
Simulation time 140859933 ps
CPU time 1.16 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 200848 kb
Host smart-ab14fa72-ffea-4f7c-b028-5200a5d9cb81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006629806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.4006629806
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2621857362
Short name T114
Test name
Test status
Simulation time 405323573 ps
CPU time 2.95 seconds
Started Aug 19 04:28:41 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 209192 kb
Host smart-161880c1-bbcd-4cc1-8c5b-9b973ee43d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621857362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2621857362
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.3538303403
Short name T109
Test name
Test status
Simulation time 799153901 ps
CPU time 2.74 seconds
Started Aug 19 04:28:38 PM PDT 24
Finished Aug 19 04:28:41 PM PDT 24
Peak memory 200984 kb
Host smart-1f8e9be9-cd2e-486e-aa6d-1353a7210468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538303403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.3538303403
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4093160525
Short name T606
Test name
Test status
Simulation time 112205445 ps
CPU time 1 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 200816 kb
Host smart-50f75b31-d233-43cb-badf-31b966c29b46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093160525 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.4093160525
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.4128163422
Short name T564
Test name
Test status
Simulation time 55363306 ps
CPU time 0.73 seconds
Started Aug 19 04:28:36 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 200768 kb
Host smart-c29734ee-9504-43d4-a3e6-2fc0e57af32f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128163422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.4128163422
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3280008529
Short name T96
Test name
Test status
Simulation time 101322840 ps
CPU time 1.21 seconds
Started Aug 19 04:28:46 PM PDT 24
Finished Aug 19 04:28:47 PM PDT 24
Peak memory 200992 kb
Host smart-b7b35865-4bae-4576-8b89-2dd68bd43c13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280008529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sa
me_csr_outstanding.3280008529
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.1127540494
Short name T572
Test name
Test status
Simulation time 485952446 ps
CPU time 3.53 seconds
Started Aug 19 04:28:45 PM PDT 24
Finished Aug 19 04:28:48 PM PDT 24
Peak memory 217292 kb
Host smart-0da209da-6bee-4cec-9527-1b587ed43875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127540494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1127540494
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1006385530
Short name T126
Test name
Test status
Simulation time 892319828 ps
CPU time 2.93 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200920 kb
Host smart-29e8a603-d0a4-4abe-bf5a-2ebc6a357410
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006385530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err
.1006385530
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.851661757
Short name T549
Test name
Test status
Simulation time 104856735 ps
CPU time 1.26 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 209100 kb
Host smart-5305979b-6cb4-43f1-b8d4-be13c8fb3d13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851661757 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.851661757
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.3664367382
Short name T593
Test name
Test status
Simulation time 73986082 ps
CPU time 0.82 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 200796 kb
Host smart-e4e57c58-026b-455e-9449-9fce7de95e8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664367382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3664367382
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.714707899
Short name T596
Test name
Test status
Simulation time 88830657 ps
CPU time 0.97 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:41 PM PDT 24
Peak memory 200856 kb
Host smart-3d2982f1-26fc-49fc-b7cf-87017a6d3692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714707899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sam
e_csr_outstanding.714707899
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.3564387553
Short name T578
Test name
Test status
Simulation time 226324564 ps
CPU time 1.93 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:42 PM PDT 24
Peak memory 209084 kb
Host smart-ec3b3856-aefd-4f35-b176-3565c06b8823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564387553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3564387553
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3134683169
Short name T554
Test name
Test status
Simulation time 421243332 ps
CPU time 1.86 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 201020 kb
Host smart-eac54cdf-24b7-4b94-86a3-cf996cefefcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134683169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.3134683169
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.365712883
Short name T343
Test name
Test status
Simulation time 58532874 ps
CPU time 0.73 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:44 PM PDT 24
Peak memory 200460 kb
Host smart-84c9dec2-4217-4984-ba91-f1509023bb23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365712883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.365712883
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.2150739450
Short name T31
Test name
Test status
Simulation time 1227614187 ps
CPU time 5.5 seconds
Started Aug 19 04:33:57 PM PDT 24
Finished Aug 19 04:34:02 PM PDT 24
Peak memory 218024 kb
Host smart-7e60d74c-3bcd-4be0-84aa-f7dadf4c9310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150739450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2150739450
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.625613324
Short name T362
Test name
Test status
Simulation time 245247036 ps
CPU time 1.08 seconds
Started Aug 19 04:33:58 PM PDT 24
Finished Aug 19 04:33:59 PM PDT 24
Peak memory 217780 kb
Host smart-b3bd4ad9-0ef4-475b-af13-ce7e639a0cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625613324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.625613324
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.835357723
Short name T258
Test name
Test status
Simulation time 146581699 ps
CPU time 0.86 seconds
Started Aug 19 04:33:41 PM PDT 24
Finished Aug 19 04:33:42 PM PDT 24
Peak memory 200440 kb
Host smart-fbd1a931-0226-4b26-b460-f53e1322252e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835357723 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.835357723
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.1742381082
Short name T29
Test name
Test status
Simulation time 775903139 ps
CPU time 4.46 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:06 PM PDT 24
Peak memory 200820 kb
Host smart-23f4b41e-5863-42b8-ac58-1b8cd18c93a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742381082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1742381082
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.4114438236
Short name T79
Test name
Test status
Simulation time 8280928230 ps
CPU time 15.2 seconds
Started Aug 19 04:33:58 PM PDT 24
Finished Aug 19 04:34:13 PM PDT 24
Peak memory 217404 kb
Host smart-2a4880b0-f921-41b5-9711-bc66c9d7e606
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114438236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4114438236
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2956423347
Short name T178
Test name
Test status
Simulation time 102611317 ps
CPU time 1.01 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:01 PM PDT 24
Peak memory 200612 kb
Host smart-322398b6-2d2f-42ac-be2b-f3ee4ed8a271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956423347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2956423347
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.4092395455
Short name T489
Test name
Test status
Simulation time 252455985 ps
CPU time 1.53 seconds
Started Aug 19 04:33:42 PM PDT 24
Finished Aug 19 04:33:49 PM PDT 24
Peak memory 200700 kb
Host smart-a434629a-403e-4d0c-8ace-aed93966caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092395455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4092395455
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.4250618692
Short name T377
Test name
Test status
Simulation time 10594698890 ps
CPU time 35.9 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:34:22 PM PDT 24
Peak memory 209752 kb
Host smart-ebc47a55-5ba4-4f01-88ee-9c58616e2e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250618692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4250618692
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.942971445
Short name T468
Test name
Test status
Simulation time 355528754 ps
CPU time 2.36 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 200532 kb
Host smart-5d3537c3-e36f-42ad-a8e2-a6c0ef4aaa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942971445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.942971445
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2366298364
Short name T142
Test name
Test status
Simulation time 77238532 ps
CPU time 0.78 seconds
Started Aug 19 04:33:45 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 200612 kb
Host smart-2e0fe29a-257d-4ea8-86eb-7392c6a01a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366298364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2366298364
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.2920323669
Short name T506
Test name
Test status
Simulation time 67076856 ps
CPU time 0.72 seconds
Started Aug 19 04:34:00 PM PDT 24
Finished Aug 19 04:34:01 PM PDT 24
Peak memory 200488 kb
Host smart-a75661f7-3709-4c5b-a5bd-96c7fb02e4b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920323669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2920323669
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.24720857
Short name T525
Test name
Test status
Simulation time 2178000877 ps
CPU time 8.67 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:08 PM PDT 24
Peak memory 221940 kb
Host smart-fd8b526c-140a-4130-99f6-416ce77ac706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24720857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.24720857
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_reset.1521825821
Short name T481
Test name
Test status
Simulation time 1022836126 ps
CPU time 4.93 seconds
Started Aug 19 04:33:51 PM PDT 24
Finished Aug 19 04:33:56 PM PDT 24
Peak memory 200764 kb
Host smart-ce8c71fb-037d-44a2-87e4-af9c64c3c7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521825821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1521825821
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.1600507559
Short name T76
Test name
Test status
Simulation time 16547827166 ps
CPU time 25.43 seconds
Started Aug 19 04:33:44 PM PDT 24
Finished Aug 19 04:34:09 PM PDT 24
Peak memory 217300 kb
Host smart-2ef07fd9-8013-44f4-b174-305560639e05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600507559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1600507559
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1062693878
Short name T364
Test name
Test status
Simulation time 145647074 ps
CPU time 1.11 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:44 PM PDT 24
Peak memory 200636 kb
Host smart-ec1f4fed-d247-4217-a8c3-18df1920e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062693878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1062693878
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1463302478
Short name T216
Test name
Test status
Simulation time 120989910 ps
CPU time 1.14 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:49 PM PDT 24
Peak memory 200660 kb
Host smart-5bf638f3-b864-4f4c-a19b-c70105cd8bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463302478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1463302478
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.4106693026
Short name T341
Test name
Test status
Simulation time 4025386452 ps
CPU time 16.87 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:34:00 PM PDT 24
Peak memory 209016 kb
Host smart-050390ee-a557-4a7b-9f8e-500b0b6fb6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106693026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4106693026
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.3025764339
Short name T439
Test name
Test status
Simulation time 120454796 ps
CPU time 1.41 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:45 PM PDT 24
Peak memory 200436 kb
Host smart-c5e82ecb-be66-4303-b6c6-9088481531fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025764339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.3025764339
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.3448948778
Short name T388
Test name
Test status
Simulation time 77580128 ps
CPU time 0.78 seconds
Started Aug 19 04:34:01 PM PDT 24
Finished Aug 19 04:34:02 PM PDT 24
Peak memory 200468 kb
Host smart-e64cdaac-3016-4af3-b7a8-3eca943a8815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448948778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3448948778
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2485712182
Short name T151
Test name
Test status
Simulation time 244584251 ps
CPU time 1.13 seconds
Started Aug 19 04:33:58 PM PDT 24
Finished Aug 19 04:33:59 PM PDT 24
Peak memory 217792 kb
Host smart-31933f3b-103e-4538-9deb-453246b745b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485712182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2485712182
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.3652132530
Short name T411
Test name
Test status
Simulation time 88732724 ps
CPU time 0.78 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:22 PM PDT 24
Peak memory 200448 kb
Host smart-b55cef7d-94ce-4b0e-a889-53b36f43bfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652132530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3652132530
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/10.rstmgr_reset.2320414163
Short name T274
Test name
Test status
Simulation time 710659733 ps
CPU time 3.71 seconds
Started Aug 19 04:34:14 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 200776 kb
Host smart-2d7ffbd6-115e-46fe-8e82-481379e4acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320414163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2320414163
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3399320309
Short name T474
Test name
Test status
Simulation time 170070935 ps
CPU time 1.13 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:17 PM PDT 24
Peak memory 200636 kb
Host smart-1b66d768-3627-482a-b9c4-9ffb7b6320b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399320309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3399320309
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.4040636709
Short name T447
Test name
Test status
Simulation time 118730356 ps
CPU time 1.17 seconds
Started Aug 19 04:33:44 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 200724 kb
Host smart-e18d8d27-11c9-4447-a42c-ba498c56665d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040636709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.4040636709
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.3478552767
Short name T310
Test name
Test status
Simulation time 3706346059 ps
CPU time 13.59 seconds
Started Aug 19 04:33:56 PM PDT 24
Finished Aug 19 04:34:09 PM PDT 24
Peak memory 200800 kb
Host smart-09ddfe44-1398-48b1-a457-41135b41ce34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478552767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3478552767
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.3731215862
Short name T500
Test name
Test status
Simulation time 142482422 ps
CPU time 1.63 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 200520 kb
Host smart-25502a8c-6fd5-411a-99f7-ae92f3a30936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731215862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3731215862
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.2583419371
Short name T464
Test name
Test status
Simulation time 74873287 ps
CPU time 0.79 seconds
Started Aug 19 04:33:55 PM PDT 24
Finished Aug 19 04:33:56 PM PDT 24
Peak memory 200612 kb
Host smart-0bd353c3-da04-48f0-b271-c33e8b2f7dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583419371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2583419371
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1680230832
Short name T266
Test name
Test status
Simulation time 65612130 ps
CPU time 0.75 seconds
Started Aug 19 04:34:01 PM PDT 24
Finished Aug 19 04:34:02 PM PDT 24
Peak memory 200464 kb
Host smart-fe8f9880-3c84-4cd4-8a6b-02f1c4d42a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680230832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1680230832
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.3003971457
Short name T419
Test name
Test status
Simulation time 1222244120 ps
CPU time 5.39 seconds
Started Aug 19 04:34:00 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 217892 kb
Host smart-ec70638a-0ebc-43ec-a837-69af928d33b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003971457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3003971457
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1944397327
Short name T9
Test name
Test status
Simulation time 243404708 ps
CPU time 1.14 seconds
Started Aug 19 04:33:58 PM PDT 24
Finished Aug 19 04:34:00 PM PDT 24
Peak memory 217664 kb
Host smart-f37f7516-ed2d-4f69-8994-741fb0e41c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944397327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1944397327
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.536568746
Short name T380
Test name
Test status
Simulation time 109457801 ps
CPU time 0.73 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:44 PM PDT 24
Peak memory 200276 kb
Host smart-fe8b5597-64d3-4f7f-82ee-ac5a048534d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536568746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.536568746
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.698220595
Short name T311
Test name
Test status
Simulation time 1010082437 ps
CPU time 4.71 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:48 PM PDT 24
Peak memory 201064 kb
Host smart-825561c2-559e-4d98-967d-abd437fac406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698220595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.698220595
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2824349551
Short name T458
Test name
Test status
Simulation time 102499500 ps
CPU time 1 seconds
Started Aug 19 04:34:00 PM PDT 24
Finished Aug 19 04:34:01 PM PDT 24
Peak memory 200608 kb
Host smart-7d9a0fa9-04bd-46b5-8fbc-38ed2a2342b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824349551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2824349551
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.1394027155
Short name T538
Test name
Test status
Simulation time 243148489 ps
CPU time 1.45 seconds
Started Aug 19 04:33:58 PM PDT 24
Finished Aug 19 04:33:59 PM PDT 24
Peak memory 200652 kb
Host smart-32502b2d-2ec4-4091-ad4e-ea7882cc6507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394027155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1394027155
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.4195969321
Short name T17
Test name
Test status
Simulation time 1960886358 ps
CPU time 8.15 seconds
Started Aug 19 04:33:45 PM PDT 24
Finished Aug 19 04:33:53 PM PDT 24
Peak memory 200648 kb
Host smart-854b6c29-028c-4bd1-92d1-0944280563f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195969321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.4195969321
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.3164947555
Short name T526
Test name
Test status
Simulation time 378489396 ps
CPU time 1.99 seconds
Started Aug 19 04:34:03 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 200492 kb
Host smart-f6e9bd88-3f42-4242-861f-f32e2f09734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164947555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.3164947555
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.1196620794
Short name T394
Test name
Test status
Simulation time 105451527 ps
CPU time 1.02 seconds
Started Aug 19 04:34:15 PM PDT 24
Finished Aug 19 04:34:17 PM PDT 24
Peak memory 200636 kb
Host smart-be225e5d-a564-4941-9f65-782699280b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196620794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1196620794
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.1063573254
Short name T285
Test name
Test status
Simulation time 79908471 ps
CPU time 0.78 seconds
Started Aug 19 04:33:45 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 200352 kb
Host smart-2f76f80a-2ae3-4147-be55-fccdb41bbe48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063573254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1063573254
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.2679371275
Short name T52
Test name
Test status
Simulation time 1230781921 ps
CPU time 5.69 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:08 PM PDT 24
Peak memory 221012 kb
Host smart-a9d58057-ce9b-4c4f-8ca7-48a8e63edc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679371275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2679371275
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1048376433
Short name T177
Test name
Test status
Simulation time 247993648 ps
CPU time 1.03 seconds
Started Aug 19 04:33:57 PM PDT 24
Finished Aug 19 04:33:58 PM PDT 24
Peak memory 217748 kb
Host smart-7f486ec0-2dc9-4202-a418-a2c7c9748833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048376433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1048376433
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1225183726
Short name T26
Test name
Test status
Simulation time 139611451 ps
CPU time 0.86 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 200448 kb
Host smart-d1b0a4cc-b2a7-479f-ac0d-af90ce40b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225183726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1225183726
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2714753826
Short name T363
Test name
Test status
Simulation time 1063699929 ps
CPU time 4.93 seconds
Started Aug 19 04:33:57 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200736 kb
Host smart-4665331e-b36b-438c-b2f8-f6cf0a0fecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714753826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2714753826
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1755145254
Short name T484
Test name
Test status
Simulation time 167537412 ps
CPU time 1.24 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200600 kb
Host smart-22eeebca-ce2e-48ab-a11c-c1ff152c3c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755145254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1755145254
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.2478690654
Short name T327
Test name
Test status
Simulation time 121196822 ps
CPU time 1.25 seconds
Started Aug 19 04:34:06 PM PDT 24
Finished Aug 19 04:34:07 PM PDT 24
Peak memory 200608 kb
Host smart-04e0d4fb-3ca0-4b53-841f-9e8cb94b4ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478690654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2478690654
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.942976870
Short name T88
Test name
Test status
Simulation time 8119926306 ps
CPU time 35.75 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:52 PM PDT 24
Peak memory 217208 kb
Host smart-1e0f52fa-35fa-4b4f-a7b8-c91f7b1d49ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942976870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.942976870
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.2143189036
Short name T494
Test name
Test status
Simulation time 408857672 ps
CPU time 2.28 seconds
Started Aug 19 04:33:57 PM PDT 24
Finished Aug 19 04:33:59 PM PDT 24
Peak memory 208584 kb
Host smart-a92d1922-178c-4472-ab96-fe76c58887a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143189036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2143189036
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1152373094
Short name T397
Test name
Test status
Simulation time 114985099 ps
CPU time 0.92 seconds
Started Aug 19 04:34:20 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 200640 kb
Host smart-cb1e42a7-7c44-4f91-95d7-5703bd9a196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152373094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1152373094
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.2179950322
Short name T429
Test name
Test status
Simulation time 82740042 ps
CPU time 0.84 seconds
Started Aug 19 04:33:56 PM PDT 24
Finished Aug 19 04:33:57 PM PDT 24
Peak memory 200384 kb
Host smart-c86c3c8f-8061-4973-a099-9894f18fc973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179950322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2179950322
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1217903959
Short name T200
Test name
Test status
Simulation time 244409935 ps
CPU time 1.17 seconds
Started Aug 19 04:34:00 PM PDT 24
Finished Aug 19 04:34:02 PM PDT 24
Peak memory 217704 kb
Host smart-158537ec-435b-44a2-8c48-8f7db287bead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217903959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1217903959
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.1852725468
Short name T240
Test name
Test status
Simulation time 173908403 ps
CPU time 0.85 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:47 PM PDT 24
Peak memory 200424 kb
Host smart-619e7118-c367-484e-bf66-78dc5b3e2151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852725468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1852725468
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.3928974380
Short name T478
Test name
Test status
Simulation time 962364874 ps
CPU time 4.61 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 200660 kb
Host smart-eb33e92a-085e-44a2-9739-b00a98148b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928974380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3928974380
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.785712020
Short name T485
Test name
Test status
Simulation time 103038590 ps
CPU time 1.06 seconds
Started Aug 19 04:34:19 PM PDT 24
Finished Aug 19 04:34:20 PM PDT 24
Peak memory 200644 kb
Host smart-5504996f-308e-412f-8757-6fa2101400bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785712020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.785712020
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1594332893
Short name T535
Test name
Test status
Simulation time 200444546 ps
CPU time 1.31 seconds
Started Aug 19 04:34:01 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200752 kb
Host smart-ac50aae5-bdc1-41fb-9a8e-23725c6e6638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594332893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1594332893
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.2138815097
Short name T483
Test name
Test status
Simulation time 1832626587 ps
CPU time 6.49 seconds
Started Aug 19 04:34:19 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 208984 kb
Host smart-7560e0ea-9dc7-4a0d-92bd-24b52d68dcbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138815097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2138815097
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.1018313491
Short name T336
Test name
Test status
Simulation time 376909538 ps
CPU time 2.4 seconds
Started Aug 19 04:34:15 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 200504 kb
Host smart-39e8dc37-2f18-4b78-b4b9-3845a191f1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018313491 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1018313491
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.3431977013
Short name T368
Test name
Test status
Simulation time 74570043 ps
CPU time 0.78 seconds
Started Aug 19 04:33:44 PM PDT 24
Finished Aug 19 04:33:45 PM PDT 24
Peak memory 200516 kb
Host smart-0a441f65-20ad-4b01-8774-9712fa7286af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431977013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.3431977013
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.3397225311
Short name T460
Test name
Test status
Simulation time 66821341 ps
CPU time 0.77 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200444 kb
Host smart-05782a9b-b1b1-4a97-9dd3-ddd7cd2793a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397225311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.3397225311
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.2600110827
Short name T41
Test name
Test status
Simulation time 1900971511 ps
CPU time 7.25 seconds
Started Aug 19 04:34:22 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 217320 kb
Host smart-a32afba8-7141-4090-a124-1be27da8b504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600110827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.2600110827
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.649003633
Short name T81
Test name
Test status
Simulation time 243870490 ps
CPU time 1.03 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 217736 kb
Host smart-d5b0d3eb-3e56-48b6-96b0-836f81a56798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649003633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.649003633
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.1349821775
Short name T260
Test name
Test status
Simulation time 162107706 ps
CPU time 0.83 seconds
Started Aug 19 04:34:07 PM PDT 24
Finished Aug 19 04:34:07 PM PDT 24
Peak memory 200420 kb
Host smart-7a065893-8aac-438b-9300-330708afc541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349821775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1349821775
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2216373957
Short name T338
Test name
Test status
Simulation time 833908802 ps
CPU time 4.39 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:20 PM PDT 24
Peak memory 200788 kb
Host smart-738b18f0-bbaf-47f9-90bd-db4e462a5d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216373957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2216373957
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1625862182
Short name T454
Test name
Test status
Simulation time 171610428 ps
CPU time 1.2 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200636 kb
Host smart-988bc44f-c49b-4c40-896f-4d6956b045a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625862182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1625862182
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2653131077
Short name T195
Test name
Test status
Simulation time 196787168 ps
CPU time 1.49 seconds
Started Aug 19 04:33:57 PM PDT 24
Finished Aug 19 04:33:58 PM PDT 24
Peak memory 200656 kb
Host smart-ebb4b05e-bf79-41f6-8909-0a00bd9c89d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653131077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2653131077
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.3653646325
Short name T472
Test name
Test status
Simulation time 876029255 ps
CPU time 4.36 seconds
Started Aug 19 04:34:18 PM PDT 24
Finished Aug 19 04:34:23 PM PDT 24
Peak memory 200784 kb
Host smart-d75d59ee-42a3-4c91-9dab-8dca30beff80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653646325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3653646325
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.573346481
Short name T225
Test name
Test status
Simulation time 537658909 ps
CPU time 2.7 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:19 PM PDT 24
Peak memory 200536 kb
Host smart-7dbe4a4b-30d2-436c-b946-224124521573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573346481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.573346481
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.337438316
Short name T233
Test name
Test status
Simulation time 234903743 ps
CPU time 1.35 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:00 PM PDT 24
Peak memory 200512 kb
Host smart-0cad3e91-00e0-4133-98a4-cbdad700caac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337438316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.337438316
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.2673822215
Short name T428
Test name
Test status
Simulation time 67290776 ps
CPU time 0.78 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 200492 kb
Host smart-a0df440d-f938-4514-af72-a816a0256112
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673822215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2673822215
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.2943172129
Short name T518
Test name
Test status
Simulation time 1212082435 ps
CPU time 5.72 seconds
Started Aug 19 04:34:15 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 217624 kb
Host smart-d063566c-4dbd-4e24-97fa-b15181101c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943172129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2943172129
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.2706108042
Short name T540
Test name
Test status
Simulation time 245078906 ps
CPU time 1.02 seconds
Started Aug 19 04:34:07 PM PDT 24
Finished Aug 19 04:34:08 PM PDT 24
Peak memory 217852 kb
Host smart-02d6ab8c-ff38-4b44-abf2-cee777706017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706108042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.2706108042
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.3806759039
Short name T510
Test name
Test status
Simulation time 247706609 ps
CPU time 0.99 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200304 kb
Host smart-e195ffbd-92c2-47f8-81bf-e25a04682b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806759039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3806759039
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.4021347022
Short name T212
Test name
Test status
Simulation time 1206453096 ps
CPU time 5.26 seconds
Started Aug 19 04:34:04 PM PDT 24
Finished Aug 19 04:34:09 PM PDT 24
Peak memory 200728 kb
Host smart-3fd667b8-2e2a-4053-9c60-eed4225c918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021347022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.4021347022
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2251013356
Short name T243
Test name
Test status
Simulation time 152957444 ps
CPU time 1.12 seconds
Started Aug 19 04:34:22 PM PDT 24
Finished Aug 19 04:34:23 PM PDT 24
Peak memory 200644 kb
Host smart-8c4226c2-977a-42f9-9528-c0f92dc16bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251013356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2251013356
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.819630229
Short name T505
Test name
Test status
Simulation time 121036123 ps
CPU time 1.23 seconds
Started Aug 19 04:34:03 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 200692 kb
Host smart-e1cb8e44-1274-445a-8ce0-bfac4dc5c28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819630229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.819630229
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.3765135094
Short name T455
Test name
Test status
Simulation time 9523699747 ps
CPU time 34.45 seconds
Started Aug 19 04:34:19 PM PDT 24
Finished Aug 19 04:34:53 PM PDT 24
Peak memory 200900 kb
Host smart-a930d340-0dd5-4dd1-9dbe-734b7e907c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765135094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3765135094
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2883465283
Short name T473
Test name
Test status
Simulation time 116702568 ps
CPU time 1.35 seconds
Started Aug 19 04:34:13 PM PDT 24
Finished Aug 19 04:34:15 PM PDT 24
Peak memory 200516 kb
Host smart-f00ee11b-2bab-4564-b705-c4d6f6b632ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883465283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2883465283
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.370904517
Short name T398
Test name
Test status
Simulation time 155035386 ps
CPU time 1.06 seconds
Started Aug 19 04:34:08 PM PDT 24
Finished Aug 19 04:34:09 PM PDT 24
Peak memory 200632 kb
Host smart-a1f76bc5-e88b-43e3-b591-e96963c495f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370904517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.370904517
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.3305011990
Short name T496
Test name
Test status
Simulation time 73608353 ps
CPU time 0.79 seconds
Started Aug 19 04:34:01 PM PDT 24
Finished Aug 19 04:34:02 PM PDT 24
Peak memory 200364 kb
Host smart-92ac54c0-4849-4f5b-bc75-e4dcf63fe4d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305011990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3305011990
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.185235751
Short name T340
Test name
Test status
Simulation time 1232632170 ps
CPU time 5.88 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:23 PM PDT 24
Peak memory 217972 kb
Host smart-dba558ca-2768-4dcd-899c-c43331ceb98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185235751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.185235751
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1494600934
Short name T437
Test name
Test status
Simulation time 244737028 ps
CPU time 1.11 seconds
Started Aug 19 04:34:08 PM PDT 24
Finished Aug 19 04:34:10 PM PDT 24
Peak memory 217740 kb
Host smart-524ee664-a832-424c-b69f-20c2338897e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494600934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1494600934
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.4021913246
Short name T24
Test name
Test status
Simulation time 141740310 ps
CPU time 0.92 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200340 kb
Host smart-b33cfbcc-b0ba-4c8c-ab3e-6289639d95a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021913246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4021913246
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3342189657
Short name T206
Test name
Test status
Simulation time 792028482 ps
CPU time 3.99 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200760 kb
Host smart-cf40de26-4228-484e-afa8-1d25667bf5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342189657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3342189657
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3282103785
Short name T386
Test name
Test status
Simulation time 113572588 ps
CPU time 1.11 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 200624 kb
Host smart-eadfdd35-af2c-48f6-ba6f-ef1db75cf675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282103785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3282103785
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.2158880260
Short name T207
Test name
Test status
Simulation time 111487043 ps
CPU time 1.32 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:19 PM PDT 24
Peak memory 200720 kb
Host smart-bec48472-a62e-430f-972d-5ce53f5cba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158880260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2158880260
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1753175490
Short name T218
Test name
Test status
Simulation time 2733170005 ps
CPU time 12 seconds
Started Aug 19 04:34:08 PM PDT 24
Finished Aug 19 04:34:20 PM PDT 24
Peak memory 209080 kb
Host smart-3c41f390-9841-49f4-9231-f956870396da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753175490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1753175490
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.2098731045
Short name T222
Test name
Test status
Simulation time 468252163 ps
CPU time 2.32 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200456 kb
Host smart-7e175091-28db-4ee2-aeda-b6de2141545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098731045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2098731045
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2033627211
Short name T309
Test name
Test status
Simulation time 101280691 ps
CPU time 0.97 seconds
Started Aug 19 04:34:04 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 200492 kb
Host smart-6ce585af-9ac5-4fcb-841c-5d63bbf5cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033627211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2033627211
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.1126261852
Short name T326
Test name
Test status
Simulation time 70119593 ps
CPU time 0.78 seconds
Started Aug 19 04:34:07 PM PDT 24
Finished Aug 19 04:34:08 PM PDT 24
Peak memory 200484 kb
Host smart-505b5757-f094-4957-bbea-14fd3ea90472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126261852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1126261852
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.478787013
Short name T471
Test name
Test status
Simulation time 1222368029 ps
CPU time 5.21 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 217928 kb
Host smart-48f61650-3d34-4b2e-b6aa-54a5e712f4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478787013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.478787013
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.4225299258
Short name T48
Test name
Test status
Simulation time 243998189 ps
CPU time 1.04 seconds
Started Aug 19 04:34:03 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 217756 kb
Host smart-88bffe95-ceb8-48b0-b360-5c8cfe5d4cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225299258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.4225299258
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.4135854285
Short name T345
Test name
Test status
Simulation time 126916480 ps
CPU time 0.78 seconds
Started Aug 19 04:34:06 PM PDT 24
Finished Aug 19 04:34:07 PM PDT 24
Peak memory 200388 kb
Host smart-374f4a37-f66e-49b9-918f-5835f8b443f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135854285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4135854285
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.2914824575
Short name T492
Test name
Test status
Simulation time 873203210 ps
CPU time 4.35 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200776 kb
Host smart-9e35e803-dbf0-4368-add3-b9d626e24731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914824575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2914824575
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.599827455
Short name T381
Test name
Test status
Simulation time 183193355 ps
CPU time 1.15 seconds
Started Aug 19 04:34:07 PM PDT 24
Finished Aug 19 04:34:08 PM PDT 24
Peak memory 200608 kb
Host smart-f4cfb26c-3aac-4931-af15-961db2057d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599827455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.599827455
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.1370655541
Short name T358
Test name
Test status
Simulation time 247192465 ps
CPU time 1.51 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 200752 kb
Host smart-e86a2571-9daf-45ef-9fbf-5b4a2e3fb3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370655541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1370655541
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.82140015
Short name T280
Test name
Test status
Simulation time 985783738 ps
CPU time 4.77 seconds
Started Aug 19 04:34:11 PM PDT 24
Finished Aug 19 04:34:16 PM PDT 24
Peak memory 200764 kb
Host smart-efeb9204-a716-4e3e-b210-1309ac564aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82140015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.82140015
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2742032619
Short name T366
Test name
Test status
Simulation time 269876207 ps
CPU time 1.91 seconds
Started Aug 19 04:34:05 PM PDT 24
Finished Aug 19 04:34:07 PM PDT 24
Peak memory 200468 kb
Host smart-ddb5ddcd-72e6-4da8-b47c-570cee8df58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742032619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2742032619
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3786385632
Short name T15
Test name
Test status
Simulation time 130707031 ps
CPU time 1.06 seconds
Started Aug 19 04:34:20 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 200636 kb
Host smart-52caaa4e-abb7-43e5-b842-0e1ff51458cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786385632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3786385632
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.2373621062
Short name T440
Test name
Test status
Simulation time 73242858 ps
CPU time 0.78 seconds
Started Aug 19 04:34:04 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 200448 kb
Host smart-b2025ed3-f00a-4a41-a7e1-29ebfe78a5c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373621062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2373621062
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.3202194897
Short name T68
Test name
Test status
Simulation time 1901163168 ps
CPU time 7.54 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:35 PM PDT 24
Peak memory 217900 kb
Host smart-5b1ed611-fe8f-4e4f-81bb-b4d0d82b085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202194897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3202194897
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1019089369
Short name T469
Test name
Test status
Simulation time 244608628 ps
CPU time 1.17 seconds
Started Aug 19 04:34:07 PM PDT 24
Finished Aug 19 04:34:09 PM PDT 24
Peak memory 217716 kb
Host smart-5aca818d-764e-47d8-ad98-90e5b6822894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019089369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1019089369
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.2684860612
Short name T193
Test name
Test status
Simulation time 183453425 ps
CPU time 0.87 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200388 kb
Host smart-896af2af-39d3-4b84-8229-c590863e594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684860612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2684860612
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.3124254320
Short name T349
Test name
Test status
Simulation time 804545456 ps
CPU time 4.25 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200792 kb
Host smart-bd8832a0-5d69-4aeb-b958-279ca9daffbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124254320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3124254320
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.999302858
Short name T517
Test name
Test status
Simulation time 176743266 ps
CPU time 1.13 seconds
Started Aug 19 04:34:10 PM PDT 24
Finished Aug 19 04:34:11 PM PDT 24
Peak memory 200580 kb
Host smart-08f5756b-580f-41c2-a6b5-4532c583e56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999302858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.999302858
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.845183332
Short name T321
Test name
Test status
Simulation time 123189278 ps
CPU time 1.16 seconds
Started Aug 19 04:34:03 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 200664 kb
Host smart-877c23e6-34f7-4599-b5f3-c9d7ffea8d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845183332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.845183332
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1959840374
Short name T438
Test name
Test status
Simulation time 10950127818 ps
CPU time 40.96 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 200844 kb
Host smart-0d6245b7-5033-4352-b5a5-cb62093b0fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959840374 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1959840374
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1079970370
Short name T536
Test name
Test status
Simulation time 383654277 ps
CPU time 2.37 seconds
Started Aug 19 04:34:15 PM PDT 24
Finished Aug 19 04:34:17 PM PDT 24
Peak memory 200540 kb
Host smart-635688a9-54fb-45aa-960b-f2295351e198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079970370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1079970370
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.1232993510
Short name T450
Test name
Test status
Simulation time 62652434 ps
CPU time 0.75 seconds
Started Aug 19 04:34:22 PM PDT 24
Finished Aug 19 04:34:23 PM PDT 24
Peak memory 200460 kb
Host smart-76199ea5-bba4-4ef6-a932-5ea4752eee81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232993510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.1232993510
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.2395132150
Short name T399
Test name
Test status
Simulation time 2163665681 ps
CPU time 7.64 seconds
Started Aug 19 04:34:08 PM PDT 24
Finished Aug 19 04:34:16 PM PDT 24
Peak memory 218016 kb
Host smart-59472653-f0a0-45a6-a7f9-c726fcd1a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395132150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2395132150
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4035710443
Short name T55
Test name
Test status
Simulation time 244369842 ps
CPU time 1.12 seconds
Started Aug 19 04:34:03 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 217796 kb
Host smart-a1f24fda-2bed-4fd5-8c09-a103e41c2c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035710443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4035710443
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.1461798874
Short name T27
Test name
Test status
Simulation time 136323627 ps
CPU time 0.82 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:22 PM PDT 24
Peak memory 200412 kb
Host smart-dd28da0d-3b11-49c5-a8ab-efab72237f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461798874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1461798874
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.1006837634
Short name T523
Test name
Test status
Simulation time 1093122782 ps
CPU time 5.49 seconds
Started Aug 19 04:34:01 PM PDT 24
Finished Aug 19 04:34:06 PM PDT 24
Peak memory 200760 kb
Host smart-7b5f644e-666c-4348-a04f-346fc2d232a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006837634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1006837634
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2834810301
Short name T239
Test name
Test status
Simulation time 154484754 ps
CPU time 1.14 seconds
Started Aug 19 04:34:15 PM PDT 24
Finished Aug 19 04:34:16 PM PDT 24
Peak memory 200620 kb
Host smart-da502e6a-49b0-40c9-b742-94cc36fb4ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834810301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2834810301
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2422742013
Short name T246
Test name
Test status
Simulation time 123071814 ps
CPU time 1.17 seconds
Started Aug 19 04:34:04 PM PDT 24
Finished Aug 19 04:34:06 PM PDT 24
Peak memory 200708 kb
Host smart-0dc57e8d-44af-4a8b-a919-97407c71a251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422742013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2422742013
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3602735306
Short name T90
Test name
Test status
Simulation time 2622389603 ps
CPU time 8.97 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:12 PM PDT 24
Peak memory 200836 kb
Host smart-26b79351-1a37-47f5-802f-48b274b9db75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602735306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3602735306
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.1926089849
Short name T459
Test name
Test status
Simulation time 67405897 ps
CPU time 0.83 seconds
Started Aug 19 04:34:13 PM PDT 24
Finished Aug 19 04:34:13 PM PDT 24
Peak memory 200536 kb
Host smart-ca229a40-a94f-439e-9e23-0008a35f4d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926089849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1926089849
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.789311823
Short name T389
Test name
Test status
Simulation time 85326160 ps
CPU time 0.77 seconds
Started Aug 19 04:34:08 PM PDT 24
Finished Aug 19 04:34:09 PM PDT 24
Peak memory 200496 kb
Host smart-d232a9f1-8dbb-45e7-af94-8083d3d82c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789311823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.789311823
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.608150342
Short name T542
Test name
Test status
Simulation time 1220174439 ps
CPU time 5.2 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:07 PM PDT 24
Peak memory 221892 kb
Host smart-303672de-6818-4cdd-931c-15c0f2825158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608150342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.608150342
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1840534534
Short name T284
Test name
Test status
Simulation time 244619011 ps
CPU time 1.11 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:49 PM PDT 24
Peak memory 217712 kb
Host smart-8ab206c9-a81b-46fb-a013-d4de09635a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840534534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1840534534
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.1532718546
Short name T230
Test name
Test status
Simulation time 228786459 ps
CPU time 0.89 seconds
Started Aug 19 04:33:58 PM PDT 24
Finished Aug 19 04:33:59 PM PDT 24
Peak memory 200428 kb
Host smart-b828bc41-db42-4cb0-b8b2-e7a975a4a00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532718546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1532718546
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.1547922978
Short name T529
Test name
Test status
Simulation time 1056752245 ps
CPU time 4.86 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:48 PM PDT 24
Peak memory 200740 kb
Host smart-2108a985-d673-4aa1-a42b-4d9f475da401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547922978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1547922978
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.152919251
Short name T383
Test name
Test status
Simulation time 175533077 ps
CPU time 1.15 seconds
Started Aug 19 04:34:04 PM PDT 24
Finished Aug 19 04:34:05 PM PDT 24
Peak memory 200612 kb
Host smart-f5fdcf99-7f73-48b5-9805-0f5e1bde25ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152919251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.152919251
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.718704051
Short name T322
Test name
Test status
Simulation time 110358988 ps
CPU time 1.11 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:01 PM PDT 24
Peak memory 200664 kb
Host smart-3eea6c4e-93fd-4279-8d30-068ed4c58a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718704051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.718704051
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1015110408
Short name T414
Test name
Test status
Simulation time 1262251325 ps
CPU time 5.49 seconds
Started Aug 19 04:34:07 PM PDT 24
Finished Aug 19 04:34:12 PM PDT 24
Peak memory 200780 kb
Host smart-55fe2f43-d563-40a7-b853-89c98ab688ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015110408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1015110408
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.996127216
Short name T495
Test name
Test status
Simulation time 299907843 ps
CPU time 1.89 seconds
Started Aug 19 04:34:00 PM PDT 24
Finished Aug 19 04:34:02 PM PDT 24
Peak memory 208708 kb
Host smart-7eeea2f3-acdc-497c-83fe-e5d5df4618dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996127216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.996127216
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.1546367461
Short name T490
Test name
Test status
Simulation time 273910870 ps
CPU time 1.41 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:50 PM PDT 24
Peak memory 200608 kb
Host smart-335f53b2-3067-4e23-a429-b4044c5f0c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546367461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1546367461
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3957894728
Short name T180
Test name
Test status
Simulation time 70321101 ps
CPU time 0.79 seconds
Started Aug 19 04:34:01 PM PDT 24
Finished Aug 19 04:34:02 PM PDT 24
Peak memory 200340 kb
Host smart-c9306b0b-fc88-4fd1-bbaa-5607dc274dbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957894728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3957894728
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.2331920510
Short name T515
Test name
Test status
Simulation time 1900915496 ps
CPU time 7.13 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 217884 kb
Host smart-c11abc9b-9a96-46a6-82c0-0dcbb2bdc523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331920510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2331920510
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3932828522
Short name T361
Test name
Test status
Simulation time 243908693 ps
CPU time 1.01 seconds
Started Aug 19 04:34:15 PM PDT 24
Finished Aug 19 04:34:16 PM PDT 24
Peak memory 217744 kb
Host smart-7d19cb36-2943-45aa-afa0-374df7660251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932828522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3932828522
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.2128503628
Short name T344
Test name
Test status
Simulation time 113397625 ps
CPU time 0.8 seconds
Started Aug 19 04:34:07 PM PDT 24
Finished Aug 19 04:34:08 PM PDT 24
Peak memory 200424 kb
Host smart-14ccc386-96d3-4a63-bc01-acae67039a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128503628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2128503628
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.1807896706
Short name T11
Test name
Test status
Simulation time 722704824 ps
CPU time 3.92 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200792 kb
Host smart-9c885a33-2597-4eb8-9cf5-391b69358800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807896706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1807896706
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.4221766306
Short name T352
Test name
Test status
Simulation time 175361254 ps
CPU time 1.21 seconds
Started Aug 19 04:34:13 PM PDT 24
Finished Aug 19 04:34:15 PM PDT 24
Peak memory 200644 kb
Host smart-836202e8-d675-4abf-a763-7190e7102cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221766306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.4221766306
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.1404434286
Short name T354
Test name
Test status
Simulation time 254123741 ps
CPU time 1.46 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:23 PM PDT 24
Peak memory 200736 kb
Host smart-5bcda0e9-1330-4814-b23d-38f635c42dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404434286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1404434286
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1158876397
Short name T213
Test name
Test status
Simulation time 7795793396 ps
CPU time 34.32 seconds
Started Aug 19 04:34:05 PM PDT 24
Finished Aug 19 04:34:39 PM PDT 24
Peak memory 209936 kb
Host smart-6467ca2b-5c58-42b3-8843-6efe9daa693d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158876397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1158876397
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.2905347078
Short name T303
Test name
Test status
Simulation time 440696461 ps
CPU time 2.49 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 200452 kb
Host smart-9bc5bd47-c8e2-4ad4-9a80-bd6c388b5a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905347078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2905347078
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.4149395881
Short name T132
Test name
Test status
Simulation time 133861076 ps
CPU time 1.04 seconds
Started Aug 19 04:34:14 PM PDT 24
Finished Aug 19 04:34:15 PM PDT 24
Peak memory 200536 kb
Host smart-63b01d3a-7a65-4a26-9d4a-02599f2d2589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149395881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.4149395881
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.965293686
Short name T202
Test name
Test status
Simulation time 70813143 ps
CPU time 0.79 seconds
Started Aug 19 04:34:18 PM PDT 24
Finished Aug 19 04:34:19 PM PDT 24
Peak memory 200472 kb
Host smart-f7b9dda5-a0ee-42ab-b1c4-e87266e8e3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965293686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.965293686
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.3534689851
Short name T390
Test name
Test status
Simulation time 1219917727 ps
CPU time 5.5 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 217708 kb
Host smart-ea4311b5-9a65-43d0-9246-ff6fdae4c0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534689851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3534689851
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.765735248
Short name T158
Test name
Test status
Simulation time 246156249 ps
CPU time 1.06 seconds
Started Aug 19 04:34:12 PM PDT 24
Finished Aug 19 04:34:13 PM PDT 24
Peak memory 217708 kb
Host smart-38b612e7-de91-4df5-9d07-6ea11c4b1b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765735248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.765735248
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.1660381549
Short name T23
Test name
Test status
Simulation time 168241066 ps
CPU time 0.82 seconds
Started Aug 19 04:34:20 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 200372 kb
Host smart-f77268e0-411e-4679-aaa6-5da38be959a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660381549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1660381549
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.1158781837
Short name T61
Test name
Test status
Simulation time 1819790036 ps
CPU time 7.38 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:06 PM PDT 24
Peak memory 200740 kb
Host smart-1542aa0e-0f22-420f-95d8-9713313e7090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158781837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1158781837
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.861125875
Short name T276
Test name
Test status
Simulation time 108954735 ps
CPU time 0.98 seconds
Started Aug 19 04:34:10 PM PDT 24
Finished Aug 19 04:34:11 PM PDT 24
Peak memory 200552 kb
Host smart-0438029c-c24d-428f-9618-fd06cc082a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861125875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.861125875
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.2974557118
Short name T232
Test name
Test status
Simulation time 123732524 ps
CPU time 1.15 seconds
Started Aug 19 04:34:18 PM PDT 24
Finished Aug 19 04:34:19 PM PDT 24
Peak memory 200676 kb
Host smart-ed8603f0-7080-4931-a26c-290370336c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974557118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2974557118
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.1352543355
Short name T319
Test name
Test status
Simulation time 828499464 ps
CPU time 4.45 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 200796 kb
Host smart-1d1b556c-32fb-44d3-bea7-822e60391847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352543355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1352543355
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2613639258
Short name T281
Test name
Test status
Simulation time 116945958 ps
CPU time 1.31 seconds
Started Aug 19 04:34:15 PM PDT 24
Finished Aug 19 04:34:17 PM PDT 24
Peak memory 200488 kb
Host smart-69631c78-f026-4cb5-815d-68a55db67584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613639258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2613639258
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.3745476103
Short name T161
Test name
Test status
Simulation time 65486786 ps
CPU time 0.75 seconds
Started Aug 19 04:34:03 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 200596 kb
Host smart-19739e30-3aaa-43b9-b9e8-8d9185cb60b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745476103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3745476103
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.3971490175
Short name T424
Test name
Test status
Simulation time 88858921 ps
CPU time 0.83 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200472 kb
Host smart-f565dd28-a8fc-4ea0-88a5-269c02345be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971490175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.3971490175
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.3640504361
Short name T39
Test name
Test status
Simulation time 1225839257 ps
CPU time 5.41 seconds
Started Aug 19 04:34:18 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 217888 kb
Host smart-592ec615-99f7-41a1-a4b7-9997cb2f36c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640504361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3640504361
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1840236861
Short name T527
Test name
Test status
Simulation time 244410706 ps
CPU time 1.04 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 217708 kb
Host smart-bbbb3439-e81e-404a-a56f-f8906b69c3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840236861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1840236861
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.686962388
Short name T188
Test name
Test status
Simulation time 200956312 ps
CPU time 0.83 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200428 kb
Host smart-bbca8673-091b-458a-971b-3a745012b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686962388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.686962388
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.578485574
Short name T367
Test name
Test status
Simulation time 1698079993 ps
CPU time 6.62 seconds
Started Aug 19 04:34:13 PM PDT 24
Finished Aug 19 04:34:20 PM PDT 24
Peak memory 200756 kb
Host smart-5aaa8ae9-b58d-4f2a-aa9e-39eab6e47739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578485574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.578485574
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1143301361
Short name T360
Test name
Test status
Simulation time 165278900 ps
CPU time 1.14 seconds
Started Aug 19 04:34:19 PM PDT 24
Finished Aug 19 04:34:20 PM PDT 24
Peak memory 200572 kb
Host smart-24f44e68-4b74-4436-ba25-f9f312458ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143301361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1143301361
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.2824445465
Short name T263
Test name
Test status
Simulation time 124820493 ps
CPU time 1.16 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200708 kb
Host smart-f3b44893-b0c8-40fd-b168-93ee16f98c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824445465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2824445465
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.2532776605
Short name T282
Test name
Test status
Simulation time 84368670 ps
CPU time 0.92 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200404 kb
Host smart-907db0ed-b607-4bfb-8a3f-d76493aa50e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532776605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2532776605
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.736452528
Short name T479
Test name
Test status
Simulation time 151287858 ps
CPU time 1.83 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200532 kb
Host smart-65fdf031-0bbc-49f4-b390-19b69db5233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736452528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.736452528
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.4021986383
Short name T449
Test name
Test status
Simulation time 99367726 ps
CPU time 0.94 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200512 kb
Host smart-75e0c248-3ce7-42d5-aaba-8b5573819408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021986383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4021986383
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.1326009035
Short name T223
Test name
Test status
Simulation time 59230140 ps
CPU time 0.71 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:22 PM PDT 24
Peak memory 200484 kb
Host smart-800115d4-ff88-496c-8dc4-8fa2742a848e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326009035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1326009035
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.44984676
Short name T351
Test name
Test status
Simulation time 1890417307 ps
CPU time 7.04 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 217980 kb
Host smart-b9531cb7-61d4-4e2f-a60b-3e9751aec403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44984676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.44984676
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3557538267
Short name T253
Test name
Test status
Simulation time 244530136 ps
CPU time 1.08 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 217772 kb
Host smart-5b7eb49a-8895-4233-af6c-e02ad2cf815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557538267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3557538267
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.2829417622
Short name T431
Test name
Test status
Simulation time 211992177 ps
CPU time 0.93 seconds
Started Aug 19 04:34:16 PM PDT 24
Finished Aug 19 04:34:17 PM PDT 24
Peak memory 200456 kb
Host smart-061f32bd-1589-4863-aa4f-330cdc3ca1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829417622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2829417622
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.3711476892
Short name T320
Test name
Test status
Simulation time 1643785209 ps
CPU time 6.01 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:38 PM PDT 24
Peak memory 200756 kb
Host smart-9a4664cc-865e-47b3-86bf-5f809d4d04d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711476892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3711476892
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.2079127890
Short name T181
Test name
Test status
Simulation time 250831215 ps
CPU time 1.44 seconds
Started Aug 19 04:34:11 PM PDT 24
Finished Aug 19 04:34:12 PM PDT 24
Peak memory 200724 kb
Host smart-245b8a08-55d1-4761-b3df-fa2deb79f2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079127890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2079127890
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.3548773706
Short name T119
Test name
Test status
Simulation time 2157546895 ps
CPU time 7.51 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200696 kb
Host smart-6738028f-d4c3-4a42-be4d-32df3de44ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548773706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3548773706
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.3314046407
Short name T46
Test name
Test status
Simulation time 365415820 ps
CPU time 2.34 seconds
Started Aug 19 04:34:22 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200564 kb
Host smart-f494c9ee-d611-43af-ad5f-6642a760bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314046407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.3314046407
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.4151767353
Short name T227
Test name
Test status
Simulation time 265692600 ps
CPU time 1.38 seconds
Started Aug 19 04:34:17 PM PDT 24
Finished Aug 19 04:34:18 PM PDT 24
Peak memory 200616 kb
Host smart-8571dea6-5e75-453e-9ff2-111cb2f4c440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151767353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4151767353
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.512773956
Short name T203
Test name
Test status
Simulation time 63865962 ps
CPU time 0.73 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 200420 kb
Host smart-9ed03a96-dcef-4b2b-9ffc-058d72723c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512773956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.512773956
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.441830843
Short name T456
Test name
Test status
Simulation time 1909995632 ps
CPU time 7.78 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 217972 kb
Host smart-e39873f6-ea3a-4104-ba7b-b14f225bfd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441830843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.441830843
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1831464053
Short name T299
Test name
Test status
Simulation time 243621393 ps
CPU time 1.1 seconds
Started Aug 19 04:34:18 PM PDT 24
Finished Aug 19 04:34:19 PM PDT 24
Peak memory 217732 kb
Host smart-e9487bbf-572c-4663-a686-c42d00be934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831464053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1831464053
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.3130273766
Short name T297
Test name
Test status
Simulation time 149279995 ps
CPU time 0.84 seconds
Started Aug 19 04:34:09 PM PDT 24
Finished Aug 19 04:34:10 PM PDT 24
Peak memory 200300 kb
Host smart-6f8a62db-b923-4816-8542-118c06fa5648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130273766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3130273766
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.2922638073
Short name T476
Test name
Test status
Simulation time 1669382670 ps
CPU time 6.74 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 200840 kb
Host smart-13d2ad10-204e-4936-acaf-589f31f8e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922638073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2922638073
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2204041896
Short name T140
Test name
Test status
Simulation time 144206019 ps
CPU time 1.09 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200660 kb
Host smart-fbd0d862-2788-4c48-ab95-460ae50b316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204041896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2204041896
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.3675978339
Short name T291
Test name
Test status
Simulation time 116358315 ps
CPU time 1.19 seconds
Started Aug 19 04:34:20 PM PDT 24
Finished Aug 19 04:34:21 PM PDT 24
Peak memory 200752 kb
Host smart-5641ef7e-c026-4cfc-b354-6e4fd4a9c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675978339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3675978339
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.74209759
Short name T514
Test name
Test status
Simulation time 3193973172 ps
CPU time 14.97 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:38 PM PDT 24
Peak memory 210040 kb
Host smart-512cc062-5b26-4af6-9b90-5593df184459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74209759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.74209759
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3075898205
Short name T329
Test name
Test status
Simulation time 300368325 ps
CPU time 2.05 seconds
Started Aug 19 04:34:22 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200492 kb
Host smart-90dd2afc-1fad-4ef2-99ae-88b55a09126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075898205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3075898205
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.2093706484
Short name T130
Test name
Test status
Simulation time 170039173 ps
CPU time 1.35 seconds
Started Aug 19 04:34:18 PM PDT 24
Finished Aug 19 04:34:20 PM PDT 24
Peak memory 200684 kb
Host smart-96fcde6c-d24f-4c78-b900-9a7fba56ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093706484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2093706484
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.1130017193
Short name T318
Test name
Test status
Simulation time 117786906 ps
CPU time 0.85 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200528 kb
Host smart-ce28e6c2-9ea7-494e-82d3-f98cfcec21cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130017193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1130017193
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3966077192
Short name T66
Test name
Test status
Simulation time 2354586395 ps
CPU time 8.32 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 221920 kb
Host smart-26007f7f-6005-4b4c-a444-ba46015a66ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966077192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3966077192
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.777737558
Short name T392
Test name
Test status
Simulation time 244660590 ps
CPU time 1.17 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 217736 kb
Host smart-f59e80a9-8e59-470e-b6be-6f02f481aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777737558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.777737558
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.829366754
Short name T272
Test name
Test status
Simulation time 223745190 ps
CPU time 0.97 seconds
Started Aug 19 04:34:13 PM PDT 24
Finished Aug 19 04:34:14 PM PDT 24
Peak memory 200424 kb
Host smart-704f2963-88b9-48dc-9920-5c77f24be78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829366754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.829366754
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.1291631985
Short name T462
Test name
Test status
Simulation time 1304085487 ps
CPU time 5.31 seconds
Started Aug 19 04:34:32 PM PDT 24
Finished Aug 19 04:34:38 PM PDT 24
Peak memory 200800 kb
Host smart-642dee04-6eeb-430a-aa8f-2f0898dd5f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291631985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1291631985
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3130759106
Short name T146
Test name
Test status
Simulation time 108772735 ps
CPU time 1.03 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200516 kb
Host smart-72084446-16d8-4247-ae99-7d0878eacf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130759106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3130759106
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.4162211520
Short name T503
Test name
Test status
Simulation time 245917658 ps
CPU time 1.6 seconds
Started Aug 19 04:34:13 PM PDT 24
Finished Aug 19 04:34:14 PM PDT 24
Peak memory 200728 kb
Host smart-4d9d4022-614f-4ae7-8965-d01ac13a6d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162211520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4162211520
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.656367696
Short name T210
Test name
Test status
Simulation time 730195926 ps
CPU time 2.69 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200736 kb
Host smart-a50d1d2e-3eac-4d02-9f98-246a5acb8054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656367696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.656367696
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.47038882
Short name T248
Test name
Test status
Simulation time 116784591 ps
CPU time 1.59 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 200540 kb
Host smart-1c0eb1a8-9a72-480a-abac-0093657afd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47038882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.47038882
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.3495949484
Short name T170
Test name
Test status
Simulation time 189247210 ps
CPU time 1.12 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200588 kb
Host smart-fd6eb1d0-2e2a-4cab-b605-0a0207378594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495949484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3495949484
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.3791433966
Short name T382
Test name
Test status
Simulation time 58363372 ps
CPU time 0.75 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200456 kb
Host smart-12623d17-9cae-4498-9f27-1db087e5efbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791433966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3791433966
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.4291401772
Short name T530
Test name
Test status
Simulation time 244282244 ps
CPU time 1.09 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 217720 kb
Host smart-56804ae5-a099-4b7a-9f57-c8765bbd230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291401772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.4291401772
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.1962334230
Short name T185
Test name
Test status
Simulation time 205605843 ps
CPU time 0.91 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200388 kb
Host smart-877965e2-4127-4ceb-847d-5a9c9411c9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962334230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1962334230
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.2542431919
Short name T488
Test name
Test status
Simulation time 1540885901 ps
CPU time 5.5 seconds
Started Aug 19 04:34:10 PM PDT 24
Finished Aug 19 04:34:15 PM PDT 24
Peak memory 200792 kb
Host smart-6617c210-67e4-4852-ba06-d30885c4a374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542431919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2542431919
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2054668570
Short name T294
Test name
Test status
Simulation time 159666656 ps
CPU time 1.05 seconds
Started Aug 19 04:34:22 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200488 kb
Host smart-63a159c9-3fa6-4a22-826e-58a2d3196df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054668570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2054668570
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.3844021549
Short name T400
Test name
Test status
Simulation time 241115523 ps
CPU time 1.47 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200724 kb
Host smart-89f48bcb-0c4c-4168-9a19-bc2a1340fd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844021549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3844021549
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.562299551
Short name T289
Test name
Test status
Simulation time 12647499728 ps
CPU time 43.6 seconds
Started Aug 19 04:34:13 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 200840 kb
Host smart-63a58971-6e1a-43d9-8037-53db9594d68e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562299551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.562299551
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.580132219
Short name T337
Test name
Test status
Simulation time 410043521 ps
CPU time 2.21 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 200484 kb
Host smart-9c397ab9-8d32-409c-8680-7b5fcb1e98b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580132219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.580132219
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2810387853
Short name T396
Test name
Test status
Simulation time 101788526 ps
CPU time 0.86 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 200640 kb
Host smart-a5cf91e5-b5ed-4c5b-81b3-53a524f06d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810387853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2810387853
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2184645392
Short name T475
Test name
Test status
Simulation time 64706451 ps
CPU time 0.74 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200472 kb
Host smart-5d3edbe4-d95a-4655-8731-9949e62bf4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184645392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2184645392
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.4015151732
Short name T273
Test name
Test status
Simulation time 2365377785 ps
CPU time 8.53 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 218040 kb
Host smart-1c787180-05df-4417-8a38-dfdcaef8ac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015151732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.4015151732
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.847857260
Short name T387
Test name
Test status
Simulation time 244247142 ps
CPU time 1.11 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 217852 kb
Host smart-0105b5b5-2aa6-4482-ba6c-e601afce5e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847857260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.847857260
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.3334138084
Short name T491
Test name
Test status
Simulation time 199661521 ps
CPU time 0.89 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200444 kb
Host smart-50d4bc0e-f099-4d3c-8dc8-761bd83b5b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334138084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3334138084
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.295347467
Short name T270
Test name
Test status
Simulation time 1371800414 ps
CPU time 5.5 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:34:44 PM PDT 24
Peak memory 200748 kb
Host smart-b420ffa0-c475-4eaf-84c3-25f0ab21e310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295347467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.295347467
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3314619173
Short name T264
Test name
Test status
Simulation time 99790810 ps
CPU time 0.99 seconds
Started Aug 19 04:34:15 PM PDT 24
Finished Aug 19 04:34:16 PM PDT 24
Peak memory 200588 kb
Host smart-cec4c351-78aa-4e9b-9bbc-ff18ed4c619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314619173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3314619173
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.3664444910
Short name T196
Test name
Test status
Simulation time 121440991 ps
CPU time 1.23 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200752 kb
Host smart-0b9f3fe7-e9ba-448b-b122-d32c3747770d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664444910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3664444910
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.730459944
Short name T92
Test name
Test status
Simulation time 1240337827 ps
CPU time 5.79 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 200820 kb
Host smart-072bc9af-1bd1-447b-a0c4-3f01eeda71be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730459944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.730459944
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.1988080185
Short name T342
Test name
Test status
Simulation time 473373679 ps
CPU time 2.66 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200528 kb
Host smart-3f3e1540-6e1e-44ee-84ca-0b143474f89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988080185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1988080185
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4115797052
Short name T134
Test name
Test status
Simulation time 69374349 ps
CPU time 0.76 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200624 kb
Host smart-420a5091-2f27-4019-af80-556d939a05dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115797052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4115797052
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.4069959857
Short name T378
Test name
Test status
Simulation time 63830442 ps
CPU time 0.75 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:39 PM PDT 24
Peak memory 200388 kb
Host smart-15459dbe-21c4-4e59-af3f-a69bb9314797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069959857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.4069959857
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.1729360963
Short name T405
Test name
Test status
Simulation time 1869260090 ps
CPU time 7.44 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 221868 kb
Host smart-96d770f6-f7ea-47b8-96ef-88515aa27a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729360963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1729360963
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2388697221
Short name T251
Test name
Test status
Simulation time 243534308 ps
CPU time 1.12 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 217752 kb
Host smart-a5385d52-c474-4780-a0a1-38c3c67eaa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388697221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2388697221
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.2921699328
Short name T19
Test name
Test status
Simulation time 78363721 ps
CPU time 0.77 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200328 kb
Host smart-f21f5053-7e73-4034-8555-4e6a9d2bb870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921699328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.2921699328
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.486940160
Short name T57
Test name
Test status
Simulation time 735541572 ps
CPU time 3.45 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200652 kb
Host smart-57b13639-3c84-4567-8b3a-3b7fd44f694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486940160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.486940160
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1518665544
Short name T312
Test name
Test status
Simulation time 150029612 ps
CPU time 1.09 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200588 kb
Host smart-b2abe783-e5ee-4b6d-9c02-fb21556ab373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518665544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1518665544
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.906430571
Short name T267
Test name
Test status
Simulation time 201983768 ps
CPU time 1.39 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:35 PM PDT 24
Peak memory 200604 kb
Host smart-da68cb88-1979-4b5d-b590-569c3838fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906430571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.906430571
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.2908168462
Short name T235
Test name
Test status
Simulation time 1053532649 ps
CPU time 5.8 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 200760 kb
Host smart-fe6cf3ac-757a-41cb-bf00-09c44e2365a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908168462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2908168462
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.2927659487
Short name T430
Test name
Test status
Simulation time 380201668 ps
CPU time 2.32 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200488 kb
Host smart-9173a1f6-072e-406d-938e-c11df1252ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927659487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.2927659487
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.3304067032
Short name T477
Test name
Test status
Simulation time 175659601 ps
CPU time 1.23 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200608 kb
Host smart-10a0cb91-28fd-44e1-8ec7-410c2e4569f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304067032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3304067032
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.1621244629
Short name T391
Test name
Test status
Simulation time 74151155 ps
CPU time 0.74 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200460 kb
Host smart-18e86bb5-81e3-4b6e-aed2-38e504484130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621244629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1621244629
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.407608363
Short name T49
Test name
Test status
Simulation time 2169466443 ps
CPU time 7.45 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:38 PM PDT 24
Peak memory 217776 kb
Host smart-aac2ad46-d529-4a92-887e-0d830106e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407608363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.407608363
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3093111910
Short name T418
Test name
Test status
Simulation time 244699924 ps
CPU time 1.03 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 217780 kb
Host smart-5fee0ac6-e1d3-47ff-97e4-68573076ac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093111910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3093111910
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.1444145023
Short name T451
Test name
Test status
Simulation time 167615788 ps
CPU time 0.93 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 200424 kb
Host smart-cf8b2e44-2e79-4bf5-943c-e1b3b411dcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444145023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1444145023
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3000303716
Short name T314
Test name
Test status
Simulation time 1928506371 ps
CPU time 6.45 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200816 kb
Host smart-d0fc48aa-f81a-4522-939b-96813e773bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000303716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3000303716
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.875333393
Short name T58
Test name
Test status
Simulation time 146282937 ps
CPU time 1.07 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 200628 kb
Host smart-40adce99-6434-49bc-b969-2059f5c4a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875333393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.875333393
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.988926403
Short name T452
Test name
Test status
Simulation time 229320698 ps
CPU time 1.38 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 200732 kb
Host smart-bc437927-5fca-4f76-9392-89d1679dd126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988926403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.988926403
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.2264479521
Short name T204
Test name
Test status
Simulation time 305410484 ps
CPU time 2.06 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 200536 kb
Host smart-868adeed-77f7-4ad1-8f26-f49b657e4d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264479521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2264479521
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.1649333759
Short name T157
Test name
Test status
Simulation time 192745586 ps
CPU time 1.37 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200640 kb
Host smart-efc62da9-c4f5-49e4-8588-366c0e098625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649333759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1649333759
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.3790388679
Short name T331
Test name
Test status
Simulation time 65411161 ps
CPU time 0.77 seconds
Started Aug 19 04:33:42 PM PDT 24
Finished Aug 19 04:33:43 PM PDT 24
Peak memory 200496 kb
Host smart-34b3c4af-fb78-4d88-8d99-c67f444df936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790388679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3790388679
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.96127071
Short name T53
Test name
Test status
Simulation time 1901466441 ps
CPU time 7.54 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:53 PM PDT 24
Peak memory 216984 kb
Host smart-558baf5d-17a0-4a54-9526-959d74644256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96127071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.96127071
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3573530682
Short name T137
Test name
Test status
Simulation time 243650633 ps
CPU time 1.06 seconds
Started Aug 19 04:33:39 PM PDT 24
Finished Aug 19 04:33:40 PM PDT 24
Peak memory 216384 kb
Host smart-c2c5c9aa-717e-4e70-92ee-c653ed31d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573530682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3573530682
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.542114634
Short name T353
Test name
Test status
Simulation time 98616179 ps
CPU time 0.81 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200424 kb
Host smart-a7c68aca-6af3-4cab-b3a3-083f11d84c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542114634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.542114634
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.4180737429
Short name T465
Test name
Test status
Simulation time 1009296472 ps
CPU time 4.6 seconds
Started Aug 19 04:33:55 PM PDT 24
Finished Aug 19 04:34:00 PM PDT 24
Peak memory 200768 kb
Host smart-e086141d-8705-4a24-893d-41d864bd323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180737429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4180737429
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.1317637153
Short name T77
Test name
Test status
Simulation time 16674336013 ps
CPU time 24.87 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 217752 kb
Host smart-414da1e9-8cc1-4179-b1a6-21a6ac2ef0e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317637153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.1317637153
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1654860330
Short name T160
Test name
Test status
Simulation time 181662297 ps
CPU time 1.19 seconds
Started Aug 19 04:33:57 PM PDT 24
Finished Aug 19 04:33:58 PM PDT 24
Peak memory 200608 kb
Host smart-de9536b9-88b9-472a-946d-8cf83b5ce1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654860330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1654860330
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.825400355
Short name T229
Test name
Test status
Simulation time 249774279 ps
CPU time 1.47 seconds
Started Aug 19 04:33:56 PM PDT 24
Finished Aug 19 04:33:57 PM PDT 24
Peak memory 200752 kb
Host smart-893ce928-066c-4f57-9215-c77abf0c0742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825400355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.825400355
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.1276232080
Short name T247
Test name
Test status
Simulation time 285027240 ps
CPU time 1.74 seconds
Started Aug 19 04:33:42 PM PDT 24
Finished Aug 19 04:33:44 PM PDT 24
Peak memory 200612 kb
Host smart-4ab4c726-7dd4-4bc5-b867-261be06f6200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276232080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.1276232080
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.3918638180
Short name T192
Test name
Test status
Simulation time 118248410 ps
CPU time 1.45 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:49 PM PDT 24
Peak memory 200416 kb
Host smart-30b59b27-5d5b-4b87-88e5-9f1d70029569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918638180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3918638180
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.3687275495
Short name T187
Test name
Test status
Simulation time 129944032 ps
CPU time 1.12 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:49 PM PDT 24
Peak memory 200516 kb
Host smart-e2df346d-bc72-4675-8f4a-9bb7d7232896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687275495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3687275495
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.2956287061
Short name T410
Test name
Test status
Simulation time 88607305 ps
CPU time 0.83 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 200368 kb
Host smart-95f4fda0-5143-4f01-aaad-63722434f4a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956287061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2956287061
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.1647912427
Short name T482
Test name
Test status
Simulation time 1879579177 ps
CPU time 6.79 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:37 PM PDT 24
Peak memory 218032 kb
Host smart-36c1d12b-51d0-4f10-b338-9a71f5717918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647912427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1647912427
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3977097683
Short name T136
Test name
Test status
Simulation time 243983843 ps
CPU time 1.18 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 217788 kb
Host smart-3628adfe-e96d-4ff7-86a9-5c2a7e2e0d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977097683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3977097683
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.4195764181
Short name T290
Test name
Test status
Simulation time 90323821 ps
CPU time 0.77 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200448 kb
Host smart-4e40cae7-920d-4be9-9950-25db8c2c0f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195764181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.4195764181
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.3057113267
Short name T325
Test name
Test status
Simulation time 1041627581 ps
CPU time 5.08 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:35 PM PDT 24
Peak memory 200728 kb
Host smart-40bf0679-eb60-4afc-8a51-18adfb35c543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057113267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3057113267
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1747249428
Short name T252
Test name
Test status
Simulation time 155231430 ps
CPU time 1.22 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200604 kb
Host smart-7e5bc932-5021-4a12-b8a6-45e0a55011bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747249428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1747249428
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.3410966251
Short name T403
Test name
Test status
Simulation time 204870097 ps
CPU time 1.41 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200432 kb
Host smart-ff463af7-cf43-431f-bc8d-deb0581fac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410966251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3410966251
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.3011874666
Short name T283
Test name
Test status
Simulation time 1308502163 ps
CPU time 6.36 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:37 PM PDT 24
Peak memory 209108 kb
Host smart-82509730-453e-4fe9-83bc-e6e98716cd2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011874666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3011874666
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.3271519900
Short name T402
Test name
Test status
Simulation time 138904593 ps
CPU time 1.87 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200488 kb
Host smart-2b772892-9a3b-4ff6-9d35-9ecb71b838c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271519900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3271519900
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2892994971
Short name T372
Test name
Test status
Simulation time 287120448 ps
CPU time 1.44 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200512 kb
Host smart-7b2bb671-f2d5-4a50-bf10-7db63a02eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892994971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2892994971
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.33707126
Short name T461
Test name
Test status
Simulation time 63240119 ps
CPU time 0.76 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 200476 kb
Host smart-5dc31707-226f-4c6b-9b0c-9f61eb14caca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33707126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.33707126
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.2639450764
Short name T43
Test name
Test status
Simulation time 1214666731 ps
CPU time 5.84 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 221912 kb
Host smart-030797dc-9ed3-47ae-b0e4-cc9a0959982c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639450764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2639450764
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2993436804
Short name T330
Test name
Test status
Simulation time 244489392 ps
CPU time 1.02 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 217800 kb
Host smart-0a00c559-3887-432d-b79a-41caabc3b02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993436804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2993436804
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.1590872095
Short name T257
Test name
Test status
Simulation time 171195346 ps
CPU time 0.83 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200304 kb
Host smart-a8cc25ac-e845-449e-8b00-4d3d1d76966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590872095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1590872095
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.925285448
Short name T125
Test name
Test status
Simulation time 1715664598 ps
CPU time 6.22 seconds
Started Aug 19 04:34:32 PM PDT 24
Finished Aug 19 04:34:38 PM PDT 24
Peak memory 200844 kb
Host smart-a2738a0b-2526-48ac-9454-a87d2371de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925285448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.925285448
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3774837545
Short name T296
Test name
Test status
Simulation time 101782352 ps
CPU time 1.15 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200600 kb
Host smart-55c41dd2-9d41-4e76-8b81-20e8d3d9fecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774837545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3774837545
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2638919008
Short name T156
Test name
Test status
Simulation time 254532291 ps
CPU time 1.42 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200756 kb
Host smart-6e48ca5c-cd15-4ca4-91f3-1d32a9ab2a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638919008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2638919008
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3236948637
Short name T453
Test name
Test status
Simulation time 8264230431 ps
CPU time 27.41 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:48 PM PDT 24
Peak memory 200888 kb
Host smart-e23deb94-805a-49ce-98e7-46acbff62548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236948637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3236948637
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.1540592449
Short name T541
Test name
Test status
Simulation time 372661811 ps
CPU time 2.3 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 200496 kb
Host smart-cff52532-a85f-4e92-bc3c-89c57f784daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540592449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1540592449
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.275182114
Short name T420
Test name
Test status
Simulation time 153649058 ps
CPU time 1.06 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200612 kb
Host smart-3ada2993-6d8f-47b8-9e88-e8b5541f515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275182114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.275182114
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.267618709
Short name T254
Test name
Test status
Simulation time 73901292 ps
CPU time 0.73 seconds
Started Aug 19 04:34:32 PM PDT 24
Finished Aug 19 04:34:33 PM PDT 24
Peak memory 200472 kb
Host smart-a88938a4-f618-4af1-92b3-27d8ad4e6e99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267618709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.267618709
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.1033330037
Short name T412
Test name
Test status
Simulation time 2358762945 ps
CPU time 8.58 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:40 PM PDT 24
Peak memory 218028 kb
Host smart-8684220e-9c78-45a1-bed4-a6bbb0c1bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033330037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1033330037
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3381295473
Short name T308
Test name
Test status
Simulation time 244235024 ps
CPU time 1.14 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 217776 kb
Host smart-29636ed1-ad10-46ad-ab8d-bf00dcd558ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381295473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3381295473
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.1344671062
Short name T348
Test name
Test status
Simulation time 106785808 ps
CPU time 0.76 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200324 kb
Host smart-bece0d81-62b2-4d49-b366-6940df2c960c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344671062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1344671062
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.1331570252
Short name T118
Test name
Test status
Simulation time 1597831114 ps
CPU time 6.6 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 200668 kb
Host smart-ff491bf6-2f06-4bb4-bcc5-85629a7daeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331570252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1331570252
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.46286638
Short name T365
Test name
Test status
Simulation time 107399885 ps
CPU time 1.09 seconds
Started Aug 19 04:34:23 PM PDT 24
Finished Aug 19 04:34:24 PM PDT 24
Peak memory 200552 kb
Host smart-aef8eba8-261e-4f81-9165-5b40ffd6216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46286638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.46286638
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2679855476
Short name T487
Test name
Test status
Simulation time 125663571 ps
CPU time 1.25 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200700 kb
Host smart-b73158c0-e6f2-4c22-a116-027dadbce70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679855476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2679855476
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2143182452
Short name T416
Test name
Test status
Simulation time 10510647197 ps
CPU time 36.09 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:35:01 PM PDT 24
Peak memory 200812 kb
Host smart-ccf05ead-060c-4d19-b6bd-5d5e0121b26f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143182452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2143182452
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.4071984228
Short name T369
Test name
Test status
Simulation time 533789453 ps
CPU time 2.87 seconds
Started Aug 19 04:34:25 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200488 kb
Host smart-614979b3-1aba-4587-a184-60814236db77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071984228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4071984228
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.744134621
Short name T2
Test name
Test status
Simulation time 86368155 ps
CPU time 0.8 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:22 PM PDT 24
Peak memory 200576 kb
Host smart-3126d0a8-d372-4673-a1a4-c516ca3ec2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744134621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.744134621
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.741405415
Short name T441
Test name
Test status
Simulation time 83831696 ps
CPU time 0.8 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200480 kb
Host smart-76355fa1-328b-4ea5-baef-0e87fe96a8c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741405415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.741405415
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3346746988
Short name T44
Test name
Test status
Simulation time 1218161273 ps
CPU time 5.63 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:37 PM PDT 24
Peak memory 217636 kb
Host smart-f8bace86-8912-4f88-b9c9-20ac7878de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346746988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3346746988
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1295329182
Short name T245
Test name
Test status
Simulation time 245151907 ps
CPU time 1.05 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 217764 kb
Host smart-6843b9e8-da32-4433-a658-c3f02df37941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295329182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1295329182
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.348200842
Short name T28
Test name
Test status
Simulation time 96870671 ps
CPU time 0.84 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200416 kb
Host smart-453c7d19-f77f-472e-95bb-f0e7bcae7778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348200842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.348200842
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.2687992701
Short name T533
Test name
Test status
Simulation time 1499495493 ps
CPU time 5.67 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 200748 kb
Host smart-7b764bb0-cb98-4ef9-b41a-4028792500e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687992701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2687992701
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1385316691
Short name T148
Test name
Test status
Simulation time 112238024 ps
CPU time 1.14 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200536 kb
Host smart-cee42a32-5a17-4491-8744-41661532720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385316691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1385316691
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.641703401
Short name T139
Test name
Test status
Simulation time 198531598 ps
CPU time 1.41 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:26 PM PDT 24
Peak memory 200736 kb
Host smart-7b70e75a-6ded-42a0-b31a-69921044e8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641703401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.641703401
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.145701868
Short name T544
Test name
Test status
Simulation time 1500423890 ps
CPU time 6.92 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:37 PM PDT 24
Peak memory 217076 kb
Host smart-b077c503-62e7-4861-9404-ab64b69fe6a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145701868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.145701868
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.382713613
Short name T408
Test name
Test status
Simulation time 451291631 ps
CPU time 2.31 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200512 kb
Host smart-f5e9df76-07bf-4b6e-9e8a-cb3346740a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382713613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.382713613
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.3076049630
Short name T379
Test name
Test status
Simulation time 189159924 ps
CPU time 1.2 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200240 kb
Host smart-c33c7bba-4190-4c0e-861c-6c4a4c7f5239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076049630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3076049630
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.267741054
Short name T277
Test name
Test status
Simulation time 102863707 ps
CPU time 0.81 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200460 kb
Host smart-30f8aace-139b-4813-bcbd-68e285c808ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267741054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.267741054
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.3513998496
Short name T328
Test name
Test status
Simulation time 1903592632 ps
CPU time 7.21 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 221948 kb
Host smart-afb65a8f-70cb-40a5-b159-feebf9da7c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513998496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.3513998496
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.144243831
Short name T307
Test name
Test status
Simulation time 245871060 ps
CPU time 1.05 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 217804 kb
Host smart-89e3027f-2b1e-4c04-806e-539e43844538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144243831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.144243831
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.411655475
Short name T356
Test name
Test status
Simulation time 211485074 ps
CPU time 1 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 200420 kb
Host smart-10211240-a60c-41ed-a49a-c9db4248c997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411655475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.411655475
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.2612484915
Short name T423
Test name
Test status
Simulation time 744162455 ps
CPU time 4.24 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:33 PM PDT 24
Peak memory 200808 kb
Host smart-9f8cd16f-dcb8-459a-a84b-ad8a551277b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612484915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2612484915
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.946305155
Short name T32
Test name
Test status
Simulation time 102190141 ps
CPU time 0.97 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200616 kb
Host smart-15c391c4-e38c-43e4-b964-e21ad4227b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946305155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.946305155
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.3823526196
Short name T175
Test name
Test status
Simulation time 121986476 ps
CPU time 1.24 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200744 kb
Host smart-9f2e7122-6629-440a-bf6b-48cf628d552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823526196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3823526196
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.1369626543
Short name T335
Test name
Test status
Simulation time 169452485 ps
CPU time 1.14 seconds
Started Aug 19 04:34:21 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 200608 kb
Host smart-32c7dec5-f014-43b7-8658-3d6c1b6c8d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369626543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1369626543
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.19962893
Short name T520
Test name
Test status
Simulation time 396321615 ps
CPU time 2.47 seconds
Started Aug 19 04:34:33 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 200548 kb
Host smart-24316082-60e0-456f-9dfc-d916c83733ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19962893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.19962893
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.3713481008
Short name T292
Test name
Test status
Simulation time 161647201 ps
CPU time 1.23 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200656 kb
Host smart-b503f746-af31-4b38-8823-2e5ea91a8d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713481008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.3713481008
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.4053395936
Short name T182
Test name
Test status
Simulation time 57289091 ps
CPU time 0.71 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 199964 kb
Host smart-2809d429-f2c6-421a-97ab-0047e7527c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053395936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.4053395936
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.3348522892
Short name T305
Test name
Test status
Simulation time 2154973339 ps
CPU time 7.66 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 221964 kb
Host smart-6eabc865-2f23-4ca7-8de7-42a493a9ee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348522892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3348522892
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1918195714
Short name T498
Test name
Test status
Simulation time 243452633 ps
CPU time 1.19 seconds
Started Aug 19 04:35:18 PM PDT 24
Finished Aug 19 04:35:20 PM PDT 24
Peak memory 217796 kb
Host smart-00c79b5a-cc20-41bb-ae4e-d5c3c9afb29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918195714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1918195714
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.191341810
Short name T432
Test name
Test status
Simulation time 94609986 ps
CPU time 0.76 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200324 kb
Host smart-9922f84c-ab94-4521-a591-e71914312d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191341810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.191341810
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2567354186
Short name T241
Test name
Test status
Simulation time 1289957665 ps
CPU time 4.8 seconds
Started Aug 19 04:34:33 PM PDT 24
Finished Aug 19 04:34:37 PM PDT 24
Peak memory 200660 kb
Host smart-b4dcf856-8253-4f2b-bc47-d9fa2a7f9bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567354186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2567354186
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.984411322
Short name T138
Test name
Test status
Simulation time 176784361 ps
CPU time 1.15 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:33 PM PDT 24
Peak memory 199996 kb
Host smart-b1e27248-b31a-49ee-97f0-15a1897d483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984411322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.984411322
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.4221624989
Short name T287
Test name
Test status
Simulation time 120232999 ps
CPU time 1.18 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:33 PM PDT 24
Peak memory 200456 kb
Host smart-ce6e65cc-3d1e-471c-b1b6-04b4efce8673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221624989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4221624989
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.2819297979
Short name T534
Test name
Test status
Simulation time 8131061874 ps
CPU time 25.36 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:51 PM PDT 24
Peak memory 208936 kb
Host smart-4c70432c-32a7-4102-9ccd-c3d950426051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819297979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2819297979
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.3477943607
Short name T121
Test name
Test status
Simulation time 455618023 ps
CPU time 2.34 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200496 kb
Host smart-35bed8cc-fdf6-4f2d-ae53-2973eaf35f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477943607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3477943607
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2615805890
Short name T395
Test name
Test status
Simulation time 213232915 ps
CPU time 1.33 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 200616 kb
Host smart-36e093e2-f434-4edb-abee-87f0c8252760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615805890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2615805890
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.1303568319
Short name T190
Test name
Test status
Simulation time 71567992 ps
CPU time 0.75 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 200356 kb
Host smart-101a4940-631d-4827-9d21-b9978affdd02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303568319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.1303568319
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.2746267794
Short name T50
Test name
Test status
Simulation time 1905369947 ps
CPU time 6.76 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:35 PM PDT 24
Peak memory 217916 kb
Host smart-2ce5b901-22aa-48b2-b5df-bb31b9132a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746267794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2746267794
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2173541210
Short name T261
Test name
Test status
Simulation time 244817543 ps
CPU time 1.16 seconds
Started Aug 19 04:34:32 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 217736 kb
Host smart-98917bfa-c77a-459c-847e-4f552925942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173541210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2173541210
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.3048114253
Short name T262
Test name
Test status
Simulation time 241152867 ps
CPU time 0.89 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200424 kb
Host smart-f1067c50-cada-4568-9f37-bb396d922c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048114253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3048114253
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.1940437881
Short name T334
Test name
Test status
Simulation time 1573128668 ps
CPU time 5.81 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 200668 kb
Host smart-9e10c3ab-3329-4f42-b5d2-70fb9f9a9dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940437881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1940437881
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.4187587485
Short name T507
Test name
Test status
Simulation time 105357322 ps
CPU time 0.97 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200616 kb
Host smart-b6a48947-b42e-4e31-bb09-0ca560647a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187587485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.4187587485
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.390210921
Short name T539
Test name
Test status
Simulation time 242832034 ps
CPU time 1.53 seconds
Started Aug 19 04:34:37 PM PDT 24
Finished Aug 19 04:34:39 PM PDT 24
Peak memory 200708 kb
Host smart-02bfd3a2-888f-46ce-8a6a-3b192c827c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390210921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.390210921
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.375244469
Short name T186
Test name
Test status
Simulation time 4477975068 ps
CPU time 16.19 seconds
Started Aug 19 04:34:33 PM PDT 24
Finished Aug 19 04:34:50 PM PDT 24
Peak memory 200780 kb
Host smart-bcce32be-362c-4f0f-86a4-9af6375a07ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375244469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.375244469
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.137077135
Short name T163
Test name
Test status
Simulation time 126623207 ps
CPU time 1.57 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:33 PM PDT 24
Peak memory 200340 kb
Host smart-c9b00935-f13a-48d5-99ca-35ab430ce69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137077135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.137077135
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.2595529217
Short name T427
Test name
Test status
Simulation time 90615153 ps
CPU time 0.88 seconds
Started Aug 19 04:34:26 PM PDT 24
Finished Aug 19 04:34:27 PM PDT 24
Peak memory 200588 kb
Host smart-8976a931-6185-4c8c-8fe1-8412bd64e9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595529217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2595529217
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.2664101407
Short name T234
Test name
Test status
Simulation time 78496054 ps
CPU time 0.85 seconds
Started Aug 19 04:34:40 PM PDT 24
Finished Aug 19 04:34:46 PM PDT 24
Peak memory 200504 kb
Host smart-bf1a5d39-2e46-4fc1-9281-e01b51000237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664101407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2664101407
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.3386178595
Short name T65
Test name
Test status
Simulation time 1890540965 ps
CPU time 6.75 seconds
Started Aug 19 04:34:36 PM PDT 24
Finished Aug 19 04:34:42 PM PDT 24
Peak memory 217572 kb
Host smart-51db3b12-a1d2-41ab-affa-d2745aef9805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386178595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3386178595
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1943041776
Short name T149
Test name
Test status
Simulation time 244742859 ps
CPU time 1.13 seconds
Started Aug 19 04:34:27 PM PDT 24
Finished Aug 19 04:34:28 PM PDT 24
Peak memory 217772 kb
Host smart-fc5266e6-8ff1-47a9-af95-78ae22e4cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943041776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1943041776
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.2374673131
Short name T189
Test name
Test status
Simulation time 86689250 ps
CPU time 0.78 seconds
Started Aug 19 04:34:24 PM PDT 24
Finished Aug 19 04:34:25 PM PDT 24
Peak memory 200420 kb
Host smart-6795a4d7-d405-48e2-a47b-ac31fa6650a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374673131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2374673131
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2929838746
Short name T521
Test name
Test status
Simulation time 1726336742 ps
CPU time 6.44 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 200784 kb
Host smart-6d3631f0-4d5b-49c5-af48-6d0bc0a9b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929838746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2929838746
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3746227842
Short name T154
Test name
Test status
Simulation time 150242534 ps
CPU time 1.1 seconds
Started Aug 19 04:34:51 PM PDT 24
Finished Aug 19 04:34:52 PM PDT 24
Peak memory 200592 kb
Host smart-d9295059-b6c6-4538-937e-88bcf242ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746227842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3746227842
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.3405297490
Short name T220
Test name
Test status
Simulation time 228692898 ps
CPU time 1.4 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200708 kb
Host smart-a3801a37-adbe-40ec-ba11-659a61562384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405297490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3405297490
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.2462442606
Short name T120
Test name
Test status
Simulation time 10811274656 ps
CPU time 32.67 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 200716 kb
Host smart-8f370ff7-1d28-42a5-ac28-fec552090116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462442606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2462442606
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3781350616
Short name T3
Test name
Test status
Simulation time 131742551 ps
CPU time 1.64 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 200508 kb
Host smart-1028632a-e122-48fc-acda-2d7e3f1dfa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781350616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3781350616
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.460942390
Short name T237
Test name
Test status
Simulation time 171121634 ps
CPU time 1.1 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:34:49 PM PDT 24
Peak memory 200644 kb
Host smart-c44f7952-646e-4e18-8cae-63abf3a6b08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460942390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.460942390
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3771050077
Short name T304
Test name
Test status
Simulation time 71191767 ps
CPU time 0.76 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 200492 kb
Host smart-229322f3-5955-45f9-abdc-fba13a8737ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771050077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3771050077
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3075562299
Short name T350
Test name
Test status
Simulation time 244250498 ps
CPU time 1.1 seconds
Started Aug 19 04:34:42 PM PDT 24
Finished Aug 19 04:34:43 PM PDT 24
Peak memory 217776 kb
Host smart-da4cd081-0127-49d8-a225-d689a2a0d534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075562299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3075562299
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2570888129
Short name T279
Test name
Test status
Simulation time 243528970 ps
CPU time 0.97 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 200416 kb
Host smart-66ddcae0-9263-43f7-ae6a-f024130d638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570888129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2570888129
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.2426023072
Short name T317
Test name
Test status
Simulation time 848944480 ps
CPU time 4.43 seconds
Started Aug 19 04:34:33 PM PDT 24
Finished Aug 19 04:34:38 PM PDT 24
Peak memory 200776 kb
Host smart-bf90e4fa-6513-4293-82f5-3b80dedcef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426023072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2426023072
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.538988338
Short name T384
Test name
Test status
Simulation time 154914576 ps
CPU time 1.1 seconds
Started Aug 19 04:34:31 PM PDT 24
Finished Aug 19 04:34:33 PM PDT 24
Peak memory 200640 kb
Host smart-b41db1c9-4c3e-4580-8d8b-e7602e625d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538988338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.538988338
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.1327857364
Short name T133
Test name
Test status
Simulation time 115165178 ps
CPU time 1.15 seconds
Started Aug 19 04:34:54 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 200668 kb
Host smart-9bb2749b-e9dc-47be-99f4-8e499527b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327857364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1327857364
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3276664784
Short name T93
Test name
Test status
Simulation time 6760093424 ps
CPU time 27.63 seconds
Started Aug 19 04:34:49 PM PDT 24
Finished Aug 19 04:35:17 PM PDT 24
Peak memory 200844 kb
Host smart-0703a5a2-895c-4d11-9ab3-599578dc1fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276664784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3276664784
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.4146037098
Short name T512
Test name
Test status
Simulation time 131207839 ps
CPU time 1.63 seconds
Started Aug 19 04:34:38 PM PDT 24
Finished Aug 19 04:34:40 PM PDT 24
Peak memory 208708 kb
Host smart-2ab3c7f5-b60c-4d8e-b110-1fdccaf955a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146037098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4146037098
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.4118795825
Short name T393
Test name
Test status
Simulation time 101277632 ps
CPU time 0.89 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200672 kb
Host smart-e8ddbb1c-d397-4003-8dee-2d0e26272b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118795825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.4118795825
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1216193255
Short name T499
Test name
Test status
Simulation time 67113208 ps
CPU time 0.8 seconds
Started Aug 19 04:35:06 PM PDT 24
Finished Aug 19 04:35:07 PM PDT 24
Peak memory 200464 kb
Host smart-2353179e-c535-412d-bd63-b80d1bc340d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216193255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1216193255
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.1705799474
Short name T67
Test name
Test status
Simulation time 2347881265 ps
CPU time 7.81 seconds
Started Aug 19 04:34:34 PM PDT 24
Finished Aug 19 04:34:42 PM PDT 24
Peak memory 218072 kb
Host smart-69fa6a38-1cd0-4eee-a612-1a147b5436b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705799474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1705799474
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2949435003
Short name T508
Test name
Test status
Simulation time 244116661 ps
CPU time 1.06 seconds
Started Aug 19 04:34:36 PM PDT 24
Finished Aug 19 04:34:37 PM PDT 24
Peak memory 217632 kb
Host smart-3b2ee545-d590-4863-8ffa-7c6c62fe622b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949435003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2949435003
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1229289047
Short name T470
Test name
Test status
Simulation time 194564100 ps
CPU time 0.96 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:34:39 PM PDT 24
Peak memory 200392 kb
Host smart-3d8dce5a-d17a-4f42-b601-ab904d114b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229289047 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1229289047
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.1055314710
Short name T117
Test name
Test status
Simulation time 1978376895 ps
CPU time 7.71 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:34:43 PM PDT 24
Peak memory 200788 kb
Host smart-7bfde704-bd17-494c-bae5-9cc4949f874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055314710 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1055314710
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1336861895
Short name T288
Test name
Test status
Simulation time 148411468 ps
CPU time 1.07 seconds
Started Aug 19 04:34:34 PM PDT 24
Finished Aug 19 04:34:35 PM PDT 24
Peak memory 200612 kb
Host smart-647f9861-f554-4b9f-9981-bdb6f437d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336861895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1336861895
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.1376598413
Short name T301
Test name
Test status
Simulation time 223290513 ps
CPU time 1.38 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 200728 kb
Host smart-226fa8a0-cd42-47ac-8756-db32d31a6dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376598413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.1376598413
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.3879192828
Short name T445
Test name
Test status
Simulation time 1088125658 ps
CPU time 5.04 seconds
Started Aug 19 04:34:34 PM PDT 24
Finished Aug 19 04:34:39 PM PDT 24
Peak memory 200764 kb
Host smart-eaec9276-8992-4672-8dd5-9cef9518370f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879192828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3879192828
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.3789355872
Short name T513
Test name
Test status
Simulation time 435331647 ps
CPU time 2.3 seconds
Started Aug 19 04:34:33 PM PDT 24
Finished Aug 19 04:34:35 PM PDT 24
Peak memory 208732 kb
Host smart-b7b8302e-12ad-416f-8041-2c309e41372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789355872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3789355872
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2696329891
Short name T422
Test name
Test status
Simulation time 132157805 ps
CPU time 0.96 seconds
Started Aug 19 04:34:33 PM PDT 24
Finished Aug 19 04:34:34 PM PDT 24
Peak memory 200632 kb
Host smart-39fa60a6-6cbb-44df-b2c1-943e8b55f505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696329891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2696329891
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.1756573268
Short name T164
Test name
Test status
Simulation time 61938117 ps
CPU time 0.72 seconds
Started Aug 19 04:33:50 PM PDT 24
Finished Aug 19 04:33:51 PM PDT 24
Peak memory 200492 kb
Host smart-f1848393-c407-43d8-90c6-47ec36daac19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756573268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1756573268
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2610488889
Short name T12
Test name
Test status
Simulation time 1222544743 ps
CPU time 5.71 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:06 PM PDT 24
Peak memory 217652 kb
Host smart-064b80cf-04de-4edd-9bc3-c3c6f7cdcc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610488889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2610488889
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3686191271
Short name T255
Test name
Test status
Simulation time 244663828 ps
CPU time 1.03 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:49 PM PDT 24
Peak memory 217792 kb
Host smart-a22bcc76-182f-4ce1-97ef-8b8cd3b9a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686191271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3686191271
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.1110222178
Short name T426
Test name
Test status
Simulation time 109650888 ps
CPU time 0.78 seconds
Started Aug 19 04:33:42 PM PDT 24
Finished Aug 19 04:33:43 PM PDT 24
Peak memory 200424 kb
Host smart-7733999e-faab-49be-9071-99be038903e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110222178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1110222178
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.310023658
Short name T169
Test name
Test status
Simulation time 1555843611 ps
CPU time 5.81 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:08 PM PDT 24
Peak memory 200772 kb
Host smart-ca857d84-992c-45ee-b45b-71bca6d17b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310023658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.310023658
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.4079491081
Short name T80
Test name
Test status
Simulation time 16742419450 ps
CPU time 24.73 seconds
Started Aug 19 04:33:42 PM PDT 24
Finished Aug 19 04:34:06 PM PDT 24
Peak memory 218340 kb
Host smart-1a29eb95-0db5-4af5-a995-a5f8cdcbb010
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079491081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.4079491081
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.941981293
Short name T466
Test name
Test status
Simulation time 102817779 ps
CPU time 0.99 seconds
Started Aug 19 04:33:49 PM PDT 24
Finished Aug 19 04:33:50 PM PDT 24
Peak memory 200640 kb
Host smart-f42e135d-7849-4f2c-8e17-4646cf809436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941981293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.941981293
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3797527167
Short name T35
Test name
Test status
Simulation time 2585169612 ps
CPU time 8.49 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:52 PM PDT 24
Peak memory 209028 kb
Host smart-c749177e-b279-4d8e-ba32-e0f1b913a552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797527167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3797527167
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.198224599
Short name T333
Test name
Test status
Simulation time 365407704 ps
CPU time 1.96 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:50 PM PDT 24
Peak memory 200532 kb
Host smart-50d65deb-7114-4a9d-81a5-a2683bce327f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198224599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.198224599
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.1886026982
Short name T62
Test name
Test status
Simulation time 234662819 ps
CPU time 1.38 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:47 PM PDT 24
Peak memory 200740 kb
Host smart-bd0d9d1e-f27e-4977-af28-ae258e010397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886026982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1886026982
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.2418446249
Short name T298
Test name
Test status
Simulation time 84481267 ps
CPU time 0.81 seconds
Started Aug 19 04:34:37 PM PDT 24
Finished Aug 19 04:34:38 PM PDT 24
Peak memory 200492 kb
Host smart-814818a3-1001-4dc5-abf4-5f67f33ce374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418446249 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2418446249
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.4263848357
Short name T467
Test name
Test status
Simulation time 2350462818 ps
CPU time 8.52 seconds
Started Aug 19 04:34:34 PM PDT 24
Finished Aug 19 04:34:43 PM PDT 24
Peak memory 221968 kb
Host smart-90c7aa94-3ac7-466e-b5ea-e487aaa8a608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263848357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.4263848357
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.553216707
Short name T228
Test name
Test status
Simulation time 245251024 ps
CPU time 1.07 seconds
Started Aug 19 04:34:36 PM PDT 24
Finished Aug 19 04:34:37 PM PDT 24
Peak memory 217732 kb
Host smart-04e93587-280e-42a2-8fe2-b37b4f6c53f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553216707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.553216707
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.611247356
Short name T275
Test name
Test status
Simulation time 237413291 ps
CPU time 0.97 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 200416 kb
Host smart-41a02892-580b-4bf4-b490-4f53eb091004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611247356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.611247356
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.3378357320
Short name T457
Test name
Test status
Simulation time 731666375 ps
CPU time 3.89 seconds
Started Aug 19 04:34:40 PM PDT 24
Finished Aug 19 04:34:44 PM PDT 24
Peak memory 200792 kb
Host smart-c34903ed-f91c-4c4c-a496-96f830362e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378357320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3378357320
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2374005485
Short name T497
Test name
Test status
Simulation time 145457794 ps
CPU time 1.21 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 200492 kb
Host smart-e4df3554-c28d-4d8e-9d1e-511d476ce618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374005485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2374005485
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.3079928946
Short name T183
Test name
Test status
Simulation time 207201265 ps
CPU time 1.42 seconds
Started Aug 19 04:34:51 PM PDT 24
Finished Aug 19 04:34:53 PM PDT 24
Peak memory 200748 kb
Host smart-c2725710-ca38-4b0f-85e8-7669d935c535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079928946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3079928946
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.3826662630
Short name T171
Test name
Test status
Simulation time 5500783160 ps
CPU time 20.83 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 209048 kb
Host smart-d413038f-3dea-4e26-b046-c2ac8910a8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826662630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3826662630
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.421230009
Short name T198
Test name
Test status
Simulation time 425209913 ps
CPU time 2.44 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 208740 kb
Host smart-42275f3e-def7-4d8b-b19f-06f950c19bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421230009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.421230009
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.915928227
Short name T374
Test name
Test status
Simulation time 72822753 ps
CPU time 0.78 seconds
Started Aug 19 04:34:36 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 200488 kb
Host smart-9e572dd3-b42e-4023-aa89-3307ea7a077d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915928227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.915928227
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1629258368
Short name T421
Test name
Test status
Simulation time 59355878 ps
CPU time 0.7 seconds
Started Aug 19 04:34:58 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 200436 kb
Host smart-87a880ed-a6d6-4bf0-9dc6-123055ca561f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629258368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1629258368
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.236666201
Short name T54
Test name
Test status
Simulation time 1893257232 ps
CPU time 6.62 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:35:04 PM PDT 24
Peak memory 216948 kb
Host smart-0a67b196-b5ff-47b9-9bed-d99c2f2e93ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236666201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.236666201
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1295616394
Short name T174
Test name
Test status
Simulation time 244117153 ps
CPU time 1.04 seconds
Started Aug 19 04:34:44 PM PDT 24
Finished Aug 19 04:34:45 PM PDT 24
Peak memory 217616 kb
Host smart-3b5271de-3d3a-4a8d-a81f-1bdd474f5cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295616394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1295616394
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.1182352708
Short name T376
Test name
Test status
Simulation time 159781813 ps
CPU time 0.85 seconds
Started Aug 19 04:34:45 PM PDT 24
Finished Aug 19 04:34:46 PM PDT 24
Peak memory 200460 kb
Host smart-4f1b31bb-e52a-4c39-b240-c041ddec31a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182352708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1182352708
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.3755027496
Short name T537
Test name
Test status
Simulation time 1827628919 ps
CPU time 7.63 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 200820 kb
Host smart-b7fa541b-2542-4ee5-be72-b90be61e20f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755027496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3755027496
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3821063786
Short name T162
Test name
Test status
Simulation time 150821928 ps
CPU time 1.06 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:34:50 PM PDT 24
Peak memory 200616 kb
Host smart-8181dc52-a9b0-490f-8b98-92e1678c9cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821063786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3821063786
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.4252728232
Short name T332
Test name
Test status
Simulation time 232701678 ps
CPU time 1.54 seconds
Started Aug 19 04:34:30 PM PDT 24
Finished Aug 19 04:34:32 PM PDT 24
Peak memory 200732 kb
Host smart-46c98483-fb8c-417f-9460-d0f8ad454d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252728232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4252728232
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1444099449
Short name T373
Test name
Test status
Simulation time 7600342603 ps
CPU time 27.6 seconds
Started Aug 19 04:34:32 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 209028 kb
Host smart-d674b2f4-5fa3-4bf8-8a1d-3e61e662e23e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444099449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1444099449
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.368940312
Short name T5
Test name
Test status
Simulation time 392869466 ps
CPU time 2.34 seconds
Started Aug 19 04:34:36 PM PDT 24
Finished Aug 19 04:34:39 PM PDT 24
Peak memory 200508 kb
Host smart-94211911-e0de-438e-bd3b-665e10945d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368940312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.368940312
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.1564065442
Short name T502
Test name
Test status
Simulation time 236121315 ps
CPU time 1.4 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 200868 kb
Host smart-0fa02977-754a-4ca6-80cc-2c58aaa72c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564065442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1564065442
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.474516591
Short name T313
Test name
Test status
Simulation time 75249459 ps
CPU time 0.73 seconds
Started Aug 19 04:34:58 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 200480 kb
Host smart-5d339329-8d8f-41eb-94f1-359d54a5131c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474516591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.474516591
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.692198582
Short name T51
Test name
Test status
Simulation time 1226047848 ps
CPU time 6.23 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:35 PM PDT 24
Peak memory 221872 kb
Host smart-f5711f24-b1ae-4817-95cc-d85d005df248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692198582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.692198582
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3759664334
Short name T143
Test name
Test status
Simulation time 248291697 ps
CPU time 1.03 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:30 PM PDT 24
Peak memory 217764 kb
Host smart-426e5903-7220-4a88-995f-a21604f47f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759664334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3759664334
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3575533754
Short name T486
Test name
Test status
Simulation time 145695553 ps
CPU time 0.81 seconds
Started Aug 19 04:34:36 PM PDT 24
Finished Aug 19 04:34:39 PM PDT 24
Peak memory 200392 kb
Host smart-1c06a7a1-0a00-4799-a3c4-0488290930a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575533754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3575533754
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.3677227293
Short name T221
Test name
Test status
Simulation time 1707470936 ps
CPU time 6.01 seconds
Started Aug 19 04:34:29 PM PDT 24
Finished Aug 19 04:34:35 PM PDT 24
Peak memory 200828 kb
Host smart-23f45d5f-3196-4949-b412-4e2b40b435fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677227293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3677227293
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2728372042
Short name T144
Test name
Test status
Simulation time 148038351 ps
CPU time 1.19 seconds
Started Aug 19 04:34:51 PM PDT 24
Finished Aug 19 04:34:53 PM PDT 24
Peak memory 200612 kb
Host smart-0c1919ba-3e29-4a79-ba54-7f9c2cf51164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728372042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2728372042
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.1607145622
Short name T522
Test name
Test status
Simulation time 192076058 ps
CPU time 1.32 seconds
Started Aug 19 04:34:35 PM PDT 24
Finished Aug 19 04:34:36 PM PDT 24
Peak memory 200716 kb
Host smart-3cb9e09f-5409-47ba-8a5f-f73ace6ee8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607145622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.1607145622
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.3469858804
Short name T346
Test name
Test status
Simulation time 1797924265 ps
CPU time 6.57 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:06 PM PDT 24
Peak memory 200772 kb
Host smart-0f49cf8c-4914-47e1-8f45-9706c16d0d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469858804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3469858804
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1256907163
Short name T34
Test name
Test status
Simulation time 337523915 ps
CPU time 2.34 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:31 PM PDT 24
Peak memory 200536 kb
Host smart-0980fc6e-67d8-48e0-b423-8265b38ac9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256907163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1256907163
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3116100954
Short name T59
Test name
Test status
Simulation time 130083214 ps
CPU time 1.13 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 200580 kb
Host smart-769bc536-55e6-4bc1-bf61-4ec35e49de84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116100954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3116100954
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2470810240
Short name T370
Test name
Test status
Simulation time 2171718166 ps
CPU time 7.37 seconds
Started Aug 19 04:34:36 PM PDT 24
Finished Aug 19 04:34:44 PM PDT 24
Peak memory 217916 kb
Host smart-b3aa7d25-e5b3-43a6-8fb6-7fba2f131faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470810240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2470810240
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2277214646
Short name T147
Test name
Test status
Simulation time 243660702 ps
CPU time 1.11 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:34:50 PM PDT 24
Peak memory 217720 kb
Host smart-af469625-8866-46a1-abc1-e3d3ac7d0e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277214646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2277214646
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.2535543490
Short name T504
Test name
Test status
Simulation time 220693048 ps
CPU time 0.93 seconds
Started Aug 19 04:34:58 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 200388 kb
Host smart-d5ab604e-560a-45c8-aa1f-181837a2b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535543490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2535543490
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.205250116
Short name T436
Test name
Test status
Simulation time 1007332370 ps
CPU time 5.1 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 200568 kb
Host smart-3e73e3ae-165a-4d15-91b8-f981bd520eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205250116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.205250116
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.930292858
Short name T323
Test name
Test status
Simulation time 111039464 ps
CPU time 0.97 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 200584 kb
Host smart-d5fca6d6-b630-49b9-a494-bb45a80c841d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930292858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.930292858
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.712814863
Short name T269
Test name
Test status
Simulation time 119080182 ps
CPU time 1.13 seconds
Started Aug 19 04:34:52 PM PDT 24
Finished Aug 19 04:34:53 PM PDT 24
Peak memory 200668 kb
Host smart-e5ff45de-8d82-4e51-b57c-2b62e164b82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712814863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.712814863
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.3312835232
Short name T168
Test name
Test status
Simulation time 118284814 ps
CPU time 1.52 seconds
Started Aug 19 04:34:52 PM PDT 24
Finished Aug 19 04:34:54 PM PDT 24
Peak memory 200476 kb
Host smart-46bdf9a9-1270-4abc-9a97-b66f96ea856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312835232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3312835232
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3117787397
Short name T355
Test name
Test status
Simulation time 280872623 ps
CPU time 1.44 seconds
Started Aug 19 04:35:02 PM PDT 24
Finished Aug 19 04:35:03 PM PDT 24
Peak memory 200580 kb
Host smart-58f65c04-2ab4-46b3-9ee5-ad1874e60b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117787397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3117787397
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.269906427
Short name T172
Test name
Test status
Simulation time 65204229 ps
CPU time 0.69 seconds
Started Aug 19 04:34:58 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 200480 kb
Host smart-ffb6cd9d-51c9-42d2-abff-dd8629e11552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269906427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.269906427
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.2161713106
Short name T199
Test name
Test status
Simulation time 2368130833 ps
CPU time 7.77 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:35:05 PM PDT 24
Peak memory 221864 kb
Host smart-dfc23305-4f35-4274-aa97-9f802d1d4467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161713106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2161713106
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1334709069
Short name T316
Test name
Test status
Simulation time 244657847 ps
CPU time 1.11 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:34:50 PM PDT 24
Peak memory 217784 kb
Host smart-666278b0-6066-4eb9-a968-d854b7909aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334709069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1334709069
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.200686801
Short name T20
Test name
Test status
Simulation time 110369756 ps
CPU time 0.76 seconds
Started Aug 19 04:34:50 PM PDT 24
Finished Aug 19 04:34:51 PM PDT 24
Peak memory 200420 kb
Host smart-a94396e3-7b61-46da-b5fd-a46d2775c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200686801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.200686801
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_reset.3428443352
Short name T444
Test name
Test status
Simulation time 1732380533 ps
CPU time 6.56 seconds
Started Aug 19 04:34:41 PM PDT 24
Finished Aug 19 04:34:47 PM PDT 24
Peak memory 200776 kb
Host smart-c4bfc2ae-72dd-4c24-8903-1f208e50af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428443352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3428443352
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1920771177
Short name T295
Test name
Test status
Simulation time 197660168 ps
CPU time 1.17 seconds
Started Aug 19 04:34:50 PM PDT 24
Finished Aug 19 04:34:52 PM PDT 24
Peak memory 200612 kb
Host smart-a0487cfb-c883-4dad-a3f9-70f8c439abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920771177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1920771177
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.128467731
Short name T238
Test name
Test status
Simulation time 199272408 ps
CPU time 1.31 seconds
Started Aug 19 04:34:28 PM PDT 24
Finished Aug 19 04:34:29 PM PDT 24
Peak memory 200732 kb
Host smart-adcb4fff-8602-4e0a-9fb1-00c81e43c09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128467731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.128467731
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.1848133837
Short name T509
Test name
Test status
Simulation time 1120625344 ps
CPU time 4.32 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 200724 kb
Host smart-52b20da4-ef36-4c39-9908-8171d88a212a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848133837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1848133837
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.4280847170
Short name T306
Test name
Test status
Simulation time 270316620 ps
CPU time 1.86 seconds
Started Aug 19 04:34:54 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 200492 kb
Host smart-56439576-62e2-4f2f-af71-9c1eb4de3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280847170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.4280847170
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.484712996
Short name T259
Test name
Test status
Simulation time 89981601 ps
CPU time 0.88 seconds
Started Aug 19 04:35:14 PM PDT 24
Finished Aug 19 04:35:15 PM PDT 24
Peak memory 200608 kb
Host smart-2efa12af-af53-4657-95dd-cfe475d89f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484712996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.484712996
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.4268862444
Short name T145
Test name
Test status
Simulation time 74691243 ps
CPU time 0.79 seconds
Started Aug 19 04:35:02 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 200496 kb
Host smart-7dc0f169-4dd4-4a8d-8e3d-6f46a206f73f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268862444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4268862444
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.934079733
Short name T37
Test name
Test status
Simulation time 2185386108 ps
CPU time 7.89 seconds
Started Aug 19 04:34:50 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 218004 kb
Host smart-21d73fb3-27f5-4709-8e30-e7068d29f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934079733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.934079733
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3506517197
Short name T532
Test name
Test status
Simulation time 244741449 ps
CPU time 1.15 seconds
Started Aug 19 04:35:18 PM PDT 24
Finished Aug 19 04:35:19 PM PDT 24
Peak memory 217792 kb
Host smart-378599ac-a98a-4acc-9c93-fa709a44bf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506517197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3506517197
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.3911543116
Short name T21
Test name
Test status
Simulation time 239739142 ps
CPU time 1.06 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 200420 kb
Host smart-bbafceb9-6f5e-43b1-afac-c42a88724a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911543116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3911543116
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1286107397
Short name T13
Test name
Test status
Simulation time 1865626150 ps
CPU time 6.31 seconds
Started Aug 19 04:34:44 PM PDT 24
Finished Aug 19 04:34:50 PM PDT 24
Peak memory 200768 kb
Host smart-25b6640c-e2b2-4010-a232-9f98c2e19fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286107397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1286107397
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.1418880015
Short name T244
Test name
Test status
Simulation time 97826302 ps
CPU time 0.98 seconds
Started Aug 19 04:34:45 PM PDT 24
Finished Aug 19 04:34:46 PM PDT 24
Peak memory 200584 kb
Host smart-e7dc5341-271c-4a26-b530-f988fa37ee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418880015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.1418880015
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.3844568209
Short name T60
Test name
Test status
Simulation time 107404963 ps
CPU time 1.1 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:34:49 PM PDT 24
Peak memory 200756 kb
Host smart-4f77ec20-bdc9-43d4-bcf8-e9ffd88f2c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844568209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3844568209
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.106762547
Short name T33
Test name
Test status
Simulation time 3808264355 ps
CPU time 16.09 seconds
Started Aug 19 04:34:52 PM PDT 24
Finished Aug 19 04:35:08 PM PDT 24
Peak memory 200828 kb
Host smart-393c93b1-1a9a-46ab-9270-ef1706195756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106762547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.106762547
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.3958600824
Short name T10
Test name
Test status
Simulation time 257273256 ps
CPU time 1.61 seconds
Started Aug 19 04:34:46 PM PDT 24
Finished Aug 19 04:34:48 PM PDT 24
Peak memory 200508 kb
Host smart-1057a571-615d-40d3-8bc2-28e8068263e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958600824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3958600824
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.3138572583
Short name T173
Test name
Test status
Simulation time 284402631 ps
CPU time 1.57 seconds
Started Aug 19 04:34:38 PM PDT 24
Finished Aug 19 04:34:45 PM PDT 24
Peak memory 200628 kb
Host smart-5ba62a37-b575-425d-9ac7-f9c44d303f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138572583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.3138572583
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.3805578275
Short name T197
Test name
Test status
Simulation time 83039238 ps
CPU time 0.76 seconds
Started Aug 19 04:34:38 PM PDT 24
Finished Aug 19 04:34:44 PM PDT 24
Peak memory 200492 kb
Host smart-a1fcf2a1-17b6-412d-8daa-ff49615c9343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805578275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3805578275
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1827710450
Short name T404
Test name
Test status
Simulation time 2360548074 ps
CPU time 8.31 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:35:05 PM PDT 24
Peak memory 218084 kb
Host smart-480c21d3-dbc2-487a-8791-70f92a5fc3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827710450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1827710450
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2651529839
Short name T249
Test name
Test status
Simulation time 244568402 ps
CPU time 1.06 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:58 PM PDT 24
Peak memory 217728 kb
Host smart-7a7c0e1e-79aa-4b9e-ace2-b4a79c35e22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651529839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2651529839
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4148031763
Short name T205
Test name
Test status
Simulation time 90325615 ps
CPU time 0.8 seconds
Started Aug 19 04:34:49 PM PDT 24
Finished Aug 19 04:34:50 PM PDT 24
Peak memory 200420 kb
Host smart-a5b1ebfa-497a-4e76-91e5-38bb829951d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148031763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4148031763
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.1756049951
Short name T448
Test name
Test status
Simulation time 1289326464 ps
CPU time 5.22 seconds
Started Aug 19 04:35:11 PM PDT 24
Finished Aug 19 04:35:17 PM PDT 24
Peak memory 200764 kb
Host smart-68e4578f-e1d6-4f35-af96-b5541a97c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756049951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1756049951
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.540884407
Short name T339
Test name
Test status
Simulation time 97165969 ps
CPU time 0.96 seconds
Started Aug 19 04:34:53 PM PDT 24
Finished Aug 19 04:34:54 PM PDT 24
Peak memory 200616 kb
Host smart-1426bc0a-8e60-4789-ab88-10d5ed2c1a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540884407 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.540884407
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.1646305090
Short name T286
Test name
Test status
Simulation time 114160910 ps
CPU time 1.23 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:01 PM PDT 24
Peak memory 200740 kb
Host smart-ec60b269-f778-4e0d-b63f-b6aac7c19fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646305090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.1646305090
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.3930821357
Short name T371
Test name
Test status
Simulation time 13150507921 ps
CPU time 45.96 seconds
Started Aug 19 04:34:47 PM PDT 24
Finished Aug 19 04:35:33 PM PDT 24
Peak memory 209048 kb
Host smart-149ddb04-adc5-4260-98e9-6a1e47b0b627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930821357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3930821357
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.1247917668
Short name T45
Test name
Test status
Simulation time 136873279 ps
CPU time 1.79 seconds
Started Aug 19 04:35:01 PM PDT 24
Finished Aug 19 04:35:03 PM PDT 24
Peak memory 200508 kb
Host smart-4fe807cb-6acd-4682-8f8d-990fb1d0d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247917668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.1247917668
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.2233694411
Short name T434
Test name
Test status
Simulation time 132370352 ps
CPU time 1.13 seconds
Started Aug 19 04:34:47 PM PDT 24
Finished Aug 19 04:34:49 PM PDT 24
Peak memory 200576 kb
Host smart-d2325fce-f525-42fa-b733-500c7931965b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233694411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2233694411
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.3678435021
Short name T4
Test name
Test status
Simulation time 82278184 ps
CPU time 0.74 seconds
Started Aug 19 04:34:43 PM PDT 24
Finished Aug 19 04:34:44 PM PDT 24
Peak memory 200492 kb
Host smart-fe799972-77bb-4e2e-9ddc-0b3ff2abeb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678435021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3678435021
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_cnsty.1447876891
Short name T528
Test name
Test status
Simulation time 1886508908 ps
CPU time 7.43 seconds
Started Aug 19 04:34:53 PM PDT 24
Finished Aug 19 04:35:01 PM PDT 24
Peak memory 221852 kb
Host smart-81f637d0-d6c1-4d29-877c-2251f1d32b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447876891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1447876891
Directory /workspace/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.536651103
Short name T407
Test name
Test status
Simulation time 245288028 ps
CPU time 1.07 seconds
Started Aug 19 04:34:50 PM PDT 24
Finished Aug 19 04:34:51 PM PDT 24
Peak memory 217824 kb
Host smart-42aac063-6cf5-4062-9a86-bb6297c726d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536651103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.536651103
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2077249418
Short name T209
Test name
Test status
Simulation time 126698825 ps
CPU time 0.75 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:34:48 PM PDT 24
Peak memory 200424 kb
Host smart-b4d37546-aed5-45b6-b2b9-9b2e0e19f925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077249418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2077249418
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.4291691866
Short name T302
Test name
Test status
Simulation time 774947323 ps
CPU time 3.88 seconds
Started Aug 19 04:34:51 PM PDT 24
Finished Aug 19 04:34:55 PM PDT 24
Peak memory 200720 kb
Host smart-d5c56643-d271-4f2e-a719-46791c28f774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291691866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.4291691866
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3610040660
Short name T214
Test name
Test status
Simulation time 182147861 ps
CPU time 1.2 seconds
Started Aug 19 04:34:42 PM PDT 24
Finished Aug 19 04:34:43 PM PDT 24
Peak memory 200620 kb
Host smart-0e9371df-4b74-4d0b-a184-bc798b295b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610040660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3610040660
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.1644467968
Short name T413
Test name
Test status
Simulation time 122363856 ps
CPU time 1.16 seconds
Started Aug 19 04:34:49 PM PDT 24
Finished Aug 19 04:34:50 PM PDT 24
Peak memory 200708 kb
Host smart-c03f61b0-cf26-48ae-823b-d934565b21c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644467968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1644467968
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.2931031070
Short name T442
Test name
Test status
Simulation time 10885696166 ps
CPU time 40.61 seconds
Started Aug 19 04:35:11 PM PDT 24
Finished Aug 19 04:35:51 PM PDT 24
Peak memory 209060 kb
Host smart-fefca462-21d3-416d-a70e-bf8de63fb750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931031070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2931031070
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.2960557133
Short name T122
Test name
Test status
Simulation time 381368140 ps
CPU time 2.16 seconds
Started Aug 19 04:35:08 PM PDT 24
Finished Aug 19 04:35:10 PM PDT 24
Peak memory 200544 kb
Host smart-162cfbb4-be52-4fc7-a3cb-b998ed85ad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960557133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2960557133
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.2233934568
Short name T131
Test name
Test status
Simulation time 225948508 ps
CPU time 1.3 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 200616 kb
Host smart-b3fc45af-111a-4c20-826e-230a38811bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233934568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2233934568
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.3022728273
Short name T208
Test name
Test status
Simulation time 73790736 ps
CPU time 0.79 seconds
Started Aug 19 04:34:46 PM PDT 24
Finished Aug 19 04:34:47 PM PDT 24
Peak memory 200492 kb
Host smart-49f53f17-8ba6-4e91-a9f4-3a63044ef2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022728273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3022728273
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2476663615
Short name T63
Test name
Test status
Simulation time 1224210798 ps
CPU time 5.49 seconds
Started Aug 19 04:34:48 PM PDT 24
Finished Aug 19 04:34:54 PM PDT 24
Peak memory 217928 kb
Host smart-860a9dbf-733d-4096-bdfb-02dc058550ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476663615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2476663615
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3541866659
Short name T6
Test name
Test status
Simulation time 244700471 ps
CPU time 1.05 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 217800 kb
Host smart-74369a7a-939a-4678-a8b8-c1b8b6f30f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541866659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3541866659
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.474882486
Short name T256
Test name
Test status
Simulation time 143650898 ps
CPU time 0.83 seconds
Started Aug 19 04:34:44 PM PDT 24
Finished Aug 19 04:34:44 PM PDT 24
Peak memory 200452 kb
Host smart-0844c43e-ec02-44d8-ba78-ff5e0d5c8730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474882486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.474882486
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1148932714
Short name T95
Test name
Test status
Simulation time 901870509 ps
CPU time 4.27 seconds
Started Aug 19 04:34:50 PM PDT 24
Finished Aug 19 04:34:55 PM PDT 24
Peak memory 200776 kb
Host smart-d9ef40ce-3cde-4033-a8bc-86823e3def6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148932714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1148932714
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.154251673
Short name T226
Test name
Test status
Simulation time 96114942 ps
CPU time 1 seconds
Started Aug 19 04:34:51 PM PDT 24
Finished Aug 19 04:34:52 PM PDT 24
Peak memory 200588 kb
Host smart-7271fddc-5360-4933-a09e-dbaa8f9cbc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154251673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.154251673
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.3762472998
Short name T425
Test name
Test status
Simulation time 198657746 ps
CPU time 1.37 seconds
Started Aug 19 04:34:51 PM PDT 24
Finished Aug 19 04:34:52 PM PDT 24
Peak memory 200708 kb
Host smart-85a4a2f6-4507-4c3e-a4ad-b97bc1fd8f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762472998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3762472998
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.4275486825
Short name T179
Test name
Test status
Simulation time 7507250382 ps
CPU time 26.52 seconds
Started Aug 19 04:35:07 PM PDT 24
Finished Aug 19 04:35:34 PM PDT 24
Peak memory 200868 kb
Host smart-281a68b7-b2b9-45c1-9d61-93515c9e0395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275486825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.4275486825
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.3412842108
Short name T47
Test name
Test status
Simulation time 156371741 ps
CPU time 1.92 seconds
Started Aug 19 04:34:52 PM PDT 24
Finished Aug 19 04:34:54 PM PDT 24
Peak memory 200508 kb
Host smart-4373d98e-59e9-4df7-bfd8-4610bde8e73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412842108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3412842108
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.4246054358
Short name T250
Test name
Test status
Simulation time 88779867 ps
CPU time 0.85 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:00 PM PDT 24
Peak memory 200652 kb
Host smart-a9a5b2e1-8994-43fa-9f75-cce13c8907b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246054358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4246054358
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.653709605
Short name T357
Test name
Test status
Simulation time 80446596 ps
CPU time 0.86 seconds
Started Aug 19 04:35:10 PM PDT 24
Finished Aug 19 04:35:11 PM PDT 24
Peak memory 200504 kb
Host smart-bcca8ba7-d4f4-4103-99ee-a13102feaf58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653709605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.653709605
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.896780733
Short name T40
Test name
Test status
Simulation time 2389136162 ps
CPU time 8.12 seconds
Started Aug 19 04:34:56 PM PDT 24
Finished Aug 19 04:35:05 PM PDT 24
Peak memory 222016 kb
Host smart-7ed9ac0c-c159-4344-8778-14d927b3ad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896780733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.896780733
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1836959313
Short name T166
Test name
Test status
Simulation time 244943621 ps
CPU time 1.12 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:00 PM PDT 24
Peak memory 217708 kb
Host smart-f9ede415-d2a3-41a5-8c28-aa7bf0fc8d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836959313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1836959313
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.1181314169
Short name T385
Test name
Test status
Simulation time 122490101 ps
CPU time 0.78 seconds
Started Aug 19 04:34:55 PM PDT 24
Finished Aug 19 04:34:56 PM PDT 24
Peak memory 200424 kb
Host smart-bea0f24e-c312-4ba5-aaf2-b7142883eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181314169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1181314169
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.971943500
Short name T347
Test name
Test status
Simulation time 1279533473 ps
CPU time 5.86 seconds
Started Aug 19 04:34:51 PM PDT 24
Finished Aug 19 04:34:57 PM PDT 24
Peak memory 200768 kb
Host smart-498fba82-c749-4fce-9d23-5c78f6f01ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971943500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.971943500
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1450546263
Short name T236
Test name
Test status
Simulation time 162860745 ps
CPU time 1.18 seconds
Started Aug 19 04:34:49 PM PDT 24
Finished Aug 19 04:34:51 PM PDT 24
Peak memory 200596 kb
Host smart-5420e04a-a4d3-4a3f-9e16-a41eac67545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450546263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1450546263
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1296056529
Short name T463
Test name
Test status
Simulation time 200665465 ps
CPU time 1.34 seconds
Started Aug 19 04:34:59 PM PDT 24
Finished Aug 19 04:35:01 PM PDT 24
Peak memory 200784 kb
Host smart-3a790742-4d05-426b-bc82-141ea1b82df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296056529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1296056529
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.41541357
Short name T159
Test name
Test status
Simulation time 2302670064 ps
CPU time 11.82 seconds
Started Aug 19 04:34:50 PM PDT 24
Finished Aug 19 04:35:02 PM PDT 24
Peak memory 210208 kb
Host smart-a33cac24-28b1-42ed-be52-b8726cc43b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41541357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.41541357
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.3446444384
Short name T409
Test name
Test status
Simulation time 144149308 ps
CPU time 1.74 seconds
Started Aug 19 04:35:02 PM PDT 24
Finished Aug 19 04:35:04 PM PDT 24
Peak memory 208720 kb
Host smart-3b4076c9-6f37-4abe-9f43-069bdf94ea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446444384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3446444384
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.765909634
Short name T7
Test name
Test status
Simulation time 121897653 ps
CPU time 1.06 seconds
Started Aug 19 04:34:57 PM PDT 24
Finished Aug 19 04:34:59 PM PDT 24
Peak memory 200648 kb
Host smart-760fa7a6-6826-4282-a862-3327ccd98421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765909634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.765909634
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.4283769394
Short name T211
Test name
Test status
Simulation time 63281171 ps
CPU time 0.76 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200484 kb
Host smart-4600b83c-c014-4821-8beb-3f4ae3645f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283769394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4283769394
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3481258630
Short name T415
Test name
Test status
Simulation time 2350752553 ps
CPU time 8.64 seconds
Started Aug 19 04:33:39 PM PDT 24
Finished Aug 19 04:33:48 PM PDT 24
Peak memory 218084 kb
Host smart-fdb86574-0f31-4aac-b1e1-b0ade16f9deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481258630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3481258630
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2962024437
Short name T217
Test name
Test status
Simulation time 244149734 ps
CPU time 1.18 seconds
Started Aug 19 04:33:55 PM PDT 24
Finished Aug 19 04:33:56 PM PDT 24
Peak memory 217732 kb
Host smart-69f1ef34-8c21-483a-b144-dc46870e97c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962024437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2962024437
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.957616988
Short name T519
Test name
Test status
Simulation time 172073822 ps
CPU time 0.86 seconds
Started Aug 19 04:33:36 PM PDT 24
Finished Aug 19 04:33:37 PM PDT 24
Peak memory 200420 kb
Host smart-f92b73fc-8428-4e44-a661-21640449ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957616988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.957616988
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1279176808
Short name T293
Test name
Test status
Simulation time 896285503 ps
CPU time 4.87 seconds
Started Aug 19 04:33:37 PM PDT 24
Finished Aug 19 04:33:41 PM PDT 24
Peak memory 200752 kb
Host smart-a8b0db5a-41e6-4800-a747-612cc7f8af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279176808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1279176808
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2260276727
Short name T524
Test name
Test status
Simulation time 97406854 ps
CPU time 0.96 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:49 PM PDT 24
Peak memory 200636 kb
Host smart-9c94da44-de17-4d7f-879c-db3dcd229372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260276727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2260276727
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.1437323225
Short name T375
Test name
Test status
Simulation time 250904677 ps
CPU time 1.46 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:50 PM PDT 24
Peak memory 200772 kb
Host smart-42683f41-59e6-49b1-9322-70ff4c4714cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437323225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1437323225
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.3908739792
Short name T265
Test name
Test status
Simulation time 5642626055 ps
CPU time 20.86 seconds
Started Aug 19 04:33:58 PM PDT 24
Finished Aug 19 04:34:19 PM PDT 24
Peak memory 209936 kb
Host smart-c23ea12e-14b0-4053-8998-cb29420afdc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908739792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3908739792
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.637184531
Short name T406
Test name
Test status
Simulation time 272148946 ps
CPU time 1.83 seconds
Started Aug 19 04:33:57 PM PDT 24
Finished Aug 19 04:33:59 PM PDT 24
Peak memory 200484 kb
Host smart-3ed4c828-ca2d-4eb3-86a9-17115ce545e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637184531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.637184531
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.2026167008
Short name T501
Test name
Test status
Simulation time 88945625 ps
CPU time 0.87 seconds
Started Aug 19 04:33:41 PM PDT 24
Finished Aug 19 04:33:42 PM PDT 24
Peak memory 200612 kb
Host smart-06c2334c-d6be-4339-a5a2-7d9778266177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026167008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.2026167008
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.3752475180
Short name T150
Test name
Test status
Simulation time 66202213 ps
CPU time 0.75 seconds
Started Aug 19 04:33:47 PM PDT 24
Finished Aug 19 04:33:48 PM PDT 24
Peak memory 200488 kb
Host smart-3066779b-f81d-411a-ae88-b041a540fc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752475180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3752475180
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.4151970077
Short name T433
Test name
Test status
Simulation time 1898923616 ps
CPU time 7.12 seconds
Started Aug 19 04:33:59 PM PDT 24
Finished Aug 19 04:34:06 PM PDT 24
Peak memory 217904 kb
Host smart-551c69fe-ea05-49b7-8a86-65b3a0f945fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151970077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.4151970077
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.624571142
Short name T242
Test name
Test status
Simulation time 245738201 ps
CPU time 1.09 seconds
Started Aug 19 04:33:53 PM PDT 24
Finished Aug 19 04:33:54 PM PDT 24
Peak memory 217776 kb
Host smart-8f23676f-bebe-4bb1-9219-7249bcac835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624571142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.624571142
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.860258506
Short name T268
Test name
Test status
Simulation time 133189474 ps
CPU time 0.85 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:43 PM PDT 24
Peak memory 200452 kb
Host smart-36d80f6a-fbb1-4e2f-8c09-d54b438f1ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860258506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.860258506
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.3846454727
Short name T417
Test name
Test status
Simulation time 1739494115 ps
CPU time 6.12 seconds
Started Aug 19 04:33:50 PM PDT 24
Finished Aug 19 04:33:56 PM PDT 24
Peak memory 200792 kb
Host smart-f8deffc4-3cd5-4357-a294-c9785c6e2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846454727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3846454727
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.193635343
Short name T135
Test name
Test status
Simulation time 141910432 ps
CPU time 1.11 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:47 PM PDT 24
Peak memory 200616 kb
Host smart-e09fc010-0dd8-48ef-a238-4fd569eef8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193635343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.193635343
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3664193920
Short name T543
Test name
Test status
Simulation time 194947462 ps
CPU time 1.39 seconds
Started Aug 19 04:33:45 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 200752 kb
Host smart-293176db-1f42-45d9-98d6-88780e6aabcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664193920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3664193920
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.57116733
Short name T300
Test name
Test status
Simulation time 11259292493 ps
CPU time 38.46 seconds
Started Aug 19 04:33:54 PM PDT 24
Finished Aug 19 04:34:33 PM PDT 24
Peak memory 209036 kb
Host smart-7bffc85f-65de-48ee-8f3a-779dd5ed313f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57116733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.57116733
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.617684350
Short name T123
Test name
Test status
Simulation time 409875607 ps
CPU time 2.04 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:49 PM PDT 24
Peak memory 200532 kb
Host smart-a4b2b956-150b-4071-a240-68cc1243ea3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617684350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.617684350
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.3687506454
Short name T152
Test name
Test status
Simulation time 92322949 ps
CPU time 0.83 seconds
Started Aug 19 04:33:58 PM PDT 24
Finished Aug 19 04:33:59 PM PDT 24
Peak memory 200588 kb
Host smart-588e91ff-6dbe-4626-bd60-35bc189d4fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687506454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3687506454
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.4240096992
Short name T219
Test name
Test status
Simulation time 66117307 ps
CPU time 0.78 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:47 PM PDT 24
Peak memory 200452 kb
Host smart-56d242e3-bb80-4031-9bea-8b7a6ee887ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240096992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.4240096992
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.874383341
Short name T493
Test name
Test status
Simulation time 1889088731 ps
CPU time 7.22 seconds
Started Aug 19 04:33:47 PM PDT 24
Finished Aug 19 04:33:54 PM PDT 24
Peak memory 217896 kb
Host smart-63443e30-3fe4-4344-b6cb-386cc13996ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874383341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.874383341
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2287947620
Short name T194
Test name
Test status
Simulation time 243952099 ps
CPU time 1.13 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:48 PM PDT 24
Peak memory 217764 kb
Host smart-4ab4ad1a-d981-4a32-bb22-ee27b821ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287947620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2287947620
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.271660959
Short name T22
Test name
Test status
Simulation time 151443031 ps
CPU time 0.8 seconds
Started Aug 19 04:33:47 PM PDT 24
Finished Aug 19 04:33:48 PM PDT 24
Peak memory 200448 kb
Host smart-b85a38ce-a2b6-4222-bfac-a2e9ffaaca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271660959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.271660959
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.3567210219
Short name T443
Test name
Test status
Simulation time 817457421 ps
CPU time 4.14 seconds
Started Aug 19 04:34:07 PM PDT 24
Finished Aug 19 04:34:11 PM PDT 24
Peak memory 200744 kb
Host smart-22644c90-7b8b-45fd-8865-593f5445ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567210219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3567210219
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.3932532946
Short name T201
Test name
Test status
Simulation time 109952542 ps
CPU time 1.03 seconds
Started Aug 19 04:33:47 PM PDT 24
Finished Aug 19 04:33:54 PM PDT 24
Peak memory 200640 kb
Host smart-e837dab5-6a34-48f5-8407-4318cc14f795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932532946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.3932532946
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.4109459415
Short name T315
Test name
Test status
Simulation time 114359780 ps
CPU time 1.16 seconds
Started Aug 19 04:33:50 PM PDT 24
Finished Aug 19 04:33:51 PM PDT 24
Peak memory 200696 kb
Host smart-33fb646c-8585-4267-8e87-5af09cf20642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109459415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4109459415
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.846243474
Short name T359
Test name
Test status
Simulation time 2936472448 ps
CPU time 13.61 seconds
Started Aug 19 04:33:44 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200752 kb
Host smart-3f393f25-7809-4256-9061-1c78f8ae8b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846243474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.846243474
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.1433072661
Short name T215
Test name
Test status
Simulation time 114541484 ps
CPU time 1.45 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 200516 kb
Host smart-450054dd-a8b3-4e7d-9b58-f9dbffa9ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433072661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1433072661
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.4253483542
Short name T191
Test name
Test status
Simulation time 175661124 ps
CPU time 1.24 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:03 PM PDT 24
Peak memory 200708 kb
Host smart-1d240855-40c9-4d31-97d9-bc3bdf690480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253483542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.4253483542
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.423452403
Short name T78
Test name
Test status
Simulation time 71154941 ps
CPU time 0.79 seconds
Started Aug 19 04:34:01 PM PDT 24
Finished Aug 19 04:34:01 PM PDT 24
Peak memory 200456 kb
Host smart-a3d06d30-149d-42ec-9323-046505d3bdb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423452403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.423452403
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.2388853637
Short name T42
Test name
Test status
Simulation time 1216589826 ps
CPU time 5.4 seconds
Started Aug 19 04:34:04 PM PDT 24
Finished Aug 19 04:34:10 PM PDT 24
Peak memory 217992 kb
Host smart-60fc7a02-ae29-4ddc-a40e-f77762fa0f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388853637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.2388853637
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.69959124
Short name T176
Test name
Test status
Simulation time 244527821 ps
CPU time 1.1 seconds
Started Aug 19 04:33:35 PM PDT 24
Finished Aug 19 04:33:36 PM PDT 24
Peak memory 217732 kb
Host smart-3ad0f338-339b-42f4-96dc-6d935f492555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69959124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.69959124
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.743257009
Short name T480
Test name
Test status
Simulation time 130240804 ps
CPU time 0.84 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:47 PM PDT 24
Peak memory 200416 kb
Host smart-5cc27049-1c69-47d4-9d2f-ada91a58cfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743257009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.743257009
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.2024422845
Short name T94
Test name
Test status
Simulation time 1658252887 ps
CPU time 6.13 seconds
Started Aug 19 04:33:46 PM PDT 24
Finished Aug 19 04:33:53 PM PDT 24
Peak memory 200760 kb
Host smart-539aa30a-d4e1-4845-8969-55b7eb3e1f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024422845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2024422845
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1623788171
Short name T124
Test name
Test status
Simulation time 172080990 ps
CPU time 1.16 seconds
Started Aug 19 04:34:00 PM PDT 24
Finished Aug 19 04:34:01 PM PDT 24
Peak memory 200496 kb
Host smart-5317282f-b3d8-471a-98ac-09cd7d8c513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623788171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1623788171
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2600272266
Short name T324
Test name
Test status
Simulation time 201208001 ps
CPU time 1.34 seconds
Started Aug 19 04:33:51 PM PDT 24
Finished Aug 19 04:33:53 PM PDT 24
Peak memory 200640 kb
Host smart-619428d8-1e1a-48bd-818a-8074b3d22f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600272266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2600272266
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3158414290
Short name T167
Test name
Test status
Simulation time 231290875 ps
CPU time 1.43 seconds
Started Aug 19 04:33:42 PM PDT 24
Finished Aug 19 04:33:44 PM PDT 24
Peak memory 200580 kb
Host smart-5012042e-a4d4-4cdd-8104-39d25f92bab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158414290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3158414290
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.3033095607
Short name T165
Test name
Test status
Simulation time 312398861 ps
CPU time 2.08 seconds
Started Aug 19 04:33:54 PM PDT 24
Finished Aug 19 04:33:56 PM PDT 24
Peak memory 208676 kb
Host smart-6dea07b3-bf22-41b8-bb76-0c163dfe5909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033095607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3033095607
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.3468836240
Short name T184
Test name
Test status
Simulation time 82441616 ps
CPU time 0.87 seconds
Started Aug 19 04:33:48 PM PDT 24
Finished Aug 19 04:33:54 PM PDT 24
Peak memory 200596 kb
Host smart-69144ed0-42fd-4721-8e07-db28e933b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468836240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3468836240
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3301573064
Short name T155
Test name
Test status
Simulation time 90118578 ps
CPU time 0.86 seconds
Started Aug 19 04:34:05 PM PDT 24
Finished Aug 19 04:34:06 PM PDT 24
Peak memory 200488 kb
Host smart-ddd9c234-148e-427e-bca0-be83e24b0d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301573064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3301573064
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2430910325
Short name T446
Test name
Test status
Simulation time 1227925401 ps
CPU time 5.67 seconds
Started Aug 19 04:34:01 PM PDT 24
Finished Aug 19 04:34:07 PM PDT 24
Peak memory 217916 kb
Host smart-05a95f15-a2f2-496f-a936-47c3d630beb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430910325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2430910325
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2153912056
Short name T531
Test name
Test status
Simulation time 244370768 ps
CPU time 1.05 seconds
Started Aug 19 04:33:43 PM PDT 24
Finished Aug 19 04:33:44 PM PDT 24
Peak memory 218052 kb
Host smart-0317a112-ad71-4016-8a38-7bf1c5d80138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153912056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2153912056
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.3608412055
Short name T278
Test name
Test status
Simulation time 194531820 ps
CPU time 0.87 seconds
Started Aug 19 04:34:03 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 200424 kb
Host smart-7ca39a51-4a38-4974-ba66-a82bd9143002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608412055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3608412055
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.156899884
Short name T435
Test name
Test status
Simulation time 1563034697 ps
CPU time 5.79 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:07 PM PDT 24
Peak memory 200812 kb
Host smart-2d68cc31-0b49-4e1b-8897-042f6a5fbbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156899884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.156899884
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.817039150
Short name T224
Test name
Test status
Simulation time 149909384 ps
CPU time 1.28 seconds
Started Aug 19 04:33:45 PM PDT 24
Finished Aug 19 04:33:46 PM PDT 24
Peak memory 200512 kb
Host smart-810942d2-15dd-42a6-80ee-2d6993b38fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817039150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.817039150
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.2634971946
Short name T511
Test name
Test status
Simulation time 252331319 ps
CPU time 1.58 seconds
Started Aug 19 04:33:57 PM PDT 24
Finished Aug 19 04:33:58 PM PDT 24
Peak memory 200656 kb
Host smart-2d2d2e25-2e13-4355-8145-521e7c779380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634971946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2634971946
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.1069489683
Short name T516
Test name
Test status
Simulation time 8200631811 ps
CPU time 31.25 seconds
Started Aug 19 04:33:47 PM PDT 24
Finished Aug 19 04:34:19 PM PDT 24
Peak memory 200844 kb
Host smart-8d809bc5-c779-4a9f-a867-ddc4dac8c244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069489683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1069489683
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.3058701248
Short name T401
Test name
Test status
Simulation time 145291533 ps
CPU time 1.76 seconds
Started Aug 19 04:34:02 PM PDT 24
Finished Aug 19 04:34:04 PM PDT 24
Peak memory 200508 kb
Host smart-12962202-e6e1-4667-b89d-2eed8d91113d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058701248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3058701248
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.1702265230
Short name T271
Test name
Test status
Simulation time 121442364 ps
CPU time 1.05 seconds
Started Aug 19 04:34:11 PM PDT 24
Finished Aug 19 04:34:12 PM PDT 24
Peak memory 200616 kb
Host smart-8ddd1bec-d60d-42cf-a2bf-3484d29ace16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702265230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1702265230
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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