Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7958

1

T5

3

T6

5

T11

23

auto[1]

11009

1

T1

4

T3

4

T5

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5786	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6474	1			T1	2		T2	1		T3	2
reset_info_cp[2]	2927	1			T1	1		T3	1		T8	1
reset_info_cp[4]	3845	1			T1	1		T3	1		T8	1
reset_info_cp[8]	111	1			T5	1		T11	1		T93	3
reset_info_cp[16]	98	1			T6	1		T91	1		T52	1
reset_info_cp[32]	116	1			T6	1		T13	1		T43	1
reset_info_cp[64]	111	1			T1	1		T90	1		T91	1
reset_info_cp[128]	119	1			T12	1		T91	1		T43	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3081	1			T11	7		T13	13		T90	12
reset_info_cp[1]	auto[1]	2773	1			T1	1		T3	1		T8	1
reset_info_cp[2]	auto[0]	922	1			T11	2		T13	8		T90	5
reset_info_cp[2]	auto[1]	2005	1			T1	1		T3	1		T8	1
reset_info_cp[4]	auto[0]	1360	1			T11	6		T13	3		T90	5
reset_info_cp[4]	auto[1]	2485	1			T1	1		T3	1		T8	1
reset_info_cp[8]	auto[0]	42	1			T5	1		T11	1		T93	1
reset_info_cp[8]	auto[1]	69	1			T93	2		T60	3		T26	1
reset_info_cp[16]	auto[0]	38	1			T91	1		T142	1		T111	1
reset_info_cp[16]	auto[1]	60	1			T6	1		T52	1		T25	2
reset_info_cp[32]	auto[0]	43	1			T6	1		T93	1		T143	1
reset_info_cp[32]	auto[1]	73	1			T13	1		T43	1		T89	1
reset_info_cp[64]	auto[0]	43	1			T91	1		T110	2		T111	2
reset_info_cp[64]	auto[1]	68	1			T1	1		T90	1		T25	2
reset_info_cp[128]	auto[0]	40	1			T91	1		T56	1		T89	1
reset_info_cp[128]	auto[1]	79	1			T12	1		T43	1		T44	1