Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7768

1

T3

7

T9

32

T12

10

auto[1]

10908

1

T1

4

T3

1

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5833	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6295	1			T1	2		T2	1		T3	1
reset_info_cp[2]	2902	1			T1	1		T4	1		T8	1
reset_info_cp[4]	3758	1			T1	1		T4	1		T8	1
reset_info_cp[8]	99	1			T25	1		T41	1		T50	2
reset_info_cp[16]	113	1			T23	1		T25	2		T137	1
reset_info_cp[32]	103	1			T1	1		T57	1		T25	1
reset_info_cp[64]	93	1			T12	1		T22	1		T23	1
reset_info_cp[128]	100	1			T3	1		T23	1		T57	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3035	1			T9	8		T23	18		T49	13
reset_info_cp[1]	auto[1]	2640	1			T1	1		T4	1		T8	1
reset_info_cp[2]	auto[0]	892	1			T9	9		T49	2		T38	7
reset_info_cp[2]	auto[1]	2010	1			T1	1		T4	1		T8	1
reset_info_cp[4]	auto[0]	1297	1			T9	9		T49	8		T38	7
reset_info_cp[4]	auto[1]	2461	1			T1	1		T4	1		T8	1
reset_info_cp[8]	auto[0]	33	1			T97	1		T119	1		T146	1
reset_info_cp[8]	auto[1]	66	1			T25	1		T41	1		T50	2
reset_info_cp[16]	auto[0]	44	1			T137	1		T99	1		T79	1
reset_info_cp[16]	auto[1]	69	1			T23	1		T25	2		T107	1
reset_info_cp[32]	auto[0]	35	1			T57	1		T106	1		T111	1
reset_info_cp[32]	auto[1]	68	1			T1	1		T25	1		T133	1
reset_info_cp[64]	auto[0]	40	1			T12	1		T22	1		T137	1
reset_info_cp[64]	auto[1]	53	1			T23	1		T50	1		T78	2
reset_info_cp[128]	auto[0]	40	1			T3	1		T57	1		T99	1
reset_info_cp[128]	auto[1]	60	1			T23	1		T134	1		T26	1