Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.45	99.40	99.24	100.00		99.83	99.46	98.77

Total test records in report: 620

T539	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.3442397914	Sep 04 12:40:32 PM UTC 24	Sep 04 12:41:07 PM UTC 24	1688827817 ps
T540	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.2796854464	Sep 04 12:40:31 PM UTC 24	Sep 04 12:41:09 PM UTC 24	2458809561 ps
T541	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.4292852227	Sep 04 12:40:32 PM UTC 24	Sep 04 12:41:10 PM UTC 24	2432712910 ps
T542	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.159392913	Sep 04 12:40:31 PM UTC 24	Sep 04 12:41:25 PM UTC 24	5227363237 ps
T543	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.3539705019	Sep 04 12:40:40 PM UTC 24	Sep 04 12:41:28 PM UTC 24	12711475242 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.793539733	Sep 04 12:40:48 PM UTC 24	Sep 04 12:40:53 PM UTC 24	115745741 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3856440324	Sep 04 12:40:50 PM UTC 24	Sep 04 12:40:53 PM UTC 24	150324908 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4228671415	Sep 04 12:40:45 PM UTC 24	Sep 04 12:40:55 PM UTC 24	200956251 ps
T68	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.2577529712	Sep 04 12:40:40 PM UTC 24	Sep 04 12:40:56 PM UTC 24	460620737 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.936034600	Sep 04 12:40:56 PM UTC 24	Sep 04 12:40:58 PM UTC 24	76197702 ps
T63	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4071644671	Sep 04 12:40:56 PM UTC 24	Sep 04 12:40:58 PM UTC 24	103402552 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1894770316	Sep 04 12:40:43 PM UTC 24	Sep 04 12:40:58 PM UTC 24	89915782 ps
T120	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.963806458	Sep 04 12:40:43 PM UTC 24	Sep 04 12:40:58 PM UTC 24	65825971 ps
T69	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3893955738	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:10 PM UTC 24	310250820 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.812254743	Sep 04 12:40:44 PM UTC 24	Sep 04 12:40:59 PM UTC 24	122623334 ps
T121	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.689923035	Sep 04 12:40:43 PM UTC 24	Sep 04 12:40:59 PM UTC 24	136074310 ps
T86	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4129267636	Sep 04 12:40:43 PM UTC 24	Sep 04 12:41:00 PM UTC 24	358815900 ps
T88	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.691856253	Sep 04 12:40:54 PM UTC 24	Sep 04 12:41:00 PM UTC 24	260201876 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2467551738	Sep 04 12:40:58 PM UTC 24	Sep 04 12:41:00 PM UTC 24	128746649 ps
T144	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2043244705	Sep 04 12:40:57 PM UTC 24	Sep 04 12:41:01 PM UTC 24	352663315 ps
T87	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.41513721	Sep 04 12:40:45 PM UTC 24	Sep 04 12:41:01 PM UTC 24	95749149 ps
T122	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2448412967	Sep 04 12:40:45 PM UTC 24	Sep 04 12:41:01 PM UTC 24	59233884 ps
T123	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2382132210	Sep 04 12:40:58 PM UTC 24	Sep 04 12:41:01 PM UTC 24	228568300 ps
T83	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.634976819	Sep 04 12:40:54 PM UTC 24	Sep 04 12:41:01 PM UTC 24	789670660 ps
T544	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1709750496	Sep 04 12:40:56 PM UTC 24	Sep 04 12:41:01 PM UTC 24	800790085 ps
T545	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3562520579	Sep 04 12:40:59 PM UTC 24	Sep 04 12:41:02 PM UTC 24	134743276 ps
T546	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.687271366	Sep 04 12:40:59 PM UTC 24	Sep 04 12:41:02 PM UTC 24	62866780 ps
T124	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3866149756	Sep 04 12:40:49 PM UTC 24	Sep 04 12:41:02 PM UTC 24	154536795 ps
T145	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2992002397	Sep 04 12:40:59 PM UTC 24	Sep 04 12:41:02 PM UTC 24	115824997 ps
T91	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2628832477	Sep 04 12:40:59 PM UTC 24	Sep 04 12:41:02 PM UTC 24	119575807 ps
T84	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.267507706	Sep 04 12:40:59 PM UTC 24	Sep 04 12:41:03 PM UTC 24	468948685 ps
T85	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3886690587	Sep 04 12:40:45 PM UTC 24	Sep 04 12:41:03 PM UTC 24	760536020 ps
T105	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1756731577	Sep 04 12:41:01 PM UTC 24	Sep 04 12:41:03 PM UTC 24	115856681 ps
T125	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1466223087	Sep 04 12:41:01 PM UTC 24	Sep 04 12:41:03 PM UTC 24	199070636 ps
T92	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1787885287	Sep 04 12:40:42 PM UTC 24	Sep 04 12:41:04 PM UTC 24	944659023 ps
T547	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.267071053	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:04 PM UTC 24	105650372 ps
T126	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.243907195	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:04 PM UTC 24	73026320 ps
T548	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.1336498267	Sep 04 12:41:01 PM UTC 24	Sep 04 12:41:04 PM UTC 24	347366505 ps
T549	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2398855549	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:04 PM UTC 24	71651884 ps
T127	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1559478821	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:04 PM UTC 24	131317893 ps
T128	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1517211015	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:04 PM UTC 24	125689100 ps
T550	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.572494589	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:05 PM UTC 24	196034898 ps
T140	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3509812403	Sep 04 12:41:01 PM UTC 24	Sep 04 12:41:05 PM UTC 24	492659860 ps
T551	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1495094891	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:05 PM UTC 24	132613197 ps
T552	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4194921886	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:05 PM UTC 24	217366735 ps
T94	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.590300620	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:05 PM UTC 24	133445767 ps
T553	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2166121011	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:05 PM UTC 24	432498351 ps
T554	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4259532491	Sep 04 12:40:43 PM UTC 24	Sep 04 12:41:06 PM UTC 24	1568083481 ps
T555	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1287110866	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:06 PM UTC 24	266458525 ps
T556	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.309283914	Sep 04 12:40:59 PM UTC 24	Sep 04 12:41:06 PM UTC 24	478877308 ps
T557	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.3928107145	Sep 04 12:41:02 PM UTC 24	Sep 04 12:41:06 PM UTC 24	389108201 ps
T558	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.4117636946	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:07 PM UTC 24	359072097 ps
T559	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.3285306559	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:08 PM UTC 24	79191005 ps
T560	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3618748298	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:08 PM UTC 24	78609855 ps
T561	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.313505808	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:08 PM UTC 24	82035274 ps
T141	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1565652217	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:08 PM UTC 24	1011621667 ps
T562	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3213942622	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:08 PM UTC 24	196458086 ps
T563	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.346952185	Sep 04 12:41:06 PM UTC 24	Sep 04 12:41:08 PM UTC 24	66205070 ps
T564	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1531112331	Sep 04 12:41:06 PM UTC 24	Sep 04 12:41:09 PM UTC 24	126363665 ps
T565	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.4251840095	Sep 04 12:41:03 PM UTC 24	Sep 04 12:41:09 PM UTC 24	68025979 ps
T566	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.2823474030	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:09 PM UTC 24	75897939 ps
T567	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3644097325	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:09 PM UTC 24	219038878 ps
T568	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1306728107	Sep 04 12:41:06 PM UTC 24	Sep 04 12:41:09 PM UTC 24	140198452 ps
T569	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3087587766	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:09 PM UTC 24	86244802 ps
T570	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.39546270	Sep 04 12:41:03 PM UTC 24	Sep 04 12:41:09 PM UTC 24	142202027 ps
T571	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.208225463	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:09 PM UTC 24	60283554 ps
T572	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3395986144	Sep 04 12:41:06 PM UTC 24	Sep 04 12:41:09 PM UTC 24	90079647 ps
T573	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2635801504	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:09 PM UTC 24	113445840 ps
T574	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.4013747335	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:09 PM UTC 24	122955085 ps
T575	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.172605992	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:09 PM UTC 24	72486379 ps
T576	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2065272558	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:09 PM UTC 24	203488887 ps
T577	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.669158419	Sep 04 12:41:06 PM UTC 24	Sep 04 12:41:09 PM UTC 24	229166081 ps
T578	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4217643971	Sep 04 12:41:03 PM UTC 24	Sep 04 12:41:10 PM UTC 24	424028425 ps
T579	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4000047704	Sep 04 12:41:08 PM UTC 24	Sep 04 12:41:10 PM UTC 24	196527134 ps
T143	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.806758846	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:10 PM UTC 24	882922314 ps
T580	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.484287422	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:10 PM UTC 24	149831985 ps
T142	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1392332546	Sep 04 12:41:04 PM UTC 24	Sep 04 12:41:11 PM UTC 24	879874049 ps
T581	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3259077746	Sep 04 12:41:06 PM UTC 24	Sep 04 12:41:11 PM UTC 24	943995271 ps
T89	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2744613262	Sep 04 12:41:05 PM UTC 24	Sep 04 12:41:11 PM UTC 24	917117621 ps
T582	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3756891353	Sep 04 12:40:45 PM UTC 24	Sep 04 12:41:13 PM UTC 24	2308545524 ps
T583	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.164490154	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:13 PM UTC 24	72784917 ps
T584	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3250536340	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:13 PM UTC 24	87817415 ps
T585	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4061150581	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:13 PM UTC 24	126829228 ps
T586	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.1716166771	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:13 PM UTC 24	84369881 ps
T587	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2249837720	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:13 PM UTC 24	132659082 ps
T588	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3016505141	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:14 PM UTC 24	63490880 ps
T589	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3830325931	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:14 PM UTC 24	241576230 ps
T590	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3152122419	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:14 PM UTC 24	137247780 ps
T591	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1454586500	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:14 PM UTC 24	159248843 ps
T592	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3285117489	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:14 PM UTC 24	289612957 ps
T593	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2593086003	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:14 PM UTC 24	114192399 ps
T594	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1781945366	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:14 PM UTC 24	184993864 ps
T595	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2761239046	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:14 PM UTC 24	173690794 ps
T93	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3298915617	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:15 PM UTC 24	790460626 ps
T596	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4132522915	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:15 PM UTC 24	895208400 ps
T597	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1570128302	Sep 04 12:41:12 PM UTC 24	Sep 04 12:41:17 PM UTC 24	59452425 ps
T598	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2643837180	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:18 PM UTC 24	84365569 ps
T599	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2555196239	Sep 04 12:41:12 PM UTC 24	Sep 04 12:41:18 PM UTC 24	243280339 ps
T600	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3772023703	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:18 PM UTC 24	87578287 ps
T601	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4009187490	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:19 PM UTC 24	214328725 ps
T602	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4134473841	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:19 PM UTC 24	441412126 ps
T603	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.359177225	Sep 04 12:41:12 PM UTC 24	Sep 04 12:41:19 PM UTC 24	824700186 ps
T604	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.217807149	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:20 PM UTC 24	466111428 ps
T605	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.249007135	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:21 PM UTC 24	894497583 ps
T606	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1866463427	Sep 04 12:41:14 PM UTC 24	Sep 04 12:41:23 PM UTC 24	67816973 ps
T607	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.739311424	Sep 04 12:41:08 PM UTC 24	Sep 04 12:41:23 PM UTC 24	71481877 ps
T608	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2840221401	Sep 04 12:41:08 PM UTC 24	Sep 04 12:41:23 PM UTC 24	125700200 ps
T609	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1642824958	Sep 04 12:41:14 PM UTC 24	Sep 04 12:41:23 PM UTC 24	73407570 ps
T610	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3050136868	Sep 04 12:41:14 PM UTC 24	Sep 04 12:41:23 PM UTC 24	122036805 ps
T611	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1850708715	Sep 04 12:41:14 PM UTC 24	Sep 04 12:41:24 PM UTC 24	212617069 ps
T612	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2292148522	Sep 04 12:41:14 PM UTC 24	Sep 04 12:41:24 PM UTC 24	534067063 ps
T613	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.4127443660	Sep 04 12:41:12 PM UTC 24	Sep 04 12:41:28 PM UTC 24	228482378 ps
T614	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3499949185	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:29 PM UTC 24	122442455 ps
T615	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1739797134	Sep 04 12:41:08 PM UTC 24	Sep 04 12:41:31 PM UTC 24	306989658 ps
T616	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.270046719	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:32 PM UTC 24	101615716 ps
T617	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2243743680	Sep 04 12:41:11 PM UTC 24	Sep 04 12:41:32 PM UTC 24	518910530 ps
T618	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.898753652	Sep 04 12:41:12 PM UTC 24	Sep 04 12:41:32 PM UTC 24	181828024 ps
T619	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.1187909588	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:32 PM UTC 24	278958497 ps
T620	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1235060908	Sep 04 12:41:09 PM UTC 24	Sep 04 12:41:33 PM UTC 24	161151184 ps
T90	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3379510399	Sep 04 12:41:08 PM UTC 24	Sep 04 12:41:36 PM UTC 24	2694061702 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.2124171886
Short name	T8
Test name
Test status
Simulation time	247107780 ps
CPU time	1.66 seconds
Started	Sep 04 12:38:51 PM UTC 24
Finished	Sep 04 12:38:54 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124171886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2124171886
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.643459774
Short name	T5
Test name
Test status
Simulation time	452775197 ps
CPU time	3.06 seconds
Started	Sep 04 12:38:47 PM UTC 24
Finished	Sep 04 12:38:52 PM UTC 24
Peak memory	209052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643459774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.643459774
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.580414897
Short name	T47
Test name
Test status
Simulation time	96248210 ps
CPU time	1.19 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:38:58 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580414897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.580414897
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3856440324
Short name	T60
Test name
Test status
Simulation time	150324908 ps
CPU time	1.2 seconds
Started	Sep 04 12:40:50 PM UTC 24
Finished	Sep 04 12:40:53 PM UTC 24
Peak memory	221072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3856440324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.3856440324
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.1972706496
Short name	T23
Test name
Test status
Simulation time	1270078960 ps
CPU time	6.71 seconds
Started	Sep 04 12:38:50 PM UTC 24
Finished	Sep 04 12:38:58 PM UTC 24
Peak memory	242320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972706496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1972706496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.2801931514
Short name	T65
Test name
Test status
Simulation time	8646640354 ps
CPU time	14.76 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:39:12 PM UTC 24
Peak memory	241804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801931514 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2801931514
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.477138606
Short name	T106
Test name
Test status
Simulation time	1609206499 ps
CPU time	6.36 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:39:03 PM UTC 24
Peak memory	209340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477138606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.477138606
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.1787885287
Short name	T92
Test name
Test status
Simulation time	944659023 ps
CPU time	3.31 seconds
Started	Sep 04 12:40:42 PM UTC 24
Finished	Sep 04 12:41:04 PM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787885287 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.1787885287
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.477493793
Short name	T25
Test name
Test status
Simulation time	1273754310 ps
CPU time	6.88 seconds
Started	Sep 04 12:38:52 PM UTC 24
Finished	Sep 04 12:39:00 PM UTC 24
Peak memory	242400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477493793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.477493793
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.1100865048
Short name	T146
Test name
Test status
Simulation time	6844130400 ps
CPU time	27.98 seconds
Started	Sep 04 12:38:50 PM UTC 24
Finished	Sep 04 12:39:19 PM UTC 24
Peak memory	220100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100865048 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1100865048
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.875823326
Short name	T7
Test name
Test status
Simulation time	58451084 ps
CPU time	0.9 seconds
Started	Sep 04 12:38:51 PM UTC 24
Finished	Sep 04 12:38:53 PM UTC 24
Peak memory	208112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875823326 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.875823326
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.1336498267
Short name	T548
Test name
Test status
Simulation time	347366505 ps
CPU time	2.4 seconds
Started	Sep 04 12:41:01 PM UTC 24
Finished	Sep 04 12:41:04 PM UTC 24
Peak memory	217696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336498267 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1336498267
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3041209594
Short name	T137
Test name
Test status
Simulation time	166275626 ps
CPU time	1.27 seconds
Started	Sep 04 12:39:01 PM UTC 24
Finished	Sep 04 12:39:03 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041209594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3041209594
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.678842092
Short name	T110
Test name
Test status
Simulation time	1436242361 ps
CPU time	6.16 seconds
Started	Sep 04 12:39:04 PM UTC 24
Finished	Sep 04 12:39:11 PM UTC 24
Peak memory	209280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678842092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.678842092
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.3259077746
Short name	T581
Test name
Test status
Simulation time	943995271 ps
CPU time	3.32 seconds
Started	Sep 04 12:41:06 PM UTC 24
Finished	Sep 04 12:41:11 PM UTC 24
Peak memory	208320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259077746 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.3259077746
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.4080831696
Short name	T27
Test name
Test status
Simulation time	1265838448 ps
CPU time	7.28 seconds
Started	Sep 04 12:39:00 PM UTC 24
Finished	Sep 04 12:39:08 PM UTC 24
Peak memory	242348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080831696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4080831696
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.689923035
Short name	T121
Test name
Test status
Simulation time	136074310 ps
CPU time	1.25 seconds
Started	Sep 04 12:40:43 PM UTC 24
Finished	Sep 04 12:40:59 PM UTC 24
Peak memory	207792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689923035 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.689923035
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2628832477
Short name	T91
Test name
Test status
Simulation time	119575807 ps
CPU time	1.69 seconds
Started	Sep 04 12:40:59 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	217648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628832477 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2628832477
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1644154767
Short name	T102
Test name
Test status
Simulation time	2557758416 ps
CPU time	12.9 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:39:10 PM UTC 24
Peak memory	225596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644154767 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1644154767
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.2221043801
Short name	T78
Test name
Test status
Simulation time	2454999100 ps
CPU time	10.32 seconds
Started	Sep 04 12:39:01 PM UTC 24
Finished	Sep 04 12:39:13 PM UTC 24
Peak memory	241796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221043801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2221043801
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1585525628
Short name	T2
Test name
Test status
Simulation time	182616612 ps
CPU time	1.08 seconds
Started	Sep 04 12:38:46 PM UTC 24
Finished	Sep 04 12:38:48 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585525628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1585525628
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3886690587
Short name	T85
Test name
Test status
Simulation time	760536020 ps
CPU time	2.92 seconds
Started	Sep 04 12:40:45 PM UTC 24
Finished	Sep 04 12:41:03 PM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886690587 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.3886690587
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4129267636
Short name	T86
Test name
Test status
Simulation time	358815900 ps
CPU time	2.45 seconds
Started	Sep 04 12:40:43 PM UTC 24
Finished	Sep 04 12:41:00 PM UTC 24
Peak memory	208796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129267636 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4129267636
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.4259532491
Short name	T554
Test name
Test status
Simulation time	1568083481 ps
CPU time	8.12 seconds
Started	Sep 04 12:40:43 PM UTC 24
Finished	Sep 04 12:41:06 PM UTC 24
Peak memory	208856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259532491 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.4259532491
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1894770316
Short name	T64
Test name
Test status
Simulation time	89915782 ps
CPU time	0.8 seconds
Started	Sep 04 12:40:43 PM UTC 24
Finished	Sep 04 12:40:58 PM UTC 24
Peak memory	207652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894770316 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1894770316
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.812254743
Short name	T71
Test name
Test status
Simulation time	122623334 ps
CPU time	0.98 seconds
Started	Sep 04 12:40:44 PM UTC 24
Finished	Sep 04 12:40:59 PM UTC 24
Peak memory	207776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=812254743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_wi th_rand_reset.812254743
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.963806458
Short name	T120
Test name
Test status
Simulation time	65825971 ps
CPU time	0.77 seconds
Started	Sep 04 12:40:43 PM UTC 24
Finished	Sep 04 12:40:58 PM UTC 24
Peak memory	207708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963806458 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.963806458
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.2577529712
Short name	T68
Test name
Test status
Simulation time	460620737 ps
CPU time	3.23 seconds
Started	Sep 04 12:40:40 PM UTC 24
Finished	Sep 04 12:40:56 PM UTC 24
Peak memory	217852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577529712 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2577529712
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.793539733
Short name	T59
Test name
Test status
Simulation time	115745741 ps
CPU time	1.28 seconds
Started	Sep 04 12:40:48 PM UTC 24
Finished	Sep 04 12:40:53 PM UTC 24
Peak memory	208516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793539733 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.793539733
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.3756891353
Short name	T582
Test name
Test status
Simulation time	2308545524 ps
CPU time	12.43 seconds
Started	Sep 04 12:40:45 PM UTC 24
Finished	Sep 04 12:41:13 PM UTC 24
Peak memory	208840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756891353 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.3756891353
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.41513721
Short name	T87
Test name
Test status
Simulation time	95749149 ps
CPU time	0.84 seconds
Started	Sep 04 12:40:45 PM UTC 24
Finished	Sep 04 12:41:01 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41513721 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.41513721
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2448412967
Short name	T122
Test name
Test status
Simulation time	59233884 ps
CPU time	0.84 seconds
Started	Sep 04 12:40:45 PM UTC 24
Finished	Sep 04 12:41:01 PM UTC 24
Peak memory	207708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448412967 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2448412967
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3866149756
Short name	T124
Test name
Test status
Simulation time	154536795 ps
CPU time	1.46 seconds
Started	Sep 04 12:40:49 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	207780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866149756 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.3866149756
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4228671415
Short name	T61
Test name
Test status
Simulation time	200956251 ps
CPU time	2.72 seconds
Started	Sep 04 12:40:45 PM UTC 24
Finished	Sep 04 12:40:55 PM UTC 24
Peak memory	217788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228671415 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4228671415
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1531112331
Short name	T564
Test name
Test status
Simulation time	126363665 ps
CPU time	1.11 seconds
Started	Sep 04 12:41:06 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1531112331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_ with_rand_reset.1531112331
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3618748298
Short name	T560
Test name
Test status
Simulation time	78609855 ps
CPU time	0.87 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:08 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618748298 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.3618748298
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1306728107
Short name	T568
Test name
Test status
Simulation time	140198452 ps
CPU time	1.32 seconds
Started	Sep 04 12:41:06 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306728107 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.1306728107
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.4013747335
Short name	T574
Test name
Test status
Simulation time	122955085 ps
CPU time	1.73 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	217628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013747335 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4013747335
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2744613262
Short name	T89
Test name
Test status
Simulation time	917117621 ps
CPU time	3.71 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:11 PM UTC 24
Peak memory	208796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744613262 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.2744613262
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.4000047704
Short name	T579
Test name
Test status
Simulation time	196527134 ps
CPU time	1.3 seconds
Started	Sep 04 12:41:08 PM UTC 24
Finished	Sep 04 12:41:10 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4000047704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_ with_rand_reset.4000047704
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.346952185
Short name	T563
Test name
Test status
Simulation time	66205070 ps
CPU time	0.93 seconds
Started	Sep 04 12:41:06 PM UTC 24
Finished	Sep 04 12:41:08 PM UTC 24
Peak memory	206796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346952185 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.346952185
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.3395986144
Short name	T572
Test name
Test status
Simulation time	90079647 ps
CPU time	1.26 seconds
Started	Sep 04 12:41:06 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395986144 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.3395986144
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.669158419
Short name	T577
Test name
Test status
Simulation time	229166081 ps
CPU time	1.89 seconds
Started	Sep 04 12:41:06 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	217708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669158419 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.669158419
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1235060908
Short name	T620
Test name
Test status
Simulation time	161151184 ps
CPU time	2.35 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:33 PM UTC 24
Peak memory	217860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1235060908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_ with_rand_reset.1235060908
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.739311424
Short name	T607
Test name
Test status
Simulation time	71481877 ps
CPU time	0.98 seconds
Started	Sep 04 12:41:08 PM UTC 24
Finished	Sep 04 12:41:23 PM UTC 24
Peak memory	207712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739311424 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.739311424
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2840221401
Short name	T608
Test name
Test status
Simulation time	125700200 ps
CPU time	1.06 seconds
Started	Sep 04 12:41:08 PM UTC 24
Finished	Sep 04 12:41:23 PM UTC 24
Peak memory	207844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840221401 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.2840221401
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.1739797134
Short name	T615
Test name
Test status
Simulation time	306989658 ps
CPU time	2.05 seconds
Started	Sep 04 12:41:08 PM UTC 24
Finished	Sep 04 12:41:31 PM UTC 24
Peak memory	217784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739797134 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.1739797134
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3379510399
Short name	T90
Test name
Test status
Simulation time	2694061702 ps
CPU time	7.52 seconds
Started	Sep 04 12:41:08 PM UTC 24
Finished	Sep 04 12:41:36 PM UTC 24
Peak memory	208840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379510399 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.3379510399
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.4009187490
Short name	T601
Test name
Test status
Simulation time	214328725 ps
CPU time	1.46 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:19 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4009187490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_ with_rand_reset.4009187490
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2643837180
Short name	T598
Test name
Test status
Simulation time	84365569 ps
CPU time	0.83 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:18 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643837180 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2643837180
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.270046719
Short name	T616
Test name
Test status
Simulation time	101615716 ps
CPU time	1.39 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:32 PM UTC 24
Peak memory	207792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270046719 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.270046719
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.1187909588
Short name	T619
Test name
Test status
Simulation time	278958497 ps
CPU time	2.09 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:32 PM UTC 24
Peak memory	217788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187909588 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.1187909588
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.4134473841
Short name	T602
Test name
Test status
Simulation time	441412126 ps
CPU time	1.84 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:19 PM UTC 24
Peak memory	207712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134473841 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.4134473841
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1781945366
Short name	T594
Test name
Test status
Simulation time	184993864 ps
CPU time	1.6 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:14 PM UTC 24
Peak memory	217644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1781945366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_ with_rand_reset.1781945366
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3772023703
Short name	T600
Test name
Test status
Simulation time	87578287 ps
CPU time	0.94 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:18 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772023703 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3772023703
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3499949185
Short name	T614
Test name
Test status
Simulation time	122442455 ps
CPU time	1.13 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:29 PM UTC 24
Peak memory	207844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499949185 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.3499949185
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.217807149
Short name	T604
Test name
Test status
Simulation time	466111428 ps
CPU time	3.03 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:20 PM UTC 24
Peak memory	217784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217807149 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.217807149
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.249007135
Short name	T605
Test name
Test status
Simulation time	894497583 ps
CPU time	3.4 seconds
Started	Sep 04 12:41:09 PM UTC 24
Finished	Sep 04 12:41:21 PM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249007135 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.249007135
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2761239046
Short name	T595
Test name
Test status
Simulation time	173690794 ps
CPU time	1.66 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:14 PM UTC 24
Peak memory	223716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2761239046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_ with_rand_reset.2761239046
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3016505141
Short name	T588
Test name
Test status
Simulation time	63490880 ps
CPU time	0.73 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:14 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016505141 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3016505141
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1454586500
Short name	T591
Test name
Test status
Simulation time	159248843 ps
CPU time	1.13 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:14 PM UTC 24
Peak memory	207844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454586500 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.1454586500
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2593086003
Short name	T593
Test name
Test status
Simulation time	114192399 ps
CPU time	1.43 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:14 PM UTC 24
Peak memory	207776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593086003 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2593086003
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2243743680
Short name	T617
Test name
Test status
Simulation time	518910530 ps
CPU time	2.4 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:32 PM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243743680 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.2243743680
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.4061150581
Short name	T585
Test name
Test status
Simulation time	126829228 ps
CPU time	0.97 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:13 PM UTC 24
Peak memory	207776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4061150581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_ with_rand_reset.4061150581
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.164490154
Short name	T583
Test name
Test status
Simulation time	72784917 ps
CPU time	0.84 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:13 PM UTC 24
Peak memory	207712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164490154 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.164490154
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3250536340
Short name	T584
Test name
Test status
Simulation time	87817415 ps
CPU time	0.95 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:13 PM UTC 24
Peak memory	207844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250536340 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.3250536340
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3285117489
Short name	T592
Test name
Test status
Simulation time	289612957 ps
CPU time	2.14 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:14 PM UTC 24
Peak memory	221792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285117489 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3285117489
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.4132522915
Short name	T596
Test name
Test status
Simulation time	895208400 ps
CPU time	2.92 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:15 PM UTC 24
Peak memory	208792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132522915 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.4132522915
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2249837720
Short name	T587
Test name
Test status
Simulation time	132659082 ps
CPU time	1.02 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:13 PM UTC 24
Peak memory	207776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2249837720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_ with_rand_reset.2249837720
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.1716166771
Short name	T586
Test name
Test status
Simulation time	84369881 ps
CPU time	0.87 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:13 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716166771 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.1716166771
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3830325931
Short name	T589
Test name
Test status
Simulation time	241576230 ps
CPU time	1.58 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:14 PM UTC 24
Peak memory	207792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830325931 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.3830325931
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3152122419
Short name	T590
Test name
Test status
Simulation time	137247780 ps
CPU time	1.83 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:14 PM UTC 24
Peak memory	219684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152122419 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.3152122419
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3298915617
Short name	T93
Test name
Test status
Simulation time	790460626 ps
CPU time	2.65 seconds
Started	Sep 04 12:41:11 PM UTC 24
Finished	Sep 04 12:41:15 PM UTC 24
Peak memory	208776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298915617 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.3298915617
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.898753652
Short name	T618
Test name
Test status
Simulation time	181828024 ps
CPU time	1.8 seconds
Started	Sep 04 12:41:12 PM UTC 24
Finished	Sep 04 12:41:32 PM UTC 24
Peak memory	217648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=898753652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_w ith_rand_reset.898753652
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1570128302
Short name	T597
Test name
Test status
Simulation time	59452425 ps
CPU time	0.73 seconds
Started	Sep 04 12:41:12 PM UTC 24
Finished	Sep 04 12:41:17 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570128302 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1570128302
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.2555196239
Short name	T599
Test name
Test status
Simulation time	243280339 ps
CPU time	1.51 seconds
Started	Sep 04 12:41:12 PM UTC 24
Finished	Sep 04 12:41:18 PM UTC 24
Peak memory	207792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555196239 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.2555196239
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.4127443660
Short name	T613
Test name
Test status
Simulation time	228482378 ps
CPU time	1.87 seconds
Started	Sep 04 12:41:12 PM UTC 24
Finished	Sep 04 12:41:28 PM UTC 24
Peak memory	217640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127443660 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.4127443660
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.359177225
Short name	T603
Test name
Test status
Simulation time	824700186 ps
CPU time	3 seconds
Started	Sep 04 12:41:12 PM UTC 24
Finished	Sep 04 12:41:19 PM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359177225 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.359177225
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3050136868
Short name	T610
Test name
Test status
Simulation time	122036805 ps
CPU time	1.15 seconds
Started	Sep 04 12:41:14 PM UTC 24
Finished	Sep 04 12:41:23 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3050136868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.3050136868
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1866463427
Short name	T606
Test name
Test status
Simulation time	67816973 ps
CPU time	0.74 seconds
Started	Sep 04 12:41:14 PM UTC 24
Finished	Sep 04 12:41:23 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866463427 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1866463427
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1642824958
Short name	T609
Test name
Test status
Simulation time	73407570 ps
CPU time	0.82 seconds
Started	Sep 04 12:41:14 PM UTC 24
Finished	Sep 04 12:41:23 PM UTC 24
Peak memory	207844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642824958 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.1642824958
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1850708715
Short name	T611
Test name
Test status
Simulation time	212617069 ps
CPU time	1.67 seconds
Started	Sep 04 12:41:14 PM UTC 24
Finished	Sep 04 12:41:24 PM UTC 24
Peak memory	224788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850708715 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1850708715
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2292148522
Short name	T612
Test name
Test status
Simulation time	534067063 ps
CPU time	1.93 seconds
Started	Sep 04 12:41:14 PM UTC 24
Finished	Sep 04 12:41:24 PM UTC 24
Peak memory	207712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292148522 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.2292148522
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.2043244705
Short name	T144
Test name
Test status
Simulation time	352663315 ps
CPU time	2.34 seconds
Started	Sep 04 12:40:57 PM UTC 24
Finished	Sep 04 12:41:01 PM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043244705 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.2043244705
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1709750496
Short name	T544
Test name
Test status
Simulation time	800790085 ps
CPU time	4.17 seconds
Started	Sep 04 12:40:56 PM UTC 24
Finished	Sep 04 12:41:01 PM UTC 24
Peak memory	208796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709750496 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1709750496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4071644671
Short name	T63
Test name
Test status
Simulation time	103402552 ps
CPU time	0.82 seconds
Started	Sep 04 12:40:56 PM UTC 24
Finished	Sep 04 12:40:58 PM UTC 24
Peak memory	207776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071644671 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4071644671
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2467551738
Short name	T72
Test name
Test status
Simulation time	128746649 ps
CPU time	1.03 seconds
Started	Sep 04 12:40:58 PM UTC 24
Finished	Sep 04 12:41:00 PM UTC 24
Peak memory	207712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2467551738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w ith_rand_reset.2467551738
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.936034600
Short name	T62
Test name
Test status
Simulation time	76197702 ps
CPU time	0.73 seconds
Started	Sep 04 12:40:56 PM UTC 24
Finished	Sep 04 12:40:58 PM UTC 24
Peak memory	207708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936034600 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.936034600
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2382132210
Short name	T123
Test name
Test status
Simulation time	228568300 ps
CPU time	1.65 seconds
Started	Sep 04 12:40:58 PM UTC 24
Finished	Sep 04 12:41:01 PM UTC 24
Peak memory	207732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382132210 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.2382132210
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.691856253
Short name	T88
Test name
Test status
Simulation time	260201876 ps
CPU time	1.9 seconds
Started	Sep 04 12:40:54 PM UTC 24
Finished	Sep 04 12:41:00 PM UTC 24
Peak memory	219688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691856253 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.691856253
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.634976819
Short name	T83
Test name
Test status
Simulation time	789670660 ps
CPU time	3.06 seconds
Started	Sep 04 12:40:54 PM UTC 24
Finished	Sep 04 12:41:01 PM UTC 24
Peak memory	208796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634976819 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.634976819
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2992002397
Short name	T145
Test name
Test status
Simulation time	115824997 ps
CPU time	1.4 seconds
Started	Sep 04 12:40:59 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	207684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992002397 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2992002397
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.309283914
Short name	T556
Test name
Test status
Simulation time	478877308 ps
CPU time	5.39 seconds
Started	Sep 04 12:40:59 PM UTC 24
Finished	Sep 04 12:41:06 PM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309283914 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.309283914
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3562520579
Short name	T545
Test name
Test status
Simulation time	134743276 ps
CPU time	1.05 seconds
Started	Sep 04 12:40:59 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	207776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562520579 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3562520579
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1756731577
Short name	T105
Test name
Test status
Simulation time	115856681 ps
CPU time	1.21 seconds
Started	Sep 04 12:41:01 PM UTC 24
Finished	Sep 04 12:41:03 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1756731577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w ith_rand_reset.1756731577
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.687271366
Short name	T546
Test name
Test status
Simulation time	62866780 ps
CPU time	1.07 seconds
Started	Sep 04 12:40:59 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	207684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687271366 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.687271366
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1466223087
Short name	T125
Test name
Test status
Simulation time	199070636 ps
CPU time	1.5 seconds
Started	Sep 04 12:41:01 PM UTC 24
Finished	Sep 04 12:41:03 PM UTC 24
Peak memory	207776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466223087 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.1466223087
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.267507706
Short name	T84
Test name
Test status
Simulation time	468948685 ps
CPU time	2.21 seconds
Started	Sep 04 12:40:59 PM UTC 24
Finished	Sep 04 12:41:03 PM UTC 24
Peak memory	208816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267507706 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.267507706
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4194921886
Short name	T552
Test name
Test status
Simulation time	217366735 ps
CPU time	1.69 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:05 PM UTC 24
Peak memory	207724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194921886 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.4194921886
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1287110866
Short name	T555
Test name
Test status
Simulation time	266458525 ps
CPU time	3.11 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:06 PM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287110866 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1287110866
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.267071053
Short name	T547
Test name
Test status
Simulation time	105650372 ps
CPU time	0.87 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:04 PM UTC 24
Peak memory	207648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267071053 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.267071053
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.572494589
Short name	T550
Test name
Test status
Simulation time	196034898 ps
CPU time	1.54 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:05 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=572494589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_wi th_rand_reset.572494589
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.243907195
Short name	T126
Test name
Test status
Simulation time	73026320 ps
CPU time	0.84 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:04 PM UTC 24
Peak memory	207652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243907195 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.243907195
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1559478821
Short name	T127
Test name
Test status
Simulation time	131317893 ps
CPU time	1.2 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:04 PM UTC 24
Peak memory	207780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559478821 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.1559478821
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3509812403
Short name	T140
Test name
Test status
Simulation time	492659860 ps
CPU time	2 seconds
Started	Sep 04 12:41:01 PM UTC 24
Finished	Sep 04 12:41:05 PM UTC 24
Peak memory	207712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509812403 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.3509812403
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1495094891
Short name	T551
Test name
Test status
Simulation time	132613197 ps
CPU time	1.42 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:05 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1495094891 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w ith_rand_reset.1495094891
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2398855549
Short name	T549
Test name
Test status
Simulation time	71651884 ps
CPU time	0.89 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:04 PM UTC 24
Peak memory	207708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398855549 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2398855549
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1517211015
Short name	T128
Test name
Test status
Simulation time	125689100 ps
CPU time	1.16 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:04 PM UTC 24
Peak memory	207780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517211015 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.1517211015
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.590300620
Short name	T94
Test name
Test status
Simulation time	133445767 ps
CPU time	1.98 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:05 PM UTC 24
Peak memory	217636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590300620 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.590300620
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2166121011
Short name	T553
Test name
Test status
Simulation time	432498351 ps
CPU time	1.99 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:05 PM UTC 24
Peak memory	207712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166121011 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.2166121011
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2635801504
Short name	T573
Test name
Test status
Simulation time	113445840 ps
CPU time	1.33 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2635801504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.2635801504
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.4251840095
Short name	T565
Test name
Test status
Simulation time	68025979 ps
CPU time	1.02 seconds
Started	Sep 04 12:41:03 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251840095 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.4251840095
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.39546270
Short name	T570
Test name
Test status
Simulation time	142202027 ps
CPU time	1.29 seconds
Started	Sep 04 12:41:03 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39546270 -assert nopostproc +UV M_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.39546270
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.3928107145
Short name	T557
Test name
Test status
Simulation time	389108201 ps
CPU time	2.93 seconds
Started	Sep 04 12:41:02 PM UTC 24
Finished	Sep 04 12:41:06 PM UTC 24
Peak memory	217788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928107145 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3928107145
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.4217643971
Short name	T578
Test name
Test status
Simulation time	424028425 ps
CPU time	2.1 seconds
Started	Sep 04 12:41:03 PM UTC 24
Finished	Sep 04 12:41:10 PM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217643971 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.4217643971
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2065272558
Short name	T576
Test name
Test status
Simulation time	203488887 ps
CPU time	1.37 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2065272558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w ith_rand_reset.2065272558
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.2823474030
Short name	T566
Test name
Test status
Simulation time	75897939 ps
CPU time	0.94 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823474030 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2823474030
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3087587766
Short name	T569
Test name
Test status
Simulation time	86244802 ps
CPU time	1.01 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087587766 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.3087587766
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.4117636946
Short name	T558
Test name
Test status
Simulation time	359072097 ps
CPU time	2.55 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:07 PM UTC 24
Peak memory	217832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117636946 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4117636946
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1392332546
Short name	T142
Test name
Test status
Simulation time	879874049 ps
CPU time	2.98 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:11 PM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392332546 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.1392332546
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3213942622
Short name	T562
Test name
Test status
Simulation time	196458086 ps
CPU time	1.32 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:08 PM UTC 24
Peak memory	207712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3213942622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w ith_rand_reset.3213942622
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.208225463
Short name	T571
Test name
Test status
Simulation time	60283554 ps
CPU time	0.94 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208225463 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.208225463
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.172605992
Short name	T575
Test name
Test status
Simulation time	72486379 ps
CPU time	1.09 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172605992 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.172605992
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.484287422
Short name	T580
Test name
Test status
Simulation time	149831985 ps
CPU time	2.36 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:10 PM UTC 24
Peak memory	209036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484287422 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.484287422
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1565652217
Short name	T141
Test name
Test status
Simulation time	1011621667 ps
CPU time	3.43 seconds
Started	Sep 04 12:41:04 PM UTC 24
Finished	Sep 04 12:41:08 PM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565652217 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.1565652217
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3644097325
Short name	T567
Test name
Test status
Simulation time	219038878 ps
CPU time	1.55 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	217568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3644097325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w ith_rand_reset.3644097325
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.3285306559
Short name	T559
Test name
Test status
Simulation time	79191005 ps
CPU time	0.83 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:08 PM UTC 24
Peak memory	207708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285306559 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.3285306559
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.313505808
Short name	T561
Test name
Test status
Simulation time	82035274 ps
CPU time	1.07 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:08 PM UTC 24
Peak memory	207716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313505808 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.313505808
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3893955738
Short name	T69
Test name
Test status
Simulation time	310250820 ps
CPU time	2.75 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:10 PM UTC 24
Peak memory	219744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893955738 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3893955738
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.806758846
Short name	T143
Test name
Test status
Simulation time	882922314 ps
CPU time	2.98 seconds
Started	Sep 04 12:41:05 PM UTC 24
Finished	Sep 04 12:41:10 PM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806758846 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.806758846
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.934842590
Short name	T6
Test name
Test status
Simulation time	301501253 ps
CPU time	1.46 seconds
Started	Sep 04 12:38:50 PM UTC 24
Finished	Sep 04 12:38:52 PM UTC 24
Peak memory	237624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934842590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.934842590
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.1795918398
Short name	T9
Test name
Test status
Simulation time	1024540836 ps
CPU time	6.75 seconds
Started	Sep 04 12:38:46 PM UTC 24
Finished	Sep 04 12:38:54 PM UTC 24
Peak memory	209312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795918398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1795918398
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.1122057097
Short name	T66
Test name
Test status
Simulation time	16553613901 ps
CPU time	31.83 seconds
Started	Sep 04 12:38:50 PM UTC 24
Finished	Sep 04 12:39:23 PM UTC 24
Peak memory	242332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122057097 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1122057097
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2888886584
Short name	T4
Test name
Test status
Simulation time	103082827 ps
CPU time	1.03 seconds
Started	Sep 04 12:38:48 PM UTC 24
Finished	Sep 04 12:38:51 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888886584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2888886584
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.2388962903
Short name	T1
Test name
Test status
Simulation time	248916790 ps
CPU time	1.68 seconds
Started	Sep 04 12:38:45 PM UTC 24
Finished	Sep 04 12:38:48 PM UTC 24
Peak memory	208660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388962903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2388962903
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.2626634202
Short name	T3
Test name
Test status
Simulation time	139859813 ps
CPU time	1.15 seconds
Started	Sep 04 12:38:47 PM UTC 24
Finished	Sep 04 12:38:50 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626634202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2626634202
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.438579652
Short name	T70
Test name
Test status
Simulation time	75202903 ps
CPU time	0.81 seconds
Started	Sep 04 12:38:53 PM UTC 24
Finished	Sep 04 12:38:55 PM UTC 24
Peak memory	208112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438579652 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.438579652
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2003881565
Short name	T24
Test name
Test status
Simulation time	300539117 ps
CPU time	1.42 seconds
Started	Sep 04 12:38:52 PM UTC 24
Finished	Sep 04 12:38:55 PM UTC 24
Peak memory	237624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003881565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2003881565
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3009223786
Short name	T10
Test name
Test status
Simulation time	218484507 ps
CPU time	1.32 seconds
Started	Sep 04 12:38:52 PM UTC 24
Finished	Sep 04 12:38:54 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009223786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3009223786
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.3180270839
Short name	T38
Test name
Test status
Simulation time	1636511481 ps
CPU time	7.7 seconds
Started	Sep 04 12:38:52 PM UTC 24
Finished	Sep 04 12:39:01 PM UTC 24
Peak memory	209316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180270839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3180270839
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3772988497
Short name	T67
Test name
Test status
Simulation time	17182342917 ps
CPU time	29.91 seconds
Started	Sep 04 12:38:53 PM UTC 24
Finished	Sep 04 12:39:25 PM UTC 24
Peak memory	241828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772988497 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3772988497
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3753960473
Short name	T11
Test name
Test status
Simulation time	109856878 ps
CPU time	1.23 seconds
Started	Sep 04 12:38:52 PM UTC 24
Finished	Sep 04 12:38:55 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753960473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3753960473
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.810975939
Short name	T49
Test name
Test status
Simulation time	1607453414 ps
CPU time	6.74 seconds
Started	Sep 04 12:38:52 PM UTC 24
Finished	Sep 04 12:39:00 PM UTC 24
Peak memory	209188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810975939 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.810975939
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.4172520942
Short name	T58
Test name
Test status
Simulation time	349823109 ps
CPU time	2.51 seconds
Started	Sep 04 12:38:52 PM UTC 24
Finished	Sep 04 12:38:56 PM UTC 24
Peak memory	217848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172520942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.4172520942
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1052629697
Short name	T12
Test name
Test status
Simulation time	160319600 ps
CPU time	1.5 seconds
Started	Sep 04 12:38:52 PM UTC 24
Finished	Sep 04 12:38:55 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052629697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1052629697
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.308261282
Short name	T161
Test name
Test status
Simulation time	78148411 ps
CPU time	1.04 seconds
Started	Sep 04 12:39:15 PM UTC 24
Finished	Sep 04 12:39:17 PM UTC 24
Peak memory	208116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308261282 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.308261282
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.134870754
Short name	T44
Test name
Test status
Simulation time	1270625220 ps
CPU time	6.25 seconds
Started	Sep 04 12:39:14 PM UTC 24
Finished	Sep 04 12:39:21 PM UTC 24
Peak memory	241668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134870754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.134870754
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.973548473
Short name	T163
Test name
Test status
Simulation time	301165859 ps
CPU time	1.22 seconds
Started	Sep 04 12:39:15 PM UTC 24
Finished	Sep 04 12:39:17 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973548473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.973548473
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.3098789879
Short name	T157
Test name
Test status
Simulation time	140063678 ps
CPU time	1.21 seconds
Started	Sep 04 12:39:12 PM UTC 24
Finished	Sep 04 12:39:15 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098789879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3098789879
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3277111357
Short name	T112
Test name
Test status
Simulation time	733443797 ps
CPU time	4.53 seconds
Started	Sep 04 12:39:12 PM UTC 24
Finished	Sep 04 12:39:18 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277111357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3277111357
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1611441252
Short name	T160
Test name
Test status
Simulation time	104956803 ps
CPU time	1.32 seconds
Started	Sep 04 12:39:14 PM UTC 24
Finished	Sep 04 12:39:16 PM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611441252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1611441252
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.921772568
Short name	T159
Test name
Test status
Simulation time	212625356 ps
CPU time	1.73 seconds
Started	Sep 04 12:39:12 PM UTC 24
Finished	Sep 04 12:39:15 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921772568 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.921772568
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.1800765198
Short name	T180
Test name
Test status
Simulation time	1875503197 ps
CPU time	7.46 seconds
Started	Sep 04 12:39:15 PM UTC 24
Finished	Sep 04 12:39:23 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800765198 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1800765198
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.2477331361
Short name	T139
Test name
Test status
Simulation time	384234389 ps
CPU time	2.72 seconds
Started	Sep 04 12:39:14 PM UTC 24
Finished	Sep 04 12:39:18 PM UTC 24
Peak memory	217792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477331361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2477331361
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.2833781655
Short name	T147
Test name
Test status
Simulation time	136117589 ps
CPU time	1.32 seconds
Started	Sep 04 12:39:13 PM UTC 24
Finished	Sep 04 12:39:16 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833781655 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2833781655
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.2367325498
Short name	T168
Test name
Test status
Simulation time	88499655 ps
CPU time	1.25 seconds
Started	Sep 04 12:39:17 PM UTC 24
Finished	Sep 04 12:39:20 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367325498 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2367325498
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.1250313179
Short name	T45
Test name
Test status
Simulation time	1279788973 ps
CPU time	6.66 seconds
Started	Sep 04 12:39:17 PM UTC 24
Finished	Sep 04 12:39:25 PM UTC 24
Peak memory	241636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250313179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1250313179
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3101759862
Short name	T170
Test name
Test status
Simulation time	301996540 ps
CPU time	1.41 seconds
Started	Sep 04 12:39:17 PM UTC 24
Finished	Sep 04 12:39:20 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101759862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3101759862
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.125658389
Short name	T162
Test name
Test status
Simulation time	235541792 ps
CPU time	1.06 seconds
Started	Sep 04 12:39:15 PM UTC 24
Finished	Sep 04 12:39:17 PM UTC 24
Peak memory	208184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125658389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.125658389
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3575960571
Short name	T115
Test name
Test status
Simulation time	1986926352 ps
CPU time	7.71 seconds
Started	Sep 04 12:39:16 PM UTC 24
Finished	Sep 04 12:39:25 PM UTC 24
Peak memory	209188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575960571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3575960571
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3850759195
Short name	T166
Test name
Test status
Simulation time	157817021 ps
CPU time	1.32 seconds
Started	Sep 04 12:39:17 PM UTC 24
Finished	Sep 04 12:39:20 PM UTC 24
Peak memory	208356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850759195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3850759195
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.1239493200
Short name	T164
Test name
Test status
Simulation time	200070660 ps
CPU time	1.76 seconds
Started	Sep 04 12:39:15 PM UTC 24
Finished	Sep 04 12:39:18 PM UTC 24
Peak memory	208260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239493200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.1239493200
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.2744189356
Short name	T230
Test name
Test status
Simulation time	4233889287 ps
CPU time	19.66 seconds
Started	Sep 04 12:39:17 PM UTC 24
Finished	Sep 04 12:39:38 PM UTC 24
Peak memory	209376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744189356 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2744189356
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.1126079260
Short name	T171
Test name
Test status
Simulation time	418457657 ps
CPU time	2.7 seconds
Started	Sep 04 12:39:16 PM UTC 24
Finished	Sep 04 12:39:20 PM UTC 24
Peak memory	217852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126079260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1126079260
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.1668209492
Short name	T165
Test name
Test status
Simulation time	76146712 ps
CPU time	0.91 seconds
Started	Sep 04 12:39:16 PM UTC 24
Finished	Sep 04 12:39:18 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668209492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1668209492
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3824640604
Short name	T174
Test name
Test status
Simulation time	86661676 ps
CPU time	0.95 seconds
Started	Sep 04 12:39:20 PM UTC 24
Finished	Sep 04 12:39:22 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824640604 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3824640604
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.2190720768
Short name	T197
Test name
Test status
Simulation time	2454097019 ps
CPU time	8.43 seconds
Started	Sep 04 12:39:19 PM UTC 24
Finished	Sep 04 12:39:28 PM UTC 24
Peak memory	242464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190720768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2190720768
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3583830933
Short name	T177
Test name
Test status
Simulation time	301207343 ps
CPU time	1.36 seconds
Started	Sep 04 12:39:20 PM UTC 24
Finished	Sep 04 12:39:22 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583830933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3583830933
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.2383955098
Short name	T167
Test name
Test status
Simulation time	136528798 ps
CPU time	1.05 seconds
Started	Sep 04 12:39:17 PM UTC 24
Finished	Sep 04 12:39:20 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383955098 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2383955098
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.1466844978
Short name	T129
Test name
Test status
Simulation time	1593998629 ps
CPU time	6.75 seconds
Started	Sep 04 12:39:19 PM UTC 24
Finished	Sep 04 12:39:26 PM UTC 24
Peak memory	209320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466844978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.1466844978
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.197358549
Short name	T173
Test name
Test status
Simulation time	108455627 ps
CPU time	1.23 seconds
Started	Sep 04 12:39:19 PM UTC 24
Finished	Sep 04 12:39:21 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197358549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.197358549
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.466061733
Short name	T169
Test name
Test status
Simulation time	113911594 ps
CPU time	1.21 seconds
Started	Sep 04 12:39:17 PM UTC 24
Finished	Sep 04 12:39:20 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466061733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.466061733
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.203435456
Short name	T176
Test name
Test status
Simulation time	165193837 ps
CPU time	1.29 seconds
Started	Sep 04 12:39:20 PM UTC 24
Finished	Sep 04 12:39:22 PM UTC 24
Peak memory	208236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203435456 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.203435456
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.2788000160
Short name	T104
Test name
Test status
Simulation time	117958102 ps
CPU time	1.6 seconds
Started	Sep 04 12:39:19 PM UTC 24
Finished	Sep 04 12:39:21 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788000160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2788000160
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.334852982
Short name	T172
Test name
Test status
Simulation time	76910473 ps
CPU time	1.02 seconds
Started	Sep 04 12:39:19 PM UTC 24
Finished	Sep 04 12:39:21 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334852982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.334852982
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.3220699301
Short name	T184
Test name
Test status
Simulation time	79361548 ps
CPU time	0.95 seconds
Started	Sep 04 12:39:22 PM UTC 24
Finished	Sep 04 12:39:24 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220699301 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3220699301
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.3491040158
Short name	T31
Test name
Test status
Simulation time	1960179547 ps
CPU time	7.74 seconds
Started	Sep 04 12:39:21 PM UTC 24
Finished	Sep 04 12:39:30 PM UTC 24
Peak memory	242388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491040158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3491040158
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2533065705
Short name	T181
Test name
Test status
Simulation time	301694403 ps
CPU time	1.35 seconds
Started	Sep 04 12:39:21 PM UTC 24
Finished	Sep 04 12:39:24 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533065705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2533065705
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.1652422131
Short name	T175
Test name
Test status
Simulation time	118401934 ps
CPU time	1.09 seconds
Started	Sep 04 12:39:20 PM UTC 24
Finished	Sep 04 12:39:22 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652422131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1652422131
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.1391699446
Short name	T130
Test name
Test status
Simulation time	1551006739 ps
CPU time	6.52 seconds
Started	Sep 04 12:39:21 PM UTC 24
Finished	Sep 04 12:39:29 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391699446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1391699446
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3695671969
Short name	T182
Test name
Test status
Simulation time	114994461 ps
CPU time	1.36 seconds
Started	Sep 04 12:39:21 PM UTC 24
Finished	Sep 04 12:39:24 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695671969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3695671969
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.921566036
Short name	T178
Test name
Test status
Simulation time	205731546 ps
CPU time	1.54 seconds
Started	Sep 04 12:39:20 PM UTC 24
Finished	Sep 04 12:39:22 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921566036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.921566036
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.4136794496
Short name	T236
Test name
Test status
Simulation time	3290019208 ps
CPU time	15.61 seconds
Started	Sep 04 12:39:22 PM UTC 24
Finished	Sep 04 12:39:39 PM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136794496 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.4136794496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.2496494784
Short name	T183
Test name
Test status
Simulation time	136272678 ps
CPU time	1.93 seconds
Started	Sep 04 12:39:21 PM UTC 24
Finished	Sep 04 12:39:24 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496494784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.2496494784
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.2023265548
Short name	T179
Test name
Test status
Simulation time	70113873 ps
CPU time	0.95 seconds
Started	Sep 04 12:39:21 PM UTC 24
Finished	Sep 04 12:39:23 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023265548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2023265548
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.1894818588
Short name	T192
Test name
Test status
Simulation time	60495461 ps
CPU time	1 seconds
Started	Sep 04 12:39:25 PM UTC 24
Finished	Sep 04 12:39:27 PM UTC 24
Peak memory	208132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894818588 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1894818588
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.538666379
Short name	T32
Test name
Test status
Simulation time	1977086315 ps
CPU time	7.49 seconds
Started	Sep 04 12:39:24 PM UTC 24
Finished	Sep 04 12:39:32 PM UTC 24
Peak memory	251976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538666379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.538666379
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3101416543
Short name	T189
Test name
Test status
Simulation time	302705088 ps
CPU time	1.54 seconds
Started	Sep 04 12:39:24 PM UTC 24
Finished	Sep 04 12:39:26 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101416543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.3101416543
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.3967450459
Short name	T185
Test name
Test status
Simulation time	98657988 ps
CPU time	1.05 seconds
Started	Sep 04 12:39:22 PM UTC 24
Finished	Sep 04 12:39:25 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967450459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3967450459
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1980209815
Short name	T131
Test name
Test status
Simulation time	1533420634 ps
CPU time	6.71 seconds
Started	Sep 04 12:39:22 PM UTC 24
Finished	Sep 04 12:39:30 PM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980209815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1980209815
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2025678941
Short name	T187
Test name
Test status
Simulation time	98870387 ps
CPU time	1.07 seconds
Started	Sep 04 12:39:24 PM UTC 24
Finished	Sep 04 12:39:26 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025678941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2025678941
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.747558889
Short name	T186
Test name
Test status
Simulation time	116915088 ps
CPU time	1.28 seconds
Started	Sep 04 12:39:22 PM UTC 24
Finished	Sep 04 12:39:25 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747558889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.747558889
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.1100383429
Short name	T268
Test name
Test status
Simulation time	5660247349 ps
CPU time	20.97 seconds
Started	Sep 04 12:39:24 PM UTC 24
Finished	Sep 04 12:39:46 PM UTC 24
Peak memory	218168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100383429 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1100383429
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1202039188
Short name	T190
Test name
Test status
Simulation time	124279466 ps
CPU time	1.67 seconds
Started	Sep 04 12:39:24 PM UTC 24
Finished	Sep 04 12:39:26 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202039188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1202039188
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.515284649
Short name	T188
Test name
Test status
Simulation time	246155664 ps
CPU time	1.63 seconds
Started	Sep 04 12:39:24 PM UTC 24
Finished	Sep 04 12:39:26 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515284649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.515284649
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.3326799155
Short name	T198
Test name
Test status
Simulation time	74120261 ps
CPU time	0.99 seconds
Started	Sep 04 12:39:26 PM UTC 24
Finished	Sep 04 12:39:28 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326799155 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3326799155
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.2106504777
Short name	T33
Test name
Test status
Simulation time	1969670848 ps
CPU time	8.68 seconds
Started	Sep 04 12:39:26 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	241664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106504777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.2106504777
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.213017744
Short name	T199
Test name
Test status
Simulation time	302415636 ps
CPU time	1.41 seconds
Started	Sep 04 12:39:26 PM UTC 24
Finished	Sep 04 12:39:29 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213017744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.213017744
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.605534237
Short name	T191
Test name
Test status
Simulation time	85191768 ps
CPU time	0.81 seconds
Started	Sep 04 12:39:25 PM UTC 24
Finished	Sep 04 12:39:27 PM UTC 24
Peak memory	208048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605534237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.605534237
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.1484727779
Short name	T207
Test name
Test status
Simulation time	1254830017 ps
CPU time	5.13 seconds
Started	Sep 04 12:39:25 PM UTC 24
Finished	Sep 04 12:39:31 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484727779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1484727779
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1656050188
Short name	T194
Test name
Test status
Simulation time	180863607 ps
CPU time	1.26 seconds
Started	Sep 04 12:39:25 PM UTC 24
Finished	Sep 04 12:39:27 PM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656050188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1656050188
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.2266110516
Short name	T195
Test name
Test status
Simulation time	195746152 ps
CPU time	1.54 seconds
Started	Sep 04 12:39:25 PM UTC 24
Finished	Sep 04 12:39:27 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266110516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.2266110516
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.1419110557
Short name	T313
Test name
Test status
Simulation time	7672166312 ps
CPU time	28.67 seconds
Started	Sep 04 12:39:26 PM UTC 24
Finished	Sep 04 12:39:56 PM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419110557 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1419110557
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.2271787299
Short name	T196
Test name
Test status
Simulation time	259193132 ps
CPU time	1.82 seconds
Started	Sep 04 12:39:25 PM UTC 24
Finished	Sep 04 12:39:28 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271787299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2271787299
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.398914330
Short name	T193
Test name
Test status
Simulation time	90740640 ps
CPU time	0.98 seconds
Started	Sep 04 12:39:25 PM UTC 24
Finished	Sep 04 12:39:27 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398914330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.398914330
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.3051891220
Short name	T206
Test name
Test status
Simulation time	77855010 ps
CPU time	1.21 seconds
Started	Sep 04 12:39:29 PM UTC 24
Finished	Sep 04 12:39:31 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051891220 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3051891220
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.1713920872
Short name	T34
Test name
Test status
Simulation time	2265098688 ps
CPU time	8.62 seconds
Started	Sep 04 12:39:28 PM UTC 24
Finished	Sep 04 12:39:37 PM UTC 24
Peak memory	242452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713920872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1713920872
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.191103190
Short name	T204
Test name
Test status
Simulation time	301860049 ps
CPU time	1.6 seconds
Started	Sep 04 12:39:28 PM UTC 24
Finished	Sep 04 12:39:30 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191103190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.191103190
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.4256111392
Short name	T202
Test name
Test status
Simulation time	203694289 ps
CPU time	1.38 seconds
Started	Sep 04 12:39:28 PM UTC 24
Finished	Sep 04 12:39:30 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256111392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.4256111392
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.3812147370
Short name	T223
Test name
Test status
Simulation time	1708952606 ps
CPU time	7.32 seconds
Started	Sep 04 12:39:28 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812147370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3812147370
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1206182888
Short name	T203
Test name
Test status
Simulation time	192233323 ps
CPU time	1.4 seconds
Started	Sep 04 12:39:28 PM UTC 24
Finished	Sep 04 12:39:30 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206182888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1206182888
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3332514724
Short name	T200
Test name
Test status
Simulation time	196824530 ps
CPU time	1.54 seconds
Started	Sep 04 12:39:26 PM UTC 24
Finished	Sep 04 12:39:29 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332514724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3332514724
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.2819509419
Short name	T253
Test name
Test status
Simulation time	3187635815 ps
CPU time	12.84 seconds
Started	Sep 04 12:39:29 PM UTC 24
Finished	Sep 04 12:39:43 PM UTC 24
Peak memory	209312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819509419 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2819509419
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.4229299604
Short name	T208
Test name
Test status
Simulation time	325399262 ps
CPU time	2.5 seconds
Started	Sep 04 12:39:28 PM UTC 24
Finished	Sep 04 12:39:31 PM UTC 24
Peak memory	208996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229299604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.4229299604
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.1645907489
Short name	T201
Test name
Test status
Simulation time	66036494 ps
CPU time	0.94 seconds
Started	Sep 04 12:39:28 PM UTC 24
Finished	Sep 04 12:39:30 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645907489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1645907489
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.2789468075
Short name	T212
Test name
Test status
Simulation time	85705288 ps
CPU time	0.87 seconds
Started	Sep 04 12:39:31 PM UTC 24
Finished	Sep 04 12:39:33 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789468075 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2789468075
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.85701112
Short name	T242
Test name
Test status
Simulation time	2255835145 ps
CPU time	9.34 seconds
Started	Sep 04 12:39:30 PM UTC 24
Finished	Sep 04 12:39:41 PM UTC 24
Peak memory	242464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85701112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.85701112
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2085670394
Short name	T214
Test name
Test status
Simulation time	302274205 ps
CPU time	1.36 seconds
Started	Sep 04 12:39:31 PM UTC 24
Finished	Sep 04 12:39:34 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085670394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2085670394
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1679980094
Short name	T205
Test name
Test status
Simulation time	168314983 ps
CPU time	0.97 seconds
Started	Sep 04 12:39:29 PM UTC 24
Finished	Sep 04 12:39:31 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679980094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1679980094
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.1304791396
Short name	T221
Test name
Test status
Simulation time	842031409 ps
CPU time	5.66 seconds
Started	Sep 04 12:39:29 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	209196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304791396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1304791396
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1987031918
Short name	T211
Test name
Test status
Simulation time	175287713 ps
CPU time	1.27 seconds
Started	Sep 04 12:39:30 PM UTC 24
Finished	Sep 04 12:39:33 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987031918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1987031918
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.2662470085
Short name	T210
Test name
Test status
Simulation time	197499602 ps
CPU time	1.8 seconds
Started	Sep 04 12:39:29 PM UTC 24
Finished	Sep 04 12:39:32 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662470085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.2662470085
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.2854290779
Short name	T292
Test name
Test status
Simulation time	4829198659 ps
CPU time	19 seconds
Started	Sep 04 12:39:31 PM UTC 24
Finished	Sep 04 12:39:52 PM UTC 24
Peak memory	209224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854290779 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2854290779
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.2389603453
Short name	T215
Test name
Test status
Simulation time	409744435 ps
CPU time	2.48 seconds
Started	Sep 04 12:39:30 PM UTC 24
Finished	Sep 04 12:39:34 PM UTC 24
Peak memory	209000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389603453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2389603453
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.388387656
Short name	T209
Test name
Test status
Simulation time	155413777 ps
CPU time	1.38 seconds
Started	Sep 04 12:39:29 PM UTC 24
Finished	Sep 04 12:39:32 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388387656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.388387656
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.2998002903
Short name	T224
Test name
Test status
Simulation time	84192257 ps
CPU time	1.23 seconds
Started	Sep 04 12:39:34 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	208144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998002903 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2998002903
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.525578335
Short name	T51
Test name
Test status
Simulation time	1266207855 ps
CPU time	6.02 seconds
Started	Sep 04 12:39:33 PM UTC 24
Finished	Sep 04 12:39:40 PM UTC 24
Peak memory	242060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525578335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.525578335
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3446301180
Short name	T219
Test name
Test status
Simulation time	301910831 ps
CPU time	1.3 seconds
Started	Sep 04 12:39:33 PM UTC 24
Finished	Sep 04 12:39:35 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446301180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3446301180
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.497144219
Short name	T213
Test name
Test status
Simulation time	96705277 ps
CPU time	0.86 seconds
Started	Sep 04 12:39:31 PM UTC 24
Finished	Sep 04 12:39:33 PM UTC 24
Peak memory	208184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497144219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.497144219
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.3272695746
Short name	T240
Test name
Test status
Simulation time	1728410820 ps
CPU time	7.27 seconds
Started	Sep 04 12:39:31 PM UTC 24
Finished	Sep 04 12:39:40 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272695746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.3272695746
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.423941849
Short name	T218
Test name
Test status
Simulation time	99947311 ps
CPU time	1.06 seconds
Started	Sep 04 12:39:33 PM UTC 24
Finished	Sep 04 12:39:35 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423941849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.423941849
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.240572480
Short name	T216
Test name
Test status
Simulation time	253991100 ps
CPU time	1.67 seconds
Started	Sep 04 12:39:31 PM UTC 24
Finished	Sep 04 12:39:34 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240572480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.240572480
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.493329451
Short name	T309
Test name
Test status
Simulation time	6180708279 ps
CPU time	20.28 seconds
Started	Sep 04 12:39:34 PM UTC 24
Finished	Sep 04 12:39:55 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493329451 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.493329451
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.2269359353
Short name	T220
Test name
Test status
Simulation time	283332727 ps
CPU time	1.88 seconds
Started	Sep 04 12:39:32 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269359353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2269359353
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.2131212475
Short name	T217
Test name
Test status
Simulation time	111863536 ps
CPU time	1.1 seconds
Started	Sep 04 12:39:32 PM UTC 24
Finished	Sep 04 12:39:35 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131212475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.2131212475
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.3589370923
Short name	T227
Test name
Test status
Simulation time	88992766 ps
CPU time	0.86 seconds
Started	Sep 04 12:39:35 PM UTC 24
Finished	Sep 04 12:39:37 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589370923 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3589370923
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.3585597376
Short name	T46
Test name
Test status
Simulation time	1979472431 ps
CPU time	8.12 seconds
Started	Sep 04 12:39:35 PM UTC 24
Finished	Sep 04 12:39:44 PM UTC 24
Peak memory	242400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585597376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3585597376
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2026597295
Short name	T229
Test name
Test status
Simulation time	303026924 ps
CPU time	1.76 seconds
Started	Sep 04 12:39:35 PM UTC 24
Finished	Sep 04 12:39:38 PM UTC 24
Peak memory	237436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026597295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2026597295
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.2821101412
Short name	T222
Test name
Test status
Simulation time	128415054 ps
CPU time	1 seconds
Started	Sep 04 12:39:34 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821101412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2821101412
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.1706667247
Short name	T247
Test name
Test status
Simulation time	1820668344 ps
CPU time	6.93 seconds
Started	Sep 04 12:39:34 PM UTC 24
Finished	Sep 04 12:39:42 PM UTC 24
Peak memory	209188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706667247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1706667247
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2367250361
Short name	T228
Test name
Test status
Simulation time	175456686 ps
CPU time	1.28 seconds
Started	Sep 04 12:39:35 PM UTC 24
Finished	Sep 04 12:39:37 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367250361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2367250361
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.2589847040
Short name	T226
Test name
Test status
Simulation time	124861030 ps
CPU time	1.37 seconds
Started	Sep 04 12:39:34 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589847040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2589847040
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.1768998116
Short name	T276
Test name
Test status
Simulation time	2205927682 ps
CPU time	11.08 seconds
Started	Sep 04 12:39:35 PM UTC 24
Finished	Sep 04 12:39:48 PM UTC 24
Peak memory	209224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768998116 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1768998116
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.1984871424
Short name	T232
Test name
Test status
Simulation time	385625770 ps
CPU time	2.5 seconds
Started	Sep 04 12:39:35 PM UTC 24
Finished	Sep 04 12:39:39 PM UTC 24
Peak memory	208752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984871424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.1984871424
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.803464158
Short name	T225
Test name
Test status
Simulation time	144289357 ps
CPU time	1.24 seconds
Started	Sep 04 12:39:34 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803464158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.803464158
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.656966768
Short name	T52
Test name
Test status
Simulation time	74201675 ps
CPU time	0.95 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:38:58 PM UTC 24
Peak memory	208112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656966768 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.656966768
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.745304239
Short name	T50
Test name
Test status
Simulation time	1273117683 ps
CPU time	6.83 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:39:04 PM UTC 24
Peak memory	241948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745304239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.745304239
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1278613328
Short name	T53
Test name
Test status
Simulation time	301999678 ps
CPU time	1.61 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:38:58 PM UTC 24
Peak memory	237624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278613328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1278613328
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.2055339126
Short name	T13
Test name
Test status
Simulation time	168500318 ps
CPU time	0.93 seconds
Started	Sep 04 12:38:53 PM UTC 24
Finished	Sep 04 12:38:55 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055339126 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2055339126
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.3155882982
Short name	T107
Test name
Test status
Simulation time	1773881024 ps
CPU time	7.9 seconds
Started	Sep 04 12:38:54 PM UTC 24
Finished	Sep 04 12:39:04 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155882982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3155882982
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.1331165427
Short name	T21
Test name
Test status
Simulation time	205831123 ps
CPU time	1.75 seconds
Started	Sep 04 12:38:53 PM UTC 24
Finished	Sep 04 12:38:56 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331165427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1331165427
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.1192245498
Short name	T55
Test name
Test status
Simulation time	371363941 ps
CPU time	2.41 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:38:59 PM UTC 24
Peak memory	208992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192245498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1192245498
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.1109040935
Short name	T22
Test name
Test status
Simulation time	104192760 ps
CPU time	0.98 seconds
Started	Sep 04 12:38:55 PM UTC 24
Finished	Sep 04 12:38:57 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109040935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1109040935
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.3189932903
Short name	T237
Test name
Test status
Simulation time	63151586 ps
CPU time	0.81 seconds
Started	Sep 04 12:39:38 PM UTC 24
Finished	Sep 04 12:39:40 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189932903 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3189932903
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3538633456
Short name	T259
Test name
Test status
Simulation time	1277455514 ps
CPU time	5.8 seconds
Started	Sep 04 12:39:38 PM UTC 24
Finished	Sep 04 12:39:44 PM UTC 24
Peak memory	241724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538633456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3538633456
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1502220686
Short name	T238
Test name
Test status
Simulation time	301411393 ps
CPU time	1.22 seconds
Started	Sep 04 12:39:38 PM UTC 24
Finished	Sep 04 12:39:40 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502220686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1502220686
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.3511031016
Short name	T231
Test name
Test status
Simulation time	129694403 ps
CPU time	1.13 seconds
Started	Sep 04 12:39:36 PM UTC 24
Finished	Sep 04 12:39:39 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511031016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.3511031016
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.818225117
Short name	T254
Test name
Test status
Simulation time	1680625392 ps
CPU time	5.84 seconds
Started	Sep 04 12:39:36 PM UTC 24
Finished	Sep 04 12:39:43 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818225117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.818225117
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2100068366
Short name	T239
Test name
Test status
Simulation time	141369726 ps
CPU time	1.25 seconds
Started	Sep 04 12:39:38 PM UTC 24
Finished	Sep 04 12:39:40 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100068366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2100068366
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.3716246069
Short name	T234
Test name
Test status
Simulation time	254247772 ps
CPU time	1.61 seconds
Started	Sep 04 12:39:36 PM UTC 24
Finished	Sep 04 12:39:39 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716246069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3716246069
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.2082517119
Short name	T317
Test name
Test status
Simulation time	4675070767 ps
CPU time	18.15 seconds
Started	Sep 04 12:39:38 PM UTC 24
Finished	Sep 04 12:39:57 PM UTC 24
Peak memory	209372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082517119 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2082517119
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.1240564028
Short name	T244
Test name
Test status
Simulation time	454958552 ps
CPU time	2.64 seconds
Started	Sep 04 12:39:37 PM UTC 24
Finished	Sep 04 12:39:41 PM UTC 24
Peak memory	208936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240564028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1240564028
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.1558822471
Short name	T233
Test name
Test status
Simulation time	223776105 ps
CPU time	1.4 seconds
Started	Sep 04 12:39:36 PM UTC 24
Finished	Sep 04 12:39:39 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558822471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1558822471
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.3884098643
Short name	T248
Test name
Test status
Simulation time	71772189 ps
CPU time	0.92 seconds
Started	Sep 04 12:39:40 PM UTC 24
Finished	Sep 04 12:39:42 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884098643 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3884098643
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.2873846187
Short name	T272
Test name
Test status
Simulation time	1275835493 ps
CPU time	6.09 seconds
Started	Sep 04 12:39:40 PM UTC 24
Finished	Sep 04 12:39:47 PM UTC 24
Peak memory	242376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873846187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2873846187
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.221670319
Short name	T251
Test name
Test status
Simulation time	301158329 ps
CPU time	1.46 seconds
Started	Sep 04 12:39:40 PM UTC 24
Finished	Sep 04 12:39:43 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221670319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.221670319
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.2653378902
Short name	T243
Test name
Test status
Simulation time	111576305 ps
CPU time	1.13 seconds
Started	Sep 04 12:39:39 PM UTC 24
Finished	Sep 04 12:39:41 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653378902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2653378902
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.1626093601
Short name	T262
Test name
Test status
Simulation time	1344583133 ps
CPU time	5.07 seconds
Started	Sep 04 12:39:39 PM UTC 24
Finished	Sep 04 12:39:45 PM UTC 24
Peak memory	209196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626093601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1626093601
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2676938519
Short name	T250
Test name
Test status
Simulation time	184023366 ps
CPU time	1.45 seconds
Started	Sep 04 12:39:40 PM UTC 24
Finished	Sep 04 12:39:42 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676938519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2676938519
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.1629246789
Short name	T245
Test name
Test status
Simulation time	201031505 ps
CPU time	1.7 seconds
Started	Sep 04 12:39:39 PM UTC 24
Finished	Sep 04 12:39:41 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629246789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.1629246789
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.1332599015
Short name	T455
Test name
Test status
Simulation time	12095886954 ps
CPU time	42.57 seconds
Started	Sep 04 12:39:40 PM UTC 24
Finished	Sep 04 12:40:24 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332599015 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.1332599015
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.3712302306
Short name	T246
Test name
Test status
Simulation time	254529028 ps
CPU time	2.09 seconds
Started	Sep 04 12:39:39 PM UTC 24
Finished	Sep 04 12:39:42 PM UTC 24
Peak memory	208996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712302306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3712302306
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.3638484821
Short name	T241
Test name
Test status
Simulation time	96610062 ps
CPU time	0.96 seconds
Started	Sep 04 12:39:39 PM UTC 24
Finished	Sep 04 12:39:41 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638484821 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3638484821
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.2640659846
Short name	T260
Test name
Test status
Simulation time	59495668 ps
CPU time	0.82 seconds
Started	Sep 04 12:39:43 PM UTC 24
Finished	Sep 04 12:39:45 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640659846 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2640659846
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.354831324
Short name	T283
Test name
Test status
Simulation time	1268833213 ps
CPU time	6.2 seconds
Started	Sep 04 12:39:41 PM UTC 24
Finished	Sep 04 12:39:49 PM UTC 24
Peak memory	242380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354831324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.354831324
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4085713073
Short name	T257
Test name
Test status
Simulation time	302075404 ps
CPU time	1.51 seconds
Started	Sep 04 12:39:42 PM UTC 24
Finished	Sep 04 12:39:44 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085713073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4085713073
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.1935892337
Short name	T249
Test name
Test status
Simulation time	203833205 ps
CPU time	0.9 seconds
Started	Sep 04 12:39:40 PM UTC 24
Finished	Sep 04 12:39:42 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935892337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1935892337
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.1515862205
Short name	T235
Test name
Test status
Simulation time	2035088568 ps
CPU time	8.03 seconds
Started	Sep 04 12:39:41 PM UTC 24
Finished	Sep 04 12:39:50 PM UTC 24
Peak memory	208480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515862205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.1515862205
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.500835497
Short name	T255
Test name
Test status
Simulation time	105647231 ps
CPU time	1.12 seconds
Started	Sep 04 12:39:41 PM UTC 24
Finished	Sep 04 12:39:44 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500835497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.500835497
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.4176960509
Short name	T252
Test name
Test status
Simulation time	240822813 ps
CPU time	1.53 seconds
Started	Sep 04 12:39:40 PM UTC 24
Finished	Sep 04 12:39:43 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176960509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4176960509
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.1619290397
Short name	T449
Test name
Test status
Simulation time	8086679241 ps
CPU time	39.74 seconds
Started	Sep 04 12:39:42 PM UTC 24
Finished	Sep 04 12:40:23 PM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619290397 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1619290397
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.1049366684
Short name	T258
Test name
Test status
Simulation time	143201993 ps
CPU time	1.93 seconds
Started	Sep 04 12:39:41 PM UTC 24
Finished	Sep 04 12:39:44 PM UTC 24
Peak memory	216812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049366684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1049366684
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.3686057786
Short name	T256
Test name
Test status
Simulation time	176942358 ps
CPU time	1.65 seconds
Started	Sep 04 12:39:41 PM UTC 24
Finished	Sep 04 12:39:44 PM UTC 24
Peak memory	207600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686057786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3686057786
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.1765440791
Short name	T267
Test name
Test status
Simulation time	79362580 ps
CPU time	0.86 seconds
Started	Sep 04 12:39:44 PM UTC 24
Finished	Sep 04 12:39:46 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765440791 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1765440791
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.3875047875
Short name	T298
Test name
Test status
Simulation time	1962581769 ps
CPU time	7.55 seconds
Started	Sep 04 12:39:44 PM UTC 24
Finished	Sep 04 12:39:53 PM UTC 24
Peak memory	241960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875047875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3875047875
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3396892089
Short name	T270
Test name
Test status
Simulation time	301359369 ps
CPU time	1.23 seconds
Started	Sep 04 12:39:44 PM UTC 24
Finished	Sep 04 12:39:46 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396892089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3396892089
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.793429167
Short name	T261
Test name
Test status
Simulation time	136649861 ps
CPU time	0.96 seconds
Started	Sep 04 12:39:43 PM UTC 24
Finished	Sep 04 12:39:45 PM UTC 24
Peak memory	208184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793429167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.793429167
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.3538652451
Short name	T281
Test name
Test status
Simulation time	913992898 ps
CPU time	4.7 seconds
Started	Sep 04 12:39:43 PM UTC 24
Finished	Sep 04 12:39:49 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538652451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3538652451
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.33668827
Short name	T269
Test name
Test status
Simulation time	139454450 ps
CPU time	1.27 seconds
Started	Sep 04 12:39:44 PM UTC 24
Finished	Sep 04 12:39:46 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33668827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.33668827
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.3509052996
Short name	T263
Test name
Test status
Simulation time	122784309 ps
CPU time	1.34 seconds
Started	Sep 04 12:39:43 PM UTC 24
Finished	Sep 04 12:39:45 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509052996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3509052996
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.2927489767
Short name	T359
Test name
Test status
Simulation time	4112892978 ps
CPU time	19.07 seconds
Started	Sep 04 12:39:44 PM UTC 24
Finished	Sep 04 12:40:05 PM UTC 24
Peak memory	218108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927489767 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2927489767
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.2699033879
Short name	T266
Test name
Test status
Simulation time	135693947 ps
CPU time	1.74 seconds
Started	Sep 04 12:39:43 PM UTC 24
Finished	Sep 04 12:39:46 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699033879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2699033879
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.760657017
Short name	T264
Test name
Test status
Simulation time	171665212 ps
CPU time	1.28 seconds
Started	Sep 04 12:39:43 PM UTC 24
Finished	Sep 04 12:39:45 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760657017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.760657017
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.1557672236
Short name	T280
Test name
Test status
Simulation time	69571087 ps
CPU time	1 seconds
Started	Sep 04 12:39:47 PM UTC 24
Finished	Sep 04 12:39:48 PM UTC 24
Peak memory	208020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557672236 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1557672236
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.1611490166
Short name	T302
Test name
Test status
Simulation time	1980376189 ps
CPU time	7.64 seconds
Started	Sep 04 12:39:45 PM UTC 24
Finished	Sep 04 12:39:54 PM UTC 24
Peak memory	242344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611490166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1611490166
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1503612906
Short name	T279
Test name
Test status
Simulation time	301578898 ps
CPU time	1.59 seconds
Started	Sep 04 12:39:45 PM UTC 24
Finished	Sep 04 12:39:48 PM UTC 24
Peak memory	237564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503612906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1503612906
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.1300264147
Short name	T273
Test name
Test status
Simulation time	201371836 ps
CPU time	1.03 seconds
Started	Sep 04 12:39:45 PM UTC 24
Finished	Sep 04 12:39:47 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300264147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1300264147
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.4133576910
Short name	T289
Test name
Test status
Simulation time	882212800 ps
CPU time	4.76 seconds
Started	Sep 04 12:39:45 PM UTC 24
Finished	Sep 04 12:39:51 PM UTC 24
Peak memory	209196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133576910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.4133576910
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.840982451
Short name	T275
Test name
Test status
Simulation time	99563777 ps
CPU time	1.19 seconds
Started	Sep 04 12:39:45 PM UTC 24
Finished	Sep 04 12:39:48 PM UTC 24
Peak memory	208324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840982451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.840982451
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.3905051770
Short name	T271
Test name
Test status
Simulation time	233899636 ps
CPU time	1.58 seconds
Started	Sep 04 12:39:44 PM UTC 24
Finished	Sep 04 12:39:47 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905051770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3905051770
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3412564150
Short name	T349
Test name
Test status
Simulation time	3296309137 ps
CPU time	15.2 seconds
Started	Sep 04 12:39:46 PM UTC 24
Finished	Sep 04 12:40:03 PM UTC 24
Peak memory	209056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412564150 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3412564150
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.510229651
Short name	T278
Test name
Test status
Simulation time	134814618 ps
CPU time	1.68 seconds
Started	Sep 04 12:39:45 PM UTC 24
Finished	Sep 04 12:39:48 PM UTC 24
Peak memory	216744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510229651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.510229651
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.11995539
Short name	T274
Test name
Test status
Simulation time	62289004 ps
CPU time	1.01 seconds
Started	Sep 04 12:39:45 PM UTC 24
Finished	Sep 04 12:39:47 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11995539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.11995539
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.4082262832
Short name	T265
Test name
Test status
Simulation time	63744631 ps
CPU time	0.96 seconds
Started	Sep 04 12:39:48 PM UTC 24
Finished	Sep 04 12:39:50 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082262832 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4082262832
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.3185053096
Short name	T319
Test name
Test status
Simulation time	1967374142 ps
CPU time	8.23 seconds
Started	Sep 04 12:39:48 PM UTC 24
Finished	Sep 04 12:39:57 PM UTC 24
Peak memory	242376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185053096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3185053096
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.424085161
Short name	T288
Test name
Test status
Simulation time	302107852 ps
CPU time	1.57 seconds
Started	Sep 04 12:39:48 PM UTC 24
Finished	Sep 04 12:39:50 PM UTC 24
Peak memory	237688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424085161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.424085161
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.1311926262
Short name	T282
Test name
Test status
Simulation time	129362695 ps
CPU time	0.98 seconds
Started	Sep 04 12:39:47 PM UTC 24
Finished	Sep 04 12:39:49 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311926262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1311926262
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.4128514872
Short name	T308
Test name
Test status
Simulation time	1680758013 ps
CPU time	7.3 seconds
Started	Sep 04 12:39:47 PM UTC 24
Finished	Sep 04 12:39:55 PM UTC 24
Peak memory	209384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128514872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.4128514872
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2780566506
Short name	T287
Test name
Test status
Simulation time	142905707 ps
CPU time	1.34 seconds
Started	Sep 04 12:39:48 PM UTC 24
Finished	Sep 04 12:39:50 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780566506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2780566506
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.3735925312
Short name	T284
Test name
Test status
Simulation time	130189266 ps
CPU time	1.3 seconds
Started	Sep 04 12:39:47 PM UTC 24
Finished	Sep 04 12:39:49 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735925312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.3735925312
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.1982566063
Short name	T477
Test name
Test status
Simulation time	8727397045 ps
CPU time	39.78 seconds
Started	Sep 04 12:39:48 PM UTC 24
Finished	Sep 04 12:40:29 PM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982566063 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1982566063
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.2165502328
Short name	T295
Test name
Test status
Simulation time	392535768 ps
CPU time	3.08 seconds
Started	Sep 04 12:39:48 PM UTC 24
Finished	Sep 04 12:39:52 PM UTC 24
Peak memory	208996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165502328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2165502328
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.1421573733
Short name	T285
Test name
Test status
Simulation time	202874125 ps
CPU time	1.26 seconds
Started	Sep 04 12:39:47 PM UTC 24
Finished	Sep 04 12:39:49 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421573733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1421573733
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.1643205429
Short name	T297
Test name
Test status
Simulation time	68951256 ps
CPU time	1.07 seconds
Started	Sep 04 12:39:51 PM UTC 24
Finished	Sep 04 12:39:53 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643205429 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1643205429
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.2328429071
Short name	T327
Test name
Test status
Simulation time	1977537390 ps
CPU time	7.67 seconds
Started	Sep 04 12:39:49 PM UTC 24
Finished	Sep 04 12:39:58 PM UTC 24
Peak memory	241924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328429071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2328429071
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1270608982
Short name	T294
Test name
Test status
Simulation time	301741568 ps
CPU time	1.23 seconds
Started	Sep 04 12:39:49 PM UTC 24
Finished	Sep 04 12:39:52 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270608982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1270608982
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.3328829854
Short name	T293
Test name
Test status
Simulation time	191530569 ps
CPU time	1.47 seconds
Started	Sep 04 12:39:49 PM UTC 24
Finished	Sep 04 12:39:52 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328829854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3328829854
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.843027927
Short name	T320
Test name
Test status
Simulation time	1667844559 ps
CPU time	6.96 seconds
Started	Sep 04 12:39:49 PM UTC 24
Finished	Sep 04 12:39:57 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843027927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.843027927
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2810957722
Short name	T291
Test name
Test status
Simulation time	93027008 ps
CPU time	1.27 seconds
Started	Sep 04 12:39:49 PM UTC 24
Finished	Sep 04 12:39:52 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810957722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2810957722
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.4204250514
Short name	T286
Test name
Test status
Simulation time	201325880 ps
CPU time	1.44 seconds
Started	Sep 04 12:39:48 PM UTC 24
Finished	Sep 04 12:39:51 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204250514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4204250514
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.1603441358
Short name	T321
Test name
Test status
Simulation time	1872552472 ps
CPU time	6.86 seconds
Started	Sep 04 12:39:49 PM UTC 24
Finished	Sep 04 12:39:57 PM UTC 24
Peak memory	218080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603441358 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1603441358
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.319005110
Short name	T300
Test name
Test status
Simulation time	456117971 ps
CPU time	3.19 seconds
Started	Sep 04 12:39:49 PM UTC 24
Finished	Sep 04 12:39:54 PM UTC 24
Peak memory	208996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319005110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.319005110
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.2548064128
Short name	T290
Test name
Test status
Simulation time	91915786 ps
CPU time	1.2 seconds
Started	Sep 04 12:39:49 PM UTC 24
Finished	Sep 04 12:39:51 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548064128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2548064128
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.1456924593
Short name	T306
Test name
Test status
Simulation time	73577824 ps
CPU time	0.84 seconds
Started	Sep 04 12:39:53 PM UTC 24
Finished	Sep 04 12:39:55 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456924593 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1456924593
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.1725595217
Short name	T355
Test name
Test status
Simulation time	2442508880 ps
CPU time	10.75 seconds
Started	Sep 04 12:39:52 PM UTC 24
Finished	Sep 04 12:40:04 PM UTC 24
Peak memory	242444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725595217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1725595217
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1186035089
Short name	T304
Test name
Test status
Simulation time	301667141 ps
CPU time	1.35 seconds
Started	Sep 04 12:39:52 PM UTC 24
Finished	Sep 04 12:39:54 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186035089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1186035089
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.170504531
Short name	T296
Test name
Test status
Simulation time	83540361 ps
CPU time	0.85 seconds
Started	Sep 04 12:39:51 PM UTC 24
Finished	Sep 04 12:39:52 PM UTC 24
Peak memory	208184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170504531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.170504531
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.2092379286
Short name	T328
Test name
Test status
Simulation time	1589088317 ps
CPU time	6.48 seconds
Started	Sep 04 12:39:51 PM UTC 24
Finished	Sep 04 12:39:58 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092379286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2092379286
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.640164135
Short name	T303
Test name
Test status
Simulation time	141606827 ps
CPU time	1.47 seconds
Started	Sep 04 12:39:52 PM UTC 24
Finished	Sep 04 12:39:54 PM UTC 24
Peak memory	208368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640164135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.640164135
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.2409258837
Short name	T299
Test name
Test status
Simulation time	186035267 ps
CPU time	1.53 seconds
Started	Sep 04 12:39:51 PM UTC 24
Finished	Sep 04 12:39:53 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409258837 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2409258837
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.3249294460
Short name	T484
Test name
Test status
Simulation time	9455153126 ps
CPU time	35.95 seconds
Started	Sep 04 12:39:53 PM UTC 24
Finished	Sep 04 12:40:30 PM UTC 24
Peak memory	218232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249294460 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3249294460
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.4063302977
Short name	T305
Test name
Test status
Simulation time	252372824 ps
CPU time	2.12 seconds
Started	Sep 04 12:39:52 PM UTC 24
Finished	Sep 04 12:39:55 PM UTC 24
Peak memory	208996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063302977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.4063302977
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.3684434662
Short name	T301
Test name
Test status
Simulation time	118316092 ps
CPU time	1.18 seconds
Started	Sep 04 12:39:52 PM UTC 24
Finished	Sep 04 12:39:54 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684434662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3684434662
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.3675813770
Short name	T323
Test name
Test status
Simulation time	72955559 ps
CPU time	1.11 seconds
Started	Sep 04 12:39:55 PM UTC 24
Finished	Sep 04 12:39:58 PM UTC 24
Peak memory	207836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675813770 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.3675813770
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.2831466553
Short name	T358
Test name
Test status
Simulation time	2251473687 ps
CPU time	8.99 seconds
Started	Sep 04 12:39:54 PM UTC 24
Finished	Sep 04 12:40:04 PM UTC 24
Peak memory	242168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831466553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2831466553
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2810483281
Short name	T315
Test name
Test status
Simulation time	302284792 ps
CPU time	1.26 seconds
Started	Sep 04 12:39:54 PM UTC 24
Finished	Sep 04 12:39:57 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810483281 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2810483281
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.645767130
Short name	T307
Test name
Test status
Simulation time	87150597 ps
CPU time	0.88 seconds
Started	Sep 04 12:39:53 PM UTC 24
Finished	Sep 04 12:39:55 PM UTC 24
Peak memory	208172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645767130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.645767130
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.3077587690
Short name	T353
Test name
Test status
Simulation time	2220421433 ps
CPU time	9.29 seconds
Started	Sep 04 12:39:53 PM UTC 24
Finished	Sep 04 12:40:04 PM UTC 24
Peak memory	209320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077587690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3077587690
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3875917420
Short name	T314
Test name
Test status
Simulation time	110522528 ps
CPU time	1.21 seconds
Started	Sep 04 12:39:54 PM UTC 24
Finished	Sep 04 12:39:56 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875917420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3875917420
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.2069197956
Short name	T311
Test name
Test status
Simulation time	262533592 ps
CPU time	1.88 seconds
Started	Sep 04 12:39:53 PM UTC 24
Finished	Sep 04 12:39:56 PM UTC 24
Peak memory	208256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069197956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2069197956
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.1772384404
Short name	T316
Test name
Test status
Simulation time	196825084 ps
CPU time	1.35 seconds
Started	Sep 04 12:39:54 PM UTC 24
Finished	Sep 04 12:39:57 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772384404 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1772384404
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.169082866
Short name	T312
Test name
Test status
Simulation time	295324487 ps
CPU time	2.2 seconds
Started	Sep 04 12:39:53 PM UTC 24
Finished	Sep 04 12:39:56 PM UTC 24
Peak memory	217780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169082866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.169082866
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.1477294670
Short name	T310
Test name
Test status
Simulation time	234534794 ps
CPU time	1.49 seconds
Started	Sep 04 12:39:53 PM UTC 24
Finished	Sep 04 12:39:56 PM UTC 24
Peak memory	208004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477294670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1477294670
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.4287734109
Short name	T330
Test name
Test status
Simulation time	78323648 ps
CPU time	0.91 seconds
Started	Sep 04 12:39:57 PM UTC 24
Finished	Sep 04 12:39:59 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287734109 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4287734109
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.930210225
Short name	T368
Test name
Test status
Simulation time	1975753325 ps
CPU time	7.96 seconds
Started	Sep 04 12:39:57 PM UTC 24
Finished	Sep 04 12:40:06 PM UTC 24
Peak memory	242400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930210225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.930210225
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3622696474
Short name	T333
Test name
Test status
Simulation time	300957558 ps
CPU time	1.62 seconds
Started	Sep 04 12:39:57 PM UTC 24
Finished	Sep 04 12:40:00 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622696474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3622696474
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.452810387
Short name	T322
Test name
Test status
Simulation time	227708979 ps
CPU time	0.98 seconds
Started	Sep 04 12:39:56 PM UTC 24
Finished	Sep 04 12:39:58 PM UTC 24
Peak memory	207884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452810387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.452810387
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.2285657411
Short name	T341
Test name
Test status
Simulation time	946128879 ps
CPU time	4.91 seconds
Started	Sep 04 12:39:56 PM UTC 24
Finished	Sep 04 12:40:02 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285657411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2285657411
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.430033158
Short name	T325
Test name
Test status
Simulation time	110231396 ps
CPU time	1.22 seconds
Started	Sep 04 12:39:56 PM UTC 24
Finished	Sep 04 12:39:58 PM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430033158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.430033158
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.4098324551
Short name	T326
Test name
Test status
Simulation time	200619482 ps
CPU time	1.56 seconds
Started	Sep 04 12:39:56 PM UTC 24
Finished	Sep 04 12:39:58 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098324551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.4098324551
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.3827570740
Short name	T432
Test name
Test status
Simulation time	5232665818 ps
CPU time	21.59 seconds
Started	Sep 04 12:39:57 PM UTC 24
Finished	Sep 04 12:40:20 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827570740 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3827570740
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.3340030945
Short name	T332
Test name
Test status
Simulation time	464872004 ps
CPU time	2.74 seconds
Started	Sep 04 12:39:56 PM UTC 24
Finished	Sep 04 12:39:59 PM UTC 24
Peak memory	209000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340030945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3340030945
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.412969741
Short name	T324
Test name
Test status
Simulation time	67401342 ps
CPU time	1.04 seconds
Started	Sep 04 12:39:56 PM UTC 24
Finished	Sep 04 12:39:58 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412969741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.412969741
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.2480534090
Short name	T35
Test name
Test status
Simulation time	86155042 ps
CPU time	1.23 seconds
Started	Sep 04 12:38:58 PM UTC 24
Finished	Sep 04 12:39:01 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480534090 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2480534090
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.2407075304
Short name	T26
Test name
Test status
Simulation time	1266634240 ps
CPU time	5.75 seconds
Started	Sep 04 12:38:57 PM UTC 24
Finished	Sep 04 12:39:04 PM UTC 24
Peak memory	241444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407075304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.2407075304
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2289221736
Short name	T48
Test name
Test status
Simulation time	302203124 ps
CPU time	1.29 seconds
Started	Sep 04 12:38:57 PM UTC 24
Finished	Sep 04 12:39:00 PM UTC 24
Peak memory	237448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289221736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2289221736
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.3608299615
Short name	T14
Test name
Test status
Simulation time	190404716 ps
CPU time	0.95 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:38:58 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608299615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3608299615
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.2951304459
Short name	T74
Test name
Test status
Simulation time	16505754305 ps
CPU time	36.15 seconds
Started	Sep 04 12:38:58 PM UTC 24
Finished	Sep 04 12:39:36 PM UTC 24
Peak memory	241636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951304459 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2951304459
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.713816350
Short name	T56
Test name
Test status
Simulation time	100284265 ps
CPU time	1.11 seconds
Started	Sep 04 12:38:57 PM UTC 24
Finished	Sep 04 12:38:59 PM UTC 24
Peak memory	208368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713816350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.713816350
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.85859752
Short name	T54
Test name
Test status
Simulation time	200117348 ps
CPU time	1.74 seconds
Started	Sep 04 12:38:56 PM UTC 24
Finished	Sep 04 12:38:59 PM UTC 24
Peak memory	208388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85859752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.85859752
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.2754480615
Short name	T117
Test name
Test status
Simulation time	4279980973 ps
CPU time	16.5 seconds
Started	Sep 04 12:38:58 PM UTC 24
Finished	Sep 04 12:39:16 PM UTC 24
Peak memory	218076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754480615 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2754480615
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.4274037390
Short name	T37
Test name
Test status
Simulation time	403028173 ps
CPU time	2.55 seconds
Started	Sep 04 12:38:57 PM UTC 24
Finished	Sep 04 12:39:01 PM UTC 24
Peak memory	208932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274037390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.4274037390
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2183268878
Short name	T57
Test name
Test status
Simulation time	165361489 ps
CPU time	1.45 seconds
Started	Sep 04 12:38:57 PM UTC 24
Finished	Sep 04 12:39:00 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183268878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2183268878
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.1311664704
Short name	T336
Test name
Test status
Simulation time	67073969 ps
CPU time	0.91 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:00 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311664704 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1311664704
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.2372080170
Short name	T362
Test name
Test status
Simulation time	1277913508 ps
CPU time	5.93 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:05 PM UTC 24
Peak memory	241660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372080170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2372080170
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3592697972
Short name	T338
Test name
Test status
Simulation time	301829128 ps
CPU time	1.37 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:01 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592697972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3592697972
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.2389518029
Short name	T329
Test name
Test status
Simulation time	80152018 ps
CPU time	0.8 seconds
Started	Sep 04 12:39:57 PM UTC 24
Finished	Sep 04 12:39:59 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389518029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2389518029
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.790382621
Short name	T354
Test name
Test status
Simulation time	764448043 ps
CPU time	4.44 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:04 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790382621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.790382621
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.3068441428
Short name	T337
Test name
Test status
Simulation time	182203674 ps
CPU time	1.3 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:01 PM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068441428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.3068441428
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.3070208902
Short name	T331
Test name
Test status
Simulation time	125564958 ps
CPU time	1.36 seconds
Started	Sep 04 12:39:57 PM UTC 24
Finished	Sep 04 12:39:59 PM UTC 24
Peak memory	208276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070208902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3070208902
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.478607183
Short name	T343
Test name
Test status
Simulation time	604530651 ps
CPU time	2.91 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:02 PM UTC 24
Peak memory	209120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478607183 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.478607183
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.2093908277
Short name	T344
Test name
Test status
Simulation time	468072239 ps
CPU time	2.95 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:02 PM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093908277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2093908277
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.3363362166
Short name	T334
Test name
Test status
Simulation time	177365158 ps
CPU time	1.18 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:00 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363362166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3363362166
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.2309356296
Short name	T348
Test name
Test status
Simulation time	72033762 ps
CPU time	1.04 seconds
Started	Sep 04 12:40:01 PM UTC 24
Finished	Sep 04 12:40:03 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309356296 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.2309356296
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.2175465879
Short name	T372
Test name
Test status
Simulation time	1288294701 ps
CPU time	6.45 seconds
Started	Sep 04 12:40:00 PM UTC 24
Finished	Sep 04 12:40:07 PM UTC 24
Peak memory	242340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175465879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2175465879
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.80433864
Short name	T352
Test name
Test status
Simulation time	300824390 ps
CPU time	1.57 seconds
Started	Sep 04 12:40:01 PM UTC 24
Finished	Sep 04 12:40:03 PM UTC 24
Peak memory	237448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80433864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.80433864
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.1479639751
Short name	T335
Test name
Test status
Simulation time	102361065 ps
CPU time	0.86 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:00 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479639751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1479639751
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.1172889767
Short name	T318
Test name
Test status
Simulation time	1489838147 ps
CPU time	6.19 seconds
Started	Sep 04 12:40:00 PM UTC 24
Finished	Sep 04 12:40:07 PM UTC 24
Peak memory	209196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172889767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1172889767
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2677140774
Short name	T342
Test name
Test status
Simulation time	158776162 ps
CPU time	1.39 seconds
Started	Sep 04 12:40:00 PM UTC 24
Finished	Sep 04 12:40:02 PM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677140774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2677140774
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.1718154365
Short name	T340
Test name
Test status
Simulation time	195493979 ps
CPU time	1.6 seconds
Started	Sep 04 12:39:58 PM UTC 24
Finished	Sep 04 12:40:01 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718154365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1718154365
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.466006783
Short name	T402
Test name
Test status
Simulation time	3016854528 ps
CPU time	11.57 seconds
Started	Sep 04 12:40:01 PM UTC 24
Finished	Sep 04 12:40:14 PM UTC 24
Peak memory	209308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466006783 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.466006783
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.1110142657
Short name	T347
Test name
Test status
Simulation time	265042078 ps
CPU time	1.97 seconds
Started	Sep 04 12:40:00 PM UTC 24
Finished	Sep 04 12:40:03 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110142657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1110142657
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.4110606003
Short name	T345
Test name
Test status
Simulation time	181522997 ps
CPU time	1.99 seconds
Started	Sep 04 12:40:00 PM UTC 24
Finished	Sep 04 12:40:03 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110606003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.4110606003
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.2854926053
Short name	T363
Test name
Test status
Simulation time	84039667 ps
CPU time	0.95 seconds
Started	Sep 04 12:40:03 PM UTC 24
Finished	Sep 04 12:40:05 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854926053 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.2854926053
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.2050869501
Short name	T382
Test name
Test status
Simulation time	1272290182 ps
CPU time	5.91 seconds
Started	Sep 04 12:40:02 PM UTC 24
Finished	Sep 04 12:40:09 PM UTC 24
Peak memory	241668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050869501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2050869501
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.806431380
Short name	T357
Test name
Test status
Simulation time	302915869 ps
CPU time	1.18 seconds
Started	Sep 04 12:40:02 PM UTC 24
Finished	Sep 04 12:40:04 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806431380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.806431380
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.2764606759
Short name	T351
Test name
Test status
Simulation time	220034431 ps
CPU time	1.29 seconds
Started	Sep 04 12:40:01 PM UTC 24
Finished	Sep 04 12:40:03 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764606759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2764606759
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.1602167458
Short name	T375
Test name
Test status
Simulation time	1328633505 ps
CPU time	5.55 seconds
Started	Sep 04 12:40:01 PM UTC 24
Finished	Sep 04 12:40:08 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602167458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1602167458
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.736706021
Short name	T356
Test name
Test status
Simulation time	102704536 ps
CPU time	1.04 seconds
Started	Sep 04 12:40:02 PM UTC 24
Finished	Sep 04 12:40:04 PM UTC 24
Peak memory	208276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736706021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.736706021
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.371218948
Short name	T350
Test name
Test status
Simulation time	122071586 ps
CPU time	1.24 seconds
Started	Sep 04 12:40:01 PM UTC 24
Finished	Sep 04 12:40:03 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371218948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.371218948
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.2228858944
Short name	T523
Test name
Test status
Simulation time	12758259080 ps
CPU time	42.54 seconds
Started	Sep 04 12:40:03 PM UTC 24
Finished	Sep 04 12:40:47 PM UTC 24
Peak memory	209096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228858944 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2228858944
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.711257760
Short name	T361
Test name
Test status
Simulation time	261826418 ps
CPU time	1.94 seconds
Started	Sep 04 12:40:02 PM UTC 24
Finished	Sep 04 12:40:05 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711257760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.711257760
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.1295689731
Short name	T360
Test name
Test status
Simulation time	229955398 ps
CPU time	1.56 seconds
Started	Sep 04 12:40:02 PM UTC 24
Finished	Sep 04 12:40:05 PM UTC 24
Peak memory	208260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295689731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.1295689731
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.1591155281
Short name	T370
Test name
Test status
Simulation time	64564315 ps
CPU time	1.05 seconds
Started	Sep 04 12:40:05 PM UTC 24
Finished	Sep 04 12:40:07 PM UTC 24
Peak memory	208244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591155281 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1591155281
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.762038700
Short name	T406
Test name
Test status
Simulation time	2480554917 ps
CPU time	9.15 seconds
Started	Sep 04 12:40:04 PM UTC 24
Finished	Sep 04 12:40:14 PM UTC 24
Peak memory	242468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762038700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.762038700
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1460419529
Short name	T373
Test name
Test status
Simulation time	302245111 ps
CPU time	1.43 seconds
Started	Sep 04 12:40:05 PM UTC 24
Finished	Sep 04 12:40:07 PM UTC 24
Peak memory	237232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460419529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1460419529
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.86400975
Short name	T364
Test name
Test status
Simulation time	201534291 ps
CPU time	1.03 seconds
Started	Sep 04 12:40:03 PM UTC 24
Finished	Sep 04 12:40:06 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86400975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.86400975
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.1833952602
Short name	T383
Test name
Test status
Simulation time	888960857 ps
CPU time	4.62 seconds
Started	Sep 04 12:40:04 PM UTC 24
Finished	Sep 04 12:40:09 PM UTC 24
Peak memory	208984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833952602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1833952602
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3072045457
Short name	T366
Test name
Test status
Simulation time	101491146 ps
CPU time	1.05 seconds
Started	Sep 04 12:40:04 PM UTC 24
Finished	Sep 04 12:40:06 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072045457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3072045457
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.4256193496
Short name	T365
Test name
Test status
Simulation time	114522738 ps
CPU time	1.17 seconds
Started	Sep 04 12:40:03 PM UTC 24
Finished	Sep 04 12:40:06 PM UTC 24
Peak memory	208008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256193496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.4256193496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.1771961543
Short name	T401
Test name
Test status
Simulation time	1517539646 ps
CPU time	6.71 seconds
Started	Sep 04 12:40:05 PM UTC 24
Finished	Sep 04 12:40:13 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771961543 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1771961543
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.961557776
Short name	T339
Test name
Test status
Simulation time	495359063 ps
CPU time	2.55 seconds
Started	Sep 04 12:40:04 PM UTC 24
Finished	Sep 04 12:40:07 PM UTC 24
Peak memory	208936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961557776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.961557776
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.413527277
Short name	T367
Test name
Test status
Simulation time	185148376 ps
CPU time	1.37 seconds
Started	Sep 04 12:40:04 PM UTC 24
Finished	Sep 04 12:40:06 PM UTC 24
Peak memory	207572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413527277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.413527277
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.3011809064
Short name	T376
Test name
Test status
Simulation time	60578881 ps
CPU time	0.85 seconds
Started	Sep 04 12:40:06 PM UTC 24
Finished	Sep 04 12:40:08 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011809064 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3011809064
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.292337335
Short name	T422
Test name
Test status
Simulation time	2430429887 ps
CPU time	10.29 seconds
Started	Sep 04 12:40:06 PM UTC 24
Finished	Sep 04 12:40:18 PM UTC 24
Peak memory	242468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292337335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.292337335
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.436759368
Short name	T377
Test name
Test status
Simulation time	302368507 ps
CPU time	1.25 seconds
Started	Sep 04 12:40:06 PM UTC 24
Finished	Sep 04 12:40:09 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436759368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.436759368
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.2084314899
Short name	T369
Test name
Test status
Simulation time	80618652 ps
CPU time	0.88 seconds
Started	Sep 04 12:40:05 PM UTC 24
Finished	Sep 04 12:40:07 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084314899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2084314899
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.963721824
Short name	T397
Test name
Test status
Simulation time	1477589102 ps
CPU time	6.54 seconds
Started	Sep 04 12:40:05 PM UTC 24
Finished	Sep 04 12:40:12 PM UTC 24
Peak memory	209188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963721824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.963721824
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1146009840
Short name	T380
Test name
Test status
Simulation time	176944424 ps
CPU time	1.44 seconds
Started	Sep 04 12:40:06 PM UTC 24
Finished	Sep 04 12:40:09 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146009840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1146009840
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.338545246
Short name	T374
Test name
Test status
Simulation time	234209058 ps
CPU time	1.61 seconds
Started	Sep 04 12:40:05 PM UTC 24
Finished	Sep 04 12:40:07 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338545246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.338545246
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.1168539137
Short name	T410
Test name
Test status
Simulation time	1737118547 ps
CPU time	7.5 seconds
Started	Sep 04 12:40:06 PM UTC 24
Finished	Sep 04 12:40:15 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168539137 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1168539137
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.2982831595
Short name	T379
Test name
Test status
Simulation time	473874502 ps
CPU time	2.62 seconds
Started	Sep 04 12:40:05 PM UTC 24
Finished	Sep 04 12:40:09 PM UTC 24
Peak memory	217852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982831595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2982831595
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.422600100
Short name	T371
Test name
Test status
Simulation time	112197934 ps
CPU time	1.17 seconds
Started	Sep 04 12:40:05 PM UTC 24
Finished	Sep 04 12:40:07 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422600100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.422600100
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.201391271
Short name	T385
Test name
Test status
Simulation time	83124588 ps
CPU time	0.98 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:10 PM UTC 24
Peak memory	208116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201391271 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.201391271
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.103377722
Short name	T411
Test name
Test status
Simulation time	1268838470 ps
CPU time	6.12 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:15 PM UTC 24
Peak memory	241732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103377722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.103377722
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3781966896
Short name	T388
Test name
Test status
Simulation time	302984665 ps
CPU time	1.24 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:10 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781966896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3781966896
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.938930194
Short name	T378
Test name
Test status
Simulation time	251747869 ps
CPU time	1.15 seconds
Started	Sep 04 12:40:06 PM UTC 24
Finished	Sep 04 12:40:09 PM UTC 24
Peak memory	208184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938930194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.938930194
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.2892250639
Short name	T393
Test name
Test status
Simulation time	788616550 ps
CPU time	4.21 seconds
Started	Sep 04 12:40:06 PM UTC 24
Finished	Sep 04 12:40:12 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892250639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2892250639
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3328985910
Short name	T384
Test name
Test status
Simulation time	92899691 ps
CPU time	1.01 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:10 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328985910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3328985910
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.4245731156
Short name	T381
Test name
Test status
Simulation time	105694531 ps
CPU time	1.31 seconds
Started	Sep 04 12:40:06 PM UTC 24
Finished	Sep 04 12:40:09 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245731156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.4245731156
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.858622266
Short name	T514
Test name
Test status
Simulation time	8912509785 ps
CPU time	33.63 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:43 PM UTC 24
Peak memory	220152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858622266 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.858622266
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.2398573701
Short name	T391
Test name
Test status
Simulation time	347616505 ps
CPU time	2.35 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:11 PM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398573701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2398573701
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.2390964725
Short name	T387
Test name
Test status
Simulation time	174403185 ps
CPU time	1.35 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:10 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390964725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2390964725
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.2276208584
Short name	T395
Test name
Test status
Simulation time	78994031 ps
CPU time	1.06 seconds
Started	Sep 04 12:40:10 PM UTC 24
Finished	Sep 04 12:40:12 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276208584 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2276208584
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.882210455
Short name	T434
Test name
Test status
Simulation time	2466344115 ps
CPU time	8.7 seconds
Started	Sep 04 12:40:10 PM UTC 24
Finished	Sep 04 12:40:20 PM UTC 24
Peak memory	242288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882210455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.882210455
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2380376115
Short name	T400
Test name
Test status
Simulation time	301702730 ps
CPU time	1.43 seconds
Started	Sep 04 12:40:10 PM UTC 24
Finished	Sep 04 12:40:13 PM UTC 24
Peak memory	237444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380376115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2380376115
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.4110794553
Short name	T386
Test name
Test status
Simulation time	107578261 ps
CPU time	0.97 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:10 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110794553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.4110794553
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.1000088673
Short name	T407
Test name
Test status
Simulation time	776821615 ps
CPU time	4.59 seconds
Started	Sep 04 12:40:09 PM UTC 24
Finished	Sep 04 12:40:15 PM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000088673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1000088673
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3235332282
Short name	T390
Test name
Test status
Simulation time	107616431 ps
CPU time	1.07 seconds
Started	Sep 04 12:40:09 PM UTC 24
Finished	Sep 04 12:40:11 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235332282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3235332282
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.61325180
Short name	T389
Test name
Test status
Simulation time	112772780 ps
CPU time	1.38 seconds
Started	Sep 04 12:40:08 PM UTC 24
Finished	Sep 04 12:40:10 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61325180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.61325180
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.3278435187
Short name	T466
Test name
Test status
Simulation time	3151516851 ps
CPU time	15.06 seconds
Started	Sep 04 12:40:10 PM UTC 24
Finished	Sep 04 12:40:26 PM UTC 24
Peak memory	218172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278435187 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3278435187
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.1824820292
Short name	T394
Test name
Test status
Simulation time	145147107 ps
CPU time	2.04 seconds
Started	Sep 04 12:40:09 PM UTC 24
Finished	Sep 04 12:40:12 PM UTC 24
Peak memory	208936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824820292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1824820292
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.1438705401
Short name	T392
Test name
Test status
Simulation time	216273355 ps
CPU time	1.36 seconds
Started	Sep 04 12:40:09 PM UTC 24
Finished	Sep 04 12:40:11 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438705401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1438705401
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.3905689599
Short name	T403
Test name
Test status
Simulation time	72201802 ps
CPU time	0.94 seconds
Started	Sep 04 12:40:12 PM UTC 24
Finished	Sep 04 12:40:14 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905689599 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3905689599
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.1632285184
Short name	T439
Test name
Test status
Simulation time	2449752232 ps
CPU time	8.95 seconds
Started	Sep 04 12:40:11 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	242512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632285184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1632285184
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1943085237
Short name	T404
Test name
Test status
Simulation time	306738126 ps
CPU time	1.22 seconds
Started	Sep 04 12:40:11 PM UTC 24
Finished	Sep 04 12:40:14 PM UTC 24
Peak memory	237568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943085237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1943085237
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.4064066246
Short name	T398
Test name
Test status
Simulation time	187198730 ps
CPU time	1.16 seconds
Started	Sep 04 12:40:10 PM UTC 24
Finished	Sep 04 12:40:13 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064066246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.4064066246
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.2517737158
Short name	T428
Test name
Test status
Simulation time	2026384354 ps
CPU time	7.5 seconds
Started	Sep 04 12:40:10 PM UTC 24
Finished	Sep 04 12:40:19 PM UTC 24
Peak memory	209196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517737158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2517737158
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2096939063
Short name	T405
Test name
Test status
Simulation time	102579684 ps
CPU time	1.47 seconds
Started	Sep 04 12:40:11 PM UTC 24
Finished	Sep 04 12:40:14 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096939063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2096939063
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.3700426169
Short name	T399
Test name
Test status
Simulation time	111619958 ps
CPU time	1.36 seconds
Started	Sep 04 12:40:10 PM UTC 24
Finished	Sep 04 12:40:13 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700426169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.3700426169
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.993969994
Short name	T495
Test name
Test status
Simulation time	4421490059 ps
CPU time	20.52 seconds
Started	Sep 04 12:40:12 PM UTC 24
Finished	Sep 04 12:40:33 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993969994 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.993969994
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.2854872963
Short name	T408
Test name
Test status
Simulation time	305122854 ps
CPU time	2.13 seconds
Started	Sep 04 12:40:11 PM UTC 24
Finished	Sep 04 12:40:15 PM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854872963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2854872963
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.2669789497
Short name	T396
Test name
Test status
Simulation time	108858450 ps
CPU time	0.96 seconds
Started	Sep 04 12:40:10 PM UTC 24
Finished	Sep 04 12:40:12 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669789497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2669789497
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.1145574971
Short name	T416
Test name
Test status
Simulation time	77740597 ps
CPU time	1.06 seconds
Started	Sep 04 12:40:14 PM UTC 24
Finished	Sep 04 12:40:16 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145574971 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1145574971
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.4005747171
Short name	T453
Test name
Test status
Simulation time	1950588052 ps
CPU time	8.26 seconds
Started	Sep 04 12:40:14 PM UTC 24
Finished	Sep 04 12:40:23 PM UTC 24
Peak memory	242404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005747171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.4005747171
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.316658323
Short name	T417
Test name
Test status
Simulation time	311953342 ps
CPU time	1.25 seconds
Started	Sep 04 12:40:14 PM UTC 24
Finished	Sep 04 12:40:16 PM UTC 24
Peak memory	237124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316658323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.316658323
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.1712236090
Short name	T409
Test name
Test status
Simulation time	172283647 ps
CPU time	1.3 seconds
Started	Sep 04 12:40:13 PM UTC 24
Finished	Sep 04 12:40:15 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712236090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1712236090
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.3388444928
Short name	T430
Test name
Test status
Simulation time	1288379409 ps
CPU time	5.46 seconds
Started	Sep 04 12:40:13 PM UTC 24
Finished	Sep 04 12:40:19 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388444928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3388444928
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1176561770
Short name	T419
Test name
Test status
Simulation time	182113795 ps
CPU time	1.42 seconds
Started	Sep 04 12:40:14 PM UTC 24
Finished	Sep 04 12:40:16 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176561770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1176561770
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.3604608576
Short name	T413
Test name
Test status
Simulation time	264566023 ps
CPU time	1.57 seconds
Started	Sep 04 12:40:13 PM UTC 24
Finished	Sep 04 12:40:15 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604608576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3604608576
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.1024133362
Short name	T492
Test name
Test status
Simulation time	3436348846 ps
CPU time	17.14 seconds
Started	Sep 04 12:40:14 PM UTC 24
Finished	Sep 04 12:40:32 PM UTC 24
Peak memory	218148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024133362 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1024133362
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.2030521421
Short name	T414
Test name
Test status
Simulation time	146857472 ps
CPU time	2 seconds
Started	Sep 04 12:40:13 PM UTC 24
Finished	Sep 04 12:40:16 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030521421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2030521421
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.3235160016
Short name	T412
Test name
Test status
Simulation time	150951963 ps
CPU time	1.32 seconds
Started	Sep 04 12:40:13 PM UTC 24
Finished	Sep 04 12:40:15 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235160016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3235160016
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.1699334089
Short name	T425
Test name
Test status
Simulation time	78022416 ps
CPU time	1 seconds
Started	Sep 04 12:40:17 PM UTC 24
Finished	Sep 04 12:40:19 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699334089 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1699334089
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.1682339718
Short name	T444
Test name
Test status
Simulation time	1272794051 ps
CPU time	5.88 seconds
Started	Sep 04 12:40:15 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	242024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682339718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1682339718
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.905420002
Short name	T421
Test name
Test status
Simulation time	301608751 ps
CPU time	1.22 seconds
Started	Sep 04 12:40:15 PM UTC 24
Finished	Sep 04 12:40:18 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905420002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.905420002
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.2378677474
Short name	T415
Test name
Test status
Simulation time	88621666 ps
CPU time	1 seconds
Started	Sep 04 12:40:14 PM UTC 24
Finished	Sep 04 12:40:16 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378677474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2378677474
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.795022727
Short name	T437
Test name
Test status
Simulation time	900577249 ps
CPU time	4.7 seconds
Started	Sep 04 12:40:15 PM UTC 24
Finished	Sep 04 12:40:21 PM UTC 24
Peak memory	209244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795022727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.795022727
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1664602617
Short name	T423
Test name
Test status
Simulation time	109819451 ps
CPU time	1.38 seconds
Started	Sep 04 12:40:15 PM UTC 24
Finished	Sep 04 12:40:18 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664602617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1664602617
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.3055066003
Short name	T418
Test name
Test status
Simulation time	118206053 ps
CPU time	1.19 seconds
Started	Sep 04 12:40:14 PM UTC 24
Finished	Sep 04 12:40:16 PM UTC 24
Peak memory	208276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055066003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3055066003
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.2334517581
Short name	T452
Test name
Test status
Simulation time	1015666399 ps
CPU time	5.61 seconds
Started	Sep 04 12:40:16 PM UTC 24
Finished	Sep 04 12:40:23 PM UTC 24
Peak memory	209184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334517581 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2334517581
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.173833613
Short name	T424
Test name
Test status
Simulation time	115068841 ps
CPU time	1.6 seconds
Started	Sep 04 12:40:15 PM UTC 24
Finished	Sep 04 12:40:18 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173833613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.173833613
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.4185060136
Short name	T420
Test name
Test status
Simulation time	84572342 ps
CPU time	1.1 seconds
Started	Sep 04 12:40:15 PM UTC 24
Finished	Sep 04 12:40:17 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185060136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4185060136
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.3431842528
Short name	T42
Test name
Test status
Simulation time	68655800 ps
CPU time	0.91 seconds
Started	Sep 04 12:39:01 PM UTC 24
Finished	Sep 04 12:39:03 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431842528 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3431842528
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.4255230721
Short name	T39
Test name
Test status
Simulation time	302615839 ps
CPU time	1.27 seconds
Started	Sep 04 12:39:00 PM UTC 24
Finished	Sep 04 12:39:02 PM UTC 24
Peak memory	237624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255230721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.4255230721
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.3565862646
Short name	T15
Test name
Test status
Simulation time	135859003 ps
CPU time	0.9 seconds
Started	Sep 04 12:38:58 PM UTC 24
Finished	Sep 04 12:39:00 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565862646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3565862646
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.3356643867
Short name	T109
Test name
Test status
Simulation time	1870248479 ps
CPU time	7.2 seconds
Started	Sep 04 12:39:00 PM UTC 24
Finished	Sep 04 12:39:08 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356643867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3356643867
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.3143533280
Short name	T73
Test name
Test status
Simulation time	16596043687 ps
CPU time	32.36 seconds
Started	Sep 04 12:39:00 PM UTC 24
Finished	Sep 04 12:39:34 PM UTC 24
Peak memory	241780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143533280 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3143533280
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.276341915
Short name	T41
Test name
Test status
Simulation time	186689127 ps
CPU time	1.78 seconds
Started	Sep 04 12:39:00 PM UTC 24
Finished	Sep 04 12:39:03 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276341915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.276341915
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.514399114
Short name	T36
Test name
Test status
Simulation time	116814024 ps
CPU time	1.31 seconds
Started	Sep 04 12:38:58 PM UTC 24
Finished	Sep 04 12:39:01 PM UTC 24
Peak memory	208332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514399114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.514399114
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.986064049
Short name	T119
Test name
Test status
Simulation time	4478312123 ps
CPU time	17.8 seconds
Started	Sep 04 12:39:00 PM UTC 24
Finished	Sep 04 12:39:19 PM UTC 24
Peak memory	218168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986064049 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.986064049
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.638967721
Short name	T95
Test name
Test status
Simulation time	414824941 ps
CPU time	2.67 seconds
Started	Sep 04 12:39:00 PM UTC 24
Finished	Sep 04 12:39:03 PM UTC 24
Peak memory	209120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638967721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.638967721
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.1479627801
Short name	T40
Test name
Test status
Simulation time	236833566 ps
CPU time	1.65 seconds
Started	Sep 04 12:39:00 PM UTC 24
Finished	Sep 04 12:39:02 PM UTC 24
Peak memory	208284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479627801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1479627801
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.1258180901
Short name	T433
Test name
Test status
Simulation time	71787172 ps
CPU time	0.84 seconds
Started	Sep 04 12:40:18 PM UTC 24
Finished	Sep 04 12:40:20 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258180901 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1258180901
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.877976284
Short name	T456
Test name
Test status
Simulation time	1262375825 ps
CPU time	6.21 seconds
Started	Sep 04 12:40:17 PM UTC 24
Finished	Sep 04 12:40:24 PM UTC 24
Peak memory	241664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877976284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.877976284
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2143514808
Short name	T436
Test name
Test status
Simulation time	301664603 ps
CPU time	1.26 seconds
Started	Sep 04 12:40:18 PM UTC 24
Finished	Sep 04 12:40:20 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143514808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2143514808
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.3249569113
Short name	T426
Test name
Test status
Simulation time	198493539 ps
CPU time	1 seconds
Started	Sep 04 12:40:17 PM UTC 24
Finished	Sep 04 12:40:19 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249569113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3249569113
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.2144772557
Short name	T443
Test name
Test status
Simulation time	866368401 ps
CPU time	4.4 seconds
Started	Sep 04 12:40:17 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144772557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2144772557
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.2970479434
Short name	T431
Test name
Test status
Simulation time	154072187 ps
CPU time	1.61 seconds
Started	Sep 04 12:40:17 PM UTC 24
Finished	Sep 04 12:40:19 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970479434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.2970479434
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.1331286107
Short name	T429
Test name
Test status
Simulation time	225663110 ps
CPU time	1.51 seconds
Started	Sep 04 12:40:17 PM UTC 24
Finished	Sep 04 12:40:19 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331286107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.1331286107
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.2945147478
Short name	T438
Test name
Test status
Simulation time	360739972 ps
CPU time	2.33 seconds
Started	Sep 04 12:40:18 PM UTC 24
Finished	Sep 04 12:40:21 PM UTC 24
Peak memory	209180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945147478 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2945147478
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.984797264
Short name	T435
Test name
Test status
Simulation time	152165568 ps
CPU time	2.23 seconds
Started	Sep 04 12:40:17 PM UTC 24
Finished	Sep 04 12:40:20 PM UTC 24
Peak memory	208936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984797264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.984797264
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.1013127620
Short name	T427
Test name
Test status
Simulation time	150359049 ps
CPU time	1.17 seconds
Started	Sep 04 12:40:17 PM UTC 24
Finished	Sep 04 12:40:19 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013127620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.1013127620
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.3827472658
Short name	T445
Test name
Test status
Simulation time	77746800 ps
CPU time	0.93 seconds
Started	Sep 04 12:40:20 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827472658 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3827472658
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.2508374913
Short name	T473
Test name
Test status
Simulation time	1268572931 ps
CPU time	6.22 seconds
Started	Sep 04 12:40:20 PM UTC 24
Finished	Sep 04 12:40:28 PM UTC 24
Peak memory	241932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508374913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2508374913
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1630174823
Short name	T448
Test name
Test status
Simulation time	302365034 ps
CPU time	1.24 seconds
Started	Sep 04 12:40:20 PM UTC 24
Finished	Sep 04 12:40:23 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630174823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1630174823
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.3698780825
Short name	T442
Test name
Test status
Simulation time	196189251 ps
CPU time	1.1 seconds
Started	Sep 04 12:40:19 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698780825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3698780825
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.2950173739
Short name	T468
Test name
Test status
Simulation time	1604828743 ps
CPU time	6.35 seconds
Started	Sep 04 12:40:19 PM UTC 24
Finished	Sep 04 12:40:27 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950173739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2950173739
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1772385836
Short name	T447
Test name
Test status
Simulation time	96614931 ps
CPU time	0.94 seconds
Started	Sep 04 12:40:20 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772385836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1772385836
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.3209748450
Short name	T441
Test name
Test status
Simulation time	109372694 ps
CPU time	1.2 seconds
Started	Sep 04 12:40:19 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209748450 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3209748450
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.998132963
Short name	T504
Test name
Test status
Simulation time	4733485388 ps
CPU time	15.9 seconds
Started	Sep 04 12:40:20 PM UTC 24
Finished	Sep 04 12:40:38 PM UTC 24
Peak memory	218104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998132963 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.998132963
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.4234908154
Short name	T450
Test name
Test status
Simulation time	351077441 ps
CPU time	2.2 seconds
Started	Sep 04 12:40:19 PM UTC 24
Finished	Sep 04 12:40:23 PM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234908154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.4234908154
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.2783411155
Short name	T440
Test name
Test status
Simulation time	159443375 ps
CPU time	1.1 seconds
Started	Sep 04 12:40:19 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783411155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2783411155
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.1936432286
Short name	T459
Test name
Test status
Simulation time	73909062 ps
CPU time	1.09 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:25 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936432286 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.1936432286
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.3438798694
Short name	T496
Test name
Test status
Simulation time	2448046648 ps
CPU time	9.54 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:34 PM UTC 24
Peak memory	242468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438798694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3438798694
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2760367428
Short name	T461
Test name
Test status
Simulation time	301775678 ps
CPU time	1.47 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:25 PM UTC 24
Peak memory	237628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760367428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2760367428
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.1111799627
Short name	T446
Test name
Test status
Simulation time	83324795 ps
CPU time	0.91 seconds
Started	Sep 04 12:40:20 PM UTC 24
Finished	Sep 04 12:40:22 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111799627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1111799627
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.1512479977
Short name	T470
Test name
Test status
Simulation time	962835790 ps
CPU time	4.75 seconds
Started	Sep 04 12:40:22 PM UTC 24
Finished	Sep 04 12:40:27 PM UTC 24
Peak memory	209196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512479977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1512479977
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.607988239
Short name	T454
Test name
Test status
Simulation time	159831306 ps
CPU time	1.2 seconds
Started	Sep 04 12:40:22 PM UTC 24
Finished	Sep 04 12:40:24 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607988239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.607988239
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.3009589734
Short name	T451
Test name
Test status
Simulation time	196371307 ps
CPU time	1.53 seconds
Started	Sep 04 12:40:20 PM UTC 24
Finished	Sep 04 12:40:23 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009589734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3009589734
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.2532532404
Short name	T465
Test name
Test status
Simulation time	440108275 ps
CPU time	2.47 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:26 PM UTC 24
Peak memory	208988 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532532404 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2532532404
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.2004775316
Short name	T458
Test name
Test status
Simulation time	118783652 ps
CPU time	1.66 seconds
Started	Sep 04 12:40:22 PM UTC 24
Finished	Sep 04 12:40:24 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004775316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2004775316
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.229233835
Short name	T457
Test name
Test status
Simulation time	216204589 ps
CPU time	1.52 seconds
Started	Sep 04 12:40:22 PM UTC 24
Finished	Sep 04 12:40:24 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229233835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.229233835
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.2886478552
Short name	T469
Test name
Test status
Simulation time	73827282 ps
CPU time	0.85 seconds
Started	Sep 04 12:40:24 PM UTC 24
Finished	Sep 04 12:40:27 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886478552 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2886478552
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.1569845975
Short name	T497
Test name
Test status
Simulation time	1971178642 ps
CPU time	8.03 seconds
Started	Sep 04 12:40:24 PM UTC 24
Finished	Sep 04 12:40:34 PM UTC 24
Peak memory	242340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569845975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1569845975
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.3693222585
Short name	T472
Test name
Test status
Simulation time	303626389 ps
CPU time	1.35 seconds
Started	Sep 04 12:40:24 PM UTC 24
Finished	Sep 04 12:40:27 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693222585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.3693222585
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.3726450311
Short name	T460
Test name
Test status
Simulation time	210777227 ps
CPU time	1.05 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:25 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726450311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3726450311
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.1753118864
Short name	T490
Test name
Test status
Simulation time	1688673156 ps
CPU time	6.66 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:31 PM UTC 24
Peak memory	209376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753118864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1753118864
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1140501385
Short name	T462
Test name
Test status
Simulation time	95747446 ps
CPU time	1.17 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:26 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140501385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1140501385
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.2231033753
Short name	T463
Test name
Test status
Simulation time	243611318 ps
CPU time	1.52 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:26 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231033753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2231033753
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.440412368
Short name	T513
Test name
Test status
Simulation time	4456699204 ps
CPU time	15.48 seconds
Started	Sep 04 12:40:24 PM UTC 24
Finished	Sep 04 12:40:42 PM UTC 24
Peak memory	209220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440412368 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.440412368
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.401349235
Short name	T467
Test name
Test status
Simulation time	288315986 ps
CPU time	1.95 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:26 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401349235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.401349235
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.616663285
Short name	T464
Test name
Test status
Simulation time	186202998 ps
CPU time	1.52 seconds
Started	Sep 04 12:40:23 PM UTC 24
Finished	Sep 04 12:40:26 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616663285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.616663285
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.2710932840
Short name	T478
Test name
Test status
Simulation time	58248365 ps
CPU time	0.9 seconds
Started	Sep 04 12:40:27 PM UTC 24
Finished	Sep 04 12:40:29 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710932840 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2710932840
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.2212254428
Short name	T502
Test name
Test status
Simulation time	1963876976 ps
CPU time	7.75 seconds
Started	Sep 04 12:40:26 PM UTC 24
Finished	Sep 04 12:40:35 PM UTC 24
Peak memory	241728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212254428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2212254428
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.662363511
Short name	T480
Test name
Test status
Simulation time	302084052 ps
CPU time	1.46 seconds
Started	Sep 04 12:40:27 PM UTC 24
Finished	Sep 04 12:40:30 PM UTC 24
Peak memory	237568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662363511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.662363511
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.2016436135
Short name	T471
Test name
Test status
Simulation time	230069812 ps
CPU time	1.07 seconds
Started	Sep 04 12:40:24 PM UTC 24
Finished	Sep 04 12:40:27 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016436135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2016436135
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.4227606659
Short name	T498
Test name
Test status
Simulation time	2104541046 ps
CPU time	8.02 seconds
Started	Sep 04 12:40:24 PM UTC 24
Finished	Sep 04 12:40:34 PM UTC 24
Peak memory	209196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227606659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4227606659
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.572015659
Short name	T475
Test name
Test status
Simulation time	99108263 ps
CPU time	1.08 seconds
Started	Sep 04 12:40:26 PM UTC 24
Finished	Sep 04 12:40:29 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572015659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.572015659
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.376188513
Short name	T474
Test name
Test status
Simulation time	244400401 ps
CPU time	1.59 seconds
Started	Sep 04 12:40:24 PM UTC 24
Finished	Sep 04 12:40:28 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376188513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.376188513
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.204388690
Short name	T538
Test name
Test status
Simulation time	11514872349 ps
CPU time	36.46 seconds
Started	Sep 04 12:40:27 PM UTC 24
Finished	Sep 04 12:41:05 PM UTC 24
Peak memory	209100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204388690 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.204388690
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.1712218008
Short name	T481
Test name
Test status
Simulation time	339741145 ps
CPU time	2.36 seconds
Started	Sep 04 12:40:26 PM UTC 24
Finished	Sep 04 12:40:30 PM UTC 24
Peak memory	208996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712218008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1712218008
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.1715139166
Short name	T476
Test name
Test status
Simulation time	141275758 ps
CPU time	1.22 seconds
Started	Sep 04 12:40:26 PM UTC 24
Finished	Sep 04 12:40:29 PM UTC 24
Peak memory	208236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715139166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1715139166
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.3598810279
Short name	T483
Test name
Test status
Simulation time	69400150 ps
CPU time	0.86 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:30 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598810279 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3598810279
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.2958811628
Short name	T501
Test name
Test status
Simulation time	1262670170 ps
CPU time	5.78 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:35 PM UTC 24
Peak memory	241268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958811628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2958811628
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1896975022
Short name	T488
Test name
Test status
Simulation time	301582602 ps
CPU time	1.6 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:31 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896975022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1896975022
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.3581365787
Short name	T479
Test name
Test status
Simulation time	157782578 ps
CPU time	1.09 seconds
Started	Sep 04 12:40:27 PM UTC 24
Finished	Sep 04 12:40:30 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581365787 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3581365787
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.3603424538
Short name	T499
Test name
Test status
Simulation time	1278500176 ps
CPU time	5.65 seconds
Started	Sep 04 12:40:27 PM UTC 24
Finished	Sep 04 12:40:34 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603424538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3603424538
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3776268488
Short name	T487
Test name
Test status
Simulation time	167498726 ps
CPU time	1.33 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:31 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776268488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3776268488
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.1729994537
Short name	T482
Test name
Test status
Simulation time	244868622 ps
CPU time	1.59 seconds
Started	Sep 04 12:40:27 PM UTC 24
Finished	Sep 04 12:40:30 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729994537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1729994537
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.4055985846
Short name	T512
Test name
Test status
Simulation time	2516258328 ps
CPU time	11.45 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:41 PM UTC 24
Peak memory	218232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055985846 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.4055985846
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.1563316927
Short name	T493
Test name
Test status
Simulation time	468450551 ps
CPU time	2.97 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:33 PM UTC 24
Peak memory	217828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563316927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1563316927
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.1516765580
Short name	T486
Test name
Test status
Simulation time	161565817 ps
CPU time	1.21 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:31 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516765580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1516765580
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.2854656584
Short name	T515
Test name
Test status
Simulation time	75783184 ps
CPU time	0.83 seconds
Started	Sep 04 12:40:31 PM UTC 24
Finished	Sep 04 12:40:43 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854656584 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2854656584
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.2796854464
Short name	T540
Test name
Test status
Simulation time	2458809561 ps
CPU time	8.54 seconds
Started	Sep 04 12:40:31 PM UTC 24
Finished	Sep 04 12:41:09 PM UTC 24
Peak memory	241744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796854464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.2796854464
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2823070915
Short name	T534
Test name
Test status
Simulation time	301276988 ps
CPU time	1.67 seconds
Started	Sep 04 12:40:31 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	237636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823070915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2823070915
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.1038993496
Short name	T485
Test name
Test status
Simulation time	158409619 ps
CPU time	0.97 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:31 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038993496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1038993496
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.738567443
Short name	T503
Test name
Test status
Simulation time	1450284519 ps
CPU time	5.27 seconds
Started	Sep 04 12:40:29 PM UTC 24
Finished	Sep 04 12:40:36 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738567443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.738567443
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3651588697
Short name	T494
Test name
Test status
Simulation time	114325659 ps
CPU time	1.16 seconds
Started	Sep 04 12:40:29 PM UTC 24
Finished	Sep 04 12:40:33 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651588697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3651588697
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.3260824986
Short name	T489
Test name
Test status
Simulation time	196441536 ps
CPU time	1.59 seconds
Started	Sep 04 12:40:28 PM UTC 24
Finished	Sep 04 12:40:31 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260824986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3260824986
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.159392913
Short name	T542
Test name
Test status
Simulation time	5227363237 ps
CPU time	24.77 seconds
Started	Sep 04 12:40:31 PM UTC 24
Finished	Sep 04 12:41:25 PM UTC 24
Peak memory	218168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159392913 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.159392913
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.4215585071
Short name	T500
Test name
Test status
Simulation time	523367418 ps
CPU time	2.69 seconds
Started	Sep 04 12:40:29 PM UTC 24
Finished	Sep 04 12:40:34 PM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215585071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.4215585071
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.794107499
Short name	T491
Test name
Test status
Simulation time	225608717 ps
CPU time	1.45 seconds
Started	Sep 04 12:40:29 PM UTC 24
Finished	Sep 04 12:40:32 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794107499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.794107499
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.164517027
Short name	T529
Test name
Test status
Simulation time	104192754 ps
CPU time	0.9 seconds
Started	Sep 04 12:40:32 PM UTC 24
Finished	Sep 04 12:41:01 PM UTC 24
Peak memory	208108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164517027 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.164517027
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.4292852227
Short name	T541
Test name
Test status
Simulation time	2432712910 ps
CPU time	9.88 seconds
Started	Sep 04 12:40:32 PM UTC 24
Finished	Sep 04 12:41:10 PM UTC 24
Peak memory	241788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292852227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.4292852227
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2489428102
Short name	T531
Test name
Test status
Simulation time	301748761 ps
CPU time	1.28 seconds
Started	Sep 04 12:40:32 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	237448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489428102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2489428102
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.3753788032
Short name	T516
Test name
Test status
Simulation time	138607224 ps
CPU time	0.87 seconds
Started	Sep 04 12:40:31 PM UTC 24
Finished	Sep 04 12:40:43 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753788032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3753788032
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.3442397914
Short name	T539
Test name
Test status
Simulation time	1688827817 ps
CPU time	7.12 seconds
Started	Sep 04 12:40:32 PM UTC 24
Finished	Sep 04 12:41:07 PM UTC 24
Peak memory	209192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442397914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3442397914
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2134803340
Short name	T530
Test name
Test status
Simulation time	112606246 ps
CPU time	1.15 seconds
Started	Sep 04 12:40:32 PM UTC 24
Finished	Sep 04 12:41:01 PM UTC 24
Peak memory	208368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134803340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2134803340
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.1082872473
Short name	T532
Test name
Test status
Simulation time	227908753 ps
CPU time	1.57 seconds
Started	Sep 04 12:40:31 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	208108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082872473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1082872473
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3146209096
Short name	T535
Test name
Test status
Simulation time	298326829 ps
CPU time	1.51 seconds
Started	Sep 04 12:40:32 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146209096 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3146209096
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.2481144337
Short name	T533
Test name
Test status
Simulation time	315542392 ps
CPU time	2.49 seconds
Started	Sep 04 12:40:32 PM UTC 24
Finished	Sep 04 12:41:03 PM UTC 24
Peak memory	208992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481144337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2481144337
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.1751438594
Short name	T536
Test name
Test status
Simulation time	258525691 ps
CPU time	1.68 seconds
Started	Sep 04 12:40:32 PM UTC 24
Finished	Sep 04 12:41:02 PM UTC 24
Peak memory	208332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751438594 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1751438594
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.197566325
Short name	T506
Test name
Test status
Simulation time	64913357 ps
CPU time	0.76 seconds
Started	Sep 04 12:40:36 PM UTC 24
Finished	Sep 04 12:40:38 PM UTC 24
Peak memory	208116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197566325 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.197566325
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.3990479887
Short name	T524
Test name
Test status
Simulation time	1269041464 ps
CPU time	5.81 seconds
Started	Sep 04 12:40:35 PM UTC 24
Finished	Sep 04 12:40:48 PM UTC 24
Peak memory	242096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990479887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3990479887
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.77757847
Short name	T510
Test name
Test status
Simulation time	301190619 ps
CPU time	1.17 seconds
Started	Sep 04 12:40:36 PM UTC 24
Finished	Sep 04 12:40:39 PM UTC 24
Peak memory	237564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77757847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.77757847
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.1417088141
Short name	T505
Test name
Test status
Simulation time	115734629 ps
CPU time	0.92 seconds
Started	Sep 04 12:40:33 PM UTC 24
Finished	Sep 04 12:40:38 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417088141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1417088141
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.2780886535
Short name	T518
Test name
Test status
Simulation time	1383370401 ps
CPU time	5.57 seconds
Started	Sep 04 12:40:33 PM UTC 24
Finished	Sep 04 12:40:43 PM UTC 24
Peak memory	209256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780886535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.2780886535
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1707192479
Short name	T517
Test name
Test status
Simulation time	168576348 ps
CPU time	1.21 seconds
Started	Sep 04 12:40:34 PM UTC 24
Finished	Sep 04 12:40:43 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707192479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1707192479
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.4013245193
Short name	T509
Test name
Test status
Simulation time	120279135 ps
CPU time	1.22 seconds
Started	Sep 04 12:40:33 PM UTC 24
Finished	Sep 04 12:40:39 PM UTC 24
Peak memory	208276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013245193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.4013245193
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.3728616834
Short name	T526
Test name
Test status
Simulation time	4150433691 ps
CPU time	17.68 seconds
Started	Sep 04 12:40:36 PM UTC 24
Finished	Sep 04 12:40:56 PM UTC 24
Peak memory	218168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728616834 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3728616834
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.1166787490
Short name	T521
Test name
Test status
Simulation time	147274876 ps
CPU time	1.86 seconds
Started	Sep 04 12:40:34 PM UTC 24
Finished	Sep 04 12:40:44 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166787490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1166787490
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.3687366180
Short name	T507
Test name
Test status
Simulation time	118447478 ps
CPU time	1.07 seconds
Started	Sep 04 12:40:33 PM UTC 24
Finished	Sep 04 12:40:39 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687366180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3687366180
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.2023872754
Short name	T519
Test name
Test status
Simulation time	58701308 ps
CPU time	0.78 seconds
Started	Sep 04 12:40:40 PM UTC 24
Finished	Sep 04 12:40:43 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023872754 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2023872754
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.2435590830
Short name	T537
Test name
Test status
Simulation time	1272322985 ps
CPU time	5.43 seconds
Started	Sep 04 12:40:39 PM UTC 24
Finished	Sep 04 12:41:03 PM UTC 24
Peak memory	241668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435590830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2435590830
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.514355389
Short name	T528
Test name
Test status
Simulation time	304858803 ps
CPU time	1.27 seconds
Started	Sep 04 12:40:39 PM UTC 24
Finished	Sep 04 12:40:58 PM UTC 24
Peak memory	237452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514355389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.514355389
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.2526738487
Short name	T508
Test name
Test status
Simulation time	131616262 ps
CPU time	0.76 seconds
Started	Sep 04 12:40:37 PM UTC 24
Finished	Sep 04 12:40:39 PM UTC 24
Peak memory	208176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526738487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2526738487
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.648616587
Short name	T522
Test name
Test status
Simulation time	1650590605 ps
CPU time	5.85 seconds
Started	Sep 04 12:40:37 PM UTC 24
Finished	Sep 04 12:40:44 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648616587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.648616587
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1661346631
Short name	T527
Test name
Test status
Simulation time	160108677 ps
CPU time	1.2 seconds
Started	Sep 04 12:40:39 PM UTC 24
Finished	Sep 04 12:40:58 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661346631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1661346631
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.951175455
Short name	T511
Test name
Test status
Simulation time	257822307 ps
CPU time	1.49 seconds
Started	Sep 04 12:40:37 PM UTC 24
Finished	Sep 04 12:40:39 PM UTC 24
Peak memory	208328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951175455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.951175455
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.3539705019
Short name	T543
Test name
Test status
Simulation time	12711475242 ps
CPU time	44.62 seconds
Started	Sep 04 12:40:40 PM UTC 24
Finished	Sep 04 12:41:28 PM UTC 24
Peak memory	209376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539705019 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3539705019
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.134996788
Short name	T525
Test name
Test status
Simulation time	145327657 ps
CPU time	1.71 seconds
Started	Sep 04 12:40:39 PM UTC 24
Finished	Sep 04 12:40:49 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134996788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.134996788
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.1622027572
Short name	T520
Test name
Test status
Simulation time	142326277 ps
CPU time	1.16 seconds
Started	Sep 04 12:40:38 PM UTC 24
Finished	Sep 04 12:40:43 PM UTC 24
Peak memory	208304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622027572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1622027572
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.1494982522
Short name	T135
Test name
Test status
Simulation time	104744130 ps
CPU time	1 seconds
Started	Sep 04 12:39:02 PM UTC 24
Finished	Sep 04 12:39:04 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494982522 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1494982522
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2841428517
Short name	T136
Test name
Test status
Simulation time	301828107 ps
CPU time	1.5 seconds
Started	Sep 04 12:39:02 PM UTC 24
Finished	Sep 04 12:39:05 PM UTC 24
Peak memory	237448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841428517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2841428517
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.1471192680
Short name	T16
Test name
Test status
Simulation time	174037778 ps
CPU time	1.38 seconds
Started	Sep 04 12:39:01 PM UTC 24
Finished	Sep 04 12:39:03 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471192680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1471192680
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1426371240
Short name	T108
Test name
Test status
Simulation time	979243762 ps
CPU time	4.94 seconds
Started	Sep 04 12:39:01 PM UTC 24
Finished	Sep 04 12:39:07 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426371240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1426371240
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3843987901
Short name	T134
Test name
Test status
Simulation time	151114738 ps
CPU time	1.64 seconds
Started	Sep 04 12:39:01 PM UTC 24
Finished	Sep 04 12:39:04 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843987901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3843987901
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3225889992
Short name	T133
Test name
Test status
Simulation time	117234482 ps
CPU time	1.7 seconds
Started	Sep 04 12:39:01 PM UTC 24
Finished	Sep 04 12:39:04 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225889992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3225889992
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.2170296000
Short name	T346
Test name
Test status
Simulation time	15956126230 ps
CPU time	58.38 seconds
Started	Sep 04 12:39:02 PM UTC 24
Finished	Sep 04 12:40:03 PM UTC 24
Peak memory	218168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170296000 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2170296000
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1729379911
Short name	T96
Test name
Test status
Simulation time	113699970 ps
CPU time	1.88 seconds
Started	Sep 04 12:39:01 PM UTC 24
Finished	Sep 04 12:39:04 PM UTC 24
Peak memory	208264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729379911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1729379911
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.4129418662
Short name	T148
Test name
Test status
Simulation time	67405899 ps
CPU time	0.9 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:07 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129418662 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.4129418662
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.1336548859
Short name	T28
Test name
Test status
Simulation time	1971669841 ps
CPU time	8.19 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:14 PM UTC 24
Peak memory	241708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336548859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1336548859
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1270058334
Short name	T150
Test name
Test status
Simulation time	302868845 ps
CPU time	1.52 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:07 PM UTC 24
Peak memory	237624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270058334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.1270058334
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.422567289
Short name	T17
Test name
Test status
Simulation time	127579886 ps
CPU time	1.22 seconds
Started	Sep 04 12:39:04 PM UTC 24
Finished	Sep 04 12:39:06 PM UTC 24
Peak memory	208184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422567289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.422567289
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2729303797
Short name	T149
Test name
Test status
Simulation time	108372546 ps
CPU time	1.1 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:07 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729303797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2729303797
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.1520935218
Short name	T101
Test name
Test status
Simulation time	118123384 ps
CPU time	1.54 seconds
Started	Sep 04 12:39:03 PM UTC 24
Finished	Sep 04 12:39:06 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520935218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.1520935218
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1242689823
Short name	T132
Test name
Test status
Simulation time	9206445753 ps
CPU time	32.41 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:39 PM UTC 24
Peak memory	220220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242689823 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1242689823
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.1415281737
Short name	T98
Test name
Test status
Simulation time	122780715 ps
CPU time	1.82 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:08 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415281737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1415281737
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.1406438892
Short name	T97
Test name
Test status
Simulation time	156242909 ps
CPU time	1.83 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:07 PM UTC 24
Peak memory	208388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406438892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.1406438892
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.407579308
Short name	T152
Test name
Test status
Simulation time	89947129 ps
CPU time	1.04 seconds
Started	Sep 04 12:39:07 PM UTC 24
Finished	Sep 04 12:39:09 PM UTC 24
Peak memory	208112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407579308 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.407579308
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.3493378240
Short name	T29
Test name
Test status
Simulation time	2433677889 ps
CPU time	9.41 seconds
Started	Sep 04 12:39:06 PM UTC 24
Finished	Sep 04 12:39:17 PM UTC 24
Peak memory	242244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493378240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3493378240
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2008639461
Short name	T153
Test name
Test status
Simulation time	302623326 ps
CPU time	1.29 seconds
Started	Sep 04 12:39:07 PM UTC 24
Finished	Sep 04 12:39:10 PM UTC 24
Peak memory	237624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008639461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2008639461
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.2060727566
Short name	T18
Test name
Test status
Simulation time	94945991 ps
CPU time	0.89 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:07 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060727566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2060727566
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3819983543
Short name	T111
Test name
Test status
Simulation time	845157770 ps
CPU time	5.01 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:11 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819983543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3819983543
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.856543347
Short name	T151
Test name
Test status
Simulation time	145366318 ps
CPU time	1.24 seconds
Started	Sep 04 12:39:06 PM UTC 24
Finished	Sep 04 12:39:08 PM UTC 24
Peak memory	208368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856543347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.856543347
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.751799644
Short name	T103
Test name
Test status
Simulation time	111899535 ps
CPU time	1.43 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:07 PM UTC 24
Peak memory	208292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751799644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.751799644
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.1927659415
Short name	T114
Test name
Test status
Simulation time	4035189714 ps
CPU time	16.07 seconds
Started	Sep 04 12:39:07 PM UTC 24
Finished	Sep 04 12:39:24 PM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927659415 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1927659415
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3949256513
Short name	T100
Test name
Test status
Simulation time	113289229 ps
CPU time	1.46 seconds
Started	Sep 04 12:39:06 PM UTC 24
Finished	Sep 04 12:39:09 PM UTC 24
Peak memory	208268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949256513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3949256513
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.1202290574
Short name	T99
Test name
Test status
Simulation time	141901365 ps
CPU time	1.67 seconds
Started	Sep 04 12:39:05 PM UTC 24
Finished	Sep 04 12:39:08 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202290574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1202290574
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.3777452457
Short name	T75
Test name
Test status
Simulation time	84900097 ps
CPU time	1.12 seconds
Started	Sep 04 12:39:10 PM UTC 24
Finished	Sep 04 12:39:12 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777452457 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3777452457
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1798889088
Short name	T43
Test name
Test status
Simulation time	1984054981 ps
CPU time	7.53 seconds
Started	Sep 04 12:39:09 PM UTC 24
Finished	Sep 04 12:39:17 PM UTC 24
Peak memory	242052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798889088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1798889088
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3479068879
Short name	T156
Test name
Test status
Simulation time	301941197 ps
CPU time	1.4 seconds
Started	Sep 04 12:39:09 PM UTC 24
Finished	Sep 04 12:39:11 PM UTC 24
Peak memory	237624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479068879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3479068879
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.3082918969
Short name	T19
Test name
Test status
Simulation time	160028640 ps
CPU time	1.28 seconds
Started	Sep 04 12:39:08 PM UTC 24
Finished	Sep 04 12:39:11 PM UTC 24
Peak memory	208180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082918969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3082918969
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.4271872614
Short name	T118
Test name
Test status
Simulation time	1557658528 ps
CPU time	6.8 seconds
Started	Sep 04 12:39:08 PM UTC 24
Finished	Sep 04 12:39:16 PM UTC 24
Peak memory	209184 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271872614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4271872614
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1065159634
Short name	T155
Test name
Test status
Simulation time	138355536 ps
CPU time	1.25 seconds
Started	Sep 04 12:39:09 PM UTC 24
Finished	Sep 04 12:39:11 PM UTC 24
Peak memory	208372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065159634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1065159634
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.4287091128
Short name	T138
Test name
Test status
Simulation time	254319907 ps
CPU time	2.18 seconds
Started	Sep 04 12:39:07 PM UTC 24
Finished	Sep 04 12:39:11 PM UTC 24
Peak memory	209248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287091128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.4287091128
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.3660932232
Short name	T116
Test name
Test status
Simulation time	4801316761 ps
CPU time	22.39 seconds
Started	Sep 04 12:39:09 PM UTC 24
Finished	Sep 04 12:39:32 PM UTC 24
Peak memory	209312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660932232 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3660932232
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.1926943972
Short name	T76
Test name
Test status
Simulation time	456456088 ps
CPU time	2.81 seconds
Started	Sep 04 12:39:09 PM UTC 24
Finished	Sep 04 12:39:12 PM UTC 24
Peak memory	208932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926943972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1926943972
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3050649682
Short name	T154
Test name
Test status
Simulation time	63449179 ps
CPU time	0.87 seconds
Started	Sep 04 12:39:09 PM UTC 24
Finished	Sep 04 12:39:10 PM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050649682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3050649682
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.840493922
Short name	T82
Test name
Test status
Simulation time	67744943 ps
CPU time	1.03 seconds
Started	Sep 04 12:39:12 PM UTC 24
Finished	Sep 04 12:39:14 PM UTC 24
Peak memory	208112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840493922 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.840493922
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.2868997755
Short name	T30
Test name
Test status
Simulation time	2457599510 ps
CPU time	10.07 seconds
Started	Sep 04 12:39:12 PM UTC 24
Finished	Sep 04 12:39:23 PM UTC 24
Peak memory	242440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868997755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2868997755
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1898958320
Short name	T158
Test name
Test status
Simulation time	302273307 ps
CPU time	1.42 seconds
Started	Sep 04 12:39:12 PM UTC 24
Finished	Sep 04 12:39:15 PM UTC 24
Peak memory	237624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898958320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1898958320
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1411579590
Short name	T20
Test name
Test status
Simulation time	130943377 ps
CPU time	0.89 seconds
Started	Sep 04 12:39:10 PM UTC 24
Finished	Sep 04 12:39:12 PM UTC 24
Peak memory	208136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411579590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1411579590
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1422362018
Short name	T113
Test name
Test status
Simulation time	1829047796 ps
CPU time	7.3 seconds
Started	Sep 04 12:39:11 PM UTC 24
Finished	Sep 04 12:39:19 PM UTC 24
Peak memory	209188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422362018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1422362018
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.370791162
Short name	T80
Test name
Test status
Simulation time	108816653 ps
CPU time	1.43 seconds
Started	Sep 04 12:39:11 PM UTC 24
Finished	Sep 04 12:39:14 PM UTC 24
Peak memory	208368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370791162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.370791162
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.1157082317
Short name	T77
Test name
Test status
Simulation time	120064680 ps
CPU time	1.69 seconds
Started	Sep 04 12:39:10 PM UTC 24
Finished	Sep 04 12:39:13 PM UTC 24
Peak memory	208236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157082317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.1157082317
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1191975396
Short name	T277
Test name
Test status
Simulation time	6268659030 ps
CPU time	33.77 seconds
Started	Sep 04 12:39:12 PM UTC 24
Finished	Sep 04 12:39:48 PM UTC 24
Peak memory	209312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191975396 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1191975396
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.3943104840
Short name	T81
Test name
Test status
Simulation time	287616185 ps
CPU time	2.02 seconds
Started	Sep 04 12:39:11 PM UTC 24
Finished	Sep 04 12:39:14 PM UTC 24
Peak memory	217788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943104840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.3943104840
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.3589179371
Short name	T79
Test name
Test status
Simulation time	178527431 ps
CPU time	1.23 seconds
Started	Sep 04 12:39:11 PM UTC 24
Finished	Sep 04 12:39:13 PM UTC 24
Peak memory	208300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589179371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3589179371
Directory	/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest