Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7974

1

T3

8

T5

36

T11

15

auto[1]

10898

1

T1

4

T3

1

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5895	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6313	1			T1	2		T2	1		T3	1
reset_info_cp[2]	2900	1			T1	1		T4	1		T5	7
reset_info_cp[4]	3813	1			T1	1		T4	1		T5	12
reset_info_cp[8]	106	1			T1	1		T38	1		T40	1
reset_info_cp[16]	117	1			T5	2		T11	2		T22	1
reset_info_cp[32]	110	1			T5	1		T12	1		T25	1
reset_info_cp[64]	111	1			T5	1		T9	1		T11	1
reset_info_cp[128]	127	1			T11	1		T38	1		T41	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3055	1			T5	13		T11	15		T22	11
reset_info_cp[1]	auto[1]	2638	1			T1	1		T4	1		T5	7
reset_info_cp[2]	auto[0]	905	1			T5	4		T22	5		T38	12
reset_info_cp[2]	auto[1]	1995	1			T1	1		T4	1		T5	3
reset_info_cp[4]	auto[0]	1340	1			T5	8		T22	10		T38	17
reset_info_cp[4]	auto[1]	2473	1			T1	1		T4	1		T5	4
reset_info_cp[8]	auto[0]	41	1			T41	1		T82	1		T97	2
reset_info_cp[8]	auto[1]	65	1			T1	1		T38	1		T40	1
reset_info_cp[16]	auto[0]	49	1			T5	1		T80	1		T49	1
reset_info_cp[16]	auto[1]	68	1			T5	1		T11	2		T22	1
reset_info_cp[32]	auto[0]	45	1			T5	1		T12	1		T35	1
reset_info_cp[32]	auto[1]	65	1			T25	1		T38	1		T41	1
reset_info_cp[64]	auto[0]	43	1			T12	1		T38	3		T82	1
reset_info_cp[64]	auto[1]	68	1			T5	1		T9	1		T11	1
reset_info_cp[128]	auto[0]	55	1			T80	1		T132	1		T100	1
reset_info_cp[128]	auto[1]	72	1			T11	1		T38	1		T41	1