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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.46 99.40 99.31 100.00 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html

T541 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.392968358 Sep 09 08:58:44 PM UTC 24 Sep 09 08:58:58 PM UTC 24 2858215714 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.2346592057 Sep 09 08:58:36 PM UTC 24 Sep 09 08:59:05 PM UTC 24 5632955978 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.2947344207 Sep 09 08:58:41 PM UTC 24 Sep 09 08:59:07 PM UTC 24 5669366337 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.1429509299 Sep 09 08:58:33 PM UTC 24 Sep 09 08:59:09 PM UTC 24 5633251011 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1827289979 Sep 09 08:58:48 PM UTC 24 Sep 09 08:59:21 PM UTC 24 8409349371 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.737080079 Sep 09 08:58:49 PM UTC 24 Sep 09 08:58:51 PM UTC 24 91605987 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3429820741 Sep 09 08:58:49 PM UTC 24 Sep 09 08:58:52 PM UTC 24 68707611 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3116988438 Sep 09 08:58:49 PM UTC 24 Sep 09 08:58:52 PM UTC 24 258193388 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2175682637 Sep 09 08:58:51 PM UTC 24 Sep 09 08:58:53 PM UTC 24 62416001 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.2539538009 Sep 09 08:58:48 PM UTC 24 Sep 09 08:58:53 PM UTC 24 510199018 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2768860390 Sep 09 08:58:51 PM UTC 24 Sep 09 08:58:53 PM UTC 24 132198678 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4079308506 Sep 09 08:58:51 PM UTC 24 Sep 09 08:58:53 PM UTC 24 126997965 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3213723204 Sep 09 08:58:49 PM UTC 24 Sep 09 08:58:53 PM UTC 24 435117747 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1391674400 Sep 09 08:58:51 PM UTC 24 Sep 09 08:58:54 PM UTC 24 193576282 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2329151850 Sep 09 08:58:51 PM UTC 24 Sep 09 08:58:54 PM UTC 24 231906436 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3387892785 Sep 09 08:58:52 PM UTC 24 Sep 09 08:58:55 PM UTC 24 82648035 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.612985553 Sep 09 08:58:51 PM UTC 24 Sep 09 08:58:55 PM UTC 24 498275543 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1151158769 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:12 PM UTC 24 796751095 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1334992779 Sep 09 08:58:52 PM UTC 24 Sep 09 08:58:55 PM UTC 24 215032132 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2226782839 Sep 09 08:58:52 PM UTC 24 Sep 09 08:58:55 PM UTC 24 204822125 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1401859467 Sep 09 08:58:49 PM UTC 24 Sep 09 08:58:56 PM UTC 24 812955410 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3159067099 Sep 09 08:58:52 PM UTC 24 Sep 09 08:58:56 PM UTC 24 158200426 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1881411197 Sep 09 08:58:54 PM UTC 24 Sep 09 08:58:56 PM UTC 24 142374010 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.2631359662 Sep 09 08:58:54 PM UTC 24 Sep 09 08:58:56 PM UTC 24 63239857 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2551543751 Sep 09 08:58:54 PM UTC 24 Sep 09 08:58:56 PM UTC 24 72539298 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1067850845 Sep 09 08:58:54 PM UTC 24 Sep 09 08:58:57 PM UTC 24 198110851 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.574466751 Sep 09 08:58:54 PM UTC 24 Sep 09 08:58:57 PM UTC 24 204564539 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3840236107 Sep 09 08:58:55 PM UTC 24 Sep 09 08:58:58 PM UTC 24 62911268 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2320940131 Sep 09 08:58:54 PM UTC 24 Sep 09 08:58:58 PM UTC 24 442741759 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.582064928 Sep 09 08:58:55 PM UTC 24 Sep 09 08:58:58 PM UTC 24 98245842 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.1602105193 Sep 09 08:58:54 PM UTC 24 Sep 09 08:58:58 PM UTC 24 160707669 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.235196203 Sep 09 08:58:54 PM UTC 24 Sep 09 08:58:58 PM UTC 24 271070249 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.256711060 Sep 09 08:58:52 PM UTC 24 Sep 09 08:58:59 PM UTC 24 491075079 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.277709453 Sep 09 08:58:55 PM UTC 24 Sep 09 08:58:59 PM UTC 24 462791968 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1163912532 Sep 09 08:58:57 PM UTC 24 Sep 09 08:59:00 PM UTC 24 119991627 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.4083394681 Sep 09 08:58:57 PM UTC 24 Sep 09 08:59:00 PM UTC 24 64979840 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.245958282 Sep 09 08:58:57 PM UTC 24 Sep 09 08:59:00 PM UTC 24 88274197 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.641726522 Sep 09 08:58:57 PM UTC 24 Sep 09 08:59:00 PM UTC 24 180069383 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.590607715 Sep 09 08:58:57 PM UTC 24 Sep 09 08:59:01 PM UTC 24 267863194 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2812975741 Sep 09 08:58:58 PM UTC 24 Sep 09 08:59:01 PM UTC 24 357112739 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1360432619 Sep 09 08:58:57 PM UTC 24 Sep 09 08:59:02 PM UTC 24 470203467 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.4134809272 Sep 09 08:58:59 PM UTC 24 Sep 09 08:59:02 PM UTC 24 83938575 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1258748017 Sep 09 08:58:59 PM UTC 24 Sep 09 08:59:02 PM UTC 24 157068711 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.469522294 Sep 09 08:58:59 PM UTC 24 Sep 09 08:59:02 PM UTC 24 82788092 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.926390658 Sep 09 08:58:59 PM UTC 24 Sep 09 08:59:02 PM UTC 24 111906048 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3941495745 Sep 09 08:58:59 PM UTC 24 Sep 09 08:59:02 PM UTC 24 119277837 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2129616299 Sep 09 08:58:57 PM UTC 24 Sep 09 08:59:02 PM UTC 24 521290742 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1248044234 Sep 09 08:58:58 PM UTC 24 Sep 09 08:59:02 PM UTC 24 278784088 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4158882976 Sep 09 08:58:59 PM UTC 24 Sep 09 08:59:02 PM UTC 24 441274636 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.467713249 Sep 09 08:58:56 PM UTC 24 Sep 09 08:59:03 PM UTC 24 491401962 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.855748504 Sep 09 08:59:01 PM UTC 24 Sep 09 08:59:04 PM UTC 24 92908266 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1162519044 Sep 09 08:59:01 PM UTC 24 Sep 09 08:59:04 PM UTC 24 170356390 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3030635175 Sep 09 08:59:01 PM UTC 24 Sep 09 08:59:04 PM UTC 24 195197420 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1598253666 Sep 09 08:58:59 PM UTC 24 Sep 09 08:59:04 PM UTC 24 227153020 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.650611107 Sep 09 08:59:01 PM UTC 24 Sep 09 08:59:05 PM UTC 24 134814182 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.781428674 Sep 09 08:59:01 PM UTC 24 Sep 09 08:59:05 PM UTC 24 528860400 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3757097825 Sep 09 08:59:01 PM UTC 24 Sep 09 08:59:05 PM UTC 24 156872799 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2373899688 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:10 PM UTC 24 94024974 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1706915984 Sep 09 08:59:03 PM UTC 24 Sep 09 08:59:05 PM UTC 24 64398401 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1366910460 Sep 09 08:59:03 PM UTC 24 Sep 09 08:59:06 PM UTC 24 175107946 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.1271174276 Sep 09 08:59:03 PM UTC 24 Sep 09 08:59:06 PM UTC 24 71452911 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3723994571 Sep 09 08:59:03 PM UTC 24 Sep 09 08:59:06 PM UTC 24 157914972 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3925995587 Sep 09 08:59:03 PM UTC 24 Sep 09 08:59:06 PM UTC 24 412748647 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2091715611 Sep 09 08:59:03 PM UTC 24 Sep 09 08:59:07 PM UTC 24 211163282 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.1106040428 Sep 09 08:59:05 PM UTC 24 Sep 09 08:59:07 PM UTC 24 63775441 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2652836927 Sep 09 08:59:05 PM UTC 24 Sep 09 08:59:07 PM UTC 24 151032224 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.1945749131 Sep 09 08:59:03 PM UTC 24 Sep 09 08:59:08 PM UTC 24 161112978 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.929180571 Sep 09 08:59:03 PM UTC 24 Sep 09 08:59:08 PM UTC 24 926116911 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2906360409 Sep 09 08:59:05 PM UTC 24 Sep 09 08:59:08 PM UTC 24 118747919 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2856339625 Sep 09 08:59:05 PM UTC 24 Sep 09 08:59:08 PM UTC 24 161615995 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3087375407 Sep 09 08:59:05 PM UTC 24 Sep 09 08:59:09 PM UTC 24 889279961 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3028612222 Sep 09 08:59:05 PM UTC 24 Sep 09 08:59:10 PM UTC 24 231667203 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.715551658 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:10 PM UTC 24 54948244 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3770226717 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:10 PM UTC 24 131490237 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3115318108 Sep 09 08:59:05 PM UTC 24 Sep 09 08:59:10 PM UTC 24 986531041 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.4012636033 Sep 09 08:59:05 PM UTC 24 Sep 09 08:59:10 PM UTC 24 531817260 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2938505677 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:10 PM UTC 24 95498124 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2031981500 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:10 PM UTC 24 133076038 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3848791458 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:10 PM UTC 24 190581350 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1101517030 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:10 PM UTC 24 142698760 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.4022197775 Sep 09 08:59:07 PM UTC 24 Sep 09 08:59:10 PM UTC 24 167820195 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1294685566 Sep 09 08:59:09 PM UTC 24 Sep 09 08:59:12 PM UTC 24 80860206 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.675530876 Sep 09 08:59:09 PM UTC 24 Sep 09 08:59:12 PM UTC 24 91950948 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2316491697 Sep 09 08:59:09 PM UTC 24 Sep 09 08:59:12 PM UTC 24 57785329 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3713997441 Sep 09 08:59:09 PM UTC 24 Sep 09 08:59:12 PM UTC 24 172617000 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.557179121 Sep 09 08:59:10 PM UTC 24 Sep 09 08:59:12 PM UTC 24 114447210 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2345210964 Sep 09 08:59:09 PM UTC 24 Sep 09 08:59:12 PM UTC 24 81996297 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2576755349 Sep 09 08:59:09 PM UTC 24 Sep 09 08:59:13 PM UTC 24 490956082 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1166897370 Sep 09 08:59:09 PM UTC 24 Sep 09 08:59:14 PM UTC 24 809987110 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2329336589 Sep 09 08:59:09 PM UTC 24 Sep 09 08:59:14 PM UTC 24 425620237 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.2934745024 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:15 PM UTC 24 61577867 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2920919203 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:15 PM UTC 24 137620508 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3175913137 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:15 PM UTC 24 90746660 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.3761657512 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:15 PM UTC 24 56202306 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3134526662 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:16 PM UTC 24 80569196 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.210645743 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:16 PM UTC 24 114206830 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3288177603 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:16 PM UTC 24 146245461 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1460107665 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:16 PM UTC 24 114031682 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2587901106 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:16 PM UTC 24 176404730 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3627927497 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:16 PM UTC 24 164987807 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.1143683414 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:16 PM UTC 24 133162073 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.775466501 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:17 PM UTC 24 200404172 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2768060594 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:17 PM UTC 24 178871976 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.966359904 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:17 PM UTC 24 469985959 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3835781660 Sep 09 08:59:15 PM UTC 24 Sep 09 08:59:17 PM UTC 24 71200125 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.237389424 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:17 PM UTC 24 891784676 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.485997659 Sep 09 08:59:15 PM UTC 24 Sep 09 08:59:17 PM UTC 24 69949299 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1446857203 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:17 PM UTC 24 778373547 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2472306453 Sep 09 08:59:15 PM UTC 24 Sep 09 08:59:17 PM UTC 24 135946344 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.694549853 Sep 09 08:59:15 PM UTC 24 Sep 09 08:59:18 PM UTC 24 169914460 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1936437573 Sep 09 08:59:13 PM UTC 24 Sep 09 08:59:18 PM UTC 24 943831460 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.694601773 Sep 09 08:59:15 PM UTC 24 Sep 09 08:59:18 PM UTC 24 477740123 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1340885123 Sep 09 08:59:15 PM UTC 24 Sep 09 08:59:19 PM UTC 24 158317080 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2544556317 Sep 09 08:59:19 PM UTC 24 Sep 09 08:59:21 PM UTC 24 71484523 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.691000184 Sep 09 08:59:19 PM UTC 24 Sep 09 08:59:21 PM UTC 24 65819688 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1249609788 Sep 09 08:59:19 PM UTC 24 Sep 09 08:59:21 PM UTC 24 105813424 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1844624029 Sep 09 08:59:19 PM UTC 24 Sep 09 08:59:21 PM UTC 24 209538559 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.491576839 Sep 09 08:59:19 PM UTC 24 Sep 09 08:59:21 PM UTC 24 197575552 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2802921766 Sep 09 08:59:19 PM UTC 24 Sep 09 08:59:23 PM UTC 24 442610499 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2760251394 Sep 09 08:59:19 PM UTC 24 Sep 09 08:59:23 PM UTC 24 938406714 ps


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.3594346096
Short name T9
Test name
Test status
Simulation time 224033465 ps
CPU time 2.39 seconds
Started Sep 09 08:54:16 PM UTC 24
Finished Sep 09 08:54:19 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594346096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3594346096
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.2877933937
Short name T6
Test name
Test status
Simulation time 537201570 ps
CPU time 4.59 seconds
Started Sep 09 08:54:06 PM UTC 24
Finished Sep 09 08:54:12 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877933937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2877933937
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1391674400
Short name T72
Test name
Test status
Simulation time 193576282 ps
CPU time 2.1 seconds
Started Sep 09 08:58:51 PM UTC 24
Finished Sep 09 08:58:54 PM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1391674400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w
ith_rand_reset.1391674400
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2819503954
Short name T11
Test name
Test status
Simulation time 1957387851 ps
CPU time 11.7 seconds
Started Sep 09 08:54:07 PM UTC 24
Finished Sep 09 08:54:21 PM UTC 24
Peak memory 241708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819503954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2819503954
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.2293795812
Short name T69
Test name
Test status
Simulation time 16564335565 ps
CPU time 46.61 seconds
Started Sep 09 08:54:13 PM UTC 24
Finished Sep 09 08:55:01 PM UTC 24
Peak memory 241772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293795812 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2293795812
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.944539491
Short name T97
Test name
Test status
Simulation time 11376503798 ps
CPU time 44.9 seconds
Started Sep 09 08:54:44 PM UTC 24
Finished Sep 09 08:55:30 PM UTC 24
Peak memory 209224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944539491 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.944539491
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1151158769
Short name T94
Test name
Test status
Simulation time 796751095 ps
CPU time 3.04 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:12 PM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151158769 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.1151158769
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.3316235352
Short name T165
Test name
Test status
Simulation time 164023091 ps
CPU time 1.98 seconds
Started Sep 09 08:55:49 PM UTC 24
Finished Sep 09 08:55:52 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316235352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3316235352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2305676776
Short name T4
Test name
Test status
Simulation time 96610731 ps
CPU time 1.58 seconds
Started Sep 09 08:54:07 PM UTC 24
Finished Sep 09 08:54:11 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305676776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2305676776
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.3527699217
Short name T33
Test name
Test status
Simulation time 2460171037 ps
CPU time 8.28 seconds
Started Sep 09 08:56:08 PM UTC 24
Finished Sep 09 08:56:18 PM UTC 24
Peak memory 242436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527699217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3527699217
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.332236211
Short name T8
Test name
Test status
Simulation time 75118750 ps
CPU time 1.29 seconds
Started Sep 09 08:54:14 PM UTC 24
Finished Sep 09 08:54:17 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332236211 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.332236211
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3115318108
Short name T112
Test name
Test status
Simulation time 986531041 ps
CPU time 3.76 seconds
Started Sep 09 08:59:05 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115318108 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.3115318108
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2042162417
Short name T38
Test name
Test status
Simulation time 7192344396 ps
CPU time 29.69 seconds
Started Sep 09 08:54:12 PM UTC 24
Finished Sep 09 08:54:43 PM UTC 24
Peak memory 218080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042162417 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2042162417
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3757097825
Short name T563
Test name
Test status
Simulation time 156872799 ps
CPU time 2.56 seconds
Started Sep 09 08:59:01 PM UTC 24
Finished Sep 09 08:59:05 PM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757097825 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3757097825
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.3749829686
Short name T3
Test name
Test status
Simulation time 101329886 ps
CPU time 1.59 seconds
Started Sep 09 08:54:04 PM UTC 24
Finished Sep 09 08:54:07 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749829686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3749829686
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.481497473
Short name T25
Test name
Test status
Simulation time 1967920112 ps
CPU time 12.03 seconds
Started Sep 09 08:54:26 PM UTC 24
Finished Sep 09 08:54:39 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481497473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.481497473
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3429820741
Short name T64
Test name
Test status
Simulation time 68707611 ps
CPU time 1.26 seconds
Started Sep 09 08:58:49 PM UTC 24
Finished Sep 09 08:58:52 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429820741 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3429820741
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3862474197
Short name T2
Test name
Test status
Simulation time 81661034 ps
CPU time 1.21 seconds
Started Sep 09 08:54:01 PM UTC 24
Finished Sep 09 08:54:03 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862474197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3862474197
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.694601773
Short name T114
Test name
Test status
Simulation time 477740123 ps
CPU time 2.18 seconds
Started Sep 09 08:59:15 PM UTC 24
Finished Sep 09 08:59:18 PM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694601773 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.694601773
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2320940131
Short name T115
Test name
Test status
Simulation time 442741759 ps
CPU time 3.05 seconds
Started Sep 09 08:58:54 PM UTC 24
Finished Sep 09 08:58:58 PM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320940131 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.2320940131
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.3188009482
Short name T87
Test name
Test status
Simulation time 126529501 ps
CPU time 2.48 seconds
Started Sep 09 08:56:08 PM UTC 24
Finished Sep 09 08:56:12 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188009482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3188009482
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3116988438
Short name T65
Test name
Test status
Simulation time 258193388 ps
CPU time 1.93 seconds
Started Sep 09 08:58:49 PM UTC 24
Finished Sep 09 08:58:52 PM UTC 24
Peak memory 207700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116988438 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3116988438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1401859467
Short name T546
Test name
Test status
Simulation time 812955410 ps
CPU time 5.23 seconds
Started Sep 09 08:58:49 PM UTC 24
Finished Sep 09 08:58:56 PM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401859467 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1401859467
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.737080079
Short name T63
Test name
Test status
Simulation time 91605987 ps
CPU time 1.24 seconds
Started Sep 09 08:58:49 PM UTC 24
Finished Sep 09 08:58:51 PM UTC 24
Peak memory 208040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737080079 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.737080079
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2768860390
Short name T67
Test name
Test status
Simulation time 132198678 ps
CPU time 1.2 seconds
Started Sep 09 08:58:51 PM UTC 24
Finished Sep 09 08:58:53 PM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768860390 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.2768860390
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.2539538009
Short name T70
Test name
Test status
Simulation time 510199018 ps
CPU time 3.92 seconds
Started Sep 09 08:58:48 PM UTC 24
Finished Sep 09 08:58:53 PM UTC 24
Peak memory 224988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539538009 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2539538009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.3213723204
Short name T71
Test name
Test status
Simulation time 435117747 ps
CPU time 2.86 seconds
Started Sep 09 08:58:49 PM UTC 24
Finished Sep 09 08:58:53 PM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213723204 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.3213723204
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3159067099
Short name T131
Test name
Test status
Simulation time 158200426 ps
CPU time 2.54 seconds
Started Sep 09 08:58:52 PM UTC 24
Finished Sep 09 08:58:56 PM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159067099 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3159067099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.256711060
Short name T551
Test name
Test status
Simulation time 491075079 ps
CPU time 5.33 seconds
Started Sep 09 08:58:52 PM UTC 24
Finished Sep 09 08:58:59 PM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256711060 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.256711060
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4079308506
Short name T110
Test name
Test status
Simulation time 126997965 ps
CPU time 1.22 seconds
Started Sep 09 08:58:51 PM UTC 24
Finished Sep 09 08:58:53 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079308506 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4079308506
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2226782839
Short name T89
Test name
Test status
Simulation time 204822125 ps
CPU time 2.18 seconds
Started Sep 09 08:58:52 PM UTC 24
Finished Sep 09 08:58:55 PM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2226782839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w
ith_rand_reset.2226782839
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2175682637
Short name T66
Test name
Test status
Simulation time 62416001 ps
CPU time 0.86 seconds
Started Sep 09 08:58:51 PM UTC 24
Finished Sep 09 08:58:53 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175682637 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2175682637
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3387892785
Short name T103
Test name
Test status
Simulation time 82648035 ps
CPU time 1.38 seconds
Started Sep 09 08:58:52 PM UTC 24
Finished Sep 09 08:58:55 PM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387892785 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.3387892785
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2329151850
Short name T73
Test name
Test status
Simulation time 231906436 ps
CPU time 2.24 seconds
Started Sep 09 08:58:51 PM UTC 24
Finished Sep 09 08:58:54 PM UTC 24
Peak memory 217648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329151850 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2329151850
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.612985553
Short name T74
Test name
Test status
Simulation time 498275543 ps
CPU time 3.19 seconds
Started Sep 09 08:58:51 PM UTC 24
Finished Sep 09 08:58:55 PM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612985553 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.612985553
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3770226717
Short name T576
Test name
Test status
Simulation time 131490237 ps
CPU time 1.27 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3770226717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_
with_rand_reset.3770226717
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2373899688
Short name T564
Test name
Test status
Simulation time 94024974 ps
CPU time 1.35 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373899688 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2373899688
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1101517030
Short name T581
Test name
Test status
Simulation time 142698760 ps
CPU time 1.55 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101517030 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.1101517030
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.4012636033
Short name T577
Test name
Test status
Simulation time 531817260 ps
CPU time 3.76 seconds
Started Sep 09 08:59:05 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012636033 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.4012636033
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3848791458
Short name T580
Test name
Test status
Simulation time 190581350 ps
CPU time 1.31 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3848791458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_
with_rand_reset.3848791458
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.715551658
Short name T575
Test name
Test status
Simulation time 54948244 ps
CPU time 1.01 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 207704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715551658 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.715551658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2031981500
Short name T579
Test name
Test status
Simulation time 133076038 ps
CPU time 1.24 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031981500 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.2031981500
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2938505677
Short name T578
Test name
Test status
Simulation time 95498124 ps
CPU time 1.41 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 219632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938505677 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2938505677
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3713997441
Short name T586
Test name
Test status
Simulation time 172617000 ps
CPU time 1.39 seconds
Started Sep 09 08:59:09 PM UTC 24
Finished Sep 09 08:59:12 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3713997441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_
with_rand_reset.3713997441
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.675530876
Short name T584
Test name
Test status
Simulation time 91950948 ps
CPU time 0.94 seconds
Started Sep 09 08:59:09 PM UTC 24
Finished Sep 09 08:59:12 PM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675530876 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.675530876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.1294685566
Short name T583
Test name
Test status
Simulation time 80860206 ps
CPU time 0.95 seconds
Started Sep 09 08:59:09 PM UTC 24
Finished Sep 09 08:59:12 PM UTC 24
Peak memory 207764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294685566 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.1294685566
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.4022197775
Short name T582
Test name
Test status
Simulation time 167820195 ps
CPU time 1.5 seconds
Started Sep 09 08:59:07 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 217560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022197775 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4022197775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2576755349
Short name T589
Test name
Test status
Simulation time 490956082 ps
CPU time 1.95 seconds
Started Sep 09 08:59:09 PM UTC 24
Finished Sep 09 08:59:13 PM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576755349 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.2576755349
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.557179121
Short name T587
Test name
Test status
Simulation time 114447210 ps
CPU time 1.27 seconds
Started Sep 09 08:59:10 PM UTC 24
Finished Sep 09 08:59:12 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=557179121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_w
ith_rand_reset.557179121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2316491697
Short name T585
Test name
Test status
Simulation time 57785329 ps
CPU time 1.06 seconds
Started Sep 09 08:59:09 PM UTC 24
Finished Sep 09 08:59:12 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316491697 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2316491697
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2345210964
Short name T588
Test name
Test status
Simulation time 81996297 ps
CPU time 1.33 seconds
Started Sep 09 08:59:09 PM UTC 24
Finished Sep 09 08:59:12 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345210964 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.2345210964
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2329336589
Short name T591
Test name
Test status
Simulation time 425620237 ps
CPU time 3.23 seconds
Started Sep 09 08:59:09 PM UTC 24
Finished Sep 09 08:59:14 PM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329336589 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2329336589
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1166897370
Short name T590
Test name
Test status
Simulation time 809987110 ps
CPU time 3.21 seconds
Started Sep 09 08:59:09 PM UTC 24
Finished Sep 09 08:59:14 PM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166897370 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.1166897370
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3627927497
Short name T601
Test name
Test status
Simulation time 164987807 ps
CPU time 2.14 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:16 PM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3627927497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_
with_rand_reset.3627927497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.2934745024
Short name T592
Test name
Test status
Simulation time 61577867 ps
CPU time 0.89 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:15 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934745024 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.2934745024
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2920919203
Short name T593
Test name
Test status
Simulation time 137620508 ps
CPU time 1.03 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:15 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920919203 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.2920919203
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.1143683414
Short name T602
Test name
Test status
Simulation time 133162073 ps
CPU time 2.21 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:16 PM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143683414 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.1143683414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.237389424
Short name T607
Test name
Test status
Simulation time 891784676 ps
CPU time 3.06 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:17 PM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237389424 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.237389424
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3288177603
Short name T598
Test name
Test status
Simulation time 146245461 ps
CPU time 1.62 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:16 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3288177603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_
with_rand_reset.3288177603
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3175913137
Short name T594
Test name
Test status
Simulation time 90746660 ps
CPU time 1.29 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:15 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175913137 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3175913137
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1460107665
Short name T599
Test name
Test status
Simulation time 114031682 ps
CPU time 1.69 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:16 PM UTC 24
Peak memory 207752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460107665 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.1460107665
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2768060594
Short name T604
Test name
Test status
Simulation time 178871976 ps
CPU time 2.56 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:17 PM UTC 24
Peak memory 217760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768060594 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2768060594
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1446857203
Short name T609
Test name
Test status
Simulation time 778373547 ps
CPU time 3.29 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:17 PM UTC 24
Peak memory 208804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446857203 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.1446857203
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2587901106
Short name T600
Test name
Test status
Simulation time 176404730 ps
CPU time 1.38 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:16 PM UTC 24
Peak memory 217528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2587901106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_
with_rand_reset.2587901106
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.3761657512
Short name T595
Test name
Test status
Simulation time 56202306 ps
CPU time 1.03 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:15 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761657512 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.3761657512
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3134526662
Short name T596
Test name
Test status
Simulation time 80569196 ps
CPU time 1.03 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:16 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134526662 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.3134526662
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.210645743
Short name T597
Test name
Test status
Simulation time 114206830 ps
CPU time 1.52 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:16 PM UTC 24
Peak memory 217624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210645743 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.210645743
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.1936437573
Short name T612
Test name
Test status
Simulation time 943831460 ps
CPU time 3.99 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:18 PM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936437573 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.1936437573
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.694549853
Short name T611
Test name
Test status
Simulation time 169914460 ps
CPU time 1.61 seconds
Started Sep 09 08:59:15 PM UTC 24
Finished Sep 09 08:59:18 PM UTC 24
Peak memory 217648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=694549853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_w
ith_rand_reset.694549853
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3835781660
Short name T606
Test name
Test status
Simulation time 71200125 ps
CPU time 1.05 seconds
Started Sep 09 08:59:15 PM UTC 24
Finished Sep 09 08:59:17 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835781660 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3835781660
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2472306453
Short name T610
Test name
Test status
Simulation time 135946344 ps
CPU time 1.5 seconds
Started Sep 09 08:59:15 PM UTC 24
Finished Sep 09 08:59:17 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472306453 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.2472306453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.775466501
Short name T603
Test name
Test status
Simulation time 200404172 ps
CPU time 2.13 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:17 PM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775466501 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.775466501
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.966359904
Short name T605
Test name
Test status
Simulation time 469985959 ps
CPU time 2.01 seconds
Started Sep 09 08:59:13 PM UTC 24
Finished Sep 09 08:59:17 PM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966359904 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.966359904
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.1844624029
Short name T617
Test name
Test status
Simulation time 209538559 ps
CPU time 1.34 seconds
Started Sep 09 08:59:19 PM UTC 24
Finished Sep 09 08:59:21 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1844624029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_
with_rand_reset.1844624029
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.485997659
Short name T608
Test name
Test status
Simulation time 69949299 ps
CPU time 1.1 seconds
Started Sep 09 08:59:15 PM UTC 24
Finished Sep 09 08:59:17 PM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485997659 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.485997659
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1249609788
Short name T616
Test name
Test status
Simulation time 105813424 ps
CPU time 1.23 seconds
Started Sep 09 08:59:19 PM UTC 24
Finished Sep 09 08:59:21 PM UTC 24
Peak memory 207800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249609788 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.1249609788
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1340885123
Short name T613
Test name
Test status
Simulation time 158317080 ps
CPU time 2.49 seconds
Started Sep 09 08:59:15 PM UTC 24
Finished Sep 09 08:59:19 PM UTC 24
Peak memory 225008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340885123 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1340885123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.491576839
Short name T618
Test name
Test status
Simulation time 197575552 ps
CPU time 1.33 seconds
Started Sep 09 08:59:19 PM UTC 24
Finished Sep 09 08:59:21 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=491576839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_w
ith_rand_reset.491576839
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.691000184
Short name T615
Test name
Test status
Simulation time 65819688 ps
CPU time 1 seconds
Started Sep 09 08:59:19 PM UTC 24
Finished Sep 09 08:59:21 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691000184 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.691000184
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2544556317
Short name T614
Test name
Test status
Simulation time 71484523 ps
CPU time 0.92 seconds
Started Sep 09 08:59:19 PM UTC 24
Finished Sep 09 08:59:21 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544556317 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.2544556317
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2802921766
Short name T619
Test name
Test status
Simulation time 442610499 ps
CPU time 3.14 seconds
Started Sep 09 08:59:19 PM UTC 24
Finished Sep 09 08:59:23 PM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802921766 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2802921766
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2760251394
Short name T620
Test name
Test status
Simulation time 938406714 ps
CPU time 3.09 seconds
Started Sep 09 08:59:19 PM UTC 24
Finished Sep 09 08:59:23 PM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760251394 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.2760251394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.574466751
Short name T548
Test name
Test status
Simulation time 204564539 ps
CPU time 2.35 seconds
Started Sep 09 08:58:54 PM UTC 24
Finished Sep 09 08:58:57 PM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574466751 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.574466751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.235196203
Short name T550
Test name
Test status
Simulation time 271070249 ps
CPU time 3.21 seconds
Started Sep 09 08:58:54 PM UTC 24
Finished Sep 09 08:58:58 PM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235196203 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.235196203
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1881411197
Short name T547
Test name
Test status
Simulation time 142374010 ps
CPU time 1.18 seconds
Started Sep 09 08:58:54 PM UTC 24
Finished Sep 09 08:58:56 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881411197 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1881411197
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1067850845
Short name T90
Test name
Test status
Simulation time 198110851 ps
CPU time 1.5 seconds
Started Sep 09 08:58:54 PM UTC 24
Finished Sep 09 08:58:57 PM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1067850845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w
ith_rand_reset.1067850845
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.2631359662
Short name T104
Test name
Test status
Simulation time 63239857 ps
CPU time 1.22 seconds
Started Sep 09 08:58:54 PM UTC 24
Finished Sep 09 08:58:56 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631359662 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.2631359662
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2551543751
Short name T105
Test name
Test status
Simulation time 72539298 ps
CPU time 1.07 seconds
Started Sep 09 08:58:54 PM UTC 24
Finished Sep 09 08:58:56 PM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551543751 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.2551543751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1334992779
Short name T88
Test name
Test status
Simulation time 215032132 ps
CPU time 2.03 seconds
Started Sep 09 08:58:52 PM UTC 24
Finished Sep 09 08:58:55 PM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334992779 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1334992779
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.590607715
Short name T554
Test name
Test status
Simulation time 267863194 ps
CPU time 3.06 seconds
Started Sep 09 08:58:57 PM UTC 24
Finished Sep 09 08:59:01 PM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590607715 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.590607715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.467713249
Short name T559
Test name
Test status
Simulation time 491401962 ps
CPU time 5.97 seconds
Started Sep 09 08:58:56 PM UTC 24
Finished Sep 09 08:59:03 PM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467713249 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.467713249
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.582064928
Short name T549
Test name
Test status
Simulation time 98245842 ps
CPU time 1.33 seconds
Started Sep 09 08:58:55 PM UTC 24
Finished Sep 09 08:58:58 PM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582064928 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.582064928
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.641726522
Short name T92
Test name
Test status
Simulation time 180069383 ps
CPU time 1.68 seconds
Started Sep 09 08:58:57 PM UTC 24
Finished Sep 09 08:59:00 PM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=641726522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_wi
th_rand_reset.641726522
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3840236107
Short name T106
Test name
Test status
Simulation time 62911268 ps
CPU time 1.21 seconds
Started Sep 09 08:58:55 PM UTC 24
Finished Sep 09 08:58:58 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840236107 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3840236107
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.245958282
Short name T107
Test name
Test status
Simulation time 88274197 ps
CPU time 1.65 seconds
Started Sep 09 08:58:57 PM UTC 24
Finished Sep 09 08:59:00 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245958282 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.245958282
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.1602105193
Short name T91
Test name
Test status
Simulation time 160707669 ps
CPU time 2.73 seconds
Started Sep 09 08:58:54 PM UTC 24
Finished Sep 09 08:58:58 PM UTC 24
Peak memory 225168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602105193 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1602105193
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.277709453
Short name T129
Test name
Test status
Simulation time 462791968 ps
CPU time 2.64 seconds
Started Sep 09 08:58:55 PM UTC 24
Finished Sep 09 08:58:59 PM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277709453 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.277709453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2812975741
Short name T555
Test name
Test status
Simulation time 357112739 ps
CPU time 2.71 seconds
Started Sep 09 08:58:58 PM UTC 24
Finished Sep 09 08:59:01 PM UTC 24
Peak memory 208976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812975741 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2812975741
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.1248044234
Short name T558
Test name
Test status
Simulation time 278784088 ps
CPU time 3.57 seconds
Started Sep 09 08:58:58 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248044234 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.1248044234
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1163912532
Short name T552
Test name
Test status
Simulation time 119991627 ps
CPU time 1.2 seconds
Started Sep 09 08:58:57 PM UTC 24
Finished Sep 09 08:59:00 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163912532 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1163912532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.926390658
Short name T95
Test name
Test status
Simulation time 111906048 ps
CPU time 1.87 seconds
Started Sep 09 08:58:59 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=926390658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_wi
th_rand_reset.926390658
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.4083394681
Short name T553
Test name
Test status
Simulation time 64979840 ps
CPU time 1.24 seconds
Started Sep 09 08:58:57 PM UTC 24
Finished Sep 09 08:59:00 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083394681 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.4083394681
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.1258748017
Short name T108
Test name
Test status
Simulation time 157068711 ps
CPU time 1.6 seconds
Started Sep 09 08:58:59 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258748017 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.1258748017
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2129616299
Short name T119
Test name
Test status
Simulation time 521290742 ps
CPU time 3.7 seconds
Started Sep 09 08:58:57 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 221792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129616299 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2129616299
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1360432619
Short name T93
Test name
Test status
Simulation time 470203467 ps
CPU time 3.09 seconds
Started Sep 09 08:58:57 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360432619 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.1360432619
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3941495745
Short name T557
Test name
Test status
Simulation time 119277837 ps
CPU time 1.58 seconds
Started Sep 09 08:58:59 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3941495745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w
ith_rand_reset.3941495745
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.4134809272
Short name T556
Test name
Test status
Simulation time 83938575 ps
CPU time 1.36 seconds
Started Sep 09 08:58:59 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134809272 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.4134809272
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.469522294
Short name T109
Test name
Test status
Simulation time 82788092 ps
CPU time 1.44 seconds
Started Sep 09 08:58:59 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469522294 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.469522294
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1598253666
Short name T111
Test name
Test status
Simulation time 227153020 ps
CPU time 3.76 seconds
Started Sep 09 08:58:59 PM UTC 24
Finished Sep 09 08:59:04 PM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598253666 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1598253666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.4158882976
Short name T117
Test name
Test status
Simulation time 441274636 ps
CPU time 2.28 seconds
Started Sep 09 08:58:59 PM UTC 24
Finished Sep 09 08:59:02 PM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158882976 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.4158882976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.3030635175
Short name T562
Test name
Test status
Simulation time 195197420 ps
CPU time 1.56 seconds
Started Sep 09 08:59:01 PM UTC 24
Finished Sep 09 08:59:04 PM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3030635175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w
ith_rand_reset.3030635175
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.855748504
Short name T560
Test name
Test status
Simulation time 92908266 ps
CPU time 1.39 seconds
Started Sep 09 08:59:01 PM UTC 24
Finished Sep 09 08:59:04 PM UTC 24
Peak memory 207644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855748504 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.855748504
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.1162519044
Short name T561
Test name
Test status
Simulation time 170356390 ps
CPU time 1.54 seconds
Started Sep 09 08:59:01 PM UTC 24
Finished Sep 09 08:59:04 PM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162519044 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.1162519044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.650611107
Short name T120
Test name
Test status
Simulation time 134814182 ps
CPU time 2.62 seconds
Started Sep 09 08:59:01 PM UTC 24
Finished Sep 09 08:59:05 PM UTC 24
Peak memory 221940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650611107 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.650611107
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.781428674
Short name T118
Test name
Test status
Simulation time 528860400 ps
CPU time 2.64 seconds
Started Sep 09 08:59:01 PM UTC 24
Finished Sep 09 08:59:05 PM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781428674 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.781428674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1366910460
Short name T566
Test name
Test status
Simulation time 175107946 ps
CPU time 1.35 seconds
Started Sep 09 08:59:03 PM UTC 24
Finished Sep 09 08:59:06 PM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1366910460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w
ith_rand_reset.1366910460
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1706915984
Short name T565
Test name
Test status
Simulation time 64398401 ps
CPU time 0.86 seconds
Started Sep 09 08:59:03 PM UTC 24
Finished Sep 09 08:59:05 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706915984 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1706915984
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2091715611
Short name T568
Test name
Test status
Simulation time 211163282 ps
CPU time 2.32 seconds
Started Sep 09 08:59:03 PM UTC 24
Finished Sep 09 08:59:07 PM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091715611 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.2091715611
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.929180571
Short name T116
Test name
Test status
Simulation time 926116911 ps
CPU time 3.31 seconds
Started Sep 09 08:59:03 PM UTC 24
Finished Sep 09 08:59:08 PM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929180571 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.929180571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2906360409
Short name T572
Test name
Test status
Simulation time 118747919 ps
CPU time 1.86 seconds
Started Sep 09 08:59:05 PM UTC 24
Finished Sep 09 08:59:08 PM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2906360409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w
ith_rand_reset.2906360409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.1271174276
Short name T98
Test name
Test status
Simulation time 71452911 ps
CPU time 1.23 seconds
Started Sep 09 08:59:03 PM UTC 24
Finished Sep 09 08:59:06 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271174276 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.1271174276
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3723994571
Short name T567
Test name
Test status
Simulation time 157914972 ps
CPU time 1.48 seconds
Started Sep 09 08:59:03 PM UTC 24
Finished Sep 09 08:59:06 PM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723994571 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.3723994571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.1945749131
Short name T571
Test name
Test status
Simulation time 161112978 ps
CPU time 2.93 seconds
Started Sep 09 08:59:03 PM UTC 24
Finished Sep 09 08:59:08 PM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945749131 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1945749131
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3925995587
Short name T130
Test name
Test status
Simulation time 412748647 ps
CPU time 1.93 seconds
Started Sep 09 08:59:03 PM UTC 24
Finished Sep 09 08:59:06 PM UTC 24
Peak memory 207700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925995587 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.3925995587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2856339625
Short name T573
Test name
Test status
Simulation time 161615995 ps
CPU time 1.84 seconds
Started Sep 09 08:59:05 PM UTC 24
Finished Sep 09 08:59:08 PM UTC 24
Peak memory 217644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2856339625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w
ith_rand_reset.2856339625
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.1106040428
Short name T569
Test name
Test status
Simulation time 63775441 ps
CPU time 1.09 seconds
Started Sep 09 08:59:05 PM UTC 24
Finished Sep 09 08:59:07 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106040428 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1106040428
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2652836927
Short name T570
Test name
Test status
Simulation time 151032224 ps
CPU time 1.26 seconds
Started Sep 09 08:59:05 PM UTC 24
Finished Sep 09 08:59:07 PM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652836927 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.2652836927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3028612222
Short name T574
Test name
Test status
Simulation time 231667203 ps
CPU time 3.48 seconds
Started Sep 09 08:59:05 PM UTC 24
Finished Sep 09 08:59:10 PM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028612222 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3028612222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3087375407
Short name T113
Test name
Test status
Simulation time 889279961 ps
CPU time 2.95 seconds
Started Sep 09 08:59:05 PM UTC 24
Finished Sep 09 08:59:09 PM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087375407 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.3087375407
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.845074137
Short name T7
Test name
Test status
Simulation time 301120574 ps
CPU time 1.9 seconds
Started Sep 09 08:54:12 PM UTC 24
Finished Sep 09 08:54:15 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845074137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.845074137
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.262242986
Short name T5
Test name
Test status
Simulation time 1018453326 ps
CPU time 7.77 seconds
Started Sep 09 08:54:02 PM UTC 24
Finished Sep 09 08:54:11 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262242986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.262242986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.2494567233
Short name T1
Test name
Test status
Simulation time 193236854 ps
CPU time 1.63 seconds
Started Sep 09 08:53:58 PM UTC 24
Finished Sep 09 08:54:01 PM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494567233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.2494567233
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/0.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.2011002847
Short name T59
Test name
Test status
Simulation time 67441827 ps
CPU time 1.17 seconds
Started Sep 09 08:54:30 PM UTC 24
Finished Sep 09 08:54:32 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011002847 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2011002847
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1154553398
Short name T24
Test name
Test status
Simulation time 301867071 ps
CPU time 2.04 seconds
Started Sep 09 08:54:28 PM UTC 24
Finished Sep 09 08:54:31 PM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154553398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1154553398
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3917549197
Short name T10
Test name
Test status
Simulation time 229575004 ps
CPU time 1.55 seconds
Started Sep 09 08:54:17 PM UTC 24
Finished Sep 09 08:54:20 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917549197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3917549197
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.635147642
Short name T22
Test name
Test status
Simulation time 2161414287 ps
CPU time 12.51 seconds
Started Sep 09 08:54:20 PM UTC 24
Finished Sep 09 08:54:34 PM UTC 24
Peak memory 209380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635147642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.635147642
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.1607788469
Short name T68
Test name
Test status
Simulation time 8917353448 ps
CPU time 26.4 seconds
Started Sep 09 08:54:30 PM UTC 24
Finished Sep 09 08:54:58 PM UTC 24
Peak memory 241800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607788469 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1607788469
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3631662069
Short name T13
Test name
Test status
Simulation time 145817090 ps
CPU time 1.75 seconds
Started Sep 09 08:54:26 PM UTC 24
Finished Sep 09 08:54:29 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631662069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3631662069
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.596263240
Short name T41
Test name
Test status
Simulation time 1853456452 ps
CPU time 14.97 seconds
Started Sep 09 08:54:30 PM UTC 24
Finished Sep 09 08:54:46 PM UTC 24
Peak memory 218036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596263240 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.596263240
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2321882798
Short name T58
Test name
Test status
Simulation time 513156963 ps
CPU time 4.48 seconds
Started Sep 09 08:54:21 PM UTC 24
Finished Sep 09 08:54:27 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321882798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2321882798
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.3149682978
Short name T12
Test name
Test status
Simulation time 216106271 ps
CPU time 2.11 seconds
Started Sep 09 08:54:21 PM UTC 24
Finished Sep 09 08:54:24 PM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149682978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3149682978
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.4129694988
Short name T170
Test name
Test status
Simulation time 76324236 ps
CPU time 1.31 seconds
Started Sep 09 08:55:52 PM UTC 24
Finished Sep 09 08:55:55 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129694988 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.4129694988
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.261266648
Short name T176
Test name
Test status
Simulation time 2432308181 ps
CPU time 8.7 seconds
Started Sep 09 08:55:50 PM UTC 24
Finished Sep 09 08:56:00 PM UTC 24
Peak memory 241796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261266648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.261266648
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1164094553
Short name T169
Test name
Test status
Simulation time 302568328 ps
CPU time 1.92 seconds
Started Sep 09 08:55:51 PM UTC 24
Finished Sep 09 08:55:54 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164094553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1164094553
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.1952225096
Short name T162
Test name
Test status
Simulation time 153571953 ps
CPU time 1.37 seconds
Started Sep 09 08:55:48 PM UTC 24
Finished Sep 09 08:55:50 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952225096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1952225096
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.2015644592
Short name T175
Test name
Test status
Simulation time 1233954558 ps
CPU time 8.86 seconds
Started Sep 09 08:55:49 PM UTC 24
Finished Sep 09 08:55:59 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015644592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2015644592
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1277161396
Short name T166
Test name
Test status
Simulation time 110858572 ps
CPU time 1.56 seconds
Started Sep 09 08:55:50 PM UTC 24
Finished Sep 09 08:55:53 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277161396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1277161396
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.1663763230
Short name T163
Test name
Test status
Simulation time 258734287 ps
CPU time 2.38 seconds
Started Sep 09 08:55:48 PM UTC 24
Finished Sep 09 08:55:51 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663763230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.1663763230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.1661719537
Short name T101
Test name
Test status
Simulation time 2457518372 ps
CPU time 15.16 seconds
Started Sep 09 08:55:52 PM UTC 24
Finished Sep 09 08:56:09 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661719537 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.1661719537
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.1718008042
Short name T167
Test name
Test status
Simulation time 409527344 ps
CPU time 3.01 seconds
Started Sep 09 08:55:50 PM UTC 24
Finished Sep 09 08:55:54 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718008042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1718008042
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.430193573
Short name T178
Test name
Test status
Simulation time 133120905 ps
CPU time 1.37 seconds
Started Sep 09 08:55:58 PM UTC 24
Finished Sep 09 08:56:01 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430193573 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.430193573
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.1663960233
Short name T57
Test name
Test status
Simulation time 1259455269 ps
CPU time 10.32 seconds
Started Sep 09 08:55:57 PM UTC 24
Finished Sep 09 08:56:09 PM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663960233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1663960233
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3330453451
Short name T179
Test name
Test status
Simulation time 301288899 ps
CPU time 1.95 seconds
Started Sep 09 08:55:58 PM UTC 24
Finished Sep 09 08:56:01 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330453451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3330453451
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3945316042
Short name T171
Test name
Test status
Simulation time 110528130 ps
CPU time 1.28 seconds
Started Sep 09 08:55:54 PM UTC 24
Finished Sep 09 08:55:56 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945316042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3945316042
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.1091810354
Short name T121
Test name
Test status
Simulation time 1499450823 ps
CPU time 7.66 seconds
Started Sep 09 08:55:55 PM UTC 24
Finished Sep 09 08:56:03 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091810354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1091810354
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3717754937
Short name T174
Test name
Test status
Simulation time 113869998 ps
CPU time 1.6 seconds
Started Sep 09 08:55:56 PM UTC 24
Finished Sep 09 08:55:58 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717754937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3717754937
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.936230809
Short name T172
Test name
Test status
Simulation time 250404940 ps
CPU time 2.71 seconds
Started Sep 09 08:55:53 PM UTC 24
Finished Sep 09 08:55:57 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936230809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.936230809
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.3830308244
Short name T198
Test name
Test status
Simulation time 3706272277 ps
CPU time 13.34 seconds
Started Sep 09 08:55:58 PM UTC 24
Finished Sep 09 08:56:13 PM UTC 24
Peak memory 220280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830308244 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3830308244
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.2338075413
Short name T177
Test name
Test status
Simulation time 282582084 ps
CPU time 3.03 seconds
Started Sep 09 08:55:56 PM UTC 24
Finished Sep 09 08:56:00 PM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338075413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2338075413
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.1014890749
Short name T173
Test name
Test status
Simulation time 123106554 ps
CPU time 1.73 seconds
Started Sep 09 08:55:55 PM UTC 24
Finished Sep 09 08:55:57 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014890749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.1014890749
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.17033160
Short name T185
Test name
Test status
Simulation time 55819562 ps
CPU time 1.13 seconds
Started Sep 09 08:56:04 PM UTC 24
Finished Sep 09 08:56:07 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17033160 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.17033160
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.3071489532
Short name T32
Test name
Test status
Simulation time 1973169534 ps
CPU time 12.72 seconds
Started Sep 09 08:56:03 PM UTC 24
Finished Sep 09 08:56:17 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071489532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3071489532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1221355099
Short name T188
Test name
Test status
Simulation time 301692272 ps
CPU time 1.91 seconds
Started Sep 09 08:56:04 PM UTC 24
Finished Sep 09 08:56:08 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221355099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1221355099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.4193166644
Short name T181
Test name
Test status
Simulation time 102910224 ps
CPU time 1.28 seconds
Started Sep 09 08:56:01 PM UTC 24
Finished Sep 09 08:56:03 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193166644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.4193166644
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.169249681
Short name T187
Test name
Test status
Simulation time 996362335 ps
CPU time 5.47 seconds
Started Sep 09 08:56:01 PM UTC 24
Finished Sep 09 08:56:07 PM UTC 24
Peak memory 209116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169249681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.169249681
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.315006044
Short name T184
Test name
Test status
Simulation time 155952758 ps
CPU time 1.69 seconds
Started Sep 09 08:56:03 PM UTC 24
Finished Sep 09 08:56:06 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315006044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.315006044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3229228712
Short name T180
Test name
Test status
Simulation time 109166664 ps
CPU time 1.68 seconds
Started Sep 09 08:55:59 PM UTC 24
Finished Sep 09 08:56:02 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229228712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3229228712
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.1564405641
Short name T263
Test name
Test status
Simulation time 7117212863 ps
CPU time 44.3 seconds
Started Sep 09 08:56:04 PM UTC 24
Finished Sep 09 08:56:51 PM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564405641 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1564405641
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.406313718
Short name T186
Test name
Test status
Simulation time 480790745 ps
CPU time 4.41 seconds
Started Sep 09 08:56:02 PM UTC 24
Finished Sep 09 08:56:07 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406313718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.406313718
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.2594883843
Short name T182
Test name
Test status
Simulation time 126988835 ps
CPU time 1.61 seconds
Started Sep 09 08:56:01 PM UTC 24
Finished Sep 09 08:56:04 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594883843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2594883843
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.740891457
Short name T194
Test name
Test status
Simulation time 72485520 ps
CPU time 1.22 seconds
Started Sep 09 08:56:09 PM UTC 24
Finished Sep 09 08:56:12 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740891457 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.740891457
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2535638955
Short name T197
Test name
Test status
Simulation time 301830888 ps
CPU time 2.04 seconds
Started Sep 09 08:56:09 PM UTC 24
Finished Sep 09 08:56:12 PM UTC 24
Peak memory 237828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535638955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2535638955
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.3539228273
Short name T190
Test name
Test status
Simulation time 150065733 ps
CPU time 1.26 seconds
Started Sep 09 08:56:07 PM UTC 24
Finished Sep 09 08:56:09 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539228273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3539228273
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.1035976014
Short name T202
Test name
Test status
Simulation time 844157417 ps
CPU time 6.5 seconds
Started Sep 09 08:56:08 PM UTC 24
Finished Sep 09 08:56:16 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035976014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1035976014
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.3113964943
Short name T193
Test name
Test status
Simulation time 181916709 ps
CPU time 1.98 seconds
Started Sep 09 08:56:08 PM UTC 24
Finished Sep 09 08:56:11 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113964943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.3113964943
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.571908248
Short name T189
Test name
Test status
Simulation time 203450725 ps
CPU time 2.14 seconds
Started Sep 09 08:56:04 PM UTC 24
Finished Sep 09 08:56:08 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571908248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.571908248
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.735170674
Short name T123
Test name
Test status
Simulation time 2066137512 ps
CPU time 11.98 seconds
Started Sep 09 08:56:09 PM UTC 24
Finished Sep 09 08:56:23 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735170674 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.735170674
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.987385190
Short name T192
Test name
Test status
Simulation time 192990816 ps
CPU time 1.85 seconds
Started Sep 09 08:56:08 PM UTC 24
Finished Sep 09 08:56:11 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987385190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.987385190
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.2992436493
Short name T200
Test name
Test status
Simulation time 77499575 ps
CPU time 1.3 seconds
Started Sep 09 08:56:13 PM UTC 24
Finished Sep 09 08:56:15 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992436493 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2992436493
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.647674405
Short name T45
Test name
Test status
Simulation time 2444050308 ps
CPU time 10.41 seconds
Started Sep 09 08:56:13 PM UTC 24
Finished Sep 09 08:56:25 PM UTC 24
Peak memory 241800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647674405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.647674405
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1407218484
Short name T204
Test name
Test status
Simulation time 303578922 ps
CPU time 1.91 seconds
Started Sep 09 08:56:13 PM UTC 24
Finished Sep 09 08:56:16 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407218484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1407218484
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.561782705
Short name T195
Test name
Test status
Simulation time 211745725 ps
CPU time 1.54 seconds
Started Sep 09 08:56:10 PM UTC 24
Finished Sep 09 08:56:12 PM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561782705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.561782705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.2407326590
Short name T208
Test name
Test status
Simulation time 885407892 ps
CPU time 7.81 seconds
Started Sep 09 08:56:11 PM UTC 24
Finished Sep 09 08:56:20 PM UTC 24
Peak memory 209260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407326590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2407326590
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3977055738
Short name T203
Test name
Test status
Simulation time 155865012 ps
CPU time 1.77 seconds
Started Sep 09 08:56:13 PM UTC 24
Finished Sep 09 08:56:16 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977055738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3977055738
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.4293166819
Short name T196
Test name
Test status
Simulation time 126580165 ps
CPU time 1.86 seconds
Started Sep 09 08:56:09 PM UTC 24
Finished Sep 09 08:56:12 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293166819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4293166819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.1471147456
Short name T125
Test name
Test status
Simulation time 2230630170 ps
CPU time 7.84 seconds
Started Sep 09 08:56:13 PM UTC 24
Finished Sep 09 08:56:22 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471147456 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.1471147456
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.4078252415
Short name T201
Test name
Test status
Simulation time 139106938 ps
CPU time 2.64 seconds
Started Sep 09 08:56:12 PM UTC 24
Finished Sep 09 08:56:15 PM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078252415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4078252415
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.486666934
Short name T199
Test name
Test status
Simulation time 148231117 ps
CPU time 1.87 seconds
Started Sep 09 08:56:12 PM UTC 24
Finished Sep 09 08:56:15 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486666934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.486666934
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.2905358205
Short name T210
Test name
Test status
Simulation time 63316556 ps
CPU time 1.2 seconds
Started Sep 09 08:56:18 PM UTC 24
Finished Sep 09 08:56:20 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905358205 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2905358205
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.1086444359
Short name T31
Test name
Test status
Simulation time 1267758972 ps
CPU time 6.29 seconds
Started Sep 09 08:56:17 PM UTC 24
Finished Sep 09 08:56:24 PM UTC 24
Peak memory 242268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086444359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1086444359
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.624193950
Short name T212
Test name
Test status
Simulation time 301876426 ps
CPU time 2.03 seconds
Started Sep 09 08:56:18 PM UTC 24
Finished Sep 09 08:56:21 PM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624193950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.624193950
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.1942844359
Short name T206
Test name
Test status
Simulation time 223238370 ps
CPU time 1.16 seconds
Started Sep 09 08:56:15 PM UTC 24
Finished Sep 09 08:56:18 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942844359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1942844359
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.425098868
Short name T168
Test name
Test status
Simulation time 746713211 ps
CPU time 5.31 seconds
Started Sep 09 08:56:17 PM UTC 24
Finished Sep 09 08:56:23 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425098868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.425098868
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.3793827495
Short name T209
Test name
Test status
Simulation time 165125311 ps
CPU time 1.96 seconds
Started Sep 09 08:56:17 PM UTC 24
Finished Sep 09 08:56:20 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793827495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.3793827495
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.3702409230
Short name T205
Test name
Test status
Simulation time 125737279 ps
CPU time 1.95 seconds
Started Sep 09 08:56:14 PM UTC 24
Finished Sep 09 08:56:17 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702409230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3702409230
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.625539885
Short name T260
Test name
Test status
Simulation time 7951377436 ps
CPU time 30.65 seconds
Started Sep 09 08:56:18 PM UTC 24
Finished Sep 09 08:56:50 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625539885 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.625539885
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.3612964049
Short name T211
Test name
Test status
Simulation time 384120837 ps
CPU time 2.71 seconds
Started Sep 09 08:56:17 PM UTC 24
Finished Sep 09 08:56:20 PM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612964049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3612964049
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.1002810646
Short name T207
Test name
Test status
Simulation time 89661692 ps
CPU time 1.32 seconds
Started Sep 09 08:56:17 PM UTC 24
Finished Sep 09 08:56:19 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002810646 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1002810646
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.4104395409
Short name T215
Test name
Test status
Simulation time 65498581 ps
CPU time 1.11 seconds
Started Sep 09 08:56:23 PM UTC 24
Finished Sep 09 08:56:25 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104395409 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.4104395409
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.4156053613
Short name T46
Test name
Test status
Simulation time 1279665537 ps
CPU time 9.62 seconds
Started Sep 09 08:56:22 PM UTC 24
Finished Sep 09 08:56:33 PM UTC 24
Peak memory 242344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156053613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.4156053613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1587749419
Short name T216
Test name
Test status
Simulation time 301700488 ps
CPU time 2 seconds
Started Sep 09 08:56:23 PM UTC 24
Finished Sep 09 08:56:26 PM UTC 24
Peak memory 237396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587749419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1587749419
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.156657252
Short name T156
Test name
Test status
Simulation time 125620766 ps
CPU time 1.43 seconds
Started Sep 09 08:56:20 PM UTC 24
Finished Sep 09 08:56:23 PM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156657252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.156657252
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.1297919635
Short name T219
Test name
Test status
Simulation time 922707571 ps
CPU time 5.81 seconds
Started Sep 09 08:56:20 PM UTC 24
Finished Sep 09 08:56:27 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297919635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1297919635
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3266849470
Short name T214
Test name
Test status
Simulation time 137491742 ps
CPU time 1.7 seconds
Started Sep 09 08:56:22 PM UTC 24
Finished Sep 09 08:56:24 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266849470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3266849470
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.2606396826
Short name T191
Test name
Test status
Simulation time 189814679 ps
CPU time 2.27 seconds
Started Sep 09 08:56:18 PM UTC 24
Finished Sep 09 08:56:21 PM UTC 24
Peak memory 209120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606396826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2606396826
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.1257198606
Short name T239
Test name
Test status
Simulation time 2717311185 ps
CPU time 13.02 seconds
Started Sep 09 08:56:23 PM UTC 24
Finished Sep 09 08:56:37 PM UTC 24
Peak memory 218080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257198606 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1257198606
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.2086638733
Short name T153
Test name
Test status
Simulation time 269482770 ps
CPU time 2.89 seconds
Started Sep 09 08:56:22 PM UTC 24
Finished Sep 09 08:56:26 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086638733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2086638733
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.67502325
Short name T213
Test name
Test status
Simulation time 87280569 ps
CPU time 1.4 seconds
Started Sep 09 08:56:21 PM UTC 24
Finished Sep 09 08:56:23 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67502325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.67502325
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.1482953316
Short name T224
Test name
Test status
Simulation time 67832038 ps
CPU time 1.24 seconds
Started Sep 09 08:56:28 PM UTC 24
Finished Sep 09 08:56:30 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482953316 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1482953316
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.3076386737
Short name T47
Test name
Test status
Simulation time 1267675004 ps
CPU time 6.27 seconds
Started Sep 09 08:56:26 PM UTC 24
Finished Sep 09 08:56:33 PM UTC 24
Peak memory 241716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076386737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3076386737
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2071886607
Short name T223
Test name
Test status
Simulation time 302231664 ps
CPU time 1.41 seconds
Started Sep 09 08:56:27 PM UTC 24
Finished Sep 09 08:56:29 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071886607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.2071886607
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.773392203
Short name T217
Test name
Test status
Simulation time 213249620 ps
CPU time 1.56 seconds
Started Sep 09 08:56:24 PM UTC 24
Finished Sep 09 08:56:27 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773392203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.773392203
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.2248400476
Short name T231
Test name
Test status
Simulation time 1904787818 ps
CPU time 7.59 seconds
Started Sep 09 08:56:24 PM UTC 24
Finished Sep 09 08:56:33 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248400476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2248400476
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3626139846
Short name T221
Test name
Test status
Simulation time 114654416 ps
CPU time 1.56 seconds
Started Sep 09 08:56:26 PM UTC 24
Finished Sep 09 08:56:28 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626139846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3626139846
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.3806505765
Short name T218
Test name
Test status
Simulation time 122406648 ps
CPU time 1.85 seconds
Started Sep 09 08:56:24 PM UTC 24
Finished Sep 09 08:56:27 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806505765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3806505765
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.646805595
Short name T229
Test name
Test status
Simulation time 686739853 ps
CPU time 4.22 seconds
Started Sep 09 08:56:27 PM UTC 24
Finished Sep 09 08:56:32 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646805595 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.646805595
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.4038256049
Short name T222
Test name
Test status
Simulation time 145331167 ps
CPU time 2.73 seconds
Started Sep 09 08:56:26 PM UTC 24
Finished Sep 09 08:56:29 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038256049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.4038256049
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.4127116611
Short name T220
Test name
Test status
Simulation time 119946483 ps
CPU time 1.68 seconds
Started Sep 09 08:56:26 PM UTC 24
Finished Sep 09 08:56:28 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127116611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.4127116611
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.3446265811
Short name T235
Test name
Test status
Simulation time 65604817 ps
CPU time 1.24 seconds
Started Sep 09 08:56:33 PM UTC 24
Finished Sep 09 08:56:35 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446265811 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3446265811
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.3407248478
Short name T60
Test name
Test status
Simulation time 1274491767 ps
CPU time 8.94 seconds
Started Sep 09 08:56:32 PM UTC 24
Finished Sep 09 08:56:42 PM UTC 24
Peak memory 242316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407248478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.3407248478
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.982235392
Short name T233
Test name
Test status
Simulation time 301581928 ps
CPU time 2.03 seconds
Started Sep 09 08:56:32 PM UTC 24
Finished Sep 09 08:56:35 PM UTC 24
Peak memory 237832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982235392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.982235392
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.2430239687
Short name T225
Test name
Test status
Simulation time 221944701 ps
CPU time 1.62 seconds
Started Sep 09 08:56:28 PM UTC 24
Finished Sep 09 08:56:31 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430239687 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2430239687
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.1313733993
Short name T240
Test name
Test status
Simulation time 1866674332 ps
CPU time 7.6 seconds
Started Sep 09 08:56:29 PM UTC 24
Finished Sep 09 08:56:38 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313733993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1313733993
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2700746579
Short name T232
Test name
Test status
Simulation time 141947241 ps
CPU time 1.78 seconds
Started Sep 09 08:56:31 PM UTC 24
Finished Sep 09 08:56:33 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700746579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2700746579
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.836090129
Short name T226
Test name
Test status
Simulation time 195122316 ps
CPU time 2.04 seconds
Started Sep 09 08:56:28 PM UTC 24
Finished Sep 09 08:56:31 PM UTC 24
Peak memory 209120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836090129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.836090129
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.103545846
Short name T255
Test name
Test status
Simulation time 2749501996 ps
CPU time 13.99 seconds
Started Sep 09 08:56:32 PM UTC 24
Finished Sep 09 08:56:47 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103545846 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.103545846
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.2588682741
Short name T234
Test name
Test status
Simulation time 476539705 ps
CPU time 3.66 seconds
Started Sep 09 08:56:30 PM UTC 24
Finished Sep 09 08:56:35 PM UTC 24
Peak memory 217848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588682741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2588682741
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.1637605571
Short name T230
Test name
Test status
Simulation time 249945565 ps
CPU time 2.31 seconds
Started Sep 09 08:56:29 PM UTC 24
Finished Sep 09 08:56:33 PM UTC 24
Peak memory 209120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637605571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1637605571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.4205406492
Short name T242
Test name
Test status
Simulation time 57317443 ps
CPU time 1.11 seconds
Started Sep 09 08:56:37 PM UTC 24
Finished Sep 09 08:56:39 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205406492 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4205406492
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.2699146430
Short name T61
Test name
Test status
Simulation time 2247506581 ps
CPU time 8.43 seconds
Started Sep 09 08:56:37 PM UTC 24
Finished Sep 09 08:56:46 PM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699146430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2699146430
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2750454935
Short name T243
Test name
Test status
Simulation time 301243859 ps
CPU time 1.96 seconds
Started Sep 09 08:56:37 PM UTC 24
Finished Sep 09 08:56:39 PM UTC 24
Peak memory 237684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750454935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2750454935
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.2264227992
Short name T237
Test name
Test status
Simulation time 82069856 ps
CPU time 0.89 seconds
Started Sep 09 08:56:34 PM UTC 24
Finished Sep 09 08:56:36 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264227992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2264227992
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.95724160
Short name T253
Test name
Test status
Simulation time 1743830671 ps
CPU time 10.29 seconds
Started Sep 09 08:56:34 PM UTC 24
Finished Sep 09 08:56:46 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95724160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.95724160
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3834932270
Short name T241
Test name
Test status
Simulation time 186207774 ps
CPU time 2.06 seconds
Started Sep 09 08:56:35 PM UTC 24
Finished Sep 09 08:56:38 PM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834932270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3834932270
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.542516064
Short name T236
Test name
Test status
Simulation time 129858862 ps
CPU time 1.9 seconds
Started Sep 09 08:56:33 PM UTC 24
Finished Sep 09 08:56:36 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542516064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.542516064
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.1447007941
Short name T322
Test name
Test status
Simulation time 11610005694 ps
CPU time 47.49 seconds
Started Sep 09 08:56:37 PM UTC 24
Finished Sep 09 08:57:26 PM UTC 24
Peak memory 218228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447007941 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1447007941
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.441989940
Short name T244
Test name
Test status
Simulation time 470153704 ps
CPU time 4.33 seconds
Started Sep 09 08:56:34 PM UTC 24
Finished Sep 09 08:56:40 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441989940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.441989940
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.2645744945
Short name T238
Test name
Test status
Simulation time 83649526 ps
CPU time 1.31 seconds
Started Sep 09 08:56:34 PM UTC 24
Finished Sep 09 08:56:36 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645744945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2645744945
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.1114703491
Short name T42
Test name
Test status
Simulation time 164705959 ps
CPU time 1.69 seconds
Started Sep 09 08:54:45 PM UTC 24
Finished Sep 09 08:54:48 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114703491 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1114703491
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.2653512760
Short name T26
Test name
Test status
Simulation time 1279460826 ps
CPU time 6.22 seconds
Started Sep 09 08:54:40 PM UTC 24
Finished Sep 09 08:54:47 PM UTC 24
Peak memory 241672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653512760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2653512760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1069113044
Short name T39
Test name
Test status
Simulation time 301495181 ps
CPU time 2.25 seconds
Started Sep 09 08:54:41 PM UTC 24
Finished Sep 09 08:54:44 PM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069113044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1069113044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3439263559
Short name T14
Test name
Test status
Simulation time 122690309 ps
CPU time 1.29 seconds
Started Sep 09 08:54:33 PM UTC 24
Finished Sep 09 08:54:36 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439263559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3439263559
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1217006682
Short name T40
Test name
Test status
Simulation time 1375505842 ps
CPU time 9.23 seconds
Started Sep 09 08:54:34 PM UTC 24
Finished Sep 09 08:54:45 PM UTC 24
Peak memory 209224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217006682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1217006682
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.4112033240
Short name T54
Test name
Test status
Simulation time 8462468270 ps
CPU time 30.71 seconds
Started Sep 09 08:54:44 PM UTC 24
Finished Sep 09 08:55:16 PM UTC 24
Peak memory 242168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112033240 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.4112033240
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.212478691
Short name T37
Test name
Test status
Simulation time 154913148 ps
CPU time 1.98 seconds
Started Sep 09 08:54:40 PM UTC 24
Finished Sep 09 08:54:43 PM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212478691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.212478691
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.1746568143
Short name T23
Test name
Test status
Simulation time 118648086 ps
CPU time 1.77 seconds
Started Sep 09 08:54:32 PM UTC 24
Finished Sep 09 08:54:35 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746568143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1746568143
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.1450872807
Short name T36
Test name
Test status
Simulation time 106076609 ps
CPU time 2.17 seconds
Started Sep 09 08:54:37 PM UTC 24
Finished Sep 09 08:54:40 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450872807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1450872807
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.1556243471
Short name T35
Test name
Test status
Simulation time 123206084 ps
CPU time 1.53 seconds
Started Sep 09 08:54:36 PM UTC 24
Finished Sep 09 08:54:39 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556243471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1556243471
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.1577183327
Short name T251
Test name
Test status
Simulation time 65915733 ps
CPU time 1.25 seconds
Started Sep 09 08:56:43 PM UTC 24
Finished Sep 09 08:56:45 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577183327 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.1577183327
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3470685325
Short name T34
Test name
Test status
Simulation time 1956162570 ps
CPU time 10.62 seconds
Started Sep 09 08:56:40 PM UTC 24
Finished Sep 09 08:56:52 PM UTC 24
Peak memory 242396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470685325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3470685325
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.446339801
Short name T250
Test name
Test status
Simulation time 301948682 ps
CPU time 2.34 seconds
Started Sep 09 08:56:42 PM UTC 24
Finished Sep 09 08:56:45 PM UTC 24
Peak memory 237816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446339801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.446339801
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.476165270
Short name T245
Test name
Test status
Simulation time 205151683 ps
CPU time 1.43 seconds
Started Sep 09 08:56:38 PM UTC 24
Finished Sep 09 08:56:40 PM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476165270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.476165270
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.966693731
Short name T265
Test name
Test status
Simulation time 1690632031 ps
CPU time 10.74 seconds
Started Sep 09 08:56:39 PM UTC 24
Finished Sep 09 08:56:51 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966693731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.966693731
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.3427452755
Short name T248
Test name
Test status
Simulation time 108414681 ps
CPU time 1.63 seconds
Started Sep 09 08:56:40 PM UTC 24
Finished Sep 09 08:56:43 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427452755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.3427452755
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.545046200
Short name T246
Test name
Test status
Simulation time 123493842 ps
CPU time 1.86 seconds
Started Sep 09 08:56:38 PM UTC 24
Finished Sep 09 08:56:41 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545046200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.545046200
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.2690823963
Short name T266
Test name
Test status
Simulation time 1454550624 ps
CPU time 9.56 seconds
Started Sep 09 08:56:42 PM UTC 24
Finished Sep 09 08:56:52 PM UTC 24
Peak memory 209148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690823963 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2690823963
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.1367599900
Short name T249
Test name
Test status
Simulation time 136112951 ps
CPU time 2.55 seconds
Started Sep 09 08:56:40 PM UTC 24
Finished Sep 09 08:56:44 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367599900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1367599900
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.745309542
Short name T247
Test name
Test status
Simulation time 141231731 ps
CPU time 1.54 seconds
Started Sep 09 08:56:39 PM UTC 24
Finished Sep 09 08:56:42 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745309542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.745309542
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.45066431
Short name T259
Test name
Test status
Simulation time 62831244 ps
CPU time 1.22 seconds
Started Sep 09 08:56:48 PM UTC 24
Finished Sep 09 08:56:50 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45066431 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.45066431
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.2146338010
Short name T62
Test name
Test status
Simulation time 2266877489 ps
CPU time 12.76 seconds
Started Sep 09 08:56:47 PM UTC 24
Finished Sep 09 08:57:00 PM UTC 24
Peak memory 241940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146338010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2146338010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2188413044
Short name T258
Test name
Test status
Simulation time 304244750 ps
CPU time 1.92 seconds
Started Sep 09 08:56:47 PM UTC 24
Finished Sep 09 08:56:49 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188413044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2188413044
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.3957894894
Short name T252
Test name
Test status
Simulation time 165858932 ps
CPU time 1.41 seconds
Started Sep 09 08:56:43 PM UTC 24
Finished Sep 09 08:56:45 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957894894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3957894894
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.213948193
Short name T270
Test name
Test status
Simulation time 1126908363 ps
CPU time 8.83 seconds
Started Sep 09 08:56:44 PM UTC 24
Finished Sep 09 08:56:54 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213948193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.213948193
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.4287387399
Short name T257
Test name
Test status
Simulation time 182732642 ps
CPU time 1.44 seconds
Started Sep 09 08:56:46 PM UTC 24
Finished Sep 09 08:56:49 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287387399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.4287387399
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.4043712581
Short name T254
Test name
Test status
Simulation time 118494590 ps
CPU time 1.85 seconds
Started Sep 09 08:56:43 PM UTC 24
Finished Sep 09 08:56:46 PM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043712581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.4043712581
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.3686390940
Short name T348
Test name
Test status
Simulation time 12295705037 ps
CPU time 51.82 seconds
Started Sep 09 08:56:47 PM UTC 24
Finished Sep 09 08:57:40 PM UTC 24
Peak memory 220128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686390940 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3686390940
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.1803788037
Short name T261
Test name
Test status
Simulation time 149788548 ps
CPU time 2.76 seconds
Started Sep 09 08:56:46 PM UTC 24
Finished Sep 09 08:56:50 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803788037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.1803788037
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.2946048309
Short name T256
Test name
Test status
Simulation time 176083825 ps
CPU time 1.85 seconds
Started Sep 09 08:56:45 PM UTC 24
Finished Sep 09 08:56:48 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946048309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.2946048309
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.2447392941
Short name T268
Test name
Test status
Simulation time 60365768 ps
CPU time 1.02 seconds
Started Sep 09 08:56:52 PM UTC 24
Finished Sep 09 08:56:54 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447392941 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2447392941
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.2358709949
Short name T285
Test name
Test status
Simulation time 1265756817 ps
CPU time 9.22 seconds
Started Sep 09 08:56:51 PM UTC 24
Finished Sep 09 08:57:02 PM UTC 24
Peak memory 242400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358709949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2358709949
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2646727413
Short name T271
Test name
Test status
Simulation time 327449119 ps
CPU time 1.93 seconds
Started Sep 09 08:56:51 PM UTC 24
Finished Sep 09 08:56:54 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646727413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2646727413
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.2471080538
Short name T264
Test name
Test status
Simulation time 73040309 ps
CPU time 0.99 seconds
Started Sep 09 08:56:49 PM UTC 24
Finished Sep 09 08:56:51 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471080538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2471080538
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.2062755976
Short name T274
Test name
Test status
Simulation time 765823703 ps
CPU time 4.64 seconds
Started Sep 09 08:56:50 PM UTC 24
Finished Sep 09 08:56:56 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062755976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2062755976
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2247434550
Short name T269
Test name
Test status
Simulation time 101785361 ps
CPU time 1.64 seconds
Started Sep 09 08:56:51 PM UTC 24
Finished Sep 09 08:56:54 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247434550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2247434550
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.3241031654
Short name T262
Test name
Test status
Simulation time 118494518 ps
CPU time 1.78 seconds
Started Sep 09 08:56:48 PM UTC 24
Finished Sep 09 08:56:51 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241031654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3241031654
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.917504915
Short name T329
Test name
Test status
Simulation time 5611751522 ps
CPU time 36.92 seconds
Started Sep 09 08:56:51 PM UTC 24
Finished Sep 09 08:57:30 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917504915 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.917504915
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.3730533538
Short name T272
Test name
Test status
Simulation time 128238763 ps
CPU time 2.42 seconds
Started Sep 09 08:56:51 PM UTC 24
Finished Sep 09 08:56:55 PM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730533538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.3730533538
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.3598825229
Short name T267
Test name
Test status
Simulation time 99913884 ps
CPU time 1.55 seconds
Started Sep 09 08:56:50 PM UTC 24
Finished Sep 09 08:56:53 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598825229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3598825229
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.3781974087
Short name T278
Test name
Test status
Simulation time 63373242 ps
CPU time 1.18 seconds
Started Sep 09 08:56:55 PM UTC 24
Finished Sep 09 08:56:58 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781974087 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3781974087
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.1660035037
Short name T296
Test name
Test status
Simulation time 1948305435 ps
CPU time 12.51 seconds
Started Sep 09 08:56:55 PM UTC 24
Finished Sep 09 08:57:09 PM UTC 24
Peak memory 242004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660035037 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1660035037
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3799656811
Short name T279
Test name
Test status
Simulation time 305912132 ps
CPU time 1.63 seconds
Started Sep 09 08:56:55 PM UTC 24
Finished Sep 09 08:56:58 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799656811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3799656811
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.3600537468
Short name T273
Test name
Test status
Simulation time 118577348 ps
CPU time 0.97 seconds
Started Sep 09 08:56:53 PM UTC 24
Finished Sep 09 08:56:55 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600537468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3600537468
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.951574773
Short name T283
Test name
Test status
Simulation time 1129407266 ps
CPU time 5.05 seconds
Started Sep 09 08:56:53 PM UTC 24
Finished Sep 09 08:56:59 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951574773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.951574773
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3807340731
Short name T280
Test name
Test status
Simulation time 136440121 ps
CPU time 1.84 seconds
Started Sep 09 08:56:55 PM UTC 24
Finished Sep 09 08:56:58 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807340731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3807340731
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.3337496667
Short name T275
Test name
Test status
Simulation time 237608319 ps
CPU time 2.31 seconds
Started Sep 09 08:56:53 PM UTC 24
Finished Sep 09 08:56:56 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337496667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3337496667
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.683293264
Short name T349
Test name
Test status
Simulation time 6448781670 ps
CPU time 43.33 seconds
Started Sep 09 08:56:55 PM UTC 24
Finished Sep 09 08:57:40 PM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683293264 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.683293264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.2379733352
Short name T277
Test name
Test status
Simulation time 314455619 ps
CPU time 2.62 seconds
Started Sep 09 08:56:54 PM UTC 24
Finished Sep 09 08:56:58 PM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379733352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2379733352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.1661232119
Short name T276
Test name
Test status
Simulation time 183818957 ps
CPU time 1.87 seconds
Started Sep 09 08:56:54 PM UTC 24
Finished Sep 09 08:56:57 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661232119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.1661232119
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.2836002828
Short name T287
Test name
Test status
Simulation time 65901899 ps
CPU time 1.17 seconds
Started Sep 09 08:57:00 PM UTC 24
Finished Sep 09 08:57:02 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836002828 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2836002828
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.1205052005
Short name T298
Test name
Test status
Simulation time 1274958980 ps
CPU time 9.14 seconds
Started Sep 09 08:56:59 PM UTC 24
Finished Sep 09 08:57:09 PM UTC 24
Peak memory 241664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205052005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1205052005
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.539374286
Short name T227
Test name
Test status
Simulation time 301501529 ps
CPU time 2.01 seconds
Started Sep 09 08:56:59 PM UTC 24
Finished Sep 09 08:57:02 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539374286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.539374286
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.900273175
Short name T282
Test name
Test status
Simulation time 93205643 ps
CPU time 1.2 seconds
Started Sep 09 08:56:57 PM UTC 24
Finished Sep 09 08:56:59 PM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900273175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.900273175
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.3218141408
Short name T300
Test name
Test status
Simulation time 2044124389 ps
CPU time 12.91 seconds
Started Sep 09 08:56:57 PM UTC 24
Finished Sep 09 08:57:11 PM UTC 24
Peak memory 209320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218141408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.3218141408
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.2121912287
Short name T286
Test name
Test status
Simulation time 108525693 ps
CPU time 1.7 seconds
Started Sep 09 08:56:59 PM UTC 24
Finished Sep 09 08:57:02 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121912287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.2121912287
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.406930385
Short name T281
Test name
Test status
Simulation time 118533977 ps
CPU time 1.88 seconds
Started Sep 09 08:56:56 PM UTC 24
Finished Sep 09 08:56:58 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406930385 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.406930385
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3416849645
Short name T374
Test name
Test status
Simulation time 8711318384 ps
CPU time 49.72 seconds
Started Sep 09 08:56:59 PM UTC 24
Finished Sep 09 08:57:51 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416849645 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3416849645
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.4023554560
Short name T289
Test name
Test status
Simulation time 485289270 ps
CPU time 4.17 seconds
Started Sep 09 08:56:59 PM UTC 24
Finished Sep 09 08:57:04 PM UTC 24
Peak memory 209120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023554560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.4023554560
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.467652356
Short name T284
Test name
Test status
Simulation time 182202298 ps
CPU time 1.91 seconds
Started Sep 09 08:56:58 PM UTC 24
Finished Sep 09 08:57:01 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467652356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.467652356
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3222687695
Short name T292
Test name
Test status
Simulation time 59160430 ps
CPU time 1.14 seconds
Started Sep 09 08:57:05 PM UTC 24
Finished Sep 09 08:57:07 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222687695 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3222687695
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.1341439414
Short name T303
Test name
Test status
Simulation time 1271716935 ps
CPU time 7 seconds
Started Sep 09 08:57:04 PM UTC 24
Finished Sep 09 08:57:12 PM UTC 24
Peak memory 241960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341439414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.1341439414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.3217960379
Short name T294
Test name
Test status
Simulation time 302244294 ps
CPU time 1.83 seconds
Started Sep 09 08:57:05 PM UTC 24
Finished Sep 09 08:57:08 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217960379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.3217960379
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.3525380532
Short name T228
Test name
Test status
Simulation time 138576731 ps
CPU time 1.28 seconds
Started Sep 09 08:57:01 PM UTC 24
Finished Sep 09 08:57:04 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525380532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.3525380532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.507381132
Short name T297
Test name
Test status
Simulation time 1705539753 ps
CPU time 6.55 seconds
Started Sep 09 08:57:01 PM UTC 24
Finished Sep 09 08:57:09 PM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507381132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.507381132
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.4176126171
Short name T290
Test name
Test status
Simulation time 99528421 ps
CPU time 1.45 seconds
Started Sep 09 08:57:03 PM UTC 24
Finished Sep 09 08:57:05 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176126171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.4176126171
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.1058452238
Short name T288
Test name
Test status
Simulation time 203116552 ps
CPU time 2.47 seconds
Started Sep 09 08:57:00 PM UTC 24
Finished Sep 09 08:57:04 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058452238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1058452238
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.377472154
Short name T370
Test name
Test status
Simulation time 6564740242 ps
CPU time 42.69 seconds
Started Sep 09 08:57:05 PM UTC 24
Finished Sep 09 08:57:49 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377472154 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.377472154
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.2446554183
Short name T293
Test name
Test status
Simulation time 322529421 ps
CPU time 3.54 seconds
Started Sep 09 08:57:03 PM UTC 24
Finished Sep 09 08:57:07 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446554183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2446554183
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3705203152
Short name T291
Test name
Test status
Simulation time 220066696 ps
CPU time 1.99 seconds
Started Sep 09 08:57:03 PM UTC 24
Finished Sep 09 08:57:06 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705203152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3705203152
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.618148264
Short name T306
Test name
Test status
Simulation time 76992196 ps
CPU time 1.28 seconds
Started Sep 09 08:57:11 PM UTC 24
Finished Sep 09 08:57:13 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618148264 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.618148264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.2584101874
Short name T314
Test name
Test status
Simulation time 1270627013 ps
CPU time 8.49 seconds
Started Sep 09 08:57:10 PM UTC 24
Finished Sep 09 08:57:19 PM UTC 24
Peak memory 242316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584101874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2584101874
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2643007964
Short name T305
Test name
Test status
Simulation time 301334116 ps
CPU time 1.96 seconds
Started Sep 09 08:57:10 PM UTC 24
Finished Sep 09 08:57:13 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643007964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2643007964
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.1073930923
Short name T295
Test name
Test status
Simulation time 97572675 ps
CPU time 1.22 seconds
Started Sep 09 08:57:06 PM UTC 24
Finished Sep 09 08:57:08 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073930923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1073930923
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.2948865150
Short name T311
Test name
Test status
Simulation time 1674511028 ps
CPU time 8.28 seconds
Started Sep 09 08:57:08 PM UTC 24
Finished Sep 09 08:57:18 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948865150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2948865150
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2581871260
Short name T304
Test name
Test status
Simulation time 108730369 ps
CPU time 1.59 seconds
Started Sep 09 08:57:10 PM UTC 24
Finished Sep 09 08:57:12 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581871260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2581871260
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.4220770362
Short name T299
Test name
Test status
Simulation time 263205520 ps
CPU time 2.36 seconds
Started Sep 09 08:57:06 PM UTC 24
Finished Sep 09 08:57:10 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220770362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4220770362
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.579497830
Short name T350
Test name
Test status
Simulation time 4264106069 ps
CPU time 29.2 seconds
Started Sep 09 08:57:10 PM UTC 24
Finished Sep 09 08:57:40 PM UTC 24
Peak memory 220216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579497830 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.579497830
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.2495634876
Short name T301
Test name
Test status
Simulation time 105998003 ps
CPU time 2.1 seconds
Started Sep 09 08:57:08 PM UTC 24
Finished Sep 09 08:57:12 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495634876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2495634876
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.2824328479
Short name T302
Test name
Test status
Simulation time 167291909 ps
CPU time 2.11 seconds
Started Sep 09 08:57:08 PM UTC 24
Finished Sep 09 08:57:12 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824328479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2824328479
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.2902178741
Short name T315
Test name
Test status
Simulation time 72080738 ps
CPU time 1.25 seconds
Started Sep 09 08:57:18 PM UTC 24
Finished Sep 09 08:57:20 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902178741 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2902178741
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.2332392852
Short name T325
Test name
Test status
Simulation time 1965546702 ps
CPU time 11.1 seconds
Started Sep 09 08:57:15 PM UTC 24
Finished Sep 09 08:57:27 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332392852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2332392852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1208433158
Short name T312
Test name
Test status
Simulation time 302152961 ps
CPU time 1.92 seconds
Started Sep 09 08:57:16 PM UTC 24
Finished Sep 09 08:57:19 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208433158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1208433158
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.3237737389
Short name T307
Test name
Test status
Simulation time 154663099 ps
CPU time 1.38 seconds
Started Sep 09 08:57:12 PM UTC 24
Finished Sep 09 08:57:15 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237737389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3237737389
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.4012265663
Short name T318
Test name
Test status
Simulation time 1612625083 ps
CPU time 9.65 seconds
Started Sep 09 08:57:12 PM UTC 24
Finished Sep 09 08:57:23 PM UTC 24
Peak memory 209320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012265663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.4012265663
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3008199099
Short name T310
Test name
Test status
Simulation time 152791729 ps
CPU time 1.84 seconds
Started Sep 09 08:57:14 PM UTC 24
Finished Sep 09 08:57:17 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008199099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3008199099
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.2700632588
Short name T308
Test name
Test status
Simulation time 258987239 ps
CPU time 2.48 seconds
Started Sep 09 08:57:12 PM UTC 24
Finished Sep 09 08:57:16 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700632588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2700632588
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.2096911157
Short name T358
Test name
Test status
Simulation time 6250670640 ps
CPU time 25.71 seconds
Started Sep 09 08:57:17 PM UTC 24
Finished Sep 09 08:57:44 PM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096911157 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2096911157
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.813511170
Short name T313
Test name
Test status
Simulation time 363456093 ps
CPU time 3.48 seconds
Started Sep 09 08:57:13 PM UTC 24
Finished Sep 09 08:57:19 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813511170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.813511170
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.1995888427
Short name T309
Test name
Test status
Simulation time 103531949 ps
CPU time 1.47 seconds
Started Sep 09 08:57:13 PM UTC 24
Finished Sep 09 08:57:17 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995888427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1995888427
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.755949155
Short name T324
Test name
Test status
Simulation time 64782066 ps
CPU time 1.05 seconds
Started Sep 09 08:57:24 PM UTC 24
Finished Sep 09 08:57:26 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755949155 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.755949155
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.1760278114
Short name T335
Test name
Test status
Simulation time 2440832202 ps
CPU time 10.29 seconds
Started Sep 09 08:57:21 PM UTC 24
Finished Sep 09 08:57:33 PM UTC 24
Peak memory 241792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760278114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.1760278114
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.729905548
Short name T323
Test name
Test status
Simulation time 301418158 ps
CPU time 2 seconds
Started Sep 09 08:57:23 PM UTC 24
Finished Sep 09 08:57:26 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729905548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.729905548
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.4022318917
Short name T317
Test name
Test status
Simulation time 171948188 ps
CPU time 1.5 seconds
Started Sep 09 08:57:19 PM UTC 24
Finished Sep 09 08:57:22 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022318917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.4022318917
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.1866741855
Short name T331
Test name
Test status
Simulation time 1573665358 ps
CPU time 10.39 seconds
Started Sep 09 08:57:19 PM UTC 24
Finished Sep 09 08:57:31 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866741855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1866741855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.75507576
Short name T319
Test name
Test status
Simulation time 143864514 ps
CPU time 1.17 seconds
Started Sep 09 08:57:21 PM UTC 24
Finished Sep 09 08:57:24 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75507576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.75507576
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.3005082462
Short name T316
Test name
Test status
Simulation time 123689851 ps
CPU time 1.35 seconds
Started Sep 09 08:57:18 PM UTC 24
Finished Sep 09 08:57:20 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005082462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3005082462
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.857214960
Short name T340
Test name
Test status
Simulation time 2163543203 ps
CPU time 12.56 seconds
Started Sep 09 08:57:23 PM UTC 24
Finished Sep 09 08:57:37 PM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857214960 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.857214960
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.3517425669
Short name T321
Test name
Test status
Simulation time 305982299 ps
CPU time 2.95 seconds
Started Sep 09 08:57:20 PM UTC 24
Finished Sep 09 08:57:24 PM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517425669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3517425669
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.2258503517
Short name T320
Test name
Test status
Simulation time 244364513 ps
CPU time 2.3 seconds
Started Sep 09 08:57:20 PM UTC 24
Finished Sep 09 08:57:24 PM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258503517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.2258503517
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.1390717300
Short name T334
Test name
Test status
Simulation time 73034756 ps
CPU time 1.29 seconds
Started Sep 09 08:57:30 PM UTC 24
Finished Sep 09 08:57:32 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390717300 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1390717300
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.4156112911
Short name T345
Test name
Test status
Simulation time 1282578268 ps
CPU time 8.93 seconds
Started Sep 09 08:57:29 PM UTC 24
Finished Sep 09 08:57:39 PM UTC 24
Peak memory 241292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156112911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.4156112911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2814726122
Short name T333
Test name
Test status
Simulation time 302733373 ps
CPU time 2.04 seconds
Started Sep 09 08:57:29 PM UTC 24
Finished Sep 09 08:57:32 PM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814726122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2814726122
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.2937450320
Short name T327
Test name
Test status
Simulation time 167161526 ps
CPU time 1.46 seconds
Started Sep 09 08:57:25 PM UTC 24
Finished Sep 09 08:57:28 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937450320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2937450320
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.2244322713
Short name T336
Test name
Test status
Simulation time 894747790 ps
CPU time 6.68 seconds
Started Sep 09 08:57:25 PM UTC 24
Finished Sep 09 08:57:33 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244322713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2244322713
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1667678345
Short name T330
Test name
Test status
Simulation time 148578087 ps
CPU time 1.78 seconds
Started Sep 09 08:57:27 PM UTC 24
Finished Sep 09 08:57:30 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667678345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1667678345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.378779589
Short name T326
Test name
Test status
Simulation time 122189875 ps
CPU time 1.73 seconds
Started Sep 09 08:57:25 PM UTC 24
Finished Sep 09 08:57:28 PM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378779589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.378779589
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.3453723242
Short name T482
Test name
Test status
Simulation time 16256877494 ps
CPU time 63.52 seconds
Started Sep 09 08:57:29 PM UTC 24
Finished Sep 09 08:58:34 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453723242 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3453723242
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.1720802803
Short name T332
Test name
Test status
Simulation time 130402930 ps
CPU time 2.56 seconds
Started Sep 09 08:57:27 PM UTC 24
Finished Sep 09 08:57:31 PM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720802803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1720802803
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.3769235521
Short name T328
Test name
Test status
Simulation time 86688686 ps
CPU time 1.33 seconds
Started Sep 09 08:57:26 PM UTC 24
Finished Sep 09 08:57:29 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769235521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3769235521
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.2003442404
Short name T78
Test name
Test status
Simulation time 61315867 ps
CPU time 1.24 seconds
Started Sep 09 08:54:59 PM UTC 24
Finished Sep 09 08:55:01 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003442404 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2003442404
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.3350893418
Short name T43
Test name
Test status
Simulation time 2456184676 ps
CPU time 14.47 seconds
Started Sep 09 08:54:53 PM UTC 24
Finished Sep 09 08:55:08 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350893418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3350893418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3806773526
Short name T134
Test name
Test status
Simulation time 302067816 ps
CPU time 1.49 seconds
Started Sep 09 08:54:55 PM UTC 24
Finished Sep 09 08:54:57 PM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806773526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3806773526
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.64877265
Short name T15
Test name
Test status
Simulation time 105832164 ps
CPU time 1.26 seconds
Started Sep 09 08:54:47 PM UTC 24
Finished Sep 09 08:54:50 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64877265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.64877265
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.3167845511
Short name T77
Test name
Test status
Simulation time 1575133852 ps
CPU time 10.71 seconds
Started Sep 09 08:54:47 PM UTC 24
Finished Sep 09 08:54:59 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167845511 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3167845511
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.3109159870
Short name T75
Test name
Test status
Simulation time 17099673107 ps
CPU time 42.24 seconds
Started Sep 09 08:54:58 PM UTC 24
Finished Sep 09 08:55:42 PM UTC 24
Peak memory 241796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109159870 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3109159870
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.182729546
Short name T133
Test name
Test status
Simulation time 178526278 ps
CPU time 1.98 seconds
Started Sep 09 08:54:51 PM UTC 24
Finished Sep 09 08:54:54 PM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182729546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.182729546
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1229327905
Short name T81
Test name
Test status
Simulation time 197782811 ps
CPU time 2.3 seconds
Started Sep 09 08:54:46 PM UTC 24
Finished Sep 09 08:54:50 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229327905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1229327905
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.4264043896
Short name T84
Test name
Test status
Simulation time 3557347547 ps
CPU time 23.22 seconds
Started Sep 09 08:54:56 PM UTC 24
Finished Sep 09 08:55:21 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264043896 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.4264043896
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3432309517
Short name T83
Test name
Test status
Simulation time 426491743 ps
CPU time 3.93 seconds
Started Sep 09 08:54:51 PM UTC 24
Finished Sep 09 08:54:56 PM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432309517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3432309517
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.263552982
Short name T82
Test name
Test status
Simulation time 189774122 ps
CPU time 2.01 seconds
Started Sep 09 08:54:49 PM UTC 24
Finished Sep 09 08:54:52 PM UTC 24
Peak memory 208296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263552982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.263552982
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.1847214206
Short name T343
Test name
Test status
Simulation time 76908954 ps
CPU time 1.28 seconds
Started Sep 09 08:57:35 PM UTC 24
Finished Sep 09 08:57:39 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847214206 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1847214206
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.4065678460
Short name T353
Test name
Test status
Simulation time 1274298222 ps
CPU time 6.11 seconds
Started Sep 09 08:57:33 PM UTC 24
Finished Sep 09 08:57:42 PM UTC 24
Peak memory 242316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065678460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.4065678460
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.888003462
Short name T346
Test name
Test status
Simulation time 300523980 ps
CPU time 1.96 seconds
Started Sep 09 08:57:35 PM UTC 24
Finished Sep 09 08:57:39 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888003462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.888003462
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.1725596893
Short name T337
Test name
Test status
Simulation time 123454247 ps
CPU time 1.26 seconds
Started Sep 09 08:57:31 PM UTC 24
Finished Sep 09 08:57:33 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725596893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1725596893
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.1096414201
Short name T341
Test name
Test status
Simulation time 685160767 ps
CPU time 3.84 seconds
Started Sep 09 08:57:32 PM UTC 24
Finished Sep 09 08:57:37 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096414201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1096414201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2480103463
Short name T342
Test name
Test status
Simulation time 101322840 ps
CPU time 1.48 seconds
Started Sep 09 08:57:33 PM UTC 24
Finished Sep 09 08:57:37 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480103463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2480103463
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.2205060624
Short name T338
Test name
Test status
Simulation time 127278280 ps
CPU time 1.63 seconds
Started Sep 09 08:57:31 PM UTC 24
Finished Sep 09 08:57:34 PM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205060624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2205060624
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.3454884054
Short name T411
Test name
Test status
Simulation time 6703787408 ps
CPU time 30.91 seconds
Started Sep 09 08:57:35 PM UTC 24
Finished Sep 09 08:58:09 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454884054 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3454884054
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.1847190615
Short name T344
Test name
Test status
Simulation time 322861906 ps
CPU time 3.14 seconds
Started Sep 09 08:57:33 PM UTC 24
Finished Sep 09 08:57:39 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847190615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.1847190615
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.2322666350
Short name T339
Test name
Test status
Simulation time 188622038 ps
CPU time 1.51 seconds
Started Sep 09 08:57:32 PM UTC 24
Finished Sep 09 08:57:35 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322666350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2322666350
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.1058940359
Short name T360
Test name
Test status
Simulation time 83572591 ps
CPU time 1.29 seconds
Started Sep 09 08:57:42 PM UTC 24
Finished Sep 09 08:57:45 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058940359 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1058940359
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.2300721279
Short name T372
Test name
Test status
Simulation time 2442807641 ps
CPU time 8.99 seconds
Started Sep 09 08:57:40 PM UTC 24
Finished Sep 09 08:57:51 PM UTC 24
Peak memory 241792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300721279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2300721279
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.4045876715
Short name T355
Test name
Test status
Simulation time 302705867 ps
CPU time 1.75 seconds
Started Sep 09 08:57:40 PM UTC 24
Finished Sep 09 08:57:43 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045876715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.4045876715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.1096113423
Short name T351
Test name
Test status
Simulation time 196542221 ps
CPU time 1.39 seconds
Started Sep 09 08:57:38 PM UTC 24
Finished Sep 09 08:57:41 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096113423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1096113423
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.4192081335
Short name T362
Test name
Test status
Simulation time 768254888 ps
CPU time 5.54 seconds
Started Sep 09 08:57:38 PM UTC 24
Finished Sep 09 08:57:46 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192081335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.4192081335
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2919695885
Short name T352
Test name
Test status
Simulation time 148316474 ps
CPU time 1.26 seconds
Started Sep 09 08:57:39 PM UTC 24
Finished Sep 09 08:57:42 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919695885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2919695885
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.1419835575
Short name T347
Test name
Test status
Simulation time 118915784 ps
CPU time 1.76 seconds
Started Sep 09 08:57:36 PM UTC 24
Finished Sep 09 08:57:40 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419835575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1419835575
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.126346256
Short name T385
Test name
Test status
Simulation time 3897779697 ps
CPU time 14 seconds
Started Sep 09 08:57:41 PM UTC 24
Finished Sep 09 08:57:56 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126346256 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.126346256
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.1287800187
Short name T356
Test name
Test status
Simulation time 536611768 ps
CPU time 3.11 seconds
Started Sep 09 08:57:39 PM UTC 24
Finished Sep 09 08:57:44 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287800187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1287800187
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.2945618761
Short name T354
Test name
Test status
Simulation time 150075188 ps
CPU time 1.93 seconds
Started Sep 09 08:57:38 PM UTC 24
Finished Sep 09 08:57:42 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945618761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2945618761
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.4040025058
Short name T367
Test name
Test status
Simulation time 75119608 ps
CPU time 1.28 seconds
Started Sep 09 08:57:46 PM UTC 24
Finished Sep 09 08:57:48 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040025058 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.4040025058
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.2384660525
Short name T377
Test name
Test status
Simulation time 1267240249 ps
CPU time 5.71 seconds
Started Sep 09 08:57:44 PM UTC 24
Finished Sep 09 08:57:51 PM UTC 24
Peak memory 241332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384660525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2384660525
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2547842009
Short name T366
Test name
Test status
Simulation time 301452777 ps
CPU time 2.05 seconds
Started Sep 09 08:57:44 PM UTC 24
Finished Sep 09 08:57:48 PM UTC 24
Peak memory 237772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547842009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2547842009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.1381853165
Short name T359
Test name
Test status
Simulation time 203279454 ps
CPU time 1.42 seconds
Started Sep 09 08:57:42 PM UTC 24
Finished Sep 09 08:57:45 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381853165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1381853165
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.3442147675
Short name T373
Test name
Test status
Simulation time 1634719643 ps
CPU time 7.09 seconds
Started Sep 09 08:57:42 PM UTC 24
Finished Sep 09 08:57:51 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442147675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3442147675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.338074626
Short name T364
Test name
Test status
Simulation time 149290419 ps
CPU time 1.71 seconds
Started Sep 09 08:57:43 PM UTC 24
Finished Sep 09 08:57:46 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338074626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.338074626
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.2858203589
Short name T361
Test name
Test status
Simulation time 113403103 ps
CPU time 1.84 seconds
Started Sep 09 08:57:42 PM UTC 24
Finished Sep 09 08:57:45 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858203589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2858203589
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.2434076385
Short name T431
Test name
Test status
Simulation time 5714453738 ps
CPU time 29.53 seconds
Started Sep 09 08:57:44 PM UTC 24
Finished Sep 09 08:58:16 PM UTC 24
Peak memory 218080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434076385 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2434076385
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.2295957692
Short name T365
Test name
Test status
Simulation time 134072187 ps
CPU time 2.33 seconds
Started Sep 09 08:57:43 PM UTC 24
Finished Sep 09 08:57:47 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295957692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.2295957692
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.643727194
Short name T363
Test name
Test status
Simulation time 89826354 ps
CPU time 1.39 seconds
Started Sep 09 08:57:43 PM UTC 24
Finished Sep 09 08:57:46 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643727194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.643727194
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.1327688100
Short name T378
Test name
Test status
Simulation time 81490430 ps
CPU time 1.31 seconds
Started Sep 09 08:57:49 PM UTC 24
Finished Sep 09 08:57:52 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327688100 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1327688100
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.3685344520
Short name T403
Test name
Test status
Simulation time 2434501391 ps
CPU time 14.15 seconds
Started Sep 09 08:57:48 PM UTC 24
Finished Sep 09 08:58:04 PM UTC 24
Peak memory 242444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685344520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3685344520
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3995042009
Short name T376
Test name
Test status
Simulation time 301910528 ps
CPU time 1.28 seconds
Started Sep 09 08:57:48 PM UTC 24
Finished Sep 09 08:57:51 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995042009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3995042009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.1352494540
Short name T368
Test name
Test status
Simulation time 219569180 ps
CPU time 1.57 seconds
Started Sep 09 08:57:46 PM UTC 24
Finished Sep 09 08:57:48 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352494540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1352494540
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.1547201222
Short name T392
Test name
Test status
Simulation time 1674340026 ps
CPU time 11.44 seconds
Started Sep 09 08:57:47 PM UTC 24
Finished Sep 09 08:58:00 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547201222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1547201222
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3023659344
Short name T375
Test name
Test status
Simulation time 107355481 ps
CPU time 1.55 seconds
Started Sep 09 08:57:48 PM UTC 24
Finished Sep 09 08:57:51 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023659344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3023659344
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.863178939
Short name T369
Test name
Test status
Simulation time 114069446 ps
CPU time 1.83 seconds
Started Sep 09 08:57:46 PM UTC 24
Finished Sep 09 08:57:49 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863178939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.863178939
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.886117986
Short name T489
Test name
Test status
Simulation time 12867418847 ps
CPU time 45.16 seconds
Started Sep 09 08:57:49 PM UTC 24
Finished Sep 09 08:58:37 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886117986 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.886117986
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.4140097652
Short name T357
Test name
Test status
Simulation time 114982457 ps
CPU time 2.11 seconds
Started Sep 09 08:57:47 PM UTC 24
Finished Sep 09 08:57:50 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140097652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.4140097652
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.1362241406
Short name T371
Test name
Test status
Simulation time 72831086 ps
CPU time 1.25 seconds
Started Sep 09 08:57:47 PM UTC 24
Finished Sep 09 08:57:49 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362241406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1362241406
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.3673759532
Short name T383
Test name
Test status
Simulation time 74909168 ps
CPU time 1.32 seconds
Started Sep 09 08:57:52 PM UTC 24
Finished Sep 09 08:57:55 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673759532 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3673759532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.2562787934
Short name T399
Test name
Test status
Simulation time 1274747445 ps
CPU time 10.24 seconds
Started Sep 09 08:57:52 PM UTC 24
Finished Sep 09 08:58:04 PM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562787934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2562787934
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2045126809
Short name T384
Test name
Test status
Simulation time 301908834 ps
CPU time 2.04 seconds
Started Sep 09 08:57:52 PM UTC 24
Finished Sep 09 08:57:55 PM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045126809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2045126809
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.2867359965
Short name T379
Test name
Test status
Simulation time 167867805 ps
CPU time 1.4 seconds
Started Sep 09 08:57:51 PM UTC 24
Finished Sep 09 08:57:53 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867359965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2867359965
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.451357931
Short name T393
Test name
Test status
Simulation time 1595385848 ps
CPU time 7.84 seconds
Started Sep 09 08:57:51 PM UTC 24
Finished Sep 09 08:58:00 PM UTC 24
Peak memory 209280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451357931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.451357931
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.3419606506
Short name T381
Test name
Test status
Simulation time 101650441 ps
CPU time 1.53 seconds
Started Sep 09 08:57:52 PM UTC 24
Finished Sep 09 08:57:55 PM UTC 24
Peak memory 208292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419606506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.3419606506
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.3273001414
Short name T380
Test name
Test status
Simulation time 188286859 ps
CPU time 2.43 seconds
Started Sep 09 08:57:49 PM UTC 24
Finished Sep 09 08:57:53 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273001414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.3273001414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.1031659705
Short name T407
Test name
Test status
Simulation time 2907425635 ps
CPU time 11.95 seconds
Started Sep 09 08:57:52 PM UTC 24
Finished Sep 09 08:58:05 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031659705 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1031659705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.611474528
Short name T388
Test name
Test status
Simulation time 326616702 ps
CPU time 3.47 seconds
Started Sep 09 08:57:52 PM UTC 24
Finished Sep 09 08:57:57 PM UTC 24
Peak memory 217792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611474528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.611474528
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.1023831133
Short name T382
Test name
Test status
Simulation time 145038263 ps
CPU time 1.65 seconds
Started Sep 09 08:57:52 PM UTC 24
Finished Sep 09 08:57:55 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023831133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1023831133
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.1985575208
Short name T391
Test name
Test status
Simulation time 75069418 ps
CPU time 1.29 seconds
Started Sep 09 08:57:57 PM UTC 24
Finished Sep 09 08:58:00 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985575208 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1985575208
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.4082325602
Short name T410
Test name
Test status
Simulation time 1969704378 ps
CPU time 10.68 seconds
Started Sep 09 08:57:56 PM UTC 24
Finished Sep 09 08:58:08 PM UTC 24
Peak memory 241732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082325602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.4082325602
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.658793998
Short name T394
Test name
Test status
Simulation time 301608431 ps
CPU time 2.08 seconds
Started Sep 09 08:57:57 PM UTC 24
Finished Sep 09 08:58:00 PM UTC 24
Peak memory 237768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658793998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.658793998
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.3527991690
Short name T386
Test name
Test status
Simulation time 98522337 ps
CPU time 1.04 seconds
Started Sep 09 08:57:54 PM UTC 24
Finished Sep 09 08:57:56 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527991690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3527991690
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.2147532255
Short name T405
Test name
Test status
Simulation time 1394425948 ps
CPU time 9.56 seconds
Started Sep 09 08:57:55 PM UTC 24
Finished Sep 09 08:58:05 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147532255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2147532255
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.4211896981
Short name T390
Test name
Test status
Simulation time 181457292 ps
CPU time 2 seconds
Started Sep 09 08:57:56 PM UTC 24
Finished Sep 09 08:57:59 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211896981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.4211896981
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.3164528116
Short name T387
Test name
Test status
Simulation time 192568012 ps
CPU time 2.1 seconds
Started Sep 09 08:57:53 PM UTC 24
Finished Sep 09 08:57:57 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164528116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3164528116
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.816702965
Short name T430
Test name
Test status
Simulation time 4442431407 ps
CPU time 17.14 seconds
Started Sep 09 08:57:57 PM UTC 24
Finished Sep 09 08:58:15 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816702965 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.816702965
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.522341697
Short name T396
Test name
Test status
Simulation time 545740722 ps
CPU time 3.92 seconds
Started Sep 09 08:57:56 PM UTC 24
Finished Sep 09 08:58:01 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522341697 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.522341697
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.1695270128
Short name T389
Test name
Test status
Simulation time 106069812 ps
CPU time 1.48 seconds
Started Sep 09 08:57:56 PM UTC 24
Finished Sep 09 08:57:58 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695270128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1695270128
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.424406857
Short name T404
Test name
Test status
Simulation time 72994583 ps
CPU time 1.22 seconds
Started Sep 09 08:58:02 PM UTC 24
Finished Sep 09 08:58:04 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424406857 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.424406857
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.669292380
Short name T417
Test name
Test status
Simulation time 1987083659 ps
CPU time 7.95 seconds
Started Sep 09 08:58:01 PM UTC 24
Finished Sep 09 08:58:10 PM UTC 24
Peak memory 241240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669292380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.669292380
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1486913036
Short name T400
Test name
Test status
Simulation time 302747352 ps
CPU time 1.9 seconds
Started Sep 09 08:58:01 PM UTC 24
Finished Sep 09 08:58:04 PM UTC 24
Peak memory 237188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486913036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1486913036
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.853148439
Short name T397
Test name
Test status
Simulation time 120452558 ps
CPU time 1.32 seconds
Started Sep 09 08:57:59 PM UTC 24
Finished Sep 09 08:58:02 PM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853148439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.853148439
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.1515461123
Short name T418
Test name
Test status
Simulation time 1767707176 ps
CPU time 9.51 seconds
Started Sep 09 08:57:59 PM UTC 24
Finished Sep 09 08:58:10 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515461123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1515461123
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3936694613
Short name T401
Test name
Test status
Simulation time 180942550 ps
CPU time 1.91 seconds
Started Sep 09 08:58:01 PM UTC 24
Finished Sep 09 08:58:04 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936694613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3936694613
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.3519061650
Short name T395
Test name
Test status
Simulation time 116361501 ps
CPU time 1.94 seconds
Started Sep 09 08:57:57 PM UTC 24
Finished Sep 09 08:58:00 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519061650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3519061650
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.3012987711
Short name T451
Test name
Test status
Simulation time 5037693657 ps
CPU time 20.69 seconds
Started Sep 09 08:58:02 PM UTC 24
Finished Sep 09 08:58:24 PM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012987711 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3012987711
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.2644278475
Short name T402
Test name
Test status
Simulation time 317608049 ps
CPU time 2.44 seconds
Started Sep 09 08:58:01 PM UTC 24
Finished Sep 09 08:58:04 PM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644278475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2644278475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.3791910751
Short name T398
Test name
Test status
Simulation time 122402606 ps
CPU time 1.61 seconds
Started Sep 09 08:58:01 PM UTC 24
Finished Sep 09 08:58:03 PM UTC 24
Peak memory 208096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791910751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3791910751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.3672461618
Short name T412
Test name
Test status
Simulation time 59956113 ps
CPU time 1.22 seconds
Started Sep 09 08:58:06 PM UTC 24
Finished Sep 09 08:58:09 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672461618 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3672461618
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.3857533087
Short name T429
Test name
Test status
Simulation time 1959211417 ps
CPU time 8.09 seconds
Started Sep 09 08:58:06 PM UTC 24
Finished Sep 09 08:58:15 PM UTC 24
Peak memory 242404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857533087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3857533087
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.4023581028
Short name T415
Test name
Test status
Simulation time 301566656 ps
CPU time 1.81 seconds
Started Sep 09 08:58:06 PM UTC 24
Finished Sep 09 08:58:09 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023581028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.4023581028
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.3828736067
Short name T408
Test name
Test status
Simulation time 206737546 ps
CPU time 1.56 seconds
Started Sep 09 08:58:04 PM UTC 24
Finished Sep 09 08:58:07 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828736067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3828736067
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.133504873
Short name T423
Test name
Test status
Simulation time 1450801604 ps
CPU time 7.36 seconds
Started Sep 09 08:58:04 PM UTC 24
Finished Sep 09 08:58:13 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133504873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.133504873
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2954144963
Short name T414
Test name
Test status
Simulation time 103864221 ps
CPU time 1.64 seconds
Started Sep 09 08:58:06 PM UTC 24
Finished Sep 09 08:58:09 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954144963 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2954144963
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.984141904
Short name T406
Test name
Test status
Simulation time 116367031 ps
CPU time 1.99 seconds
Started Sep 09 08:58:02 PM UTC 24
Finished Sep 09 08:58:05 PM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984141904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.984141904
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.3656653601
Short name T461
Test name
Test status
Simulation time 3528975263 ps
CPU time 20.33 seconds
Started Sep 09 08:58:06 PM UTC 24
Finished Sep 09 08:58:28 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656653601 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3656653601
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.3966901809
Short name T416
Test name
Test status
Simulation time 462125592 ps
CPU time 3.84 seconds
Started Sep 09 08:58:05 PM UTC 24
Finished Sep 09 08:58:09 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966901809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3966901809
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.1400777750
Short name T409
Test name
Test status
Simulation time 142064799 ps
CPU time 1.77 seconds
Started Sep 09 08:58:05 PM UTC 24
Finished Sep 09 08:58:07 PM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400777750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1400777750
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.3775544309
Short name T424
Test name
Test status
Simulation time 112124185 ps
CPU time 1.11 seconds
Started Sep 09 08:58:11 PM UTC 24
Finished Sep 09 08:58:13 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775544309 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3775544309
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.1546442660
Short name T447
Test name
Test status
Simulation time 1971122028 ps
CPU time 12.02 seconds
Started Sep 09 08:58:10 PM UTC 24
Finished Sep 09 08:58:23 PM UTC 24
Peak memory 242428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546442660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.1546442660
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2569319749
Short name T422
Test name
Test status
Simulation time 302483825 ps
CPU time 1.98 seconds
Started Sep 09 08:58:10 PM UTC 24
Finished Sep 09 08:58:13 PM UTC 24
Peak memory 237564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569319749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2569319749
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.3439304875
Short name T419
Test name
Test status
Simulation time 169483478 ps
CPU time 1.4 seconds
Started Sep 09 08:58:08 PM UTC 24
Finished Sep 09 08:58:11 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439304875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.3439304875
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.3635133406
Short name T433
Test name
Test status
Simulation time 1275216060 ps
CPU time 7.43 seconds
Started Sep 09 08:58:08 PM UTC 24
Finished Sep 09 08:58:17 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635133406 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3635133406
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2749111884
Short name T421
Test name
Test status
Simulation time 154987750 ps
CPU time 1.76 seconds
Started Sep 09 08:58:10 PM UTC 24
Finished Sep 09 08:58:13 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749111884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2749111884
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.2777028313
Short name T413
Test name
Test status
Simulation time 108319624 ps
CPU time 1.32 seconds
Started Sep 09 08:58:06 PM UTC 24
Finished Sep 09 08:58:09 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777028313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2777028313
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.2380588956
Short name T506
Test name
Test status
Simulation time 7633627363 ps
CPU time 30.22 seconds
Started Sep 09 08:58:10 PM UTC 24
Finished Sep 09 08:58:42 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380588956 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.2380588956
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.2829952413
Short name T428
Test name
Test status
Simulation time 524027520 ps
CPU time 4.59 seconds
Started Sep 09 08:58:10 PM UTC 24
Finished Sep 09 08:58:15 PM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829952413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2829952413
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.3879325705
Short name T420
Test name
Test status
Simulation time 132737522 ps
CPU time 1.78 seconds
Started Sep 09 08:58:09 PM UTC 24
Finished Sep 09 08:58:11 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879325705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3879325705
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.2498829396
Short name T434
Test name
Test status
Simulation time 53531243 ps
CPU time 1.14 seconds
Started Sep 09 08:58:15 PM UTC 24
Finished Sep 09 08:58:17 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498829396 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2498829396
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.2855919675
Short name T455
Test name
Test status
Simulation time 2465667724 ps
CPU time 11.11 seconds
Started Sep 09 08:58:14 PM UTC 24
Finished Sep 09 08:58:26 PM UTC 24
Peak memory 242440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855919675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2855919675
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3805979719
Short name T435
Test name
Test status
Simulation time 301276234 ps
CPU time 2.22 seconds
Started Sep 09 08:58:15 PM UTC 24
Finished Sep 09 08:58:18 PM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805979719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3805979719
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.1401708307
Short name T425
Test name
Test status
Simulation time 182873414 ps
CPU time 1.49 seconds
Started Sep 09 08:58:11 PM UTC 24
Finished Sep 09 08:58:14 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401708307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1401708307
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.1895951149
Short name T448
Test name
Test status
Simulation time 1737498092 ps
CPU time 9.61 seconds
Started Sep 09 08:58:12 PM UTC 24
Finished Sep 09 08:58:23 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895951149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1895951149
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.1564718805
Short name T432
Test name
Test status
Simulation time 107992535 ps
CPU time 1.22 seconds
Started Sep 09 08:58:14 PM UTC 24
Finished Sep 09 08:58:16 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564718805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.1564718805
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.3819142829
Short name T426
Test name
Test status
Simulation time 187444417 ps
CPU time 2.17 seconds
Started Sep 09 08:58:11 PM UTC 24
Finished Sep 09 08:58:14 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819142829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3819142829
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.404870446
Short name T467
Test name
Test status
Simulation time 3130481875 ps
CPU time 13.1 seconds
Started Sep 09 08:58:15 PM UTC 24
Finished Sep 09 08:58:29 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404870446 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.404870446
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.1282636503
Short name T438
Test name
Test status
Simulation time 493778339 ps
CPU time 4.41 seconds
Started Sep 09 08:58:14 PM UTC 24
Finished Sep 09 08:58:19 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282636503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.1282636503
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.3150273907
Short name T427
Test name
Test status
Simulation time 98114070 ps
CPU time 1.33 seconds
Started Sep 09 08:58:12 PM UTC 24
Finished Sep 09 08:58:15 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150273907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.3150273907
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.3965669349
Short name T53
Test name
Test status
Simulation time 67735256 ps
CPU time 1.21 seconds
Started Sep 09 08:55:13 PM UTC 24
Finished Sep 09 08:55:16 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965669349 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3965669349
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.1390037558
Short name T27
Test name
Test status
Simulation time 1978806372 ps
CPU time 12.05 seconds
Started Sep 09 08:55:09 PM UTC 24
Finished Sep 09 08:55:22 PM UTC 24
Peak memory 241672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390037558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.1390037558
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1435929087
Short name T51
Test name
Test status
Simulation time 303780808 ps
CPU time 1.93 seconds
Started Sep 09 08:55:10 PM UTC 24
Finished Sep 09 08:55:13 PM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435929087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1435929087
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.853038852
Short name T16
Test name
Test status
Simulation time 157607324 ps
CPU time 1.43 seconds
Started Sep 09 08:55:03 PM UTC 24
Finished Sep 09 08:55:05 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853038852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.853038852
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.2748303632
Short name T49
Test name
Test status
Simulation time 857910439 ps
CPU time 6.76 seconds
Started Sep 09 08:55:03 PM UTC 24
Finished Sep 09 08:55:10 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748303632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2748303632
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.3812265557
Short name T76
Test name
Test status
Simulation time 16577214653 ps
CPU time 30.65 seconds
Started Sep 09 08:55:11 PM UTC 24
Finished Sep 09 08:55:43 PM UTC 24
Peak memory 242396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812265557 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3812265557
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.432777326
Short name T50
Test name
Test status
Simulation time 140662456 ps
CPU time 1.72 seconds
Started Sep 09 08:55:08 PM UTC 24
Finished Sep 09 08:55:11 PM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432777326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.432777326
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2444169914
Short name T79
Test name
Test status
Simulation time 201536905 ps
CPU time 2.47 seconds
Started Sep 09 08:55:00 PM UTC 24
Finished Sep 09 08:55:04 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444169914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2444169914
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.3667303425
Short name T52
Test name
Test status
Simulation time 232166414 ps
CPU time 2.41 seconds
Started Sep 09 08:55:11 PM UTC 24
Finished Sep 09 08:55:15 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667303425 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3667303425
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.2903178232
Short name T48
Test name
Test status
Simulation time 115983786 ps
CPU time 2.24 seconds
Started Sep 09 08:55:06 PM UTC 24
Finished Sep 09 08:55:09 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903178232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.2903178232
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.1184558460
Short name T80
Test name
Test status
Simulation time 104619688 ps
CPU time 1.56 seconds
Started Sep 09 08:55:05 PM UTC 24
Finished Sep 09 08:55:07 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184558460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1184558460
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.763251414
Short name T444
Test name
Test status
Simulation time 68578803 ps
CPU time 1.19 seconds
Started Sep 09 08:58:20 PM UTC 24
Finished Sep 09 08:58:22 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763251414 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.763251414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.884961075
Short name T456
Test name
Test status
Simulation time 1268204628 ps
CPU time 7.37 seconds
Started Sep 09 08:58:18 PM UTC 24
Finished Sep 09 08:58:26 PM UTC 24
Peak memory 242248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884961075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.884961075
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3291054817
Short name T441
Test name
Test status
Simulation time 303456226 ps
CPU time 1.94 seconds
Started Sep 09 08:58:18 PM UTC 24
Finished Sep 09 08:58:21 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291054817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3291054817
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.1370693559
Short name T436
Test name
Test status
Simulation time 212942615 ps
CPU time 1.59 seconds
Started Sep 09 08:58:16 PM UTC 24
Finished Sep 09 08:58:19 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370693559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1370693559
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.4191281461
Short name T445
Test name
Test status
Simulation time 1287291547 ps
CPU time 5.18 seconds
Started Sep 09 08:58:16 PM UTC 24
Finished Sep 09 08:58:23 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191281461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.4191281461
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1964642364
Short name T440
Test name
Test status
Simulation time 108413845 ps
CPU time 1.62 seconds
Started Sep 09 08:58:18 PM UTC 24
Finished Sep 09 08:58:20 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964642364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1964642364
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.3756978114
Short name T439
Test name
Test status
Simulation time 199080232 ps
CPU time 2.31 seconds
Started Sep 09 08:58:16 PM UTC 24
Finished Sep 09 08:58:20 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756978114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3756978114
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.690077841
Short name T443
Test name
Test status
Simulation time 114403854 ps
CPU time 1.52 seconds
Started Sep 09 08:58:19 PM UTC 24
Finished Sep 09 08:58:21 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690077841 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.690077841
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.4123617532
Short name T442
Test name
Test status
Simulation time 360330671 ps
CPU time 3.38 seconds
Started Sep 09 08:58:16 PM UTC 24
Finished Sep 09 08:58:21 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123617532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4123617532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.2597842927
Short name T437
Test name
Test status
Simulation time 110398258 ps
CPU time 1.58 seconds
Started Sep 09 08:58:16 PM UTC 24
Finished Sep 09 08:58:19 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597842927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2597842927
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.435517485
Short name T457
Test name
Test status
Simulation time 76523262 ps
CPU time 1.31 seconds
Started Sep 09 08:58:24 PM UTC 24
Finished Sep 09 08:58:26 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435517485 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.435517485
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.3666620791
Short name T471
Test name
Test status
Simulation time 1965097448 ps
CPU time 7.68 seconds
Started Sep 09 08:58:23 PM UTC 24
Finished Sep 09 08:58:31 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666620791 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3666620791
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.573515786
Short name T454
Test name
Test status
Simulation time 302407524 ps
CPU time 1.44 seconds
Started Sep 09 08:58:23 PM UTC 24
Finished Sep 09 08:58:25 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573515786 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.573515786
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.3411969449
Short name T446
Test name
Test status
Simulation time 221156899 ps
CPU time 1.7 seconds
Started Sep 09 08:58:20 PM UTC 24
Finished Sep 09 08:58:23 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411969449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3411969449
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.3111766353
Short name T460
Test name
Test status
Simulation time 982578091 ps
CPU time 6.18 seconds
Started Sep 09 08:58:20 PM UTC 24
Finished Sep 09 08:58:27 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111766353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3111766353
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2390174358
Short name T450
Test name
Test status
Simulation time 150916107 ps
CPU time 1.56 seconds
Started Sep 09 08:58:21 PM UTC 24
Finished Sep 09 08:58:24 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390174358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2390174358
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.2868124163
Short name T449
Test name
Test status
Simulation time 257536251 ps
CPU time 2.66 seconds
Started Sep 09 08:58:20 PM UTC 24
Finished Sep 09 08:58:24 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868124163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2868124163
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.636915025
Short name T490
Test name
Test status
Simulation time 3015260248 ps
CPU time 11.77 seconds
Started Sep 09 08:58:24 PM UTC 24
Finished Sep 09 08:58:37 PM UTC 24
Peak memory 209380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636915025 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.636915025
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.1816444796
Short name T453
Test name
Test status
Simulation time 140868274 ps
CPU time 2.53 seconds
Started Sep 09 08:58:21 PM UTC 24
Finished Sep 09 08:58:25 PM UTC 24
Peak memory 209120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816444796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1816444796
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.2502926825
Short name T452
Test name
Test status
Simulation time 196117780 ps
CPU time 1.99 seconds
Started Sep 09 08:58:21 PM UTC 24
Finished Sep 09 08:58:24 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502926825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2502926825
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.894634648
Short name T465
Test name
Test status
Simulation time 74989728 ps
CPU time 1.26 seconds
Started Sep 09 08:58:27 PM UTC 24
Finished Sep 09 08:58:29 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894634648 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.894634648
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.1929038345
Short name T480
Test name
Test status
Simulation time 1278335084 ps
CPU time 5.86 seconds
Started Sep 09 08:58:27 PM UTC 24
Finished Sep 09 08:58:34 PM UTC 24
Peak memory 242340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929038345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1929038345
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3795154398
Short name T468
Test name
Test status
Simulation time 301441700 ps
CPU time 1.76 seconds
Started Sep 09 08:58:27 PM UTC 24
Finished Sep 09 08:58:30 PM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795154398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3795154398
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.435096182
Short name T458
Test name
Test status
Simulation time 187863746 ps
CPU time 1.46 seconds
Started Sep 09 08:58:24 PM UTC 24
Finished Sep 09 08:58:26 PM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435096182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.435096182
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.289023848
Short name T479
Test name
Test status
Simulation time 999290631 ps
CPU time 6.84 seconds
Started Sep 09 08:58:25 PM UTC 24
Finished Sep 09 08:58:33 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289023848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.289023848
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.47273234
Short name T463
Test name
Test status
Simulation time 148957545 ps
CPU time 1.95 seconds
Started Sep 09 08:58:25 PM UTC 24
Finished Sep 09 08:58:28 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47273234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.47273234
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.2347634775
Short name T459
Test name
Test status
Simulation time 201239191 ps
CPU time 2.46 seconds
Started Sep 09 08:58:24 PM UTC 24
Finished Sep 09 08:58:27 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347634775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2347634775
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.2287723198
Short name T538
Test name
Test status
Simulation time 5184907977 ps
CPU time 24.4 seconds
Started Sep 09 08:58:27 PM UTC 24
Finished Sep 09 08:58:52 PM UTC 24
Peak memory 218164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287723198 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2287723198
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.3012884817
Short name T464
Test name
Test status
Simulation time 136706199 ps
CPU time 2.48 seconds
Started Sep 09 08:58:25 PM UTC 24
Finished Sep 09 08:58:29 PM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012884817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3012884817
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.3333708740
Short name T462
Test name
Test status
Simulation time 158856346 ps
CPU time 1.86 seconds
Started Sep 09 08:58:25 PM UTC 24
Finished Sep 09 08:58:28 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333708740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3333708740
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.1630544121
Short name T477
Test name
Test status
Simulation time 66956615 ps
CPU time 1.17 seconds
Started Sep 09 08:58:31 PM UTC 24
Finished Sep 09 08:58:33 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630544121 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1630544121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.4099806722
Short name T492
Test name
Test status
Simulation time 1278296473 ps
CPU time 6.91 seconds
Started Sep 09 08:58:29 PM UTC 24
Finished Sep 09 08:58:37 PM UTC 24
Peak memory 241720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099806722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.4099806722
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4053669964
Short name T473
Test name
Test status
Simulation time 301959472 ps
CPU time 1.79 seconds
Started Sep 09 08:58:29 PM UTC 24
Finished Sep 09 08:58:32 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053669964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4053669964
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.2496251512
Short name T466
Test name
Test status
Simulation time 177609862 ps
CPU time 1.21 seconds
Started Sep 09 08:58:27 PM UTC 24
Finished Sep 09 08:58:29 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496251512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.2496251512
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.4042621888
Short name T485
Test name
Test status
Simulation time 1520493466 ps
CPU time 6.12 seconds
Started Sep 09 08:58:28 PM UTC 24
Finished Sep 09 08:58:35 PM UTC 24
Peak memory 209212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042621888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.4042621888
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2222185352
Short name T472
Test name
Test status
Simulation time 185410642 ps
CPU time 1.44 seconds
Started Sep 09 08:58:29 PM UTC 24
Finished Sep 09 08:58:32 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222185352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2222185352
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.1079967724
Short name T469
Test name
Test status
Simulation time 108529230 ps
CPU time 1.7 seconds
Started Sep 09 08:58:27 PM UTC 24
Finished Sep 09 08:58:30 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079967724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.1079967724
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.1858113537
Short name T476
Test name
Test status
Simulation time 255488583 ps
CPU time 2.27 seconds
Started Sep 09 08:58:29 PM UTC 24
Finished Sep 09 08:58:33 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858113537 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1858113537
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.1178234865
Short name T474
Test name
Test status
Simulation time 261655258 ps
CPU time 2.94 seconds
Started Sep 09 08:58:28 PM UTC 24
Finished Sep 09 08:58:32 PM UTC 24
Peak memory 209012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178234865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1178234865
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.387453412
Short name T470
Test name
Test status
Simulation time 157113149 ps
CPU time 1.89 seconds
Started Sep 09 08:58:28 PM UTC 24
Finished Sep 09 08:58:31 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387453412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.387453412
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.1259815116
Short name T486
Test name
Test status
Simulation time 67703442 ps
CPU time 1.24 seconds
Started Sep 09 08:58:33 PM UTC 24
Finished Sep 09 08:58:36 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259815116 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1259815116
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.360629080
Short name T518
Test name
Test status
Simulation time 2245916751 ps
CPU time 10.53 seconds
Started Sep 09 08:58:33 PM UTC 24
Finished Sep 09 08:58:45 PM UTC 24
Peak memory 241444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360629080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.360629080
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1436986205
Short name T487
Test name
Test status
Simulation time 302990651 ps
CPU time 1.49 seconds
Started Sep 09 08:58:33 PM UTC 24
Finished Sep 09 08:58:36 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436986205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1436986205
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.4210816121
Short name T478
Test name
Test status
Simulation time 86499023 ps
CPU time 1.18 seconds
Started Sep 09 08:58:31 PM UTC 24
Finished Sep 09 08:58:33 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210816121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4210816121
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.3814540554
Short name T497
Test name
Test status
Simulation time 1651334347 ps
CPU time 6.11 seconds
Started Sep 09 08:58:31 PM UTC 24
Finished Sep 09 08:58:38 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814540554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3814540554
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3863645600
Short name T484
Test name
Test status
Simulation time 156192584 ps
CPU time 1.75 seconds
Started Sep 09 08:58:32 PM UTC 24
Finished Sep 09 08:58:35 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863645600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3863645600
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.3012262861
Short name T483
Test name
Test status
Simulation time 253242840 ps
CPU time 2.4 seconds
Started Sep 09 08:58:31 PM UTC 24
Finished Sep 09 08:58:34 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012262861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3012262861
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.1429509299
Short name T544
Test name
Test status
Simulation time 5633251011 ps
CPU time 34.57 seconds
Started Sep 09 08:58:33 PM UTC 24
Finished Sep 09 08:59:09 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429509299 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1429509299
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.2729563341
Short name T488
Test name
Test status
Simulation time 447778847 ps
CPU time 3.32 seconds
Started Sep 09 08:58:32 PM UTC 24
Finished Sep 09 08:58:37 PM UTC 24
Peak memory 209120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729563341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2729563341
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.3553609180
Short name T481
Test name
Test status
Simulation time 148615056 ps
CPU time 1.7 seconds
Started Sep 09 08:58:31 PM UTC 24
Finished Sep 09 08:58:34 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553609180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.3553609180
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.4273749247
Short name T500
Test name
Test status
Simulation time 67530956 ps
CPU time 1.26 seconds
Started Sep 09 08:58:36 PM UTC 24
Finished Sep 09 08:58:39 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273749247 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.4273749247
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.738988393
Short name T512
Test name
Test status
Simulation time 1279831261 ps
CPU time 6.57 seconds
Started Sep 09 08:58:35 PM UTC 24
Finished Sep 09 08:58:43 PM UTC 24
Peak memory 241340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738988393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.738988393
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2573126285
Short name T494
Test name
Test status
Simulation time 302398551 ps
CPU time 1.38 seconds
Started Sep 09 08:58:35 PM UTC 24
Finished Sep 09 08:58:38 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573126285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2573126285
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.1639016010
Short name T493
Test name
Test status
Simulation time 144372841 ps
CPU time 1.5 seconds
Started Sep 09 08:58:35 PM UTC 24
Finished Sep 09 08:58:38 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639016010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.1639016010
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.2321746264
Short name T508
Test name
Test status
Simulation time 1601001863 ps
CPU time 5.83 seconds
Started Sep 09 08:58:35 PM UTC 24
Finished Sep 09 08:58:42 PM UTC 24
Peak memory 209116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321746264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.2321746264
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3303710092
Short name T496
Test name
Test status
Simulation time 156123009 ps
CPU time 1.87 seconds
Started Sep 09 08:58:35 PM UTC 24
Finished Sep 09 08:58:38 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303710092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3303710092
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.3735588651
Short name T495
Test name
Test status
Simulation time 197540721 ps
CPU time 1.66 seconds
Started Sep 09 08:58:35 PM UTC 24
Finished Sep 09 08:58:38 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735588651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.3735588651
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.2346592057
Short name T542
Test name
Test status
Simulation time 5632955978 ps
CPU time 26.91 seconds
Started Sep 09 08:58:36 PM UTC 24
Finished Sep 09 08:59:05 PM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346592057 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2346592057
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.511729475
Short name T499
Test name
Test status
Simulation time 412248535 ps
CPU time 2.69 seconds
Started Sep 09 08:58:35 PM UTC 24
Finished Sep 09 08:58:39 PM UTC 24
Peak memory 217760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511729475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.511729475
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.938686975
Short name T491
Test name
Test status
Simulation time 99916446 ps
CPU time 1.01 seconds
Started Sep 09 08:58:35 PM UTC 24
Finished Sep 09 08:58:37 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938686975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.938686975
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.3433189611
Short name T505
Test name
Test status
Simulation time 92775635 ps
CPU time 1.07 seconds
Started Sep 09 08:58:39 PM UTC 24
Finished Sep 09 08:58:42 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433189611 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3433189611
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.1455499877
Short name T521
Test name
Test status
Simulation time 1266698191 ps
CPU time 7.11 seconds
Started Sep 09 08:58:38 PM UTC 24
Finished Sep 09 08:58:46 PM UTC 24
Peak memory 242444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455499877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1455499877
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2037151438
Short name T509
Test name
Test status
Simulation time 302702498 ps
CPU time 1.87 seconds
Started Sep 09 08:58:39 PM UTC 24
Finished Sep 09 08:58:42 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037151438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2037151438
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.3583910715
Short name T498
Test name
Test status
Simulation time 113077546 ps
CPU time 1.03 seconds
Started Sep 09 08:58:37 PM UTC 24
Finished Sep 09 08:58:39 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583910715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3583910715
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.3959274864
Short name T530
Test name
Test status
Simulation time 2396960444 ps
CPU time 9.41 seconds
Started Sep 09 08:58:38 PM UTC 24
Finished Sep 09 08:58:48 PM UTC 24
Peak memory 209448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959274864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3959274864
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1190415784
Short name T503
Test name
Test status
Simulation time 174451229 ps
CPU time 1.64 seconds
Started Sep 09 08:58:38 PM UTC 24
Finished Sep 09 08:58:41 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190415784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1190415784
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.628910911
Short name T501
Test name
Test status
Simulation time 200162030 ps
CPU time 2.23 seconds
Started Sep 09 08:58:37 PM UTC 24
Finished Sep 09 08:58:40 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628910911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.628910911
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.3724024988
Short name T527
Test name
Test status
Simulation time 1369159965 ps
CPU time 7.42 seconds
Started Sep 09 08:58:39 PM UTC 24
Finished Sep 09 08:58:48 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724024988 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3724024988
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.3452630052
Short name T504
Test name
Test status
Simulation time 133411914 ps
CPU time 2.16 seconds
Started Sep 09 08:58:38 PM UTC 24
Finished Sep 09 08:58:41 PM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452630052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3452630052
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.3936259114
Short name T502
Test name
Test status
Simulation time 109649986 ps
CPU time 1.52 seconds
Started Sep 09 08:58:38 PM UTC 24
Finished Sep 09 08:58:40 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936259114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3936259114
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.506527760
Short name T517
Test name
Test status
Simulation time 74607278 ps
CPU time 1.24 seconds
Started Sep 09 08:58:42 PM UTC 24
Finished Sep 09 08:58:45 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506527760 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.506527760
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.3459340629
Short name T533
Test name
Test status
Simulation time 2253671688 ps
CPU time 8.17 seconds
Started Sep 09 08:58:41 PM UTC 24
Finished Sep 09 08:58:50 PM UTC 24
Peak memory 241440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459340629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3459340629
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2569853041
Short name T514
Test name
Test status
Simulation time 302194642 ps
CPU time 1.58 seconds
Started Sep 09 08:58:41 PM UTC 24
Finished Sep 09 08:58:44 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569853041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2569853041
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.4116377634
Short name T507
Test name
Test status
Simulation time 171947063 ps
CPU time 1.28 seconds
Started Sep 09 08:58:40 PM UTC 24
Finished Sep 09 08:58:42 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116377634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.4116377634
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.237826571
Short name T529
Test name
Test status
Simulation time 2098596440 ps
CPU time 7.7 seconds
Started Sep 09 08:58:40 PM UTC 24
Finished Sep 09 08:58:48 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237826571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.237826571
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3001734337
Short name T513
Test name
Test status
Simulation time 141823630 ps
CPU time 1.26 seconds
Started Sep 09 08:58:41 PM UTC 24
Finished Sep 09 08:58:43 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001734337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3001734337
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.125978235
Short name T511
Test name
Test status
Simulation time 226122800 ps
CPU time 2.25 seconds
Started Sep 09 08:58:40 PM UTC 24
Finished Sep 09 08:58:43 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125978235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.125978235
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.2947344207
Short name T543
Test name
Test status
Simulation time 5669366337 ps
CPU time 24.24 seconds
Started Sep 09 08:58:41 PM UTC 24
Finished Sep 09 08:59:07 PM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947344207 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2947344207
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.1528611277
Short name T515
Test name
Test status
Simulation time 383659924 ps
CPU time 3.51 seconds
Started Sep 09 08:58:40 PM UTC 24
Finished Sep 09 08:58:44 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528611277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1528611277
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.2442968247
Short name T510
Test name
Test status
Simulation time 154737655 ps
CPU time 1.73 seconds
Started Sep 09 08:58:40 PM UTC 24
Finished Sep 09 08:58:42 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442968247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2442968247
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.2982580833
Short name T525
Test name
Test status
Simulation time 79572536 ps
CPU time 0.91 seconds
Started Sep 09 08:58:45 PM UTC 24
Finished Sep 09 08:58:47 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982580833 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2982580833
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.3683019142
Short name T537
Test name
Test status
Simulation time 1274533634 ps
CPU time 6.15 seconds
Started Sep 09 08:58:44 PM UTC 24
Finished Sep 09 08:58:51 PM UTC 24
Peak memory 242340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683019142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3683019142
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.2485316477
Short name T524
Test name
Test status
Simulation time 301194258 ps
CPU time 1.95 seconds
Started Sep 09 08:58:44 PM UTC 24
Finished Sep 09 08:58:47 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485316477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.2485316477
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.320008587
Short name T516
Test name
Test status
Simulation time 85448636 ps
CPU time 0.99 seconds
Started Sep 09 08:58:42 PM UTC 24
Finished Sep 09 08:58:44 PM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320008587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.320008587
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.1090172118
Short name T539
Test name
Test status
Simulation time 1721535664 ps
CPU time 8.95 seconds
Started Sep 09 08:58:42 PM UTC 24
Finished Sep 09 08:58:53 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090172118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1090172118
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.598368561
Short name T522
Test name
Test status
Simulation time 113489693 ps
CPU time 1.51 seconds
Started Sep 09 08:58:44 PM UTC 24
Finished Sep 09 08:58:46 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598368561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.598368561
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.2979373689
Short name T519
Test name
Test status
Simulation time 131029521 ps
CPU time 1.83 seconds
Started Sep 09 08:58:42 PM UTC 24
Finished Sep 09 08:58:45 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979373689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2979373689
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.392968358
Short name T541
Test name
Test status
Simulation time 2858215714 ps
CPU time 13.1 seconds
Started Sep 09 08:58:44 PM UTC 24
Finished Sep 09 08:58:58 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392968358 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.392968358
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.1686935823
Short name T523
Test name
Test status
Simulation time 128122685 ps
CPU time 1.8 seconds
Started Sep 09 08:58:44 PM UTC 24
Finished Sep 09 08:58:47 PM UTC 24
Peak memory 216860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686935823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1686935823
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.3161929604
Short name T520
Test name
Test status
Simulation time 133860426 ps
CPU time 1.46 seconds
Started Sep 09 08:58:44 PM UTC 24
Finished Sep 09 08:58:46 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161929604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3161929604
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.2889702360
Short name T532
Test name
Test status
Simulation time 90990954 ps
CPU time 1.01 seconds
Started Sep 09 08:58:48 PM UTC 24
Finished Sep 09 08:58:50 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889702360 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2889702360
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.3069275666
Short name T540
Test name
Test status
Simulation time 1270031566 ps
CPU time 5.57 seconds
Started Sep 09 08:58:48 PM UTC 24
Finished Sep 09 08:58:54 PM UTC 24
Peak memory 242056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069275666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3069275666
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.622127590
Short name T475
Test name
Test status
Simulation time 301403639 ps
CPU time 1.58 seconds
Started Sep 09 08:58:48 PM UTC 24
Finished Sep 09 08:58:50 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622127590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.622127590
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.3308671032
Short name T526
Test name
Test status
Simulation time 107736728 ps
CPU time 1.25 seconds
Started Sep 09 08:58:45 PM UTC 24
Finished Sep 09 08:58:48 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308671032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.3308671032
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.652139799
Short name T536
Test name
Test status
Simulation time 831663658 ps
CPU time 4.42 seconds
Started Sep 09 08:58:45 PM UTC 24
Finished Sep 09 08:58:51 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652139799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.652139799
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.2148789795
Short name T535
Test name
Test status
Simulation time 179081589 ps
CPU time 1.53 seconds
Started Sep 09 08:58:48 PM UTC 24
Finished Sep 09 08:58:50 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148789795 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.2148789795
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.329087348
Short name T528
Test name
Test status
Simulation time 263067854 ps
CPU time 2.13 seconds
Started Sep 09 08:58:45 PM UTC 24
Finished Sep 09 08:58:48 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329087348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.329087348
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1827289979
Short name T545
Test name
Test status
Simulation time 8409349371 ps
CPU time 31.29 seconds
Started Sep 09 08:58:48 PM UTC 24
Finished Sep 09 08:59:21 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827289979 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1827289979
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.2643078380
Short name T534
Test name
Test status
Simulation time 299584259 ps
CPU time 2.78 seconds
Started Sep 09 08:58:46 PM UTC 24
Finished Sep 09 08:58:50 PM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643078380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2643078380
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.1679342009
Short name T531
Test name
Test status
Simulation time 161158907 ps
CPU time 1.87 seconds
Started Sep 09 08:58:46 PM UTC 24
Finished Sep 09 08:58:49 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679342009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1679342009
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.88632437
Short name T137
Test name
Test status
Simulation time 59903045 ps
CPU time 1.11 seconds
Started Sep 09 08:55:21 PM UTC 24
Finished Sep 09 08:55:23 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88632437 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.88632437
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.1621630414
Short name T28
Test name
Test status
Simulation time 1269076085 ps
CPU time 8.83 seconds
Started Sep 09 08:55:19 PM UTC 24
Finished Sep 09 08:55:29 PM UTC 24
Peak memory 242344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621630414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1621630414
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3763848860
Short name T136
Test name
Test status
Simulation time 302533860 ps
CPU time 1.97 seconds
Started Sep 09 08:55:20 PM UTC 24
Finished Sep 09 08:55:23 PM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763848860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3763848860
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.1331627394
Short name T17
Test name
Test status
Simulation time 81570867 ps
CPU time 1.18 seconds
Started Sep 09 08:55:17 PM UTC 24
Finished Sep 09 08:55:19 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331627394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1331627394
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.420539404
Short name T96
Test name
Test status
Simulation time 849326366 ps
CPU time 6.37 seconds
Started Sep 09 08:55:17 PM UTC 24
Finished Sep 09 08:55:24 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420539404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.420539404
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3899091259
Short name T135
Test name
Test status
Simulation time 96948999 ps
CPU time 1.55 seconds
Started Sep 09 08:55:19 PM UTC 24
Finished Sep 09 08:55:22 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899091259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3899091259
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.2743517960
Short name T55
Test name
Test status
Simulation time 203150582 ps
CPU time 2.21 seconds
Started Sep 09 08:55:15 PM UTC 24
Finished Sep 09 08:55:19 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743517960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.2743517960
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.1287577951
Short name T99
Test name
Test status
Simulation time 1823368940 ps
CPU time 8.86 seconds
Started Sep 09 08:55:21 PM UTC 24
Finished Sep 09 08:55:31 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287577951 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1287577951
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.2936995583
Short name T85
Test name
Test status
Simulation time 548542597 ps
CPU time 3.67 seconds
Started Sep 09 08:55:18 PM UTC 24
Finished Sep 09 08:55:23 PM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936995583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.2936995583
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3254328794
Short name T126
Test name
Test status
Simulation time 232542478 ps
CPU time 2.34 seconds
Started Sep 09 08:55:17 PM UTC 24
Finished Sep 09 08:55:20 PM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254328794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3254328794
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1343529892
Short name T141
Test name
Test status
Simulation time 75689148 ps
CPU time 1.23 seconds
Started Sep 09 08:55:29 PM UTC 24
Finished Sep 09 08:55:31 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343529892 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1343529892
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.1808567397
Short name T44
Test name
Test status
Simulation time 1275617818 ps
CPU time 8.87 seconds
Started Sep 09 08:55:26 PM UTC 24
Finished Sep 09 08:55:36 PM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808567397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1808567397
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2963013063
Short name T140
Test name
Test status
Simulation time 311155721 ps
CPU time 1.91 seconds
Started Sep 09 08:55:27 PM UTC 24
Finished Sep 09 08:55:30 PM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963013063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2963013063
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.3503233418
Short name T18
Test name
Test status
Simulation time 181872495 ps
CPU time 1.52 seconds
Started Sep 09 08:55:23 PM UTC 24
Finished Sep 09 08:55:25 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503233418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3503233418
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.4008256559
Short name T146
Test name
Test status
Simulation time 1523504324 ps
CPU time 10.86 seconds
Started Sep 09 08:55:24 PM UTC 24
Finished Sep 09 08:55:36 PM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008256559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.4008256559
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3348270922
Short name T139
Test name
Test status
Simulation time 141271962 ps
CPU time 1.7 seconds
Started Sep 09 08:55:25 PM UTC 24
Finished Sep 09 08:55:28 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348270922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3348270922
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.3192085502
Short name T127
Test name
Test status
Simulation time 225662447 ps
CPU time 2.3 seconds
Started Sep 09 08:55:23 PM UTC 24
Finished Sep 09 08:55:26 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192085502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3192085502
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1877655855
Short name T183
Test name
Test status
Simulation time 6487838004 ps
CPU time 34.88 seconds
Started Sep 09 08:55:27 PM UTC 24
Finished Sep 09 08:56:04 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877655855 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1877655855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.780311327
Short name T86
Test name
Test status
Simulation time 147907645 ps
CPU time 2.86 seconds
Started Sep 09 08:55:25 PM UTC 24
Finished Sep 09 08:55:29 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780311327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.780311327
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.477935386
Short name T138
Test name
Test status
Simulation time 210117740 ps
CPU time 2.11 seconds
Started Sep 09 08:55:24 PM UTC 24
Finished Sep 09 08:55:27 PM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477935386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.477935386
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.3897062681
Short name T147
Test name
Test status
Simulation time 62115346 ps
CPU time 1.14 seconds
Started Sep 09 08:55:34 PM UTC 24
Finished Sep 09 08:55:37 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897062681 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3897062681
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.749900879
Short name T29
Test name
Test status
Simulation time 2267262186 ps
CPU time 13.63 seconds
Started Sep 09 08:55:32 PM UTC 24
Finished Sep 09 08:55:47 PM UTC 24
Peak memory 242408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749900879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.749900879
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.3734075748
Short name T144
Test name
Test status
Simulation time 302621673 ps
CPU time 2.13 seconds
Started Sep 09 08:55:32 PM UTC 24
Finished Sep 09 08:55:35 PM UTC 24
Peak memory 237828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734075748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.3734075748
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.2937061116
Short name T19
Test name
Test status
Simulation time 147915038 ps
CPU time 1.39 seconds
Started Sep 09 08:55:30 PM UTC 24
Finished Sep 09 08:55:32 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937061116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2937061116
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3228057153
Short name T100
Test name
Test status
Simulation time 1634662611 ps
CPU time 10.16 seconds
Started Sep 09 08:55:30 PM UTC 24
Finished Sep 09 08:55:41 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228057153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.3228057153
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2459956008
Short name T143
Test name
Test status
Simulation time 107610867 ps
CPU time 1.54 seconds
Started Sep 09 08:55:32 PM UTC 24
Finished Sep 09 08:55:35 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459956008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2459956008
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.610499387
Short name T128
Test name
Test status
Simulation time 242234007 ps
CPU time 2.1 seconds
Started Sep 09 08:55:29 PM UTC 24
Finished Sep 09 08:55:32 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610499387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.610499387
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.3735556779
Short name T124
Test name
Test status
Simulation time 7619418606 ps
CPU time 34.92 seconds
Started Sep 09 08:55:33 PM UTC 24
Finished Sep 09 08:56:10 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735556779 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3735556779
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3500768149
Short name T145
Test name
Test status
Simulation time 362619724 ps
CPU time 3.66 seconds
Started Sep 09 08:55:31 PM UTC 24
Finished Sep 09 08:55:36 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500768149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3500768149
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2050768757
Short name T142
Test name
Test status
Simulation time 94616702 ps
CPU time 1.49 seconds
Started Sep 09 08:55:31 PM UTC 24
Finished Sep 09 08:55:34 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050768757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2050768757
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.3184725817
Short name T154
Test name
Test status
Simulation time 76530848 ps
CPU time 1.04 seconds
Started Sep 09 08:55:43 PM UTC 24
Finished Sep 09 08:55:45 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184725817 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.3184725817
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1745354851
Short name T30
Test name
Test status
Simulation time 2449184364 ps
CPU time 14.31 seconds
Started Sep 09 08:55:39 PM UTC 24
Finished Sep 09 08:55:55 PM UTC 24
Peak memory 242468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745354851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1745354851
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1286592751
Short name T152
Test name
Test status
Simulation time 301454922 ps
CPU time 1.99 seconds
Started Sep 09 08:55:40 PM UTC 24
Finished Sep 09 08:55:44 PM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286592751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1286592751
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.1329449855
Short name T20
Test name
Test status
Simulation time 126234287 ps
CPU time 1.28 seconds
Started Sep 09 08:55:37 PM UTC 24
Finished Sep 09 08:55:39 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329449855 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1329449855
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2918492621
Short name T102
Test name
Test status
Simulation time 851920357 ps
CPU time 6.43 seconds
Started Sep 09 08:55:37 PM UTC 24
Finished Sep 09 08:55:44 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918492621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2918492621
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3095045497
Short name T149
Test name
Test status
Simulation time 179369549 ps
CPU time 1.94 seconds
Started Sep 09 08:55:38 PM UTC 24
Finished Sep 09 08:55:41 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095045497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3095045497
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.3142989573
Short name T148
Test name
Test status
Simulation time 118109118 ps
CPU time 1.9 seconds
Started Sep 09 08:55:35 PM UTC 24
Finished Sep 09 08:55:39 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142989573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3142989573
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.839942919
Short name T151
Test name
Test status
Simulation time 97194773 ps
CPU time 1.65 seconds
Started Sep 09 08:55:40 PM UTC 24
Finished Sep 09 08:55:43 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839942919 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.839942919
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.3697251532
Short name T150
Test name
Test status
Simulation time 470447790 ps
CPU time 3.96 seconds
Started Sep 09 08:55:37 PM UTC 24
Finished Sep 09 08:55:42 PM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697251532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3697251532
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3474541707
Short name T132
Test name
Test status
Simulation time 136079750 ps
CPU time 1.79 seconds
Started Sep 09 08:55:37 PM UTC 24
Finished Sep 09 08:55:40 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474541707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3474541707
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3926206588
Short name T160
Test name
Test status
Simulation time 72152562 ps
CPU time 1.25 seconds
Started Sep 09 08:55:46 PM UTC 24
Finished Sep 09 08:55:49 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926206588 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3926206588
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.2000406819
Short name T56
Test name
Test status
Simulation time 1268454129 ps
CPU time 10.15 seconds
Started Sep 09 08:55:45 PM UTC 24
Finished Sep 09 08:55:57 PM UTC 24
Peak memory 242344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000406819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2000406819
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2916768934
Short name T159
Test name
Test status
Simulation time 301691562 ps
CPU time 1.95 seconds
Started Sep 09 08:55:45 PM UTC 24
Finished Sep 09 08:55:49 PM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916768934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2916768934
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.3339526239
Short name T21
Test name
Test status
Simulation time 155448488 ps
CPU time 1.36 seconds
Started Sep 09 08:55:43 PM UTC 24
Finished Sep 09 08:55:45 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339526239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.3339526239
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1469078798
Short name T164
Test name
Test status
Simulation time 995081799 ps
CPU time 7.42 seconds
Started Sep 09 08:55:43 PM UTC 24
Finished Sep 09 08:55:51 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469078798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1469078798
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.718814453
Short name T158
Test name
Test status
Simulation time 111156311 ps
CPU time 1.67 seconds
Started Sep 09 08:55:45 PM UTC 24
Finished Sep 09 08:55:48 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718814453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.718814453
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2459591310
Short name T155
Test name
Test status
Simulation time 115731942 ps
CPU time 1.81 seconds
Started Sep 09 08:55:43 PM UTC 24
Finished Sep 09 08:55:45 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459591310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2459591310
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_smoke/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.3669103721
Short name T122
Test name
Test status
Simulation time 3390050806 ps
CPU time 18.82 seconds
Started Sep 09 08:55:46 PM UTC 24
Finished Sep 09 08:56:07 PM UTC 24
Peak memory 209380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669103721 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_08/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.3669103721
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.2998292201
Short name T161
Test name
Test status
Simulation time 365068173 ps
CPU time 3.69 seconds
Started Sep 09 08:55:44 PM UTC 24
Finished Sep 09 08:55:49 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998292201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2998292201
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest


Test location /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1663915912
Short name T157
Test name
Test status
Simulation time 154480812 ps
CPU time 2.03 seconds
Started Sep 09 08:55:44 PM UTC 24
Finished Sep 09 08:55:48 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663915912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1663915912
Directory /workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest