Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8711

1

T4

5

T10

23

T11

6

auto[1]

11816

1

T1

4

T3

4

T4

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6304	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6855	1			T1	2		T2	1		T3	2
reset_info_cp[2]	3287	1			T1	1		T3	1		T8	1
reset_info_cp[4]	4141	1			T1	1		T3	1		T8	1
reset_info_cp[8]	103	1			T22	1		T88	1		T27	1
reset_info_cp[16]	113	1			T11	1		T35	1		T70	4
reset_info_cp[32]	110	1			T11	1		T22	1		T25	1
reset_info_cp[64]	103	1			T4	1		T13	2		T35	3
reset_info_cp[128]	131	1			T3	1		T10	1		T25	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3295	1			T10	8		T13	21		T22	10
reset_info_cp[1]	auto[1]	2940	1			T1	1		T3	1		T8	1
reset_info_cp[2]	auto[0]	1090	1			T10	2		T22	5		T54	8
reset_info_cp[2]	auto[1]	2197	1			T1	1		T3	1		T8	1
reset_info_cp[4]	auto[0]	1483	1			T10	5		T22	5		T54	6
reset_info_cp[4]	auto[1]	2658	1			T1	1		T3	1		T8	1
reset_info_cp[8]	auto[0]	39	1			T22	1		T88	1		T76	1
reset_info_cp[8]	auto[1]	64	1			T27	1		T74	1		T76	3
reset_info_cp[16]	auto[0]	43	1			T11	1		T35	1		T70	2
reset_info_cp[16]	auto[1]	70	1			T70	2		T139	1		T76	1
reset_info_cp[32]	auto[0]	35	1			T11	1		T35	1		T54	1
reset_info_cp[32]	auto[1]	75	1			T22	1		T25	1		T70	1
reset_info_cp[64]	auto[0]	47	1			T35	3		T70	1		T140	1
reset_info_cp[64]	auto[1]	56	1			T4	1		T13	2		T26	1
reset_info_cp[128]	auto[0]	50	1			T10	1		T35	1		T70	3
reset_info_cp[128]	auto[1]	81	1			T3	1		T25	1		T35	1