Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.46	99.40	99.31	100.00		99.83	99.46	98.77

Total test records in report: 620

T544	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.1373482853	Sep 11 05:05:22 PM UTC 24	Sep 11 05:05:39 PM UTC 24	4609687509 ps
T545	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.2780609533	Sep 11 05:05:33 PM UTC 24	Sep 11 05:05:45 PM UTC 24	2249378560 ps
T546	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.763026577	Sep 11 05:05:33 PM UTC 24	Sep 11 05:05:49 PM UTC 24	3455938793 ps
T547	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.2129430801	Sep 11 05:05:27 PM UTC 24	Sep 11 05:05:50 PM UTC 24	4888408126 ps
T548	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.2813799352	Sep 11 05:05:23 PM UTC 24	Sep 11 05:05:58 PM UTC 24	8999649450 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.2590213416	Sep 11 04:52:11 PM UTC 24	Sep 11 04:52:15 PM UTC 24	312743203 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.951866352	Sep 11 04:52:13 PM UTC 24	Sep 11 04:52:17 PM UTC 24	793245393 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3297970362	Sep 11 04:52:16 PM UTC 24	Sep 11 04:52:18 PM UTC 24	145983521 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3454692293	Sep 11 04:52:18 PM UTC 24	Sep 11 04:52:20 PM UTC 24	85522826 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4007758038	Sep 11 04:52:19 PM UTC 24	Sep 11 04:52:22 PM UTC 24	199362943 ps
T102	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2808195636	Sep 11 04:52:21 PM UTC 24	Sep 11 04:52:24 PM UTC 24	128912370 ps
T63	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3072234133	Sep 11 04:52:23 PM UTC 24	Sep 11 04:52:27 PM UTC 24	167781205 ps
T113	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1590507008	Sep 11 04:52:18 PM UTC 24	Sep 11 04:52:27 PM UTC 24	478365661 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.3635991962	Sep 11 04:52:23 PM UTC 24	Sep 11 04:52:29 PM UTC 24	349995977 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1972993087	Sep 11 04:52:25 PM UTC 24	Sep 11 04:52:30 PM UTC 24	467704170 ps
T549	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4244893781	Sep 11 04:52:28 PM UTC 24	Sep 11 04:52:30 PM UTC 24	84997557 ps
T138	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1104342146	Sep 11 04:52:29 PM UTC 24	Sep 11 04:52:32 PM UTC 24	79733607 ps
T550	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3842287494	Sep 11 04:52:30 PM UTC 24	Sep 11 04:52:34 PM UTC 24	204068013 ps
T103	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1192284103	Sep 11 04:52:31 PM UTC 24	Sep 11 04:52:34 PM UTC 24	90690744 ps
T80	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2566821256	Sep 11 04:52:31 PM UTC 24	Sep 11 04:52:34 PM UTC 24	196398827 ps
T551	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4126586744	Sep 11 04:52:34 PM UTC 24	Sep 11 04:52:37 PM UTC 24	85945528 ps
T104	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.1633212216	Sep 11 04:52:35 PM UTC 24	Sep 11 04:52:38 PM UTC 24	76067282 ps
T81	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2356406909	Sep 11 04:52:32 PM UTC 24	Sep 11 04:52:38 PM UTC 24	499194516 ps
T87	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1404707905	Sep 11 04:52:34 PM UTC 24	Sep 11 04:52:38 PM UTC 24	436740687 ps
T552	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.146971478	Sep 11 04:52:30 PM UTC 24	Sep 11 04:52:40 PM UTC 24	489959987 ps
T82	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2967550198	Sep 11 04:52:39 PM UTC 24	Sep 11 04:52:41 PM UTC 24	115648197 ps
T105	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2652831283	Sep 11 04:52:39 PM UTC 24	Sep 11 04:52:41 PM UTC 24	85403810 ps
T553	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1298081244	Sep 11 04:52:37 PM UTC 24	Sep 11 04:52:43 PM UTC 24	343958113 ps
T554	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2904809872	Sep 11 04:52:41 PM UTC 24	Sep 11 04:52:43 PM UTC 24	95236612 ps
T83	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.301375227	Sep 11 04:52:39 PM UTC 24	Sep 11 04:52:43 PM UTC 24	302206950 ps
T135	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1387422500	Sep 11 04:52:40 PM UTC 24	Sep 11 04:52:44 PM UTC 24	496949936 ps
T106	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.2396130636	Sep 11 04:52:42 PM UTC 24	Sep 11 04:52:45 PM UTC 24	62693981 ps
T107	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1211381791	Sep 11 04:52:43 PM UTC 24	Sep 11 04:52:46 PM UTC 24	141414568 ps
T555	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1907293087	Sep 11 04:52:43 PM UTC 24	Sep 11 04:52:46 PM UTC 24	113981933 ps
T84	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.483916297	Sep 11 04:52:44 PM UTC 24	Sep 11 04:52:47 PM UTC 24	123025068 ps
T556	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.49666587	Sep 11 04:52:37 PM UTC 24	Sep 11 04:52:47 PM UTC 24	1024080264 ps
T557	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3477810470	Sep 11 04:52:45 PM UTC 24	Sep 11 04:52:48 PM UTC 24	131827527 ps
T85	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.4284455619	Sep 11 04:52:44 PM UTC 24	Sep 11 04:52:49 PM UTC 24	241360867 ps
T108	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.421996533	Sep 11 04:52:48 PM UTC 24	Sep 11 04:52:50 PM UTC 24	61868764 ps
T117	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1108267034	Sep 11 04:52:45 PM UTC 24	Sep 11 04:52:50 PM UTC 24	462332812 ps
T86	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2810250230	Sep 11 04:52:48 PM UTC 24	Sep 11 04:52:50 PM UTC 24	97579401 ps
T109	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.215537210	Sep 11 04:52:48 PM UTC 24	Sep 11 04:52:51 PM UTC 24	90745401 ps
T558	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4218356407	Sep 11 04:52:48 PM UTC 24	Sep 11 04:52:51 PM UTC 24	204250232 ps
T559	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2636874156	Sep 11 04:52:42 PM UTC 24	Sep 11 04:52:51 PM UTC 24	815628579 ps
T110	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.3272713804	Sep 11 04:52:50 PM UTC 24	Sep 11 04:52:52 PM UTC 24	55121410 ps
T560	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.740860182	Sep 11 04:52:48 PM UTC 24	Sep 11 04:52:53 PM UTC 24	265283887 ps
T118	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2182922263	Sep 11 04:52:49 PM UTC 24	Sep 11 04:52:53 PM UTC 24	464159640 ps
T111	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2578923759	Sep 11 04:52:51 PM UTC 24	Sep 11 04:52:54 PM UTC 24	67733198 ps
T561	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2076622787	Sep 11 04:52:49 PM UTC 24	Sep 11 04:52:54 PM UTC 24	355775393 ps
T562	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3800565819	Sep 11 04:52:51 PM UTC 24	Sep 11 04:52:54 PM UTC 24	139522324 ps
T121	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4040910876	Sep 11 04:52:51 PM UTC 24	Sep 11 04:52:55 PM UTC 24	157868435 ps
T122	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2094024254	Sep 11 04:52:51 PM UTC 24	Sep 11 04:52:55 PM UTC 24	228239927 ps
T563	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2623398646	Sep 11 04:52:53 PM UTC 24	Sep 11 04:52:55 PM UTC 24	137482207 ps
T133	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1523403601	Sep 11 04:52:51 PM UTC 24	Sep 11 04:52:56 PM UTC 24	409292427 ps
T114	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.727425878	Sep 11 04:52:54 PM UTC 24	Sep 11 04:52:56 PM UTC 24	95867997 ps
T564	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1140353864	Sep 11 04:52:54 PM UTC 24	Sep 11 04:52:56 PM UTC 24	126859054 ps
T565	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.485258800	Sep 11 04:52:55 PM UTC 24	Sep 11 04:52:57 PM UTC 24	62534040 ps
T134	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1524825180	Sep 11 04:52:54 PM UTC 24	Sep 11 04:52:58 PM UTC 24	490776348 ps
T566	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2895250906	Sep 11 04:52:55 PM UTC 24	Sep 11 04:52:58 PM UTC 24	136498100 ps
T567	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3573317725	Sep 11 04:52:55 PM UTC 24	Sep 11 04:52:58 PM UTC 24	198356152 ps
T568	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2187015608	Sep 11 04:52:56 PM UTC 24	Sep 11 04:52:58 PM UTC 24	65524872 ps
T569	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.879792311	Sep 11 04:52:56 PM UTC 24	Sep 11 04:52:59 PM UTC 24	108731846 ps
T570	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.936177796	Sep 11 04:52:58 PM UTC 24	Sep 11 04:53:01 PM UTC 24	66280241 ps
T571	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3418691955	Sep 11 04:52:57 PM UTC 24	Sep 11 04:53:01 PM UTC 24	101497638 ps
T572	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2686008854	Sep 11 04:52:57 PM UTC 24	Sep 11 04:53:01 PM UTC 24	161028462 ps
T120	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3733278965	Sep 11 04:52:56 PM UTC 24	Sep 11 04:53:01 PM UTC 24	783576913 ps
T573	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3348837761	Sep 11 04:52:56 PM UTC 24	Sep 11 04:53:01 PM UTC 24	341401859 ps
T574	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1589585951	Sep 11 04:52:59 PM UTC 24	Sep 11 04:53:01 PM UTC 24	129527193 ps
T575	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.543508633	Sep 11 04:52:58 PM UTC 24	Sep 11 04:53:01 PM UTC 24	161283192 ps
T576	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.93324964	Sep 11 04:53:02 PM UTC 24	Sep 11 04:53:04 PM UTC 24	66949407 ps
T577	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.3349828104	Sep 11 04:53:00 PM UTC 24	Sep 11 04:53:04 PM UTC 24	292732484 ps
T578	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.2070213078	Sep 11 04:53:02 PM UTC 24	Sep 11 04:53:04 PM UTC 24	69995743 ps
T579	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3182038088	Sep 11 04:53:02 PM UTC 24	Sep 11 04:53:04 PM UTC 24	114538865 ps
T580	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1909242907	Sep 11 04:53:02 PM UTC 24	Sep 11 04:53:04 PM UTC 24	72326197 ps
T136	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3795828810	Sep 11 04:52:58 PM UTC 24	Sep 11 04:53:05 PM UTC 24	942239351 ps
T581	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2214486038	Sep 11 04:53:02 PM UTC 24	Sep 11 04:53:05 PM UTC 24	121607069 ps
T582	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.3050976092	Sep 11 04:53:02 PM UTC 24	Sep 11 04:53:06 PM UTC 24	151568939 ps
T115	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1660683073	Sep 11 04:53:00 PM UTC 24	Sep 11 04:53:06 PM UTC 24	970965052 ps
T583	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3728602950	Sep 11 04:53:03 PM UTC 24	Sep 11 04:53:06 PM UTC 24	204493852 ps
T584	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2440720882	Sep 11 04:53:05 PM UTC 24	Sep 11 04:53:08 PM UTC 24	65481380 ps
T585	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.208398397	Sep 11 04:53:02 PM UTC 24	Sep 11 04:53:08 PM UTC 24	885409433 ps
T586	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3750454150	Sep 11 04:53:05 PM UTC 24	Sep 11 04:53:08 PM UTC 24	197242768 ps
T587	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2609206252	Sep 11 04:53:06 PM UTC 24	Sep 11 04:53:09 PM UTC 24	182618073 ps
T588	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.3687849796	Sep 11 04:53:07 PM UTC 24	Sep 11 04:53:09 PM UTC 24	73665304 ps
T589	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.379772935	Sep 11 04:53:07 PM UTC 24	Sep 11 04:53:09 PM UTC 24	206946678 ps
T119	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2234784945	Sep 11 04:53:05 PM UTC 24	Sep 11 04:53:10 PM UTC 24	510823591 ps
T590	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.486512439	Sep 11 04:53:06 PM UTC 24	Sep 11 04:53:10 PM UTC 24	440399879 ps
T591	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1684325542	Sep 11 04:53:08 PM UTC 24	Sep 11 04:53:11 PM UTC 24	196828582 ps
T592	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.3800373930	Sep 11 04:53:05 PM UTC 24	Sep 11 04:53:11 PM UTC 24	557862245 ps
T593	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.480186818	Sep 11 04:53:09 PM UTC 24	Sep 11 04:53:11 PM UTC 24	56404303 ps
T594	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3787994688	Sep 11 04:53:09 PM UTC 24	Sep 11 04:53:12 PM UTC 24	140706968 ps
T595	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1028427142	Sep 11 04:53:07 PM UTC 24	Sep 11 04:53:12 PM UTC 24	838331671 ps
T596	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.591150874	Sep 11 04:53:10 PM UTC 24	Sep 11 04:53:12 PM UTC 24	77897950 ps
T597	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2598701	Sep 11 04:53:10 PM UTC 24	Sep 11 04:53:13 PM UTC 24	179406518 ps
T598	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2132637359	Sep 11 04:53:10 PM UTC 24	Sep 11 04:53:14 PM UTC 24	222317265 ps
T599	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2216445302	Sep 11 04:53:10 PM UTC 24	Sep 11 04:53:14 PM UTC 24	413250969 ps
T600	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2383223798	Sep 11 04:53:11 PM UTC 24	Sep 11 04:53:14 PM UTC 24	207022999 ps
T94	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.101846320	Sep 11 04:53:13 PM UTC 24	Sep 11 04:53:15 PM UTC 24	60865704 ps
T601	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2226608879	Sep 11 04:53:11 PM UTC 24	Sep 11 04:53:15 PM UTC 24	215023726 ps
T137	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1563877355	Sep 11 04:53:09 PM UTC 24	Sep 11 04:53:15 PM UTC 24	991376309 ps
T602	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2516849961	Sep 11 04:53:09 PM UTC 24	Sep 11 04:53:15 PM UTC 24	513240692 ps
T603	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.893026785	Sep 11 04:53:13 PM UTC 24	Sep 11 04:53:16 PM UTC 24	108704491 ps
T604	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3497076717	Sep 11 04:53:14 PM UTC 24	Sep 11 04:53:17 PM UTC 24	124120740 ps
T605	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3485242127	Sep 11 04:53:13 PM UTC 24	Sep 11 04:53:17 PM UTC 24	950993519 ps
T606	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2395199422	Sep 11 04:53:15 PM UTC 24	Sep 11 04:53:17 PM UTC 24	65540108 ps
T607	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2788335672	Sep 11 04:53:15 PM UTC 24	Sep 11 04:53:17 PM UTC 24	78488813 ps
T608	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.1619905720	Sep 11 04:53:14 PM UTC 24	Sep 11 04:53:17 PM UTC 24	116495244 ps
T609	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.72030158	Sep 11 04:53:13 PM UTC 24	Sep 11 04:53:17 PM UTC 24	521288774 ps
T610	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2536220946	Sep 11 04:53:16 PM UTC 24	Sep 11 04:53:19 PM UTC 24	106458068 ps
T611	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3366348936	Sep 11 04:53:16 PM UTC 24	Sep 11 04:53:19 PM UTC 24	69696933 ps
T612	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.385347325	Sep 11 04:53:16 PM UTC 24	Sep 11 04:53:19 PM UTC 24	113158578 ps
T613	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3127330935	Sep 11 04:53:16 PM UTC 24	Sep 11 04:53:19 PM UTC 24	200623889 ps
T614	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.2285929388	Sep 11 04:53:18 PM UTC 24	Sep 11 04:53:19 PM UTC 24	58868002 ps
T615	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3251762506	Sep 11 04:53:18 PM UTC 24	Sep 11 04:53:20 PM UTC 24	90106200 ps
T616	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2953430794	Sep 11 04:53:16 PM UTC 24	Sep 11 04:53:20 PM UTC 24	928032476 ps
T617	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.190100502	Sep 11 04:53:18 PM UTC 24	Sep 11 04:53:21 PM UTC 24	263075155 ps
T618	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2342200894	Sep 11 04:53:18 PM UTC 24	Sep 11 04:53:21 PM UTC 24	177824225 ps
T116	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3738260697	Sep 11 04:53:15 PM UTC 24	Sep 11 04:53:21 PM UTC 24	977875952 ps
T619	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1286142248	Sep 11 04:53:16 PM UTC 24	Sep 11 04:53:21 PM UTC 24	187324074 ps
T620	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.52281800	Sep 11 04:53:18 PM UTC 24	Sep 11 04:53:22 PM UTC 24	1045614765 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.2423181971
Short name	T8
Test name
Test status
Simulation time	128446534 ps
CPU time	2.09 seconds
Started	Sep 11 05:01:05 PM UTC 24
Finished	Sep 11 05:01:08 PM UTC 24
Peak memory	209116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423181971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2423181971
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.1846241806
Short name	T25
Test name
Test status
Simulation time	1277464605 ps
CPU time	11.05 seconds
Started	Sep 11 05:01:11 PM UTC 24
Finished	Sep 11 05:01:23 PM UTC 24
Peak memory	242344 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846241806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1846241806
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.4246758077
Short name	T7
Test name
Test status
Simulation time	512900982 ps
CPU time	4.96 seconds
Started	Sep 11 05:01:00 PM UTC 24
Finished	Sep 11 05:01:06 PM UTC 24
Peak memory	209048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246758077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4246758077
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3072234133
Short name	T63
Test name
Test status
Simulation time	167781205 ps
CPU time	2.38 seconds
Started	Sep 11 04:52:23 PM UTC 24
Finished	Sep 11 04:52:27 PM UTC 24
Peak memory	217712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3072234133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w ith_rand_reset.3072234133
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.1099302036
Short name	T45
Test name
Test status
Simulation time	8288769663 ps
CPU time	27.99 seconds
Started	Sep 11 05:01:03 PM UTC 24
Finished	Sep 11 05:01:32 PM UTC 24
Peak memory	241540 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099302036 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1099302036
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.308848843
Short name	T76
Test name
Test status
Simulation time	9285198402 ps
CPU time	45.03 seconds
Started	Sep 11 05:01:14 PM UTC 24
Finished	Sep 11 05:02:01 PM UTC 24
Peak memory	209304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308848843 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.308848843
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1404707905
Short name	T87
Test name
Test status
Simulation time	436740687 ps
CPU time	3.27 seconds
Started	Sep 11 04:52:34 PM UTC 24
Finished	Sep 11 04:52:38 PM UTC 24
Peak memory	208772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404707905 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.1404707905
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.1688775031
Short name	T35
Test name
Test status
Simulation time	154066519 ps
CPU time	2.08 seconds
Started	Sep 11 05:01:20 PM UTC 24
Finished	Sep 11 05:01:24 PM UTC 24
Peak memory	208896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688775031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1688775031
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3680569635
Short name	T3
Test name
Test status
Simulation time	109370412 ps
CPU time	1.49 seconds
Started	Sep 11 05:01:00 PM UTC 24
Finished	Sep 11 05:01:02 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680569635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3680569635
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.2590213416
Short name	T57
Test name
Test status
Simulation time	312743203 ps
CPU time	3.73 seconds
Started	Sep 11 04:52:11 PM UTC 24
Finished	Sep 11 04:52:15 PM UTC 24
Peak memory	217768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590213416 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2590213416
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.2032520624
Short name	T6
Test name
Test status
Simulation time	67748336 ps
CPU time	1.13 seconds
Started	Sep 11 05:01:03 PM UTC 24
Finished	Sep 11 05:01:05 PM UTC 24
Peak memory	207712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032520624 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2032520624
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.296024711
Short name	T54
Test name
Test status
Simulation time	2041342702 ps
CPU time	12.07 seconds
Started	Sep 11 05:01:19 PM UTC 24
Finished	Sep 11 05:01:33 PM UTC 24
Peak memory	209220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296024711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.296024711
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.2783553186
Short name	T55
Test name
Test status
Simulation time	2451000124 ps
CPU time	13.02 seconds
Started	Sep 11 05:02:11 PM UTC 24
Finished	Sep 11 05:02:25 PM UTC 24
Peak memory	242396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783553186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2783553186
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.3795828810
Short name	T136
Test name
Test status
Simulation time	942239351 ps
CPU time	5.28 seconds
Started	Sep 11 04:52:58 PM UTC 24
Finished	Sep 11 04:53:05 PM UTC 24
Peak memory	208908 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795828810 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.3795828810
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.33852029
Short name	T46
Test name
Test status
Simulation time	1273994437 ps
CPU time	8.85 seconds
Started	Sep 11 05:03:15 PM UTC 24
Finished	Sep 11 05:03:25 PM UTC 24
Peak memory	241840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33852029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.33852029
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1972993087
Short name	T65
Test name
Test status
Simulation time	467704170 ps
CPU time	3.21 seconds
Started	Sep 11 04:52:25 PM UTC 24
Finished	Sep 11 04:52:30 PM UTC 24
Peak memory	208844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972993087 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.1972993087
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1660683073
Short name	T115
Test name
Test status
Simulation time	970965052 ps
CPU time	5.47 seconds
Started	Sep 11 04:53:00 PM UTC 24
Finished	Sep 11 04:53:06 PM UTC 24
Peak memory	208852 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660683073 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.1660683073
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2808195636
Short name	T102
Test name
Test status
Simulation time	128912370 ps
CPU time	1.85 seconds
Started	Sep 11 04:52:21 PM UTC 24
Finished	Sep 11 04:52:24 PM UTC 24
Peak memory	207832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808195636 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.2808195636
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.2379775471
Short name	T2
Test name
Test status
Simulation time	202250353 ps
CPU time	1.48 seconds
Started	Sep 11 05:00:58 PM UTC 24
Finished	Sep 11 05:01:01 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379775471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2379775471
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.3349828104
Short name	T577
Test name
Test status
Simulation time	292732484 ps
CPU time	3.46 seconds
Started	Sep 11 04:53:00 PM UTC 24
Finished	Sep 11 04:53:04 PM UTC 24
Peak memory	225164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349828104 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.3349828104
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.59209164
Short name	T79
Test name
Test status
Simulation time	3688193799 ps
CPU time	24.65 seconds
Started	Sep 11 05:02:38 PM UTC 24
Finished	Sep 11 05:03:04 PM UTC 24
Peak memory	218100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59209164 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.59209164
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4007758038
Short name	T61
Test name
Test status
Simulation time	199362943 ps
CPU time	2.37 seconds
Started	Sep 11 04:52:19 PM UTC 24
Finished	Sep 11 04:52:22 PM UTC 24
Peak memory	208840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007758038 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4007758038
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1590507008
Short name	T113
Test name
Test status
Simulation time	478365661 ps
CPU time	8.07 seconds
Started	Sep 11 04:52:18 PM UTC 24
Finished	Sep 11 04:52:27 PM UTC 24
Peak memory	208840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590507008 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1590507008
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3297970362
Short name	T59
Test name
Test status
Simulation time	145983521 ps
CPU time	1.6 seconds
Started	Sep 11 04:52:16 PM UTC 24
Finished	Sep 11 04:52:18 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297970362 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3297970362
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3454692293
Short name	T60
Test name
Test status
Simulation time	85522826 ps
CPU time	1.43 seconds
Started	Sep 11 04:52:18 PM UTC 24
Finished	Sep 11 04:52:20 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454692293 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3454692293
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.951866352
Short name	T58
Test name
Test status
Simulation time	793245393 ps
CPU time	3.51 seconds
Started	Sep 11 04:52:13 PM UTC 24
Finished	Sep 11 04:52:17 PM UTC 24
Peak memory	208768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951866352 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.951866352
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3842287494
Short name	T550
Test name
Test status
Simulation time	204068013 ps
CPU time	2.38 seconds
Started	Sep 11 04:52:30 PM UTC 24
Finished	Sep 11 04:52:34 PM UTC 24
Peak memory	208768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842287494 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3842287494
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.146971478
Short name	T552
Test name
Test status
Simulation time	489959987 ps
CPU time	8.44 seconds
Started	Sep 11 04:52:30 PM UTC 24
Finished	Sep 11 04:52:40 PM UTC 24
Peak memory	208704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146971478 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.146971478
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4244893781
Short name	T549
Test name
Test status
Simulation time	84997557 ps
CPU time	1.18 seconds
Started	Sep 11 04:52:28 PM UTC 24
Finished	Sep 11 04:52:30 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244893781 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4244893781
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2566821256
Short name	T80
Test name
Test status
Simulation time	196398827 ps
CPU time	1.68 seconds
Started	Sep 11 04:52:31 PM UTC 24
Finished	Sep 11 04:52:34 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2566821256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.2566821256
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1104342146
Short name	T138
Test name
Test status
Simulation time	79733607 ps
CPU time	1.32 seconds
Started	Sep 11 04:52:29 PM UTC 24
Finished	Sep 11 04:52:32 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104342146 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1104342146
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1192284103
Short name	T103
Test name
Test status
Simulation time	90690744 ps
CPU time	1.46 seconds
Started	Sep 11 04:52:31 PM UTC 24
Finished	Sep 11 04:52:34 PM UTC 24
Peak memory	207572 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192284103 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.1192284103
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.3635991962
Short name	T64
Test name
Test status
Simulation time	349995977 ps
CPU time	4.35 seconds
Started	Sep 11 04:52:23 PM UTC 24
Finished	Sep 11 04:52:29 PM UTC 24
Peak memory	221784 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635991962 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3635991962
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.2214486038
Short name	T581
Test name
Test status
Simulation time	121607069 ps
CPU time	2.13 seconds
Started	Sep 11 04:53:02 PM UTC 24
Finished	Sep 11 04:53:05 PM UTC 24
Peak memory	217560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2214486038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_ with_rand_reset.2214486038
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.93324964
Short name	T576
Test name
Test status
Simulation time	66949407 ps
CPU time	1.27 seconds
Started	Sep 11 04:53:02 PM UTC 24
Finished	Sep 11 04:53:04 PM UTC 24
Peak memory	207764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93324964 -assert nopostproc +UVM_TESTNAME=rstmgr_ base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10 /rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.93324964
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3182038088
Short name	T579
Test name
Test status
Simulation time	114538865 ps
CPU time	1.53 seconds
Started	Sep 11 04:53:02 PM UTC 24
Finished	Sep 11 04:53:04 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182038088 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.3182038088
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3728602950
Short name	T583
Test name
Test status
Simulation time	204493852 ps
CPU time	2.23 seconds
Started	Sep 11 04:53:03 PM UTC 24
Finished	Sep 11 04:53:06 PM UTC 24
Peak memory	217560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3728602950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_ with_rand_reset.3728602950
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.2070213078
Short name	T578
Test name
Test status
Simulation time	69995743 ps
CPU time	1.36 seconds
Started	Sep 11 04:53:02 PM UTC 24
Finished	Sep 11 04:53:04 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070213078 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2070213078
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1909242907
Short name	T580
Test name
Test status
Simulation time	72326197 ps
CPU time	1.39 seconds
Started	Sep 11 04:53:02 PM UTC 24
Finished	Sep 11 04:53:04 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909242907 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.1909242907
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.3050976092
Short name	T582
Test name
Test status
Simulation time	151568939 ps
CPU time	3.11 seconds
Started	Sep 11 04:53:02 PM UTC 24
Finished	Sep 11 04:53:06 PM UTC 24
Peak memory	217848 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050976092 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3050976092
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.208398397
Short name	T585
Test name
Test status
Simulation time	885409433 ps
CPU time	5.02 seconds
Started	Sep 11 04:53:02 PM UTC 24
Finished	Sep 11 04:53:08 PM UTC 24
Peak memory	208776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208398397 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.208398397
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2609206252
Short name	T587
Test name
Test status
Simulation time	182618073 ps
CPU time	2.16 seconds
Started	Sep 11 04:53:06 PM UTC 24
Finished	Sep 11 04:53:09 PM UTC 24
Peak memory	217560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2609206252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_ with_rand_reset.2609206252
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2440720882
Short name	T584
Test name
Test status
Simulation time	65481380 ps
CPU time	1.2 seconds
Started	Sep 11 04:53:05 PM UTC 24
Finished	Sep 11 04:53:08 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440720882 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.2440720882
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3750454150
Short name	T586
Test name
Test status
Simulation time	197242768 ps
CPU time	1.59 seconds
Started	Sep 11 04:53:05 PM UTC 24
Finished	Sep 11 04:53:08 PM UTC 24
Peak memory	207836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750454150 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.3750454150
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.3800373930
Short name	T592
Test name
Test status
Simulation time	557862245 ps
CPU time	4.7 seconds
Started	Sep 11 04:53:05 PM UTC 24
Finished	Sep 11 04:53:11 PM UTC 24
Peak memory	217704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800373930 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3800373930
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.2234784945
Short name	T119
Test name
Test status
Simulation time	510823591 ps
CPU time	3.43 seconds
Started	Sep 11 04:53:05 PM UTC 24
Finished	Sep 11 04:53:10 PM UTC 24
Peak memory	208772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234784945 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.2234784945
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1684325542
Short name	T591
Test name
Test status
Simulation time	196828582 ps
CPU time	2.13 seconds
Started	Sep 11 04:53:08 PM UTC 24
Finished	Sep 11 04:53:11 PM UTC 24
Peak memory	217560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1684325542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_ with_rand_reset.1684325542
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.3687849796
Short name	T588
Test name
Test status
Simulation time	73665304 ps
CPU time	1.28 seconds
Started	Sep 11 04:53:07 PM UTC 24
Finished	Sep 11 04:53:09 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687849796 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.3687849796
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.379772935
Short name	T589
Test name
Test status
Simulation time	206946678 ps
CPU time	1.62 seconds
Started	Sep 11 04:53:07 PM UTC 24
Finished	Sep 11 04:53:09 PM UTC 24
Peak memory	207724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379772935 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.379772935
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.486512439
Short name	T590
Test name
Test status
Simulation time	440399879 ps
CPU time	3.51 seconds
Started	Sep 11 04:53:06 PM UTC 24
Finished	Sep 11 04:53:10 PM UTC 24
Peak memory	217716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486512439 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.486512439
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1028427142
Short name	T595
Test name
Test status
Simulation time	838331671 ps
CPU time	4.53 seconds
Started	Sep 11 04:53:07 PM UTC 24
Finished	Sep 11 04:53:12 PM UTC 24
Peak memory	208832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028427142 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.1028427142
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2598701
Short name	T597
Test name
Test status
Simulation time	179406518 ps
CPU time	1.86 seconds
Started	Sep 11 04:53:10 PM UTC 24
Finished	Sep 11 04:53:13 PM UTC 24
Peak memory	207776 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2598701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_wit h_rand_reset.2598701
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.480186818
Short name	T593
Test name
Test status
Simulation time	56404303 ps
CPU time	1.16 seconds
Started	Sep 11 04:53:09 PM UTC 24
Finished	Sep 11 04:53:11 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480186818 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.480186818
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3787994688
Short name	T594
Test name
Test status
Simulation time	140706968 ps
CPU time	1.73 seconds
Started	Sep 11 04:53:09 PM UTC 24
Finished	Sep 11 04:53:12 PM UTC 24
Peak memory	207836 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787994688 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.3787994688
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2516849961
Short name	T602
Test name
Test status
Simulation time	513240692 ps
CPU time	5.06 seconds
Started	Sep 11 04:53:09 PM UTC 24
Finished	Sep 11 04:53:15 PM UTC 24
Peak memory	221868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516849961 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2516849961
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1563877355
Short name	T137
Test name
Test status
Simulation time	991376309 ps
CPU time	5.16 seconds
Started	Sep 11 04:53:09 PM UTC 24
Finished	Sep 11 04:53:15 PM UTC 24
Peak memory	208720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563877355 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.1563877355
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.2383223798
Short name	T600
Test name
Test status
Simulation time	207022999 ps
CPU time	2.03 seconds
Started	Sep 11 04:53:11 PM UTC 24
Finished	Sep 11 04:53:14 PM UTC 24
Peak memory	208816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2383223798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_ with_rand_reset.2383223798
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.591150874
Short name	T596
Test name
Test status
Simulation time	77897950 ps
CPU time	1.09 seconds
Started	Sep 11 04:53:10 PM UTC 24
Finished	Sep 11 04:53:12 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591150874 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.591150874
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.2226608879
Short name	T601
Test name
Test status
Simulation time	215023726 ps
CPU time	2.57 seconds
Started	Sep 11 04:53:11 PM UTC 24
Finished	Sep 11 04:53:15 PM UTC 24
Peak memory	208712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226608879 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.2226608879
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2132637359
Short name	T598
Test name
Test status
Simulation time	222317265 ps
CPU time	2.83 seconds
Started	Sep 11 04:53:10 PM UTC 24
Finished	Sep 11 04:53:14 PM UTC 24
Peak memory	217692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132637359 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2132637359
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2216445302
Short name	T599
Test name
Test status
Simulation time	413250969 ps
CPU time	2.98 seconds
Started	Sep 11 04:53:10 PM UTC 24
Finished	Sep 11 04:53:14 PM UTC 24
Peak memory	208844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216445302 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.2216445302
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3497076717
Short name	T604
Test name
Test status
Simulation time	124120740 ps
CPU time	1.94 seconds
Started	Sep 11 04:53:14 PM UTC 24
Finished	Sep 11 04:53:17 PM UTC 24
Peak memory	217508 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3497076717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_ with_rand_reset.3497076717
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.101846320
Short name	T94
Test name
Test status
Simulation time	60865704 ps
CPU time	1.1 seconds
Started	Sep 11 04:53:13 PM UTC 24
Finished	Sep 11 04:53:15 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101846320 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.101846320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.893026785
Short name	T603
Test name
Test status
Simulation time	108704491 ps
CPU time	1.84 seconds
Started	Sep 11 04:53:13 PM UTC 24
Finished	Sep 11 04:53:16 PM UTC 24
Peak memory	207728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893026785 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.893026785
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.72030158
Short name	T609
Test name
Test status
Simulation time	521288774 ps
CPU time	3.68 seconds
Started	Sep 11 04:53:13 PM UTC 24
Finished	Sep 11 04:53:17 PM UTC 24
Peak memory	221868 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72030158 -assert nopostproc +UVM_TESTNAME=rstmgr_bas e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.72030158
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3485242127
Short name	T605
Test name
Test status
Simulation time	950993519 ps
CPU time	3.58 seconds
Started	Sep 11 04:53:13 PM UTC 24
Finished	Sep 11 04:53:17 PM UTC 24
Peak memory	208772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485242127 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.3485242127
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3127330935
Short name	T613
Test name
Test status
Simulation time	200623889 ps
CPU time	2.22 seconds
Started	Sep 11 04:53:16 PM UTC 24
Finished	Sep 11 04:53:19 PM UTC 24
Peak memory	217560 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3127330935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_ with_rand_reset.3127330935
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2395199422
Short name	T606
Test name
Test status
Simulation time	65540108 ps
CPU time	1.24 seconds
Started	Sep 11 04:53:15 PM UTC 24
Finished	Sep 11 04:53:17 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395199422 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2395199422
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.2788335672
Short name	T607
Test name
Test status
Simulation time	78488813 ps
CPU time	1.25 seconds
Started	Sep 11 04:53:15 PM UTC 24
Finished	Sep 11 04:53:17 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788335672 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.2788335672
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.1619905720
Short name	T608
Test name
Test status
Simulation time	116495244 ps
CPU time	2.48 seconds
Started	Sep 11 04:53:14 PM UTC 24
Finished	Sep 11 04:53:17 PM UTC 24
Peak memory	221976 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619905720 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.1619905720
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3738260697
Short name	T116
Test name
Test status
Simulation time	977875952 ps
CPU time	5.26 seconds
Started	Sep 11 04:53:15 PM UTC 24
Finished	Sep 11 04:53:21 PM UTC 24
Peak memory	208772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738260697 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.3738260697
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2536220946
Short name	T610
Test name
Test status
Simulation time	106458068 ps
CPU time	1.14 seconds
Started	Sep 11 04:53:16 PM UTC 24
Finished	Sep 11 04:53:19 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2536220946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_ with_rand_reset.2536220946
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3366348936
Short name	T611
Test name
Test status
Simulation time	69696933 ps
CPU time	1.27 seconds
Started	Sep 11 04:53:16 PM UTC 24
Finished	Sep 11 04:53:19 PM UTC 24
Peak memory	207672 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366348936 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3366348936
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.385347325
Short name	T612
Test name
Test status
Simulation time	113158578 ps
CPU time	1.43 seconds
Started	Sep 11 04:53:16 PM UTC 24
Finished	Sep 11 04:53:19 PM UTC 24
Peak memory	207772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385347325 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.385347325
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1286142248
Short name	T619
Test name
Test status
Simulation time	187324074 ps
CPU time	3.97 seconds
Started	Sep 11 04:53:16 PM UTC 24
Finished	Sep 11 04:53:21 PM UTC 24
Peak memory	221788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286142248 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1286142248
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2953430794
Short name	T616
Test name
Test status
Simulation time	928032476 ps
CPU time	3.2 seconds
Started	Sep 11 04:53:16 PM UTC 24
Finished	Sep 11 04:53:20 PM UTC 24
Peak memory	208772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953430794 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.2953430794
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3251762506
Short name	T615
Test name
Test status
Simulation time	90106200 ps
CPU time	1.34 seconds
Started	Sep 11 04:53:18 PM UTC 24
Finished	Sep 11 04:53:20 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3251762506 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.3251762506
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.2285929388
Short name	T614
Test name
Test status
Simulation time	58868002 ps
CPU time	0.76 seconds
Started	Sep 11 04:53:18 PM UTC 24
Finished	Sep 11 04:53:19 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285929388 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2285929388
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.190100502
Short name	T617
Test name
Test status
Simulation time	263075155 ps
CPU time	1.94 seconds
Started	Sep 11 04:53:18 PM UTC 24
Finished	Sep 11 04:53:21 PM UTC 24
Peak memory	207772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190100502 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.190100502
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.2342200894
Short name	T618
Test name
Test status
Simulation time	177824225 ps
CPU time	2.24 seconds
Started	Sep 11 04:53:18 PM UTC 24
Finished	Sep 11 04:53:21 PM UTC 24
Peak memory	208752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342200894 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2342200894
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.52281800
Short name	T620
Test name
Test status
Simulation time	1045614765 ps
CPU time	3.87 seconds
Started	Sep 11 04:53:18 PM UTC 24
Finished	Sep 11 04:53:22 PM UTC 24
Peak memory	208764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52281800 -assert nopostproc +UVM_TESTNAM E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.52281800
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.1298081244
Short name	T553
Test name
Test status
Simulation time	343958113 ps
CPU time	3.93 seconds
Started	Sep 11 04:52:37 PM UTC 24
Finished	Sep 11 04:52:43 PM UTC 24
Peak memory	208832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298081244 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.1298081244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.49666587
Short name	T556
Test name
Test status
Simulation time	1024080264 ps
CPU time	8.62 seconds
Started	Sep 11 04:52:37 PM UTC 24
Finished	Sep 11 04:52:47 PM UTC 24
Peak memory	208912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49666587 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.49666587
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4126586744
Short name	T551
Test name
Test status
Simulation time	85945528 ps
CPU time	1.3 seconds
Started	Sep 11 04:52:34 PM UTC 24
Finished	Sep 11 04:52:37 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126586744 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4126586744
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2967550198
Short name	T82
Test name
Test status
Simulation time	115648197 ps
CPU time	1.53 seconds
Started	Sep 11 04:52:39 PM UTC 24
Finished	Sep 11 04:52:41 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2967550198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w ith_rand_reset.2967550198
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.1633212216
Short name	T104
Test name
Test status
Simulation time	76067282 ps
CPU time	1.26 seconds
Started	Sep 11 04:52:35 PM UTC 24
Finished	Sep 11 04:52:38 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633212216 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1633212216
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2652831283
Short name	T105
Test name
Test status
Simulation time	85403810 ps
CPU time	1.62 seconds
Started	Sep 11 04:52:39 PM UTC 24
Finished	Sep 11 04:52:41 PM UTC 24
Peak memory	207832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652831283 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.2652831283
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2356406909
Short name	T81
Test name
Test status
Simulation time	499194516 ps
CPU time	4.91 seconds
Started	Sep 11 04:52:32 PM UTC 24
Finished	Sep 11 04:52:38 PM UTC 24
Peak memory	217688 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356406909 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2356406909
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.1907293087
Short name	T555
Test name
Test status
Simulation time	113981933 ps
CPU time	2.18 seconds
Started	Sep 11 04:52:43 PM UTC 24
Finished	Sep 11 04:52:46 PM UTC 24
Peak memory	208824 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907293087 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.1907293087
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2636874156
Short name	T559
Test name
Test status
Simulation time	815628579 ps
CPU time	7.77 seconds
Started	Sep 11 04:52:42 PM UTC 24
Finished	Sep 11 04:52:51 PM UTC 24
Peak memory	208764 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636874156 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2636874156
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2904809872
Short name	T554
Test name
Test status
Simulation time	95236612 ps
CPU time	1.33 seconds
Started	Sep 11 04:52:41 PM UTC 24
Finished	Sep 11 04:52:43 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904809872 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2904809872
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.483916297
Short name	T84
Test name
Test status
Simulation time	123025068 ps
CPU time	1.48 seconds
Started	Sep 11 04:52:44 PM UTC 24
Finished	Sep 11 04:52:47 PM UTC 24
Peak memory	207704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=483916297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_wi th_rand_reset.483916297
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.2396130636
Short name	T106
Test name
Test status
Simulation time	62693981 ps
CPU time	1.22 seconds
Started	Sep 11 04:52:42 PM UTC 24
Finished	Sep 11 04:52:45 PM UTC 24
Peak memory	207616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396130636 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2396130636
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1211381791
Short name	T107
Test name
Test status
Simulation time	141414568 ps
CPU time	1.83 seconds
Started	Sep 11 04:52:43 PM UTC 24
Finished	Sep 11 04:52:46 PM UTC 24
Peak memory	207832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211381791 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.1211381791
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.301375227
Short name	T83
Test name
Test status
Simulation time	302206950 ps
CPU time	3.68 seconds
Started	Sep 11 04:52:39 PM UTC 24
Finished	Sep 11 04:52:43 PM UTC 24
Peak memory	217696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301375227 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.301375227
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1387422500
Short name	T135
Test name
Test status
Simulation time	496949936 ps
CPU time	3.32 seconds
Started	Sep 11 04:52:40 PM UTC 24
Finished	Sep 11 04:52:44 PM UTC 24
Peak memory	208844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387422500 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.1387422500
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.4218356407
Short name	T558
Test name
Test status
Simulation time	204250232 ps
CPU time	1.94 seconds
Started	Sep 11 04:52:48 PM UTC 24
Finished	Sep 11 04:52:51 PM UTC 24
Peak memory	207656 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218356407 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.4218356407
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.740860182
Short name	T560
Test name
Test status
Simulation time	265283887 ps
CPU time	3.75 seconds
Started	Sep 11 04:52:48 PM UTC 24
Finished	Sep 11 04:52:53 PM UTC 24
Peak memory	217164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740860182 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.740860182
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3477810470
Short name	T557
Test name
Test status
Simulation time	131827527 ps
CPU time	1.55 seconds
Started	Sep 11 04:52:45 PM UTC 24
Finished	Sep 11 04:52:48 PM UTC 24
Peak memory	207700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477810470 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3477810470
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2810250230
Short name	T86
Test name
Test status
Simulation time	97579401 ps
CPU time	1.47 seconds
Started	Sep 11 04:52:48 PM UTC 24
Finished	Sep 11 04:52:50 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2810250230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w ith_rand_reset.2810250230
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.421996533
Short name	T108
Test name
Test status
Simulation time	61868764 ps
CPU time	1.19 seconds
Started	Sep 11 04:52:48 PM UTC 24
Finished	Sep 11 04:52:50 PM UTC 24
Peak memory	207200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421996533 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.421996533
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.215537210
Short name	T109
Test name
Test status
Simulation time	90745401 ps
CPU time	1.63 seconds
Started	Sep 11 04:52:48 PM UTC 24
Finished	Sep 11 04:52:51 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215537210 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.215537210
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.4284455619
Short name	T85
Test name
Test status
Simulation time	241360867 ps
CPU time	3.32 seconds
Started	Sep 11 04:52:44 PM UTC 24
Finished	Sep 11 04:52:49 PM UTC 24
Peak memory	217752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284455619 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.4284455619
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1108267034
Short name	T117
Test name
Test status
Simulation time	462332812 ps
CPU time	3.3 seconds
Started	Sep 11 04:52:45 PM UTC 24
Finished	Sep 11 04:52:50 PM UTC 24
Peak memory	208772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108267034 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.1108267034
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.4040910876
Short name	T121
Test name
Test status
Simulation time	157868435 ps
CPU time	2.36 seconds
Started	Sep 11 04:52:51 PM UTC 24
Finished	Sep 11 04:52:55 PM UTC 24
Peak memory	217772 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4040910876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w ith_rand_reset.4040910876
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.3272713804
Short name	T110
Test name
Test status
Simulation time	55121410 ps
CPU time	1.18 seconds
Started	Sep 11 04:52:50 PM UTC 24
Finished	Sep 11 04:52:52 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272713804 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3272713804
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3800565819
Short name	T562
Test name
Test status
Simulation time	139522324 ps
CPU time	1.91 seconds
Started	Sep 11 04:52:51 PM UTC 24
Finished	Sep 11 04:52:54 PM UTC 24
Peak memory	207780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800565819 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.3800565819
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2076622787
Short name	T561
Test name
Test status
Simulation time	355775393 ps
CPU time	3.98 seconds
Started	Sep 11 04:52:49 PM UTC 24
Finished	Sep 11 04:52:54 PM UTC 24
Peak memory	217704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076622787 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2076622787
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2182922263
Short name	T118
Test name
Test status
Simulation time	464159640 ps
CPU time	3.22 seconds
Started	Sep 11 04:52:49 PM UTC 24
Finished	Sep 11 04:52:53 PM UTC 24
Peak memory	208752 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182922263 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.2182922263
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1140353864
Short name	T564
Test name
Test status
Simulation time	126859054 ps
CPU time	1.7 seconds
Started	Sep 11 04:52:54 PM UTC 24
Finished	Sep 11 04:52:56 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1140353864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.1140353864
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2578923759
Short name	T111
Test name
Test status
Simulation time	67733198 ps
CPU time	1.24 seconds
Started	Sep 11 04:52:51 PM UTC 24
Finished	Sep 11 04:52:54 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578923759 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2578923759
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2623398646
Short name	T563
Test name
Test status
Simulation time	137482207 ps
CPU time	1.79 seconds
Started	Sep 11 04:52:53 PM UTC 24
Finished	Sep 11 04:52:55 PM UTC 24
Peak memory	207832 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623398646 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.2623398646
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2094024254
Short name	T122
Test name
Test status
Simulation time	228239927 ps
CPU time	2.83 seconds
Started	Sep 11 04:52:51 PM UTC 24
Finished	Sep 11 04:52:55 PM UTC 24
Peak memory	217724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094024254 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2094024254
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1523403601
Short name	T133
Test name
Test status
Simulation time	409292427 ps
CPU time	3.08 seconds
Started	Sep 11 04:52:51 PM UTC 24
Finished	Sep 11 04:52:56 PM UTC 24
Peak memory	208788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523403601 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.1523403601
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3573317725
Short name	T567
Test name
Test status
Simulation time	198356152 ps
CPU time	2.08 seconds
Started	Sep 11 04:52:55 PM UTC 24
Finished	Sep 11 04:52:58 PM UTC 24
Peak memory	208692 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3573317725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w ith_rand_reset.3573317725
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.485258800
Short name	T565
Test name
Test status
Simulation time	62534040 ps
CPU time	1.27 seconds
Started	Sep 11 04:52:55 PM UTC 24
Finished	Sep 11 04:52:57 PM UTC 24
Peak memory	207636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485258800 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.485258800
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2895250906
Short name	T566
Test name
Test status
Simulation time	136498100 ps
CPU time	2.06 seconds
Started	Sep 11 04:52:55 PM UTC 24
Finished	Sep 11 04:52:58 PM UTC 24
Peak memory	208788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895250906 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.2895250906
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.727425878
Short name	T114
Test name
Test status
Simulation time	95867997 ps
CPU time	1.7 seconds
Started	Sep 11 04:52:54 PM UTC 24
Finished	Sep 11 04:52:56 PM UTC 24
Peak memory	207796 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727425878 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.727425878
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1524825180
Short name	T134
Test name
Test status
Simulation time	490776348 ps
CPU time	3.16 seconds
Started	Sep 11 04:52:54 PM UTC 24
Finished	Sep 11 04:52:58 PM UTC 24
Peak memory	208788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524825180 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.1524825180
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2686008854
Short name	T572
Test name
Test status
Simulation time	161028462 ps
CPU time	2.54 seconds
Started	Sep 11 04:52:57 PM UTC 24
Finished	Sep 11 04:53:01 PM UTC 24
Peak memory	217728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2686008854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w ith_rand_reset.2686008854
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2187015608
Short name	T568
Test name
Test status
Simulation time	65524872 ps
CPU time	1.19 seconds
Started	Sep 11 04:52:56 PM UTC 24
Finished	Sep 11 04:52:58 PM UTC 24
Peak memory	207768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187015608 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2187015608
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.879792311
Short name	T569
Test name
Test status
Simulation time	108731846 ps
CPU time	1.96 seconds
Started	Sep 11 04:52:56 PM UTC 24
Finished	Sep 11 04:52:59 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879792311 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.879792311
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3348837761
Short name	T573
Test name
Test status
Simulation time	341401859 ps
CPU time	3.82 seconds
Started	Sep 11 04:52:56 PM UTC 24
Finished	Sep 11 04:53:01 PM UTC 24
Peak memory	217704 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348837761 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3348837761
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.3733278965
Short name	T120
Test name
Test status
Simulation time	783576913 ps
CPU time	3.78 seconds
Started	Sep 11 04:52:56 PM UTC 24
Finished	Sep 11 04:53:01 PM UTC 24
Peak memory	208844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733278965 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.3733278965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.1589585951
Short name	T574
Test name
Test status
Simulation time	129527193 ps
CPU time	1.48 seconds
Started	Sep 11 04:52:59 PM UTC 24
Finished	Sep 11 04:53:01 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1589585951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w ith_rand_reset.1589585951
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.936177796
Short name	T570
Test name
Test status
Simulation time	66280241 ps
CPU time	1.21 seconds
Started	Sep 11 04:52:58 PM UTC 24
Finished	Sep 11 04:53:01 PM UTC 24
Peak memory	207636 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936177796 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1 0/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.936177796
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.543508633
Short name	T575
Test name
Test status
Simulation time	161283192 ps
CPU time	1.88 seconds
Started	Sep 11 04:52:58 PM UTC 24
Finished	Sep 11 04:53:01 PM UTC 24
Peak memory	207708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543508633 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.543508633
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3418691955
Short name	T571
Test name
Test status
Simulation time	101497638 ps
CPU time	2.43 seconds
Started	Sep 11 04:52:57 PM UTC 24
Finished	Sep 11 04:53:01 PM UTC 24
Peak memory	217816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418691955 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3418691955
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.4144568295
Short name	T13
Test name
Test status
Simulation time	1957636669 ps
CPU time	13.84 seconds
Started	Sep 11 05:01:00 PM UTC 24
Finished	Sep 11 05:01:15 PM UTC 24
Peak memory	242404 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144568295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.4144568295
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.4083214993
Short name	T5
Test name
Test status
Simulation time	302200420 ps
CPU time	1.97 seconds
Started	Sep 11 05:01:01 PM UTC 24
Finished	Sep 11 05:01:04 PM UTC 24
Peak memory	237612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083214993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.4083214993
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.720994945
Short name	T10
Test name
Test status
Simulation time	1367741230 ps
CPU time	10.07 seconds
Started	Sep 11 05:00:58 PM UTC 24
Finished	Sep 11 05:01:10 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720994945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.720994945
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.1857327672
Short name	T1
Test name
Test status
Simulation time	116951175 ps
CPU time	1.95 seconds
Started	Sep 11 05:00:56 PM UTC 24
Finished	Sep 11 05:00:59 PM UTC 24
Peak memory	208648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857327672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.1857327672
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.4274935983
Short name	T70
Test name
Test status
Simulation time	7584970939 ps
CPU time	34.7 seconds
Started	Sep 11 05:01:02 PM UTC 24
Finished	Sep 11 05:01:38 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274935983 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.4274935983
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.3928974706
Short name	T4
Test name
Test status
Simulation time	138075745 ps
CPU time	1.63 seconds
Started	Sep 11 05:01:00 PM UTC 24
Finished	Sep 11 05:01:02 PM UTC 24
Peak memory	208296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928974706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3928974706
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.847016244
Short name	T34
Test name
Test status
Simulation time	72027558 ps
CPU time	1.24 seconds
Started	Sep 11 05:01:16 PM UTC 24
Finished	Sep 11 05:01:19 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847016244 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.847016244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3796578898
Short name	T24
Test name
Test status
Simulation time	303359980 ps
CPU time	1.98 seconds
Started	Sep 11 05:01:12 PM UTC 24
Finished	Sep 11 05:01:15 PM UTC 24
Peak memory	237316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796578898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.3796578898
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.2800865451
Short name	T9
Test name
Test status
Simulation time	175356056 ps
CPU time	1.44 seconds
Started	Sep 11 05:01:06 PM UTC 24
Finished	Sep 11 05:01:09 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800865451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2800865451
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.4288953245
Short name	T22
Test name
Test status
Simulation time	1579468324 ps
CPU time	10.47 seconds
Started	Sep 11 05:01:06 PM UTC 24
Finished	Sep 11 05:01:18 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288953245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.4288953245
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.2610137919
Short name	T43
Test name
Test status
Simulation time	8520885065 ps
CPU time	13.43 seconds
Started	Sep 11 05:01:14 PM UTC 24
Finished	Sep 11 05:01:29 PM UTC 24
Peak memory	241812 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610137919 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2610137919
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.374364712
Short name	T12
Test name
Test status
Simulation time	169273264 ps
CPU time	1.99 seconds
Started	Sep 11 05:01:10 PM UTC 24
Finished	Sep 11 05:01:13 PM UTC 24
Peak memory	208240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374364712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.374364712
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2865466634
Short name	T56
Test name
Test status
Simulation time	280155393 ps
CPU time	2.7 seconds
Started	Sep 11 05:01:10 PM UTC 24
Finished	Sep 11 05:01:13 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865466634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2865466634
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1644675657
Short name	T11
Test name
Test status
Simulation time	88231682 ps
CPU time	1.44 seconds
Started	Sep 11 05:01:08 PM UTC 24
Finished	Sep 11 05:01:11 PM UTC 24
Peak memory	208296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644675657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1644675657
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.2115789389
Short name	T172
Test name
Test status
Simulation time	63358721 ps
CPU time	1.23 seconds
Started	Sep 11 05:02:32 PM UTC 24
Finished	Sep 11 05:02:34 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115789389 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2115789389
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.2524328041
Short name	T33
Test name
Test status
Simulation time	1263246577 ps
CPU time	9.61 seconds
Started	Sep 11 05:02:30 PM UTC 24
Finished	Sep 11 05:02:41 PM UTC 24
Peak memory	251964 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524328041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.2524328041
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4024347247
Short name	T173
Test name
Test status
Simulation time	301192944 ps
CPU time	2.14 seconds
Started	Sep 11 05:02:32 PM UTC 24
Finished	Sep 11 05:02:35 PM UTC 24
Peak memory	237760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024347247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.4024347247
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.3472058323
Short name	T166
Test name
Test status
Simulation time	155452115 ps
CPU time	1.44 seconds
Started	Sep 11 05:02:29 PM UTC 24
Finished	Sep 11 05:02:31 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472058323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3472058323
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.4164781207
Short name	T175
Test name
Test status
Simulation time	815291047 ps
CPU time	6.05 seconds
Started	Sep 11 05:02:29 PM UTC 24
Finished	Sep 11 05:02:36 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164781207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.4164781207
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1274250838
Short name	T168
Test name
Test status
Simulation time	114365657 ps
CPU time	1.63 seconds
Started	Sep 11 05:02:30 PM UTC 24
Finished	Sep 11 05:02:33 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274250838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1274250838
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.108715836
Short name	T167
Test name
Test status
Simulation time	226540865 ps
CPU time	2.34 seconds
Started	Sep 11 05:02:29 PM UTC 24
Finished	Sep 11 05:02:32 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108715836 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.108715836
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.452464298
Short name	T218
Test name
Test status
Simulation time	5153489752 ps
CPU time	33.98 seconds
Started	Sep 11 05:02:32 PM UTC 24
Finished	Sep 11 05:03:07 PM UTC 24
Peak memory	218100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452464298 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.452464298
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.2353204908
Short name	T174
Test name
Test status
Simulation time	501371857 ps
CPU time	4.29 seconds
Started	Sep 11 05:02:30 PM UTC 24
Finished	Sep 11 05:02:36 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353204908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2353204908
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.2803455327
Short name	T171
Test name
Test status
Simulation time	206331584 ps
CPU time	2.23 seconds
Started	Sep 11 05:02:30 PM UTC 24
Finished	Sep 11 05:02:34 PM UTC 24
Peak memory	208900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803455327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2803455327
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.3095516941
Short name	T180
Test name
Test status
Simulation time	60359295 ps
CPU time	1.21 seconds
Started	Sep 11 05:02:38 PM UTC 24
Finished	Sep 11 05:02:41 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095516941 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3095516941
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.2549605021
Short name	T38
Test name
Test status
Simulation time	1965970955 ps
CPU time	12.15 seconds
Started	Sep 11 05:02:36 PM UTC 24
Finished	Sep 11 05:02:50 PM UTC 24
Peak memory	241700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549605021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2549605021
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.330618261
Short name	T181
Test name
Test status
Simulation time	301372032 ps
CPU time	1.69 seconds
Started	Sep 11 05:02:38 PM UTC 24
Finished	Sep 11 05:02:41 PM UTC 24
Peak memory	237444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330618261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.330618261
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3862245226
Short name	T177
Test name
Test status
Simulation time	197358149 ps
CPU time	1.48 seconds
Started	Sep 11 05:02:36 PM UTC 24
Finished	Sep 11 05:02:38 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862245226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3862245226
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.1231392569
Short name	T123
Test name
Test status
Simulation time	1557495873 ps
CPU time	6.19 seconds
Started	Sep 11 05:02:36 PM UTC 24
Finished	Sep 11 05:02:43 PM UTC 24
Peak memory	209208 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231392569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1231392569
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3857308475
Short name	T178
Test name
Test status
Simulation time	146666160 ps
CPU time	1.85 seconds
Started	Sep 11 05:02:36 PM UTC 24
Finished	Sep 11 05:02:39 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857308475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3857308475
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.2670276150
Short name	T176
Test name
Test status
Simulation time	118330102 ps
CPU time	1.85 seconds
Started	Sep 11 05:02:33 PM UTC 24
Finished	Sep 11 05:02:36 PM UTC 24
Peak memory	208264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670276150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.2670276150
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.2388885615
Short name	T182
Test name
Test status
Simulation time	481949348 ps
CPU time	4.49 seconds
Started	Sep 11 05:02:36 PM UTC 24
Finished	Sep 11 05:02:41 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388885615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2388885615
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.4259501104
Short name	T179
Test name
Test status
Simulation time	242779214 ps
CPU time	1.91 seconds
Started	Sep 11 05:02:36 PM UTC 24
Finished	Sep 11 05:02:39 PM UTC 24
Peak memory	208204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259501104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.4259501104
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3988118247
Short name	T188
Test name
Test status
Simulation time	92817442 ps
CPU time	1.32 seconds
Started	Sep 11 05:02:44 PM UTC 24
Finished	Sep 11 05:02:46 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988118247 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3988118247
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.98074668
Short name	T204
Test name
Test status
Simulation time	2261874841 ps
CPU time	14.08 seconds
Started	Sep 11 05:02:44 PM UTC 24
Finished	Sep 11 05:02:59 PM UTC 24
Peak memory	241696 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98074668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.98074668
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2580168616
Short name	T189
Test name
Test status
Simulation time	301870677 ps
CPU time	1.92 seconds
Started	Sep 11 05:02:44 PM UTC 24
Finished	Sep 11 05:02:47 PM UTC 24
Peak memory	237408 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580168616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2580168616
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3546544949
Short name	T184
Test name
Test status
Simulation time	142066529 ps
CPU time	1.28 seconds
Started	Sep 11 05:02:40 PM UTC 24
Finished	Sep 11 05:02:42 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546544949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3546544949
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.989237219
Short name	T98
Test name
Test status
Simulation time	791919910 ps
CPU time	4.76 seconds
Started	Sep 11 05:02:40 PM UTC 24
Finished	Sep 11 05:02:46 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989237219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.989237219
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2511317742
Short name	T187
Test name
Test status
Simulation time	108446399 ps
CPU time	1.48 seconds
Started	Sep 11 05:02:44 PM UTC 24
Finished	Sep 11 05:02:46 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511317742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2511317742
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.2054954827
Short name	T183
Test name
Test status
Simulation time	204076596 ps
CPU time	2.3 seconds
Started	Sep 11 05:02:38 PM UTC 24
Finished	Sep 11 05:02:42 PM UTC 24
Peak memory	209120 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054954827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2054954827
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.1407806762
Short name	T100
Test name
Test status
Simulation time	4324241682 ps
CPU time	16.06 seconds
Started	Sep 11 05:02:44 PM UTC 24
Finished	Sep 11 05:03:01 PM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407806762 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1407806762
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.2879361537
Short name	T186
Test name
Test status
Simulation time	351234220 ps
CPU time	3.69 seconds
Started	Sep 11 05:02:41 PM UTC 24
Finished	Sep 11 05:02:46 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879361537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2879361537
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.3935321724
Short name	T185
Test name
Test status
Simulation time	123150088 ps
CPU time	1.7 seconds
Started	Sep 11 05:02:40 PM UTC 24
Finished	Sep 11 05:02:43 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935321724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3935321724
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2111083087
Short name	T197
Test name
Test status
Simulation time	70984614 ps
CPU time	1.24 seconds
Started	Sep 11 05:02:50 PM UTC 24
Finished	Sep 11 05:02:53 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111083087 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2111083087
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.1595539271
Short name	T202
Test name
Test status
Simulation time	2461052867 ps
CPU time	8.74 seconds
Started	Sep 11 05:02:48 PM UTC 24
Finished	Sep 11 05:02:57 PM UTC 24
Peak memory	242056 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595539271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1595539271
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1741443770
Short name	T194
Test name
Test status
Simulation time	302122382 ps
CPU time	1.99 seconds
Started	Sep 11 05:02:48 PM UTC 24
Finished	Sep 11 05:02:51 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741443770 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1741443770
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.4224445197
Short name	T191
Test name
Test status
Simulation time	153162175 ps
CPU time	1.52 seconds
Started	Sep 11 05:02:45 PM UTC 24
Finished	Sep 11 05:02:48 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224445197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.4224445197
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.839589081
Short name	T101
Test name
Test status
Simulation time	1553375206 ps
CPU time	10.01 seconds
Started	Sep 11 05:02:47 PM UTC 24
Finished	Sep 11 05:02:59 PM UTC 24
Peak memory	209368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839589081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.839589081
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1035883473
Short name	T192
Test name
Test status
Simulation time	94777296 ps
CPU time	1.43 seconds
Started	Sep 11 05:02:48 PM UTC 24
Finished	Sep 11 05:02:50 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035883473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1035883473
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.3833885218
Short name	T190
Test name
Test status
Simulation time	190399317 ps
CPU time	1.82 seconds
Started	Sep 11 05:02:44 PM UTC 24
Finished	Sep 11 05:02:47 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833885218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3833885218
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.252043989
Short name	T196
Test name
Test status
Simulation time	206527626 ps
CPU time	2.15 seconds
Started	Sep 11 05:02:49 PM UTC 24
Finished	Sep 11 05:02:52 PM UTC 24
Peak memory	208960 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252043989 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.252043989
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.1563529763
Short name	T195
Test name
Test status
Simulation time	347651856 ps
CPU time	3.55 seconds
Started	Sep 11 05:02:48 PM UTC 24
Finished	Sep 11 05:02:52 PM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563529763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1563529763
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.4108807690
Short name	T193
Test name
Test status
Simulation time	157283248 ps
CPU time	1.79 seconds
Started	Sep 11 05:02:48 PM UTC 24
Finished	Sep 11 05:02:50 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108807690 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.4108807690
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.1018137365
Short name	T206
Test name
Test status
Simulation time	62947302 ps
CPU time	1.19 seconds
Started	Sep 11 05:02:57 PM UTC 24
Finished	Sep 11 05:03:00 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018137365 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1018137365
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.721311053
Short name	T210
Test name
Test status
Simulation time	1966583200 ps
CPU time	7.45 seconds
Started	Sep 11 05:02:54 PM UTC 24
Finished	Sep 11 05:03:03 PM UTC 24
Peak memory	241892 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721311053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.721311053
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.4223091079
Short name	T203
Test name
Test status
Simulation time	302235550 ps
CPU time	2.19 seconds
Started	Sep 11 05:02:54 PM UTC 24
Finished	Sep 11 05:02:58 PM UTC 24
Peak memory	237760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223091079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.4223091079
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.2773573139
Short name	T198
Test name
Test status
Simulation time	116486828 ps
CPU time	1.37 seconds
Started	Sep 11 05:02:52 PM UTC 24
Finished	Sep 11 05:02:55 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773573139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2773573139
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.3232332083
Short name	T124
Test name
Test status
Simulation time	1826596022 ps
CPU time	9.49 seconds
Started	Sep 11 05:02:53 PM UTC 24
Finished	Sep 11 05:03:03 PM UTC 24
Peak memory	209308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232332083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3232332083
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.32592290
Short name	T201
Test name
Test status
Simulation time	102026863 ps
CPU time	1.55 seconds
Started	Sep 11 05:02:54 PM UTC 24
Finished	Sep 11 05:02:57 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32592290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.32592290
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.3111023748
Short name	T199
Test name
Test status
Simulation time	122859712 ps
CPU time	1.91 seconds
Started	Sep 11 05:02:52 PM UTC 24
Finished	Sep 11 05:02:55 PM UTC 24
Peak memory	208260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111023748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3111023748
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.2431498580
Short name	T316
Test name
Test status
Simulation time	14954558924 ps
CPU time	59.85 seconds
Started	Sep 11 05:02:56 PM UTC 24
Finished	Sep 11 05:03:57 PM UTC 24
Peak memory	218096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431498580 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2431498580
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.2880256117
Short name	T205
Test name
Test status
Simulation time	492655551 ps
CPU time	3.94 seconds
Started	Sep 11 05:02:54 PM UTC 24
Finished	Sep 11 05:02:59 PM UTC 24
Peak memory	209048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880256117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.2880256117
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.1029890950
Short name	T200
Test name
Test status
Simulation time	307737655 ps
CPU time	2.64 seconds
Started	Sep 11 05:02:53 PM UTC 24
Finished	Sep 11 05:02:56 PM UTC 24
Peak memory	209028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029890950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.1029890950
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.3868350309
Short name	T214
Test name
Test status
Simulation time	69123874 ps
CPU time	1.05 seconds
Started	Sep 11 05:03:03 PM UTC 24
Finished	Sep 11 05:03:05 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868350309 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.3868350309
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.4259888606
Short name	T228
Test name
Test status
Simulation time	1958372008 ps
CPU time	10.61 seconds
Started	Sep 11 05:03:01 PM UTC 24
Finished	Sep 11 05:03:13 PM UTC 24
Peak memory	241620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259888606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4259888606
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1925474346
Short name	T211
Test name
Test status
Simulation time	302114265 ps
CPU time	1.39 seconds
Started	Sep 11 05:03:01 PM UTC 24
Finished	Sep 11 05:03:04 PM UTC 24
Peak memory	237380 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925474346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1925474346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.2805120825
Short name	T208
Test name
Test status
Simulation time	141662587 ps
CPU time	1.37 seconds
Started	Sep 11 05:02:59 PM UTC 24
Finished	Sep 11 05:03:01 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805120825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2805120825
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.3337649915
Short name	T219
Test name
Test status
Simulation time	1427835152 ps
CPU time	7.37 seconds
Started	Sep 11 05:02:59 PM UTC 24
Finished	Sep 11 05:03:08 PM UTC 24
Peak memory	209312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337649915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3337649915
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.1452560
Short name	T212
Test name
Test status
Simulation time	101027626 ps
CPU time	1.54 seconds
Started	Sep 11 05:03:01 PM UTC 24
Finished	Sep 11 05:03:04 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.1452560
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.771907344
Short name	T78
Test name
Test status
Simulation time	113607435 ps
CPU time	1.87 seconds
Started	Sep 11 05:02:57 PM UTC 24
Finished	Sep 11 05:03:00 PM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771907344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.771907344
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.1091387067
Short name	T324
Test name
Test status
Simulation time	16127072706 ps
CPU time	58.39 seconds
Started	Sep 11 05:03:01 PM UTC 24
Finished	Sep 11 05:04:01 PM UTC 24
Peak memory	209212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091387067 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1091387067
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.1384306048
Short name	T213
Test name
Test status
Simulation time	270400883 ps
CPU time	2.75 seconds
Started	Sep 11 05:03:01 PM UTC 24
Finished	Sep 11 05:03:05 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384306048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.1384306048
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.28324666
Short name	T209
Test name
Test status
Simulation time	70695234 ps
CPU time	1.26 seconds
Started	Sep 11 05:02:59 PM UTC 24
Finished	Sep 11 05:03:02 PM UTC 24
Peak memory	208300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28324666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.28324666
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.3477232733
Short name	T221
Test name
Test status
Simulation time	138327193 ps
CPU time	1.45 seconds
Started	Sep 11 05:03:07 PM UTC 24
Finished	Sep 11 05:03:09 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477232733 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.3477232733
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.3095488337
Short name	T39
Test name
Test status
Simulation time	1274538773 ps
CPU time	9.47 seconds
Started	Sep 11 05:03:06 PM UTC 24
Finished	Sep 11 05:03:17 PM UTC 24
Peak memory	241700 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095488337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3095488337
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3099181293
Short name	T224
Test name
Test status
Simulation time	301876356 ps
CPU time	2.21 seconds
Started	Sep 11 05:03:06 PM UTC 24
Finished	Sep 11 05:03:10 PM UTC 24
Peak memory	237760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099181293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3099181293
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.357173193
Short name	T215
Test name
Test status
Simulation time	210613188 ps
CPU time	1.23 seconds
Started	Sep 11 05:03:04 PM UTC 24
Finished	Sep 11 05:03:06 PM UTC 24
Peak memory	208180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357173193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.357173193
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.1704907779
Short name	T125
Test name
Test status
Simulation time	1907177909 ps
CPU time	8.37 seconds
Started	Sep 11 05:03:04 PM UTC 24
Finished	Sep 11 05:03:13 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704907779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1704907779
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1211952964
Short name	T222
Test name
Test status
Simulation time	170204356 ps
CPU time	2.03 seconds
Started	Sep 11 05:03:06 PM UTC 24
Finished	Sep 11 05:03:09 PM UTC 24
Peak memory	209032 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211952964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1211952964
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.2234975758
Short name	T217
Test name
Test status
Simulation time	112980879 ps
CPU time	1.98 seconds
Started	Sep 11 05:03:03 PM UTC 24
Finished	Sep 11 05:03:06 PM UTC 24
Peak memory	208260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234975758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2234975758
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.2492104866
Short name	T251
Test name
Test status
Simulation time	2170664534 ps
CPU time	16.66 seconds
Started	Sep 11 05:03:07 PM UTC 24
Finished	Sep 11 05:03:24 PM UTC 24
Peak memory	218220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492104866 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2492104866
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.658620707
Short name	T223
Test name
Test status
Simulation time	111830384 ps
CPU time	2.21 seconds
Started	Sep 11 05:03:06 PM UTC 24
Finished	Sep 11 05:03:10 PM UTC 24
Peak memory	208880 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658620707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.658620707
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.146176548
Short name	T216
Test name
Test status
Simulation time	120821907 ps
CPU time	1.34 seconds
Started	Sep 11 05:03:04 PM UTC 24
Finished	Sep 11 05:03:06 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146176548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.146176548
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.2510712870
Short name	T230
Test name
Test status
Simulation time	64530735 ps
CPU time	1.19 seconds
Started	Sep 11 05:03:13 PM UTC 24
Finished	Sep 11 05:03:15 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510712870 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2510712870
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.3867004877
Short name	T40
Test name
Test status
Simulation time	2429418701 ps
CPU time	10.9 seconds
Started	Sep 11 05:03:10 PM UTC 24
Finished	Sep 11 05:03:22 PM UTC 24
Peak memory	241788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867004877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3867004877
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.4135956257
Short name	T229
Test name
Test status
Simulation time	302249706 ps
CPU time	1.92 seconds
Started	Sep 11 05:03:10 PM UTC 24
Finished	Sep 11 05:03:13 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135956257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.4135956257
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1409533546
Short name	T220
Test name
Test status
Simulation time	107700161 ps
CPU time	1.28 seconds
Started	Sep 11 05:03:07 PM UTC 24
Finished	Sep 11 05:03:09 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409533546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1409533546
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.2877959
Short name	T238
Test name
Test status
Simulation time	1284281135 ps
CPU time	9.46 seconds
Started	Sep 11 05:03:08 PM UTC 24
Finished	Sep 11 05:03:19 PM UTC 24
Peak memory	209188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2877959
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3364244805
Short name	T225
Test name
Test status
Simulation time	101248269 ps
CPU time	1.5 seconds
Started	Sep 11 05:03:08 PM UTC 24
Finished	Sep 11 05:03:11 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364244805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3364244805
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.3447496338
Short name	T170
Test name
Test status
Simulation time	125901726 ps
CPU time	1.86 seconds
Started	Sep 11 05:03:07 PM UTC 24
Finished	Sep 11 05:03:10 PM UTC 24
Peak memory	208252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447496338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.3447496338
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.1830734807
Short name	T273
Test name
Test status
Simulation time	6456667770 ps
CPU time	22.19 seconds
Started	Sep 11 05:03:13 PM UTC 24
Finished	Sep 11 05:03:36 PM UTC 24
Peak memory	209368 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830734807 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1830734807
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.3539665904
Short name	T227
Test name
Test status
Simulation time	135943697 ps
CPU time	2.61 seconds
Started	Sep 11 05:03:08 PM UTC 24
Finished	Sep 11 05:03:12 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539665904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.3539665904
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.3011333844
Short name	T226
Test name
Test status
Simulation time	180411160 ps
CPU time	1.88 seconds
Started	Sep 11 05:03:08 PM UTC 24
Finished	Sep 11 05:03:11 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011333844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3011333844
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.117724880
Short name	T239
Test name
Test status
Simulation time	66369608 ps
CPU time	1.19 seconds
Started	Sep 11 05:03:17 PM UTC 24
Finished	Sep 11 05:03:19 PM UTC 24
Peak memory	208104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117724880 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.117724880
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1137803799
Short name	T237
Test name
Test status
Simulation time	302661242 ps
CPU time	2.04 seconds
Started	Sep 11 05:03:15 PM UTC 24
Finished	Sep 11 05:03:18 PM UTC 24
Peak memory	237816 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137803799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1137803799
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.1209239434
Short name	T231
Test name
Test status
Simulation time	134664330 ps
CPU time	1.23 seconds
Started	Sep 11 05:03:13 PM UTC 24
Finished	Sep 11 05:03:15 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209239434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1209239434
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.2508796509
Short name	T240
Test name
Test status
Simulation time	713990480 ps
CPU time	4.91 seconds
Started	Sep 11 05:03:13 PM UTC 24
Finished	Sep 11 05:03:19 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508796509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2508796509
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.414579301
Short name	T236
Test name
Test status
Simulation time	145154191 ps
CPU time	1.71 seconds
Started	Sep 11 05:03:15 PM UTC 24
Finished	Sep 11 05:03:18 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414579301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.414579301
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.401959919
Short name	T233
Test name
Test status
Simulation time	249453846 ps
CPU time	2.47 seconds
Started	Sep 11 05:03:13 PM UTC 24
Finished	Sep 11 05:03:16 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401959919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.401959919
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.340912441
Short name	T242
Test name
Test status
Simulation time	242564969 ps
CPU time	2.41 seconds
Started	Sep 11 05:03:16 PM UTC 24
Finished	Sep 11 05:03:20 PM UTC 24
Peak memory	208768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340912441 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.340912441
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.3175297241
Short name	T235
Test name
Test status
Simulation time	332115791 ps
CPU time	3.12 seconds
Started	Sep 11 05:03:13 PM UTC 24
Finished	Sep 11 05:03:17 PM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175297241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.3175297241
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.4253494752
Short name	T232
Test name
Test status
Simulation time	136247650 ps
CPU time	1.74 seconds
Started	Sep 11 05:03:13 PM UTC 24
Finished	Sep 11 05:03:16 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253494752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4253494752
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.4059923842
Short name	T247
Test name
Test status
Simulation time	80438501 ps
CPU time	1.38 seconds
Started	Sep 11 05:03:20 PM UTC 24
Finished	Sep 11 05:03:23 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059923842 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.4059923842
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.2766834969
Short name	T47
Test name
Test status
Simulation time	2462254724 ps
CPU time	9.79 seconds
Started	Sep 11 05:03:19 PM UTC 24
Finished	Sep 11 05:03:30 PM UTC 24
Peak memory	242436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766834969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.2766834969
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.819622030
Short name	T248
Test name
Test status
Simulation time	302450847 ps
CPU time	1.6 seconds
Started	Sep 11 05:03:20 PM UTC 24
Finished	Sep 11 05:03:23 PM UTC 24
Peak memory	237444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819622030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.819622030
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.2847582489
Short name	T243
Test name
Test status
Simulation time	85316237 ps
CPU time	1.24 seconds
Started	Sep 11 05:03:18 PM UTC 24
Finished	Sep 11 05:03:21 PM UTC 24
Peak memory	208160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847582489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2847582489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.4144270362
Short name	T255
Test name
Test status
Simulation time	796696145 ps
CPU time	5.96 seconds
Started	Sep 11 05:03:19 PM UTC 24
Finished	Sep 11 05:03:26 PM UTC 24
Peak memory	209236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144270362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.4144270362
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3339793866
Short name	T245
Test name
Test status
Simulation time	182359975 ps
CPU time	1.73 seconds
Started	Sep 11 05:03:19 PM UTC 24
Finished	Sep 11 05:03:21 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339793866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3339793866
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.2095068741
Short name	T241
Test name
Test status
Simulation time	118070877 ps
CPU time	1.95 seconds
Started	Sep 11 05:03:17 PM UTC 24
Finished	Sep 11 05:03:19 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095068741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2095068741
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.1182454033
Short name	T250
Test name
Test status
Simulation time	312692815 ps
CPU time	2.66 seconds
Started	Sep 11 05:03:20 PM UTC 24
Finished	Sep 11 05:03:24 PM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182454033 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1182454033
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.4237556168
Short name	T246
Test name
Test status
Simulation time	132328405 ps
CPU time	2.45 seconds
Started	Sep 11 05:03:19 PM UTC 24
Finished	Sep 11 05:03:22 PM UTC 24
Peak memory	217840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237556168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.4237556168
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.3953256155
Short name	T244
Test name
Test status
Simulation time	105399747 ps
CPU time	1.2 seconds
Started	Sep 11 05:03:19 PM UTC 24
Finished	Sep 11 05:03:21 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953256155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.3953256155
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.1924703389
Short name	T52
Test name
Test status
Simulation time	63786520 ps
CPU time	1.23 seconds
Started	Sep 11 05:01:29 PM UTC 24
Finished	Sep 11 05:01:32 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924703389 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1924703389
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.3759427843
Short name	T26
Test name
Test status
Simulation time	1281157204 ps
CPU time	8.37 seconds
Started	Sep 11 05:01:25 PM UTC 24
Finished	Sep 11 05:01:35 PM UTC 24
Peak memory	241728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759427843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3759427843
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.1821773346
Short name	T44
Test name
Test status
Simulation time	301827234 ps
CPU time	1.95 seconds
Started	Sep 11 05:01:26 PM UTC 24
Finished	Sep 11 05:01:29 PM UTC 24
Peak memory	237436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821773346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.1821773346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.737263242
Short name	T14
Test name
Test status
Simulation time	162996311 ps
CPU time	1.43 seconds
Started	Sep 11 05:01:19 PM UTC 24
Finished	Sep 11 05:01:22 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737263242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.737263242
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.435619934
Short name	T62
Test name
Test status
Simulation time	8276768919 ps
CPU time	20.53 seconds
Started	Sep 11 05:01:27 PM UTC 24
Finished	Sep 11 05:01:49 PM UTC 24
Peak memory	241860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435619934 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.435619934
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.830369345
Short name	T37
Test name
Test status
Simulation time	150361507 ps
CPU time	1.81 seconds
Started	Sep 11 05:01:25 PM UTC 24
Finished	Sep 11 05:01:28 PM UTC 24
Peak memory	208240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830369345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.830369345
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.3007793919
Short name	T23
Test name
Test status
Simulation time	116998252 ps
CPU time	1.85 seconds
Started	Sep 11 05:01:16 PM UTC 24
Finished	Sep 11 05:01:19 PM UTC 24
Peak memory	208316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007793919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.3007793919
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.107510022
Short name	T53
Test name
Test status
Simulation time	370031395 ps
CPU time	3.93 seconds
Started	Sep 11 05:01:27 PM UTC 24
Finished	Sep 11 05:01:32 PM UTC 24
Peak memory	209116 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107510022 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.107510022
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2205515235
Short name	T36
Test name
Test status
Simulation time	408030979 ps
CPU time	2.4 seconds
Started	Sep 11 05:01:23 PM UTC 24
Finished	Sep 11 05:01:26 PM UTC 24
Peak memory	217780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205515235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2205515235
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.137687635
Short name	T257
Test name
Test status
Simulation time	66649252 ps
CPU time	1.16 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:28 PM UTC 24
Peak memory	208104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137687635 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.137687635
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.121226401
Short name	T276
Test name
Test status
Simulation time	1975884487 ps
CPU time	9.53 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:37 PM UTC 24
Peak memory	241728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121226401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.121226401
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.4095125353
Short name	T261
Test name
Test status
Simulation time	302458967 ps
CPU time	1.95 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:29 PM UTC 24
Peak memory	237440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095125353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.4095125353
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.808696589
Short name	T252
Test name
Test status
Simulation time	191125145 ps
CPU time	1.22 seconds
Started	Sep 11 05:03:23 PM UTC 24
Finished	Sep 11 05:03:25 PM UTC 24
Peak memory	208180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808696589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.808696589
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.227990684
Short name	T267
Test name
Test status
Simulation time	1724545519 ps
CPU time	8.39 seconds
Started	Sep 11 05:03:23 PM UTC 24
Finished	Sep 11 05:03:32 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227990684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.227990684
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1569297400
Short name	T254
Test name
Test status
Simulation time	99529282 ps
CPU time	1.56 seconds
Started	Sep 11 05:03:23 PM UTC 24
Finished	Sep 11 05:03:25 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569297400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1569297400
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.854672025
Short name	T249
Test name
Test status
Simulation time	129290102 ps
CPU time	1.56 seconds
Started	Sep 11 05:03:21 PM UTC 24
Finished	Sep 11 05:03:23 PM UTC 24
Peak memory	208324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854672025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.854672025
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.423460016
Short name	T264
Test name
Test status
Simulation time	331486156 ps
CPU time	2.67 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:30 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423460016 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.423460016
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.1386887773
Short name	T256
Test name
Test status
Simulation time	119159715 ps
CPU time	2.33 seconds
Started	Sep 11 05:03:23 PM UTC 24
Finished	Sep 11 05:03:26 PM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386887773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.1386887773
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.1467030096
Short name	T253
Test name
Test status
Simulation time	121523573 ps
CPU time	1.55 seconds
Started	Sep 11 05:03:23 PM UTC 24
Finished	Sep 11 05:03:25 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467030096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1467030096
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.1318321016
Short name	T266
Test name
Test status
Simulation time	95703816 ps
CPU time	1.23 seconds
Started	Sep 11 05:03:29 PM UTC 24
Finished	Sep 11 05:03:31 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318321016 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1318321016
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.2013913027
Short name	T41
Test name
Test status
Simulation time	2252841995 ps
CPU time	10.07 seconds
Started	Sep 11 05:03:27 PM UTC 24
Finished	Sep 11 05:03:38 PM UTC 24
Peak memory	242464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013913027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2013913027
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1453302805
Short name	T263
Test name
Test status
Simulation time	300996669 ps
CPU time	1.89 seconds
Started	Sep 11 05:03:27 PM UTC 24
Finished	Sep 11 05:03:30 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453302805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1453302805
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.309489257
Short name	T259
Test name
Test status
Simulation time	226833616 ps
CPU time	1.55 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:29 PM UTC 24
Peak memory	208180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309489257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.309489257
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.2484055150
Short name	T268
Test name
Test status
Simulation time	926537271 ps
CPU time	6.42 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:34 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484055150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2484055150
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1374290625
Short name	T262
Test name
Test status
Simulation time	150706122 ps
CPU time	1.74 seconds
Started	Sep 11 05:03:27 PM UTC 24
Finished	Sep 11 05:03:29 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374290625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1374290625
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.2234164725
Short name	T260
Test name
Test status
Simulation time	114666029 ps
CPU time	1.84 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:29 PM UTC 24
Peak memory	208252 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234164725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2234164725
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.2766072631
Short name	T325
Test name
Test status
Simulation time	9023563159 ps
CPU time	31.53 seconds
Started	Sep 11 05:03:29 PM UTC 24
Finished	Sep 11 05:04:02 PM UTC 24
Peak memory	218240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766072631 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2766072631
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.2295643335
Short name	T265
Test name
Test status
Simulation time	135582599 ps
CPU time	2.43 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:30 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295643335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2295643335
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.445100040
Short name	T258
Test name
Test status
Simulation time	97817518 ps
CPU time	1.48 seconds
Started	Sep 11 05:03:26 PM UTC 24
Finished	Sep 11 05:03:29 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445100040 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.445100040
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.2131893878
Short name	T270
Test name
Test status
Simulation time	64153143 ps
CPU time	1.07 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:36 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131893878 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2131893878
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.589673970
Short name	T42
Test name
Test status
Simulation time	1272116504 ps
CPU time	6.41 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:41 PM UTC 24
Peak memory	241728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589673970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.589673970
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3328599399
Short name	T275
Test name
Test status
Simulation time	301790692 ps
CPU time	2.08 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:36 PM UTC 24
Peak memory	237760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328599399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3328599399
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.1589345236
Short name	T271
Test name
Test status
Simulation time	211983267 ps
CPU time	1.69 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:36 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589345236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.1589345236
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.2456575482
Short name	T281
Test name
Test status
Simulation time	891917091 ps
CPU time	6.27 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:41 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456575482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2456575482
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3375055650
Short name	T272
Test name
Test status
Simulation time	180068650 ps
CPU time	1.82 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:36 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375055650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3375055650
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.2777646314
Short name	T269
Test name
Test status
Simulation time	107696371 ps
CPU time	1.29 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:36 PM UTC 24
Peak memory	208260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777646314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2777646314
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.3560644144
Short name	T336
Test name
Test status
Simulation time	8635887092 ps
CPU time	31.87 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:04:07 PM UTC 24
Peak memory	209188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560644144 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3560644144
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.550790244
Short name	T277
Test name
Test status
Simulation time	145620971 ps
CPU time	2.49 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:37 PM UTC 24
Peak memory	208992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550790244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.550790244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.1716034043
Short name	T274
Test name
Test status
Simulation time	272692656 ps
CPU time	2.15 seconds
Started	Sep 11 05:03:33 PM UTC 24
Finished	Sep 11 05:03:36 PM UTC 24
Peak memory	208900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716034043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1716034043
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.385244929
Short name	T284
Test name
Test status
Simulation time	89867721 ps
CPU time	1.37 seconds
Started	Sep 11 05:03:40 PM UTC 24
Finished	Sep 11 05:03:42 PM UTC 24
Peak memory	207724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385244929 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.385244929
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.3098055304
Short name	T306
Test name
Test status
Simulation time	1966589634 ps
CPU time	11.86 seconds
Started	Sep 11 05:03:39 PM UTC 24
Finished	Sep 11 05:03:52 PM UTC 24
Peak memory	241720 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098055304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3098055304
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1486268183
Short name	T287
Test name
Test status
Simulation time	302277468 ps
CPU time	1.95 seconds
Started	Sep 11 05:03:40 PM UTC 24
Finished	Sep 11 05:03:42 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486268183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1486268183
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.3477878175
Short name	T279
Test name
Test status
Simulation time	181331524 ps
CPU time	1.56 seconds
Started	Sep 11 05:03:36 PM UTC 24
Finished	Sep 11 05:03:38 PM UTC 24
Peak memory	206256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477878175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.3477878175
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.658155582
Short name	T282
Test name
Test status
Simulation time	945986861 ps
CPU time	5.09 seconds
Started	Sep 11 05:03:36 PM UTC 24
Finished	Sep 11 05:03:42 PM UTC 24
Peak memory	208264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658155582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.658155582
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.167241124
Short name	T286
Test name
Test status
Simulation time	106941247 ps
CPU time	1.63 seconds
Started	Sep 11 05:03:39 PM UTC 24
Finished	Sep 11 05:03:42 PM UTC 24
Peak memory	208084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167241124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.167241124
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.3758632251
Short name	T280
Test name
Test status
Simulation time	129082592 ps
CPU time	1.61 seconds
Started	Sep 11 05:03:35 PM UTC 24
Finished	Sep 11 05:03:38 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758632251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3758632251
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.3639049086
Short name	T290
Test name
Test status
Simulation time	354874144 ps
CPU time	2.77 seconds
Started	Sep 11 05:03:40 PM UTC 24
Finished	Sep 11 05:03:43 PM UTC 24
Peak memory	218028 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639049086 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3639049086
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.308619812
Short name	T289
Test name
Test status
Simulation time	119778373 ps
CPU time	2.36 seconds
Started	Sep 11 05:03:39 PM UTC 24
Finished	Sep 11 05:03:43 PM UTC 24
Peak memory	217648 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308619812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.308619812
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.185862340
Short name	T278
Test name
Test status
Simulation time	131832412 ps
CPU time	1.49 seconds
Started	Sep 11 05:03:36 PM UTC 24
Finished	Sep 11 05:03:38 PM UTC 24
Peak memory	208300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185862340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.185862340
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.278793903
Short name	T292
Test name
Test status
Simulation time	62022949 ps
CPU time	1.21 seconds
Started	Sep 11 05:03:43 PM UTC 24
Finished	Sep 11 05:03:45 PM UTC 24
Peak memory	208044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278793903 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.278793903
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.1817798071
Short name	T48
Test name
Test status
Simulation time	1960882887 ps
CPU time	11.33 seconds
Started	Sep 11 05:03:42 PM UTC 24
Finished	Sep 11 05:03:55 PM UTC 24
Peak memory	241664 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817798071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1817798071
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1897451018
Short name	T296
Test name
Test status
Simulation time	302080069 ps
CPU time	1.99 seconds
Started	Sep 11 05:03:43 PM UTC 24
Finished	Sep 11 05:03:46 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897451018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1897451018
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.494909499
Short name	T283
Test name
Test status
Simulation time	103910597 ps
CPU time	1.25 seconds
Started	Sep 11 05:03:40 PM UTC 24
Finished	Sep 11 05:03:42 PM UTC 24
Peak memory	208180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494909499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.494909499
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.1696367390
Short name	T301
Test name
Test status
Simulation time	1526630411 ps
CPU time	7.76 seconds
Started	Sep 11 05:03:40 PM UTC 24
Finished	Sep 11 05:03:49 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696367390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1696367390
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.83745925
Short name	T294
Test name
Test status
Simulation time	172486121 ps
CPU time	1.51 seconds
Started	Sep 11 05:03:42 PM UTC 24
Finished	Sep 11 05:03:45 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83745925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.83745925
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.3576228370
Short name	T288
Test name
Test status
Simulation time	192207543 ps
CPU time	2.04 seconds
Started	Sep 11 05:03:40 PM UTC 24
Finished	Sep 11 05:03:43 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576228370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3576228370
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.3543791189
Short name	T323
Test name
Test status
Simulation time	4174515752 ps
CPU time	17.21 seconds
Started	Sep 11 05:03:43 PM UTC 24
Finished	Sep 11 05:04:01 PM UTC 24
Peak memory	220144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543791189 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.3543791189
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.2975501115
Short name	T291
Test name
Test status
Simulation time	340489701 ps
CPU time	3.34 seconds
Started	Sep 11 05:03:40 PM UTC 24
Finished	Sep 11 05:03:44 PM UTC 24
Peak memory	209048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975501115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.2975501115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.3959440550
Short name	T285
Test name
Test status
Simulation time	92119506 ps
CPU time	1.17 seconds
Started	Sep 11 05:03:40 PM UTC 24
Finished	Sep 11 05:03:42 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959440550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3959440550
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.170946232
Short name	T302
Test name
Test status
Simulation time	77271559 ps
CPU time	1.01 seconds
Started	Sep 11 05:03:47 PM UTC 24
Finished	Sep 11 05:03:49 PM UTC 24
Peak memory	208104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170946232 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.170946232
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.2067969046
Short name	T314
Test name
Test status
Simulation time	2448210378 ps
CPU time	11.24 seconds
Started	Sep 11 05:03:45 PM UTC 24
Finished	Sep 11 05:03:57 PM UTC 24
Peak memory	242464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067969046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2067969046
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.1449530502
Short name	T299
Test name
Test status
Simulation time	301834439 ps
CPU time	2.05 seconds
Started	Sep 11 05:03:45 PM UTC 24
Finished	Sep 11 05:03:48 PM UTC 24
Peak memory	237756 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449530502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.1449530502
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.2459122445
Short name	T293
Test name
Test status
Simulation time	126120099 ps
CPU time	1.15 seconds
Started	Sep 11 05:03:43 PM UTC 24
Finished	Sep 11 05:03:45 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459122445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2459122445
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.575787600
Short name	T318
Test name
Test status
Simulation time	1839669279 ps
CPU time	12.42 seconds
Started	Sep 11 05:03:44 PM UTC 24
Finished	Sep 11 05:03:58 PM UTC 24
Peak memory	208844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575787600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.575787600
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3906872552
Short name	T297
Test name
Test status
Simulation time	98162438 ps
CPU time	1.56 seconds
Started	Sep 11 05:03:45 PM UTC 24
Finished	Sep 11 05:03:47 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906872552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3906872552
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.1924478212
Short name	T295
Test name
Test status
Simulation time	112698880 ps
CPU time	1.75 seconds
Started	Sep 11 05:03:43 PM UTC 24
Finished	Sep 11 05:03:45 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924478212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1924478212
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.3856721640
Short name	T373
Test name
Test status
Simulation time	7232918534 ps
CPU time	35.34 seconds
Started	Sep 11 05:03:47 PM UTC 24
Finished	Sep 11 05:04:24 PM UTC 24
Peak memory	220204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856721640 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3856721640
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3103065993
Short name	T300
Test name
Test status
Simulation time	138742860 ps
CPU time	2.55 seconds
Started	Sep 11 05:03:45 PM UTC 24
Finished	Sep 11 05:03:48 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103065993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3103065993
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.1428396050
Short name	T298
Test name
Test status
Simulation time	223778648 ps
CPU time	2 seconds
Started	Sep 11 05:03:44 PM UTC 24
Finished	Sep 11 05:03:47 PM UTC 24
Peak memory	207844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428396050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1428396050
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.4123052489
Short name	T307
Test name
Test status
Simulation time	69779570 ps
CPU time	1.17 seconds
Started	Sep 11 05:03:51 PM UTC 24
Finished	Sep 11 05:03:53 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123052489 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4123052489
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.3238556132
Short name	T322
Test name
Test status
Simulation time	1271033983 ps
CPU time	8.78 seconds
Started	Sep 11 05:03:50 PM UTC 24
Finished	Sep 11 05:04:00 PM UTC 24
Peak memory	241724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238556132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3238556132
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1434867038
Short name	T308
Test name
Test status
Simulation time	301689958 ps
CPU time	1.94 seconds
Started	Sep 11 05:03:50 PM UTC 24
Finished	Sep 11 05:03:53 PM UTC 24
Peak memory	236680 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434867038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1434867038
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.1974422016
Short name	T303
Test name
Test status
Simulation time	108982613 ps
CPU time	1.23 seconds
Started	Sep 11 05:03:47 PM UTC 24
Finished	Sep 11 05:03:49 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974422016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1974422016
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.1311253100
Short name	T319
Test name
Test status
Simulation time	1771579284 ps
CPU time	9.81 seconds
Started	Sep 11 05:03:47 PM UTC 24
Finished	Sep 11 05:03:58 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311253100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1311253100
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.3889782998
Short name	T309
Test name
Test status
Simulation time	157905759 ps
CPU time	1.99 seconds
Started	Sep 11 05:03:50 PM UTC 24
Finished	Sep 11 05:03:53 PM UTC 24
Peak memory	206984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889782998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.3889782998
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.2357152792
Short name	T305
Test name
Test status
Simulation time	222372614 ps
CPU time	2.46 seconds
Started	Sep 11 05:03:47 PM UTC 24
Finished	Sep 11 05:03:51 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357152792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.2357152792
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.2456439073
Short name	T399
Test name
Test status
Simulation time	9926686611 ps
CPU time	43.7 seconds
Started	Sep 11 05:03:50 PM UTC 24
Finished	Sep 11 05:04:36 PM UTC 24
Peak memory	218100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456439073 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2456439073
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.740994643
Short name	T311
Test name
Test status
Simulation time	373199820 ps
CPU time	3.69 seconds
Started	Sep 11 05:03:50 PM UTC 24
Finished	Sep 11 05:03:55 PM UTC 24
Peak memory	209052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740994643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.740994643
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.3803210667
Short name	T304
Test name
Test status
Simulation time	166899646 ps
CPU time	2.16 seconds
Started	Sep 11 05:03:47 PM UTC 24
Finished	Sep 11 05:03:51 PM UTC 24
Peak memory	208900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803210667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3803210667
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.3435965154
Short name	T326
Test name
Test status
Simulation time	68203040 ps
CPU time	1.18 seconds
Started	Sep 11 05:03:59 PM UTC 24
Finished	Sep 11 05:04:02 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435965154 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3435965154
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.740786750
Short name	T334
Test name
Test status
Simulation time	1274990750 ps
CPU time	8.14 seconds
Started	Sep 11 05:03:55 PM UTC 24
Finished	Sep 11 05:04:05 PM UTC 24
Peak memory	241728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740786750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.740786750
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.725614825
Short name	T320
Test name
Test status
Simulation time	312362746 ps
CPU time	1.94 seconds
Started	Sep 11 05:03:55 PM UTC 24
Finished	Sep 11 05:03:58 PM UTC 24
Peak memory	237444 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725614825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.725614825
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.1954151860
Short name	T310
Test name
Test status
Simulation time	197280460 ps
CPU time	1.26 seconds
Started	Sep 11 05:03:52 PM UTC 24
Finished	Sep 11 05:03:54 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954151860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1954151860
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.2570800009
Short name	T321
Test name
Test status
Simulation time	848032482 ps
CPU time	6.57 seconds
Started	Sep 11 05:03:52 PM UTC 24
Finished	Sep 11 05:04:00 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570800009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.2570800009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1569038071
Short name	T317
Test name
Test status
Simulation time	107287059 ps
CPU time	1.56 seconds
Started	Sep 11 05:03:55 PM UTC 24
Finished	Sep 11 05:03:58 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569038071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1569038071
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.1400606776
Short name	T312
Test name
Test status
Simulation time	196441661 ps
CPU time	2.15 seconds
Started	Sep 11 05:03:52 PM UTC 24
Finished	Sep 11 05:03:55 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400606776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1400606776
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.208947424
Short name	T444
Test name
Test status
Simulation time	15330617915 ps
CPU time	55.37 seconds
Started	Sep 11 05:03:59 PM UTC 24
Finished	Sep 11 05:04:56 PM UTC 24
Peak memory	218160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208947424 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.208947424
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.1262254968
Short name	T315
Test name
Test status
Simulation time	257902299 ps
CPU time	2.73 seconds
Started	Sep 11 05:03:54 PM UTC 24
Finished	Sep 11 05:03:57 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262254968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1262254968
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.3255688959
Short name	T313
Test name
Test status
Simulation time	70530206 ps
CPU time	1.26 seconds
Started	Sep 11 05:03:54 PM UTC 24
Finished	Sep 11 05:03:56 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255688959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.3255688959
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.1781977368
Short name	T331
Test name
Test status
Simulation time	64831926 ps
CPU time	1.21 seconds
Started	Sep 11 05:04:02 PM UTC 24
Finished	Sep 11 05:04:04 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781977368 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1781977368
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.2302349338
Short name	T345
Test name
Test status
Simulation time	1271705462 ps
CPU time	6.28 seconds
Started	Sep 11 05:04:01 PM UTC 24
Finished	Sep 11 05:04:09 PM UTC 24
Peak memory	242276 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302349338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2302349338
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2291957286
Short name	T333
Test name
Test status
Simulation time	301414332 ps
CPU time	1.91 seconds
Started	Sep 11 05:04:02 PM UTC 24
Finished	Sep 11 05:04:04 PM UTC 24
Peak memory	237440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291957286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2291957286
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.3119699956
Short name	T327
Test name
Test status
Simulation time	208163706 ps
CPU time	1.54 seconds
Started	Sep 11 05:04:00 PM UTC 24
Finished	Sep 11 05:04:02 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119699956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3119699956
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.3789685524
Short name	T337
Test name
Test status
Simulation time	1669132270 ps
CPU time	6.95 seconds
Started	Sep 11 05:04:00 PM UTC 24
Finished	Sep 11 05:04:08 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789685524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3789685524
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3295936841
Short name	T332
Test name
Test status
Simulation time	174691604 ps
CPU time	1.91 seconds
Started	Sep 11 05:04:01 PM UTC 24
Finished	Sep 11 05:04:04 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295936841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3295936841
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.2065037946
Short name	T329
Test name
Test status
Simulation time	109482505 ps
CPU time	1.73 seconds
Started	Sep 11 05:04:00 PM UTC 24
Finished	Sep 11 05:04:02 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065037946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.2065037946
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.629948702
Short name	T397
Test name
Test status
Simulation time	7012263369 ps
CPU time	32.31 seconds
Started	Sep 11 05:04:02 PM UTC 24
Finished	Sep 11 05:04:35 PM UTC 24
Peak memory	218224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629948702 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.629948702
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.3804864716
Short name	T330
Test name
Test status
Simulation time	300285789 ps
CPU time	2.94 seconds
Started	Sep 11 05:04:00 PM UTC 24
Finished	Sep 11 05:04:04 PM UTC 24
Peak memory	217780 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804864716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.3804864716
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.3944004043
Short name	T328
Test name
Test status
Simulation time	146814146 ps
CPU time	1.41 seconds
Started	Sep 11 05:04:00 PM UTC 24
Finished	Sep 11 05:04:02 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944004043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.3944004043
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.456223736
Short name	T341
Test name
Test status
Simulation time	147744421 ps
CPU time	1.44 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:08 PM UTC 24
Peak memory	208060 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456223736 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.456223736
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.2210317225
Short name	T351
Test name
Test status
Simulation time	1270077600 ps
CPU time	6.05 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:13 PM UTC 24
Peak memory	242392 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210317225 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2210317225
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3327778515
Short name	T344
Test name
Test status
Simulation time	301106935 ps
CPU time	1.98 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:09 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327778515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3327778515
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.2976814875
Short name	T338
Test name
Test status
Simulation time	190373687 ps
CPU time	1.35 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:08 PM UTC 24
Peak memory	208140 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976814875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.2976814875
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.2627499900
Short name	T349
Test name
Test status
Simulation time	832247317 ps
CPU time	4.64 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:11 PM UTC 24
Peak memory	209196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627499900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.2627499900
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.1672993388
Short name	T339
Test name
Test status
Simulation time	99204540 ps
CPU time	1.37 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:08 PM UTC 24
Peak memory	208272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672993388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.1672993388
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.1501704919
Short name	T335
Test name
Test status
Simulation time	198656229 ps
CPU time	2.38 seconds
Started	Sep 11 05:04:02 PM UTC 24
Finished	Sep 11 05:04:05 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501704919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1501704919
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.4119799543
Short name	T378
Test name
Test status
Simulation time	4048981500 ps
CPU time	20 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:27 PM UTC 24
Peak memory	218220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119799543 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.4119799543
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.3172049618
Short name	T347
Test name
Test status
Simulation time	130529746 ps
CPU time	2.21 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:09 PM UTC 24
Peak memory	217840 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172049618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3172049618
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.230168699
Short name	T343
Test name
Test status
Simulation time	170280858 ps
CPU time	1.83 seconds
Started	Sep 11 05:04:05 PM UTC 24
Finished	Sep 11 05:04:08 PM UTC 24
Peak memory	208044 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230168699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.230168699
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.246095296
Short name	T97
Test name
Test status
Simulation time	61232471 ps
CPU time	1.15 seconds
Started	Sep 11 05:01:37 PM UTC 24
Finished	Sep 11 05:01:39 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246095296 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.246095296
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.358165415
Short name	T27
Test name
Test status
Simulation time	1962164593 ps
CPU time	13.24 seconds
Started	Sep 11 05:01:34 PM UTC 24
Finished	Sep 11 05:01:48 PM UTC 24
Peak memory	241912 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358165415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.358165415
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2174139348
Short name	T96
Test name
Test status
Simulation time	302569379 ps
CPU time	1.84 seconds
Started	Sep 11 05:01:35 PM UTC 24
Finished	Sep 11 05:01:38 PM UTC 24
Peak memory	237612 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174139348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2174139348
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.3496343875
Short name	T15
Test name
Test status
Simulation time	119778870 ps
CPU time	1.26 seconds
Started	Sep 11 05:01:30 PM UTC 24
Finished	Sep 11 05:01:33 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496343875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3496343875
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.2984284572
Short name	T88
Test name
Test status
Simulation time	771707551 ps
CPU time	5.68 seconds
Started	Sep 11 05:01:32 PM UTC 24
Finished	Sep 11 05:01:39 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984284572 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2984284572
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.924968975
Short name	T67
Test name
Test status
Simulation time	16716502883 ps
CPU time	44.49 seconds
Started	Sep 11 05:01:37 PM UTC 24
Finished	Sep 11 05:02:23 PM UTC 24
Peak memory	242324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924968975 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.924968975
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.1029070955
Short name	T95
Test name
Test status
Simulation time	100824785 ps
CPU time	1.63 seconds
Started	Sep 11 05:01:34 PM UTC 24
Finished	Sep 11 05:01:37 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029070955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.1029070955
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.176794923
Short name	T68
Test name
Test status
Simulation time	205792423 ps
CPU time	2.24 seconds
Started	Sep 11 05:01:30 PM UTC 24
Finished	Sep 11 05:01:34 PM UTC 24
Peak memory	209164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176794923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.176794923
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.2954850891
Short name	T91
Test name
Test status
Simulation time	10517163648 ps
CPU time	39.25 seconds
Started	Sep 11 05:01:36 PM UTC 24
Finished	Sep 11 05:02:17 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954850891 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2954850891
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.1512517882
Short name	T71
Test name
Test status
Simulation time	399077998 ps
CPU time	3.81 seconds
Started	Sep 11 05:01:34 PM UTC 24
Finished	Sep 11 05:01:39 PM UTC 24
Peak memory	209004 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512517882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1512517882
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.380408900
Short name	T69
Test name
Test status
Simulation time	66234129 ps
CPU time	1.24 seconds
Started	Sep 11 05:01:34 PM UTC 24
Finished	Sep 11 05:01:36 PM UTC 24
Peak memory	208296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380408900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.380408900
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.1523581954
Short name	T353
Test name
Test status
Simulation time	68564766 ps
CPU time	1.2 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:16 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523581954 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1523581954
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.2389996729
Short name	T354
Test name
Test status
Simulation time	1956500174 ps
CPU time	7.71 seconds
Started	Sep 11 05:04:07 PM UTC 24
Finished	Sep 11 05:04:16 PM UTC 24
Peak memory	242372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389996729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2389996729
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2023941584
Short name	T359
Test name
Test status
Simulation time	300691673 ps
CPU time	1.98 seconds
Started	Sep 11 05:04:13 PM UTC 24
Finished	Sep 11 05:04:16 PM UTC 24
Peak memory	237608 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023941584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2023941584
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.1930730244
Short name	T340
Test name
Test status
Simulation time	142495782 ps
CPU time	1.27 seconds
Started	Sep 11 05:04:06 PM UTC 24
Finished	Sep 11 05:04:08 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930730244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.1930730244
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.4205204163
Short name	T352
Test name
Test status
Simulation time	1837126397 ps
CPU time	7.04 seconds
Started	Sep 11 05:04:06 PM UTC 24
Finished	Sep 11 05:04:14 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205204163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.4205204163
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2766932051
Short name	T348
Test name
Test status
Simulation time	109408134 ps
CPU time	1.62 seconds
Started	Sep 11 05:04:07 PM UTC 24
Finished	Sep 11 05:04:10 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766932051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2766932051
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.2224120675
Short name	T346
Test name
Test status
Simulation time	199407839 ps
CPU time	2.05 seconds
Started	Sep 11 05:04:06 PM UTC 24
Finished	Sep 11 05:04:09 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224120675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2224120675
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.892092182
Short name	T360
Test name
Test status
Simulation time	192368114 ps
CPU time	1.98 seconds
Started	Sep 11 05:04:13 PM UTC 24
Finished	Sep 11 05:04:16 PM UTC 24
Peak memory	208284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892092182 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.892092182
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.782961920
Short name	T350
Test name
Test status
Simulation time	392781172 ps
CPU time	3.5 seconds
Started	Sep 11 05:04:07 PM UTC 24
Finished	Sep 11 05:04:12 PM UTC 24
Peak memory	209052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782961920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.782961920
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.1989825111
Short name	T342
Test name
Test status
Simulation time	106398922 ps
CPU time	1.57 seconds
Started	Sep 11 05:04:06 PM UTC 24
Finished	Sep 11 05:04:08 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989825111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.1989825111
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.3486899426
Short name	T362
Test name
Test status
Simulation time	85276391 ps
CPU time	1.24 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:17 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486899426 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.3486899426
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.3106454429
Short name	T49
Test name
Test status
Simulation time	2426915882 ps
CPU time	11.85 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:27 PM UTC 24
Peak memory	242460 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106454429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3106454429
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1433781636
Short name	T357
Test name
Test status
Simulation time	300902515 ps
CPU time	1.32 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:16 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433781636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1433781636
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.2919547783
Short name	T355
Test name
Test status
Simulation time	208991088 ps
CPU time	1.49 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:16 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919547783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2919547783
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.189473158
Short name	T365
Test name
Test status
Simulation time	1667706127 ps
CPU time	6.4 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:21 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189473158 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.189473158
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2511512576
Short name	T358
Test name
Test status
Simulation time	143319710 ps
CPU time	1.4 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:16 PM UTC 24
Peak memory	208264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511512576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2511512576
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.2846864275
Short name	T361
Test name
Test status
Simulation time	119705383 ps
CPU time	1.83 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:17 PM UTC 24
Peak memory	208260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846864275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2846864275
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.2955166161
Short name	T458
Test name
Test status
Simulation time	10698907823 ps
CPU time	46.73 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:05:02 PM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955166161 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2955166161
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.2988302555
Short name	T364
Test name
Test status
Simulation time	420458753 ps
CPU time	2.89 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:18 PM UTC 24
Peak memory	217716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988302555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2988302555
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.992046625
Short name	T356
Test name
Test status
Simulation time	117439274 ps
CPU time	1.46 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:16 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992046625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.992046625
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.3943656491
Short name	T371
Test name
Test status
Simulation time	87738437 ps
CPU time	1.3 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:24 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943656491 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3943656491
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.1971911054
Short name	T385
Test name
Test status
Simulation time	1279584123 ps
CPU time	7.47 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:30 PM UTC 24
Peak memory	242312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971911054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.1971911054
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.3525990498
Short name	T374
Test name
Test status
Simulation time	301743448 ps
CPU time	2.02 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:24 PM UTC 24
Peak memory	237768 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525990498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.3525990498
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.3471537462
Short name	T367
Test name
Test status
Simulation time	106772646 ps
CPU time	1.05 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:23 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471537462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3471537462
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.3122888183
Short name	T379
Test name
Test status
Simulation time	1090698548 ps
CPU time	5.75 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:28 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122888183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.3122888183
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.670040521
Short name	T368
Test name
Test status
Simulation time	106316830 ps
CPU time	1.17 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:23 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670040521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.670040521
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.2931766863
Short name	T363
Test name
Test status
Simulation time	194403983 ps
CPU time	2.2 seconds
Started	Sep 11 05:04:14 PM UTC 24
Finished	Sep 11 05:04:18 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931766863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2931766863
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.2741122097
Short name	T430
Test name
Test status
Simulation time	8758272017 ps
CPU time	28.66 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:51 PM UTC 24
Peak memory	209300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741122097 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2741122097
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.1906532772
Short name	T366
Test name
Test status
Simulation time	457318216 ps
CPU time	4.23 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:26 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906532772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1906532772
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.3036083656
Short name	T372
Test name
Test status
Simulation time	141985436 ps
CPU time	1.85 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:24 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036083656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.3036083656
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.1204373579
Short name	T380
Test name
Test status
Simulation time	62482073 ps
CPU time	1.16 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:29 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204373579 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1204373579
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.1264067434
Short name	T390
Test name
Test status
Simulation time	1965467517 ps
CPU time	9.17 seconds
Started	Sep 11 05:04:23 PM UTC 24
Finished	Sep 11 05:04:34 PM UTC 24
Peak memory	241808 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264067434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.1264067434
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.93408250
Short name	T383
Test name
Test status
Simulation time	303367068 ps
CPU time	1.64 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:29 PM UTC 24
Peak memory	237440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93408250 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.93408250
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.2006891027
Short name	T369
Test name
Test status
Simulation time	95702244 ps
CPU time	1.2 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:24 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006891027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2006891027
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.2860681392
Short name	T388
Test name
Test status
Simulation time	1873592738 ps
CPU time	8.35 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:31 PM UTC 24
Peak memory	209216 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860681392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.2860681392
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.935419816
Short name	T377
Test name
Test status
Simulation time	175480875 ps
CPU time	1.82 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:24 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935419816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.935419816
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.539454497
Short name	T375
Test name
Test status
Simulation time	243700217 ps
CPU time	1.86 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:24 PM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539454497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.539454497
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.1445997525
Short name	T432
Test name
Test status
Simulation time	6597842541 ps
CPU time	24.48 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:52 PM UTC 24
Peak memory	225284 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445997525 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1445997525
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.415417318
Short name	T376
Test name
Test status
Simulation time	363622196 ps
CPU time	3.12 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:26 PM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415417318 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.415417318
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.234557965
Short name	T370
Test name
Test status
Simulation time	107200038 ps
CPU time	1.11 seconds
Started	Sep 11 05:04:21 PM UTC 24
Finished	Sep 11 05:04:24 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234557965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.234557965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.2492784434
Short name	T389
Test name
Test status
Simulation time	71072409 ps
CPU time	1.18 seconds
Started	Sep 11 05:04:31 PM UTC 24
Finished	Sep 11 05:04:34 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492784434 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2492784434
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.674233320
Short name	T403
Test name
Test status
Simulation time	1962511186 ps
CPU time	8.27 seconds
Started	Sep 11 05:04:31 PM UTC 24
Finished	Sep 11 05:04:41 PM UTC 24
Peak memory	241940 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674233320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.674233320
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.2020821073
Short name	T394
Test name
Test status
Simulation time	301453819 ps
CPU time	1.93 seconds
Started	Sep 11 05:04:31 PM UTC 24
Finished	Sep 11 05:04:34 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020821073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.2020821073
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.3665168981
Short name	T382
Test name
Test status
Simulation time	86610908 ps
CPU time	1.25 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:29 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665168981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.3665168981
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.1120614676
Short name	T400
Test name
Test status
Simulation time	1569634238 ps
CPU time	9.02 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:37 PM UTC 24
Peak memory	209212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120614676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1120614676
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.487300088
Short name	T384
Test name
Test status
Simulation time	111911406 ps
CPU time	1.33 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:29 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487300088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.487300088
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.1964625742
Short name	T386
Test name
Test status
Simulation time	240447626 ps
CPU time	2.35 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:30 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964625742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1964625742
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.1596570700
Short name	T491
Test name
Test status
Simulation time	11619960551 ps
CPU time	42.88 seconds
Started	Sep 11 05:04:31 PM UTC 24
Finished	Sep 11 05:05:16 PM UTC 24
Peak memory	218084 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596570700 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1596570700
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.4121163021
Short name	T387
Test name
Test status
Simulation time	375454463 ps
CPU time	2.82 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:31 PM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121163021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.4121163021
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.1931832266
Short name	T381
Test name
Test status
Simulation time	71283987 ps
CPU time	1.29 seconds
Started	Sep 11 05:04:26 PM UTC 24
Finished	Sep 11 05:04:29 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931832266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1931832266
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.4263236013
Short name	T402
Test name
Test status
Simulation time	54031368 ps
CPU time	1.15 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:41 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263236013 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.4263236013
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.725012861
Short name	T50
Test name
Test status
Simulation time	1972501557 ps
CPU time	8.9 seconds
Started	Sep 11 05:04:32 PM UTC 24
Finished	Sep 11 05:04:42 PM UTC 24
Peak memory	241728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725012861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.725012861
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.3692550985
Short name	T395
Test name
Test status
Simulation time	302709373 ps
CPU time	1.69 seconds
Started	Sep 11 05:04:32 PM UTC 24
Finished	Sep 11 05:04:34 PM UTC 24
Peak memory	237596 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692550985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.3692550985
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.157026944
Short name	T391
Test name
Test status
Simulation time	162745393 ps
CPU time	1.34 seconds
Started	Sep 11 05:04:31 PM UTC 24
Finished	Sep 11 05:04:34 PM UTC 24
Peak memory	208096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157026944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.157026944
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.2813465023
Short name	T401
Test name
Test status
Simulation time	891373389 ps
CPU time	7.5 seconds
Started	Sep 11 05:04:31 PM UTC 24
Finished	Sep 11 05:04:40 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813465023 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2813465023
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.3469501435
Short name	T392
Test name
Test status
Simulation time	138317556 ps
CPU time	1.48 seconds
Started	Sep 11 05:04:32 PM UTC 24
Finished	Sep 11 05:04:34 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469501435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.3469501435
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.1723694028
Short name	T393
Test name
Test status
Simulation time	196487240 ps
CPU time	1.92 seconds
Started	Sep 11 05:04:31 PM UTC 24
Finished	Sep 11 05:04:34 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723694028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1723694028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.2580764130
Short name	T412
Test name
Test status
Simulation time	445323949 ps
CPU time	3.34 seconds
Started	Sep 11 05:04:38 PM UTC 24
Finished	Sep 11 05:04:43 PM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580764130 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2580764130
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.2209080021
Short name	T398
Test name
Test status
Simulation time	146489762 ps
CPU time	2.63 seconds
Started	Sep 11 05:04:32 PM UTC 24
Finished	Sep 11 05:04:35 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209080021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2209080021
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.2419326820
Short name	T396
Test name
Test status
Simulation time	151240724 ps
CPU time	1.93 seconds
Started	Sep 11 05:04:32 PM UTC 24
Finished	Sep 11 05:04:35 PM UTC 24
Peak memory	208200 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419326820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2419326820
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.2672931028
Short name	T406
Test name
Test status
Simulation time	61198551 ps
CPU time	1.19 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:41 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672931028 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2672931028
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.831748580
Short name	T51
Test name
Test status
Simulation time	1268365774 ps
CPU time	6.29 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:46 PM UTC 24
Peak memory	242324 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831748580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.831748580
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1463380909
Short name	T407
Test name
Test status
Simulation time	300995839 ps
CPU time	1.4 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:41 PM UTC 24
Peak memory	237440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463380909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1463380909
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.256941046
Short name	T404
Test name
Test status
Simulation time	221415908 ps
CPU time	1.25 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:41 PM UTC 24
Peak memory	208036 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256941046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.256941046
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.2357196965
Short name	T427
Test name
Test status
Simulation time	1767381548 ps
CPU time	9.64 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:49 PM UTC 24
Peak memory	209024 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357196965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2357196965
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1710166528
Short name	T408
Test name
Test status
Simulation time	111537835 ps
CPU time	1.64 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:41 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710166528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1710166528
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.3138116760
Short name	T405
Test name
Test status
Simulation time	120079811 ps
CPU time	1.54 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:41 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138116760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3138116760
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.1947916446
Short name	T460
Test name
Test status
Simulation time	5134123518 ps
CPU time	23.08 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:05:03 PM UTC 24
Peak memory	209304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947916446 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1947916446
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.1545068738
Short name	T411
Test name
Test status
Simulation time	349828036 ps
CPU time	2.72 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:42 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545068738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1545068738
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.3921962019
Short name	T409
Test name
Test status
Simulation time	219112674 ps
CPU time	1.82 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:41 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921962019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3921962019
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.3186217931
Short name	T419
Test name
Test status
Simulation time	80495542 ps
CPU time	1.35 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:47 PM UTC 24
Peak memory	208164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186217931 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3186217931
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.2191047306
Short name	T441
Test name
Test status
Simulation time	2462085144 ps
CPU time	9.35 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:55 PM UTC 24
Peak memory	241640 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191047306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2191047306
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3612951767
Short name	T420
Test name
Test status
Simulation time	303121245 ps
CPU time	1.72 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:48 PM UTC 24
Peak memory	237440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612951767 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3612951767
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.2922823181
Short name	T413
Test name
Test status
Simulation time	153480660 ps
CPU time	1.18 seconds
Started	Sep 11 05:04:41 PM UTC 24
Finished	Sep 11 05:04:43 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922823181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2922823181
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.459238248
Short name	T429
Test name
Test status
Simulation time	1759833874 ps
CPU time	8.07 seconds
Started	Sep 11 05:04:41 PM UTC 24
Finished	Sep 11 05:04:50 PM UTC 24
Peak memory	209152 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459238248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.459238248
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2827548117
Short name	T418
Test name
Test status
Simulation time	109116643 ps
CPU time	1.46 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:47 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827548117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2827548117
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.2431225825
Short name	T410
Test name
Test status
Simulation time	198036555 ps
CPU time	1.85 seconds
Started	Sep 11 05:04:39 PM UTC 24
Finished	Sep 11 05:04:42 PM UTC 24
Peak memory	208264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431225825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2431225825
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.266172849
Short name	T454
Test name
Test status
Simulation time	3203513554 ps
CPU time	15.11 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:05:01 PM UTC 24
Peak memory	209360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266172849 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.266172849
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.3170801498
Short name	T415
Test name
Test status
Simulation time	153158968 ps
CPU time	2.36 seconds
Started	Sep 11 05:04:41 PM UTC 24
Finished	Sep 11 05:04:44 PM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170801498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3170801498
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.4232183524
Short name	T414
Test name
Test status
Simulation time	88275153 ps
CPU time	1.24 seconds
Started	Sep 11 05:04:41 PM UTC 24
Finished	Sep 11 05:04:43 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232183524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.4232183524
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.960278791
Short name	T426
Test name
Test status
Simulation time	86162185 ps
CPU time	1.44 seconds
Started	Sep 11 05:04:47 PM UTC 24
Finished	Sep 11 05:04:49 PM UTC 24
Peak memory	207828 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960278791 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.960278791
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.2394766702
Short name	T436
Test name
Test status
Simulation time	1963954415 ps
CPU time	7.73 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:54 PM UTC 24
Peak memory	241724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394766702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2394766702
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2798493034
Short name	T421
Test name
Test status
Simulation time	302656323 ps
CPU time	1.31 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:48 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798493034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2798493034
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.1549589061
Short name	T416
Test name
Test status
Simulation time	124905780 ps
CPU time	1.19 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:47 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549589061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1549589061
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.3790885370
Short name	T431
Test name
Test status
Simulation time	859629391 ps
CPU time	5.21 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:51 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790885370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3790885370
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3181260231
Short name	T424
Test name
Test status
Simulation time	150277428 ps
CPU time	1.64 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:48 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181260231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3181260231
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.2400196800
Short name	T422
Test name
Test status
Simulation time	117326573 ps
CPU time	1.7 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:48 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400196800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2400196800
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.884801887
Short name	T471
Test name
Test status
Simulation time	4342690174 ps
CPU time	20.49 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:05:07 PM UTC 24
Peak memory	218100 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884801887 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.884801887
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.4088171277
Short name	T425
Test name
Test status
Simulation time	118855310 ps
CPU time	2.11 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:48 PM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088171277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.4088171277
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.1246830557
Short name	T423
Test name
Test status
Simulation time	134745232 ps
CPU time	1.57 seconds
Started	Sep 11 05:04:45 PM UTC 24
Finished	Sep 11 05:04:48 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246830557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1246830557
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.4284079748
Short name	T435
Test name
Test status
Simulation time	59481919 ps
CPU time	1.06 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:54 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284079748 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.4284079748
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.3199164339
Short name	T459
Test name
Test status
Simulation time	2438893019 ps
CPU time	10.04 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:05:03 PM UTC 24
Peak memory	241716 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199164339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.3199164339
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.1125992465
Short name	T440
Test name
Test status
Simulation time	302787189 ps
CPU time	1.64 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:55 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125992465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.1125992465
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.1721265966
Short name	T434
Test name
Test status
Simulation time	190161441 ps
CPU time	0.97 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:54 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721265966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1721265966
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.2176338507
Short name	T449
Test name
Test status
Simulation time	1331130197 ps
CPU time	6.3 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:59 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176338507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2176338507
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.4131911553
Short name	T438
Test name
Test status
Simulation time	143702525 ps
CPU time	1.66 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:55 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131911553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.4131911553
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.703101278
Short name	T428
Test name
Test status
Simulation time	121112266 ps
CPU time	1.89 seconds
Started	Sep 11 05:04:47 PM UTC 24
Finished	Sep 11 05:04:50 PM UTC 24
Peak memory	208076 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703101278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.703101278
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.3741287691
Short name	T472
Test name
Test status
Simulation time	3041641572 ps
CPU time	14.53 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:05:08 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741287691 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3741287691
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.3450406731
Short name	T443
Test name
Test status
Simulation time	546584992 ps
CPU time	3 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:56 PM UTC 24
Peak memory	209048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450406731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.3450406731
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.2535705733
Short name	T437
Test name
Test status
Simulation time	118864842 ps
CPU time	1.61 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:54 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535705733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2535705733
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.3639567267
Short name	T142
Test name
Test status
Simulation time	69357394 ps
CPU time	1.21 seconds
Started	Sep 11 05:01:49 PM UTC 24
Finished	Sep 11 05:01:51 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639567267 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.3639567267
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.249484856
Short name	T28
Test name
Test status
Simulation time	1276495415 ps
CPU time	9.95 seconds
Started	Sep 11 05:01:42 PM UTC 24
Finished	Sep 11 05:01:53 PM UTC 24
Peak memory	241724 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249484856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.249484856
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1011368896
Short name	T141
Test name
Test status
Simulation time	302824693 ps
CPU time	2.06 seconds
Started	Sep 11 05:01:45 PM UTC 24
Finished	Sep 11 05:01:49 PM UTC 24
Peak memory	237760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011368896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1011368896
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.827944951
Short name	T16
Test name
Test status
Simulation time	153327274 ps
CPU time	1.14 seconds
Started	Sep 11 05:01:40 PM UTC 24
Finished	Sep 11 05:01:42 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827944951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.827944951
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.3065805673
Short name	T89
Test name
Test status
Simulation time	1381333008 ps
CPU time	9.75 seconds
Started	Sep 11 05:01:40 PM UTC 24
Finished	Sep 11 05:01:50 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065805673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.3065805673
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.3504407849
Short name	T66
Test name
Test status
Simulation time	8684560961 ps
CPU time	25.04 seconds
Started	Sep 11 05:01:47 PM UTC 24
Finished	Sep 11 05:02:13 PM UTC 24
Peak memory	242360 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504407849 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.3504407849
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1015083355
Short name	T139
Test name
Test status
Simulation time	181030090 ps
CPU time	1.93 seconds
Started	Sep 11 05:01:42 PM UTC 24
Finished	Sep 11 05:01:45 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015083355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1015083355
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.3350899737
Short name	T73
Test name
Test status
Simulation time	116040776 ps
CPU time	1.83 seconds
Started	Sep 11 05:01:38 PM UTC 24
Finished	Sep 11 05:01:41 PM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350899737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3350899737
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.1490547036
Short name	T74
Test name
Test status
Simulation time	5435486325 ps
CPU time	32.9 seconds
Started	Sep 11 05:01:47 PM UTC 24
Finished	Sep 11 05:02:21 PM UTC 24
Peak memory	218072 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490547036 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.1490547036
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.3363754513
Short name	T72
Test name
Test status
Simulation time	357357767 ps
CPU time	3.46 seconds
Started	Sep 11 05:01:41 PM UTC 24
Finished	Sep 11 05:01:45 PM UTC 24
Peak memory	209048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363754513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3363754513
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.1888938412
Short name	T127
Test name
Test status
Simulation time	229981752 ps
CPU time	2.24 seconds
Started	Sep 11 05:01:41 PM UTC 24
Finished	Sep 11 05:01:44 PM UTC 24
Peak memory	208900 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888938412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1888938412
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.3044198906
Short name	T450
Test name
Test status
Simulation time	69665090 ps
CPU time	1.2 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:00 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044198906 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3044198906
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.3573637386
Short name	T417
Test name
Test status
Simulation time	1264460508 ps
CPU time	5.79 seconds
Started	Sep 11 05:04:54 PM UTC 24
Finished	Sep 11 05:05:01 PM UTC 24
Peak memory	242312 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573637386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3573637386
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2919903678
Short name	T445
Test name
Test status
Simulation time	302624667 ps
CPU time	1.41 seconds
Started	Sep 11 05:04:55 PM UTC 24
Finished	Sep 11 05:04:57 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919903678 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2919903678
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.1741105995
Short name	T439
Test name
Test status
Simulation time	186606863 ps
CPU time	1.55 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:55 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741105995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1741105995
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.2700584487
Short name	T462
Test name
Test status
Simulation time	2055458097 ps
CPU time	8.83 seconds
Started	Sep 11 05:04:54 PM UTC 24
Finished	Sep 11 05:05:04 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700584487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2700584487
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.251884967
Short name	T447
Test name
Test status
Simulation time	153034559 ps
CPU time	1.77 seconds
Started	Sep 11 05:04:54 PM UTC 24
Finished	Sep 11 05:04:57 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251884967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.251884967
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.3143491451
Short name	T442
Test name
Test status
Simulation time	202572163 ps
CPU time	2.09 seconds
Started	Sep 11 05:04:52 PM UTC 24
Finished	Sep 11 05:04:55 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143491451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3143491451
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.3439705252
Short name	T492
Test name
Test status
Simulation time	4888319057 ps
CPU time	21.67 seconds
Started	Sep 11 05:04:55 PM UTC 24
Finished	Sep 11 05:05:17 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439705252 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3439705252
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.3071141670
Short name	T448
Test name
Test status
Simulation time	122372244 ps
CPU time	2.26 seconds
Started	Sep 11 05:04:54 PM UTC 24
Finished	Sep 11 05:04:58 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071141670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3071141670
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.2090443987
Short name	T446
Test name
Test status
Simulation time	213542097 ps
CPU time	1.92 seconds
Started	Sep 11 05:04:54 PM UTC 24
Finished	Sep 11 05:04:57 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090443987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2090443987
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.3950004578
Short name	T452
Test name
Test status
Simulation time	75021520 ps
CPU time	1.28 seconds
Started	Sep 11 05:04:59 PM UTC 24
Finished	Sep 11 05:05:01 PM UTC 24
Peak memory	208096 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950004578 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3950004578
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.2510945009
Short name	T469
Test name
Test status
Simulation time	1971052100 ps
CPU time	7.52 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:07 PM UTC 24
Peak memory	242396 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510945009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2510945009
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.1772625241
Short name	T456
Test name
Test status
Simulation time	301869259 ps
CPU time	2.24 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:02 PM UTC 24
Peak memory	237760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772625241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.1772625241
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.4013714168
Short name	T451
Test name
Test status
Simulation time	156665544 ps
CPU time	1.47 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:01 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013714168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.4013714168
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.3408566054
Short name	T463
Test name
Test status
Simulation time	898417289 ps
CPU time	5.61 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:05 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408566054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3408566054
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.940068231
Short name	T453
Test name
Test status
Simulation time	179154753 ps
CPU time	1.52 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:01 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940068231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.940068231
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.387438757
Short name	T433
Test name
Test status
Simulation time	237690067 ps
CPU time	2.47 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:02 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387438757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.387438757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.981208431
Short name	T525
Test name
Test status
Simulation time	5899699178 ps
CPU time	27.67 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:27 PM UTC 24
Peak memory	209304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981208431 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.981208431
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.1557421030
Short name	T461
Test name
Test status
Simulation time	437834055 ps
CPU time	4.44 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:04 PM UTC 24
Peak memory	217844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557421030 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1557421030
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.1618186293
Short name	T455
Test name
Test status
Simulation time	161704084 ps
CPU time	1.94 seconds
Started	Sep 11 05:04:58 PM UTC 24
Finished	Sep 11 05:05:01 PM UTC 24
Peak memory	208196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618186293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1618186293
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.2444733478
Short name	T466
Test name
Test status
Simulation time	76238231 ps
CPU time	1.12 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:06 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444733478 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2444733478
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.3272466858
Short name	T489
Test name
Test status
Simulation time	2464585437 ps
CPU time	9.72 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:15 PM UTC 24
Peak memory	241712 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272466858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.3272466858
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2869378081
Short name	T470
Test name
Test status
Simulation time	302023376 ps
CPU time	1.72 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:07 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869378081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2869378081
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.1684327696
Short name	T465
Test name
Test status
Simulation time	132406192 ps
CPU time	1.17 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:06 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684327696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1684327696
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.1808697689
Short name	T474
Test name
Test status
Simulation time	852791769 ps
CPU time	4.58 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:10 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808697689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.1808697689
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.693179313
Short name	T467
Test name
Test status
Simulation time	102814763 ps
CPU time	1.46 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:07 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693179313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.693179313
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.2025132331
Short name	T457
Test name
Test status
Simulation time	200197686 ps
CPU time	2.25 seconds
Started	Sep 11 05:04:59 PM UTC 24
Finished	Sep 11 05:05:02 PM UTC 24
Peak memory	209112 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025132331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2025132331
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.72752161
Short name	T513
Test name
Test status
Simulation time	5541417890 ps
CPU time	19.18 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	218160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72752161 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.72752161
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.2491676903
Short name	T473
Test name
Test status
Simulation time	363903798 ps
CPU time	3.04 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:08 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491676903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2491676903
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.3252353757
Short name	T464
Test name
Test status
Simulation time	78911648 ps
CPU time	0.98 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:06 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252353757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3252353757
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.1304607565
Short name	T477
Test name
Test status
Simulation time	79023070 ps
CPU time	1.22 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:12 PM UTC 24
Peak memory	208136 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304607565 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1304607565
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.2973781373
Short name	T493
Test name
Test status
Simulation time	1279450457 ps
CPU time	6.71 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:18 PM UTC 24
Peak memory	241288 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973781373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2973781373
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2937018176
Short name	T480
Test name
Test status
Simulation time	301150606 ps
CPU time	1.76 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:13 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937018176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2937018176
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.1396178390
Short name	T475
Test name
Test status
Simulation time	214994722 ps
CPU time	1.36 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:12 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396178390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1396178390
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.3788252145
Short name	T505
Test name
Test status
Simulation time	2115217815 ps
CPU time	9.14 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:20 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788252145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3788252145
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.3836628771
Short name	T478
Test name
Test status
Simulation time	113240706 ps
CPU time	1.59 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:12 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836628771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.3836628771
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.3825614734
Short name	T468
Test name
Test status
Simulation time	115535103 ps
CPU time	1.32 seconds
Started	Sep 11 05:05:04 PM UTC 24
Finished	Sep 11 05:05:07 PM UTC 24
Peak memory	208260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825614734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.3825614734
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.2227593165
Short name	T522
Test name
Test status
Simulation time	3303398578 ps
CPU time	14.57 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:26 PM UTC 24
Peak memory	218156 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227593165 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2227593165
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.339909151
Short name	T482
Test name
Test status
Simulation time	135291397 ps
CPU time	1.9 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:13 PM UTC 24
Peak memory	216860 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339909151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.339909151
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.3957787033
Short name	T476
Test name
Test status
Simulation time	142582662 ps
CPU time	1.28 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:12 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957787033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3957787033
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.4231016457
Short name	T487
Test name
Test status
Simulation time	69938704 ps
CPU time	1.18 seconds
Started	Sep 11 05:05:12 PM UTC 24
Finished	Sep 11 05:05:14 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231016457 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.4231016457
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.1351126190
Short name	T508
Test name
Test status
Simulation time	2427637793 ps
CPU time	9.05 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:21 PM UTC 24
Peak memory	241728 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351126190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1351126190
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.2550106210
Short name	T484
Test name
Test status
Simulation time	301240122 ps
CPU time	1.74 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:13 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550106210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.2550106210
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.3493730117
Short name	T481
Test name
Test status
Simulation time	204192731 ps
CPU time	1.63 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:13 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493730117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3493730117
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.2323800899
Short name	T494
Test name
Test status
Simulation time	1563624720 ps
CPU time	6.75 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:18 PM UTC 24
Peak memory	209172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323800899 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2323800899
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3857098688
Short name	T483
Test name
Test status
Simulation time	155236687 ps
CPU time	1.61 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:13 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857098688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3857098688
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.453046771
Short name	T485
Test name
Test status
Simulation time	255867849 ps
CPU time	2.26 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:13 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453046771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.453046771
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.890650613
Short name	T490
Test name
Test status
Simulation time	401152805 ps
CPU time	2.3 seconds
Started	Sep 11 05:05:12 PM UTC 24
Finished	Sep 11 05:05:15 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890650613 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.890650613
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.1576197431
Short name	T486
Test name
Test status
Simulation time	130569909 ps
CPU time	2.11 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:13 PM UTC 24
Peak memory	217844 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576197431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1576197431
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.46596507
Short name	T479
Test name
Test status
Simulation time	98570468 ps
CPU time	1.3 seconds
Started	Sep 11 05:05:10 PM UTC 24
Finished	Sep 11 05:05:13 PM UTC 24
Peak memory	208300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46596507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.46596507
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.12145388
Short name	T500
Test name
Test status
Simulation time	59862669 ps
CPU time	1.12 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:19 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12145388 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.12145388
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.1529868765
Short name	T524
Test name
Test status
Simulation time	1962427797 ps
CPU time	8.54 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:26 PM UTC 24
Peak memory	241992 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529868765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1529868765
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.3563205789
Short name	T503
Test name
Test status
Simulation time	302124253 ps
CPU time	1.98 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:20 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563205789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.3563205789
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.3629146910
Short name	T495
Test name
Test status
Simulation time	193947158 ps
CPU time	0.98 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:19 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629146910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3629146910
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.171962641
Short name	T511
Test name
Test status
Simulation time	1534668230 ps
CPU time	6.63 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:24 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171962641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.171962641
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.642700488
Short name	T498
Test name
Test status
Simulation time	101991811 ps
CPU time	1.16 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:19 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642700488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.642700488
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.544933071
Short name	T488
Test name
Test status
Simulation time	117162955 ps
CPU time	1.81 seconds
Started	Sep 11 05:05:12 PM UTC 24
Finished	Sep 11 05:05:15 PM UTC 24
Peak memory	208320 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544933071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.544933071
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.3788507559
Short name	T496
Test name
Test status
Simulation time	2993133002 ps
CPU time	14.39 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:33 PM UTC 24
Peak memory	218224 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788507559 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3788507559
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.3263690471
Short name	T501
Test name
Test status
Simulation time	110495390 ps
CPU time	1.41 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:19 PM UTC 24
Peak memory	208196 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263690471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3263690471
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.991124124
Short name	T497
Test name
Test status
Simulation time	96912873 ps
CPU time	1.26 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:19 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991124124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.991124124
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.1601173471
Short name	T510
Test name
Test status
Simulation time	70747293 ps
CPU time	1.2 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:24 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601173471 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1601173471
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.4150364311
Short name	T527
Test name
Test status
Simulation time	1270200229 ps
CPU time	5.95 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:29 PM UTC 24
Peak memory	242372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150364311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.4150364311
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.763257029
Short name	T517
Test name
Test status
Simulation time	303078898 ps
CPU time	1.95 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	237620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763257029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.763257029
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.3230986327
Short name	T499
Test name
Test status
Simulation time	83614130 ps
CPU time	1.03 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:19 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230986327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.3230986327
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.1353123685
Short name	T509
Test name
Test status
Simulation time	1290243208 ps
CPU time	5.6 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:24 PM UTC 24
Peak memory	209204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353123685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1353123685
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3342312301
Short name	T507
Test name
Test status
Simulation time	149163059 ps
CPU time	1.64 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:20 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342312301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3342312301
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.4016618192
Short name	T504
Test name
Test status
Simulation time	229775074 ps
CPU time	1.82 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:20 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016618192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.4016618192
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.1373482853
Short name	T544
Test name
Test status
Simulation time	4609687509 ps
CPU time	15.77 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:39 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373482853 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1373482853
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.297327161
Short name	T506
Test name
Test status
Simulation time	129286947 ps
CPU time	1.69 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:20 PM UTC 24
Peak memory	208264 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297327161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.297327161
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.1275218264
Short name	T502
Test name
Test status
Simulation time	123531159 ps
CPU time	1.04 seconds
Started	Sep 11 05:05:17 PM UTC 24
Finished	Sep 11 05:05:19 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275218264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1275218264
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.207461148
Short name	T512
Test name
Test status
Simulation time	67498840 ps
CPU time	0.93 seconds
Started	Sep 11 05:05:23 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	208104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207461148 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.207461148
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.3748470291
Short name	T538
Test name
Test status
Simulation time	2444834071 ps
CPU time	10.52 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:34 PM UTC 24
Peak memory	241628 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748470291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3748470291
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2913312071
Short name	T521
Test name
Test status
Simulation time	302200347 ps
CPU time	1.87 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913312071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2913312071
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.3925515209
Short name	T515
Test name
Test status
Simulation time	207785195 ps
CPU time	1.55 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925515209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3925515209
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.2352576849
Short name	T526
Test name
Test status
Simulation time	1169620618 ps
CPU time	5.47 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:29 PM UTC 24
Peak memory	209212 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352576849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2352576849
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2181396397
Short name	T518
Test name
Test status
Simulation time	154864156 ps
CPU time	1.64 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	208272 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181396397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2181396397
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.2398624396
Short name	T514
Test name
Test status
Simulation time	257412642 ps
CPU time	1.52 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398624396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.2398624396
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.2813799352
Short name	T548
Test name
Test status
Simulation time	8999649450 ps
CPU time	33.61 seconds
Started	Sep 11 05:05:23 PM UTC 24
Finished	Sep 11 05:05:58 PM UTC 24
Peak memory	209300 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813799352 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2813799352
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.4225744603
Short name	T523
Test name
Test status
Simulation time	354442610 ps
CPU time	2.81 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:26 PM UTC 24
Peak memory	209048 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225744603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4225744603
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.1066000475
Short name	T519
Test name
Test status
Simulation time	167201496 ps
CPU time	1.91 seconds
Started	Sep 11 05:05:22 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	208204 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066000475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1066000475
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.2050210046
Short name	T528
Test name
Test status
Simulation time	76902559 ps
CPU time	0.93 seconds
Started	Sep 11 05:05:27 PM UTC 24
Finished	Sep 11 05:05:29 PM UTC 24
Peak memory	208172 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050210046 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2050210046
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.3966190074
Short name	T543
Test name
Test status
Simulation time	2437178481 ps
CPU time	8.87 seconds
Started	Sep 11 05:05:27 PM UTC 24
Finished	Sep 11 05:05:37 PM UTC 24
Peak memory	241788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966190074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3966190074
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3709357346
Short name	T533
Test name
Test status
Simulation time	302446168 ps
CPU time	1.85 seconds
Started	Sep 11 05:05:27 PM UTC 24
Finished	Sep 11 05:05:30 PM UTC 24
Peak memory	237616 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709357346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3709357346
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.507180436
Short name	T516
Test name
Test status
Simulation time	152455414 ps
CPU time	1.14 seconds
Started	Sep 11 05:05:23 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	208180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507180436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.507180436
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.3782452393
Short name	T531
Test name
Test status
Simulation time	1599287754 ps
CPU time	6.18 seconds
Started	Sep 11 05:05:23 PM UTC 24
Finished	Sep 11 05:05:30 PM UTC 24
Peak memory	209188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782452393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3782452393
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3674086978
Short name	T532
Test name
Test status
Simulation time	174900026 ps
CPU time	1.71 seconds
Started	Sep 11 05:05:27 PM UTC 24
Finished	Sep 11 05:05:30 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674086978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3674086978
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.2141126305
Short name	T520
Test name
Test status
Simulation time	251742080 ps
CPU time	1.75 seconds
Started	Sep 11 05:05:23 PM UTC 24
Finished	Sep 11 05:05:25 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141126305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2141126305
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.2129430801
Short name	T547
Test name
Test status
Simulation time	4888408126 ps
CPU time	21.44 seconds
Started	Sep 11 05:05:27 PM UTC 24
Finished	Sep 11 05:05:50 PM UTC 24
Peak memory	218220 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129430801 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2129430801
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.3565076745
Short name	T536
Test name
Test status
Simulation time	366911584 ps
CPU time	2.25 seconds
Started	Sep 11 05:05:27 PM UTC 24
Finished	Sep 11 05:05:30 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565076745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.3565076745
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.4218855617
Short name	T529
Test name
Test status
Simulation time	98068830 ps
CPU time	1.31 seconds
Started	Sep 11 05:05:27 PM UTC 24
Finished	Sep 11 05:05:30 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218855617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.4218855617
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.320259919
Short name	T540
Test name
Test status
Simulation time	72323158 ps
CPU time	1.02 seconds
Started	Sep 11 05:05:33 PM UTC 24
Finished	Sep 11 05:05:35 PM UTC 24
Peak memory	208104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320259919 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.320259919
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.2780609533
Short name	T545
Test name
Test status
Simulation time	2249378560 ps
CPU time	10.34 seconds
Started	Sep 11 05:05:33 PM UTC 24
Finished	Sep 11 05:05:45 PM UTC 24
Peak memory	242464 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780609533 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2780609533
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.760338774
Short name	T542
Test name
Test status
Simulation time	301573528 ps
CPU time	1.5 seconds
Started	Sep 11 05:05:33 PM UTC 24
Finished	Sep 11 05:05:36 PM UTC 24
Peak memory	237620 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760338774 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.760338774
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.2800473325
Short name	T530
Test name
Test status
Simulation time	231415662 ps
CPU time	1.05 seconds
Started	Sep 11 05:05:28 PM UTC 24
Finished	Sep 11 05:05:30 PM UTC 24
Peak memory	208168 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800473325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2800473325
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.2118196861
Short name	T539
Test name
Test status
Simulation time	1519084286 ps
CPU time	6.47 seconds
Started	Sep 11 05:05:28 PM UTC 24
Finished	Sep 11 05:05:35 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118196861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2118196861
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1096659648
Short name	T541
Test name
Test status
Simulation time	112071361 ps
CPU time	1.22 seconds
Started	Sep 11 05:05:33 PM UTC 24
Finished	Sep 11 05:05:35 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096659648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1096659648
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.4112967293
Short name	T535
Test name
Test status
Simulation time	119329027 ps
CPU time	1.89 seconds
Started	Sep 11 05:05:28 PM UTC 24
Finished	Sep 11 05:05:30 PM UTC 24
Peak memory	208256 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112967293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.4112967293
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.763026577
Short name	T546
Test name
Test status
Simulation time	3455938793 ps
CPU time	14.18 seconds
Started	Sep 11 05:05:33 PM UTC 24
Finished	Sep 11 05:05:49 PM UTC 24
Peak memory	209308 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763026577 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.763026577
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.805383286
Short name	T537
Test name
Test status
Simulation time	150565434 ps
CPU time	2.35 seconds
Started	Sep 11 05:05:28 PM UTC 24
Finished	Sep 11 05:05:31 PM UTC 24
Peak memory	208928 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805383286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.805383286
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.2161598540
Short name	T534
Test name
Test status
Simulation time	125665339 ps
CPU time	1.64 seconds
Started	Sep 11 05:05:28 PM UTC 24
Finished	Sep 11 05:05:30 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161598540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2161598540
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.3668688770
Short name	T146
Test name
Test status
Simulation time	96731588 ps
CPU time	1.31 seconds
Started	Sep 11 05:01:58 PM UTC 24
Finished	Sep 11 05:02:00 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668688770 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3668688770
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.2944720221
Short name	T29
Test name
Test status
Simulation time	1271576711 ps
CPU time	8.87 seconds
Started	Sep 11 05:01:55 PM UTC 24
Finished	Sep 11 05:02:05 PM UTC 24
Peak memory	241668 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944720221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.2944720221
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1550065541
Short name	T145
Test name
Test status
Simulation time	301942852 ps
CPU time	1.91 seconds
Started	Sep 11 05:01:55 PM UTC 24
Finished	Sep 11 05:01:58 PM UTC 24
Peak memory	237376 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550065541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1550065541
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.525330270
Short name	T17
Test name
Test status
Simulation time	115401201 ps
CPU time	1.37 seconds
Started	Sep 11 05:01:50 PM UTC 24
Finished	Sep 11 05:01:52 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525330270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.525330270
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1151212803
Short name	T112
Test name
Test status
Simulation time	1491921362 ps
CPU time	10.01 seconds
Started	Sep 11 05:01:51 PM UTC 24
Finished	Sep 11 05:02:02 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151212803 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1151212803
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2203945042
Short name	T144
Test name
Test status
Simulation time	176946362 ps
CPU time	1.31 seconds
Started	Sep 11 05:01:54 PM UTC 24
Finished	Sep 11 05:01:56 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203945042 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2203945042
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.947247463
Short name	T143
Test name
Test status
Simulation time	113397606 ps
CPU time	1.99 seconds
Started	Sep 11 05:01:50 PM UTC 24
Finished	Sep 11 05:01:53 PM UTC 24
Peak memory	208188 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947247463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.947247463
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.1035897994
Short name	T126
Test name
Test status
Simulation time	20355655724 ps
CPU time	84.78 seconds
Started	Sep 11 05:01:57 PM UTC 24
Finished	Sep 11 05:03:24 PM UTC 24
Peak memory	218160 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035897994 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1035897994
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.3132719145
Short name	T75
Test name
Test status
Simulation time	295202436 ps
CPU time	3.42 seconds
Started	Sep 11 05:01:54 PM UTC 24
Finished	Sep 11 05:01:58 PM UTC 24
Peak memory	217144 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132719145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3132719145
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3503200137
Short name	T128
Test name
Test status
Simulation time	169940868 ps
CPU time	1.79 seconds
Started	Sep 11 05:01:51 PM UTC 24
Finished	Sep 11 05:01:54 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503200137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3503200137
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.3534341176
Short name	T149
Test name
Test status
Simulation time	68036122 ps
CPU time	1.07 seconds
Started	Sep 11 05:02:06 PM UTC 24
Finished	Sep 11 05:02:08 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534341176 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.3534341176
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.1651033933
Short name	T30
Test name
Test status
Simulation time	2260545903 ps
CPU time	9.49 seconds
Started	Sep 11 05:02:06 PM UTC 24
Finished	Sep 11 05:02:17 PM UTC 24
Peak memory	242468 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651033933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.1651033933
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.113820184
Short name	T150
Test name
Test status
Simulation time	302249292 ps
CPU time	2.05 seconds
Started	Sep 11 05:02:06 PM UTC 24
Finished	Sep 11 05:02:09 PM UTC 24
Peak memory	237760 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113820184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.113820184
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.707121237
Short name	T18
Test name
Test status
Simulation time	190242668 ps
CPU time	1.68 seconds
Started	Sep 11 05:02:02 PM UTC 24
Finished	Sep 11 05:02:04 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707121237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.707121237
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.1702098356
Short name	T90
Test name
Test status
Simulation time	1778510840 ps
CPU time	11.41 seconds
Started	Sep 11 05:02:02 PM UTC 24
Finished	Sep 11 05:02:14 PM UTC 24
Peak memory	209304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702098356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1702098356
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.609621923
Short name	T148
Test name
Test status
Simulation time	173747527 ps
CPU time	1.93 seconds
Started	Sep 11 05:02:03 PM UTC 24
Finished	Sep 11 05:02:06 PM UTC 24
Peak memory	208240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609621923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.609621923
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.282388243
Short name	T147
Test name
Test status
Simulation time	110690027 ps
CPU time	1.82 seconds
Started	Sep 11 05:01:59 PM UTC 24
Finished	Sep 11 05:02:02 PM UTC 24
Peak memory	208260 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282388243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.282388243
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.3606758406
Short name	T207
Test name
Test status
Simulation time	9610395384 ps
CPU time	52.08 seconds
Started	Sep 11 05:02:06 PM UTC 24
Finished	Sep 11 05:03:00 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606758406 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3606758406
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.1925603722
Short name	T77
Test name
Test status
Simulation time	142956107 ps
CPU time	2.75 seconds
Started	Sep 11 05:02:03 PM UTC 24
Finished	Sep 11 05:02:07 PM UTC 24
Peak memory	208924 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925603722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1925603722
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.724815251
Short name	T129
Test name
Test status
Simulation time	213567365 ps
CPU time	1.69 seconds
Started	Sep 11 05:02:02 PM UTC 24
Finished	Sep 11 05:02:05 PM UTC 24
Peak memory	208296 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724815251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.724815251
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2635570040
Short name	T154
Test name
Test status
Simulation time	73948377 ps
CPU time	1.23 seconds
Started	Sep 11 05:02:15 PM UTC 24
Finished	Sep 11 05:02:17 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635570040 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2635570040
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.169564824
Short name	T153
Test name
Test status
Simulation time	302788231 ps
CPU time	1.86 seconds
Started	Sep 11 05:02:12 PM UTC 24
Finished	Sep 11 05:02:15 PM UTC 24
Peak memory	237440 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169564824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.169564824
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.2391713804
Short name	T19
Test name
Test status
Simulation time	151574991 ps
CPU time	1.51 seconds
Started	Sep 11 05:02:08 PM UTC 24
Finished	Sep 11 05:02:10 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391713804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2391713804
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.1401803115
Short name	T132
Test name
Test status
Simulation time	1338035972 ps
CPU time	8.43 seconds
Started	Sep 11 05:02:09 PM UTC 24
Finished	Sep 11 05:02:18 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401803115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1401803115
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1939979208
Short name	T152
Test name
Test status
Simulation time	108998563 ps
CPU time	1.78 seconds
Started	Sep 11 05:02:11 PM UTC 24
Finished	Sep 11 05:02:14 PM UTC 24
Peak memory	208104 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939979208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1939979208
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.680792495
Short name	T151
Test name
Test status
Simulation time	208281453 ps
CPU time	2.33 seconds
Started	Sep 11 05:02:06 PM UTC 24
Finished	Sep 11 05:02:10 PM UTC 24
Peak memory	209180 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680792495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.680792495
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.3051332185
Short name	T169
Test name
Test status
Simulation time	2988213878 ps
CPU time	17.44 seconds
Started	Sep 11 05:02:15 PM UTC 24
Finished	Sep 11 05:02:33 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051332185 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3051332185
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.1185535542
Short name	T130
Test name
Test status
Simulation time	341026005 ps
CPU time	2.25 seconds
Started	Sep 11 05:02:11 PM UTC 24
Finished	Sep 11 05:02:14 PM UTC 24
Peak memory	208708 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185535542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1185535542
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2204551736
Short name	T140
Test name
Test status
Simulation time	79033330 ps
CPU time	1.36 seconds
Started	Sep 11 05:02:09 PM UTC 24
Finished	Sep 11 05:02:11 PM UTC 24
Peak memory	208236 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204551736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2204551736
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.1730754207
Short name	T159
Test name
Test status
Simulation time	78534895 ps
CPU time	1.23 seconds
Started	Sep 11 05:02:23 PM UTC 24
Finished	Sep 11 05:02:25 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730754207 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.1730754207
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.950431278
Short name	T31
Test name
Test status
Simulation time	1966870855 ps
CPU time	8.65 seconds
Started	Sep 11 05:02:19 PM UTC 24
Finished	Sep 11 05:02:29 PM UTC 24
Peak memory	240788 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950431278 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.950431278
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3012151274
Short name	T158
Test name
Test status
Simulation time	301539120 ps
CPU time	1.68 seconds
Started	Sep 11 05:02:19 PM UTC 24
Finished	Sep 11 05:02:22 PM UTC 24
Peak memory	237316 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012151274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3012151274
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.3546105715
Short name	T20
Test name
Test status
Simulation time	222815529 ps
CPU time	1.62 seconds
Started	Sep 11 05:02:16 PM UTC 24
Finished	Sep 11 05:02:19 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546105715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3546105715
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.3216557208
Short name	T92
Test name
Test status
Simulation time	911321621 ps
CPU time	6.5 seconds
Started	Sep 11 05:02:16 PM UTC 24
Finished	Sep 11 05:02:24 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216557208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3216557208
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3100445425
Short name	T155
Test name
Test status
Simulation time	187783060 ps
CPU time	1.45 seconds
Started	Sep 11 05:02:18 PM UTC 24
Finished	Sep 11 05:02:20 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100445425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.3100445425
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.2724261829
Short name	T131
Test name
Test status
Simulation time	240610512 ps
CPU time	2.38 seconds
Started	Sep 11 05:02:15 PM UTC 24
Finished	Sep 11 05:02:18 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724261829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2724261829
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.374096831
Short name	T234
Test name
Test status
Simulation time	12565585314 ps
CPU time	55.81 seconds
Started	Sep 11 05:02:20 PM UTC 24
Finished	Sep 11 05:03:17 PM UTC 24
Peak memory	218164 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374096831 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.374096831
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.594255613
Short name	T157
Test name
Test status
Simulation time	255493206 ps
CPU time	2.81 seconds
Started	Sep 11 05:02:18 PM UTC 24
Finished	Sep 11 05:02:22 PM UTC 24
Peak memory	208984 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594255613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.594255613
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.1891063018
Short name	T156
Test name
Test status
Simulation time	197534444 ps
CPU time	2.06 seconds
Started	Sep 11 05:02:18 PM UTC 24
Finished	Sep 11 05:02:21 PM UTC 24
Peak memory	208896 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891063018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.1891063018
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.1811194612
Short name	T165
Test name
Test status
Simulation time	85122067 ps
CPU time	1.29 seconds
Started	Sep 11 05:02:28 PM UTC 24
Finished	Sep 11 05:02:31 PM UTC 24
Peak memory	208108 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811194612 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1811194612
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.776880449
Short name	T32
Test name
Test status
Simulation time	1265339893 ps
CPU time	7.79 seconds
Started	Sep 11 05:02:26 PM UTC 24
Finished	Sep 11 05:02:35 PM UTC 24
Peak memory	242372 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776880449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.776880449
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1991699866
Short name	T164
Test name
Test status
Simulation time	300749265 ps
CPU time	1.98 seconds
Started	Sep 11 05:02:26 PM UTC 24
Finished	Sep 11 05:02:29 PM UTC 24
Peak memory	237436 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991699866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1991699866
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.869463208
Short name	T21
Test name
Test status
Simulation time	170541512 ps
CPU time	1.5 seconds
Started	Sep 11 05:02:23 PM UTC 24
Finished	Sep 11 05:02:25 PM UTC 24
Peak memory	208176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869463208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.869463208
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.3421505645
Short name	T93
Test name
Test status
Simulation time	980506373 ps
CPU time	7.01 seconds
Started	Sep 11 05:02:23 PM UTC 24
Finished	Sep 11 05:02:31 PM UTC 24
Peak memory	209240 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421505645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.3421505645
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2341932323
Short name	T162
Test name
Test status
Simulation time	161651765 ps
CPU time	2.01 seconds
Started	Sep 11 05:02:24 PM UTC 24
Finished	Sep 11 05:02:27 PM UTC 24
Peak memory	208304 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341932323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2341932323
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.3914309370
Short name	T161
Test name
Test status
Simulation time	201816907 ps
CPU time	2.39 seconds
Started	Sep 11 05:02:23 PM UTC 24
Finished	Sep 11 05:02:26 PM UTC 24
Peak memory	209176 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914309370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3914309370
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.2789853270
Short name	T99
Test name
Test status
Simulation time	3594485172 ps
CPU time	24.94 seconds
Started	Sep 11 05:02:26 PM UTC 24
Finished	Sep 11 05:02:52 PM UTC 24
Peak memory	209244 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789853270 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2789853270
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.511944967
Short name	T163
Test name
Test status
Simulation time	297774553 ps
CPU time	3.45 seconds
Started	Sep 11 05:02:24 PM UTC 24
Finished	Sep 11 05:02:29 PM UTC 24
Peak memory	208988 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511944967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.511944967
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.4216937802
Short name	T160
Test name
Test status
Simulation time	167076108 ps
CPU time	2.08 seconds
Started	Sep 11 05:02:23 PM UTC 24
Finished	Sep 11 05:02:26 PM UTC 24
Peak memory	209052 kb
Host	riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216937802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.4216937802
Directory	/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest