Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8442

1

T2

2

T10

15

T12

16

auto[1]

11378

1

T2

1

T4

4

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6124	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6872	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2966	1			T4	1		T5	1		T7	1
reset_info_cp[4]	3914	1			T4	1		T5	1		T7	1
reset_info_cp[8]	109	1			T10	1		T23	1		T62	1
reset_info_cp[16]	116	1			T10	1		T12	1		T23	1
reset_info_cp[32]	112	1			T2	1		T60	1		T25	1
reset_info_cp[64]	105	1			T9	1		T23	1		T51	1
reset_info_cp[128]	122	1			T10	1		T12	2		T43	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3327	1			T23	6		T89	11		T43	19
reset_info_cp[1]	auto[1]	2925	1			T4	1		T5	1		T7	1
reset_info_cp[2]	auto[0]	929	1			T23	3		T89	6		T51	5
reset_info_cp[2]	auto[1]	2037	1			T4	1		T5	1		T7	1
reset_info_cp[4]	auto[0]	1395	1			T23	6		T89	4		T51	5
reset_info_cp[4]	auto[1]	2519	1			T4	1		T5	1		T7	1
reset_info_cp[8]	auto[0]	47	1			T10	1		T105	1		T148	1
reset_info_cp[8]	auto[1]	62	1			T23	1		T62	1		T60	2
reset_info_cp[16]	auto[0]	51	1			T10	1		T12	1		T141	1
reset_info_cp[16]	auto[1]	65	1			T23	1		T59	1		T43	1
reset_info_cp[32]	auto[0]	47	1			T2	1		T143	1		T112	3
reset_info_cp[32]	auto[1]	65	1			T60	1		T25	1		T26	1
reset_info_cp[64]	auto[0]	35	1			T23	1		T51	1		T86	1
reset_info_cp[64]	auto[1]	70	1			T9	1		T53	1		T62	1
reset_info_cp[128]	auto[0]	46	1			T10	1		T12	2		T83	1
reset_info_cp[128]	auto[1]	76	1			T43	1		T52	1		T60	2