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 LINE       1361
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T5,T7
1	1	0	Covered	T74,T98,T99
1	1	1	Covered	T2,T5,T7

 LINE       1364
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T5
1	0	1	Covered	T2,T5,T7
1	1	0	Covered	T78,T102,T99
1	1	1	Covered	T2,T5,T7